Data transmission device

Abstract

The invention discloses a data transmission device, which comprises an on-chip network interface module used for receiving messages sent by a first core grain in real time by taking data sub-packets as units and classifying each data sub-packet into a virtual channel matched with the on-chip network interface module according to the message type in each period, the on-chip network interface module internally comprises a plurality of parallel virtual channels; the interconnection control main body module is used for arbitrating and obtaining a target virtual channel in a plurality of virtual channels of the on-chip network interface module in each period, obtaining a data sub-packet from the target virtual channel, packaging a message frame, and sending the packaged message frame to the physical transmission layer module; and the physical transmission layer module is used for sending a message frame received in real time to the second core grain, and the device reduces the transmission delay of a complete message as much as possible on the premise of ensuring the correctness of data transmission between the core grains, and meanwhile, ensures the transmission efficiency and improves the transmission bandwidth.

Description

Technical Field

[0001] This invention relates to the field of digital circuit design technology, and more particularly to a data transmission device. Background Technology

[0002] As Moore's Law approaches its physical limits, heterogeneous integration technology centered on individual computing chips has become the core path for the continued development of the semiconductor industry in the post-Moore era. Especially in scenarios such as artificial intelligence training, high-performance computing, and 5G communication, system computing power no longer depends solely on the performance of a single computing chip, but rather on the efficient and reliable data collaboration capabilities between multiple chips. Therefore, achieving high-bandwidth, low-latency interconnection between chips has become a key bottleneck in improving overall system performance.

[0003] In existing technologies, standardized protocols derived from board-level interconnects are often used as solutions for inter-chip communication. To achieve high reliability and versatility, these protocols typically require transactions to be encapsulated into data packets containing header and footer checksums for transmission. However, when faced with extreme latency and bandwidth requirements between chips, this mechanism reveals inherent flaws: for large data transmissions, complete data packets must be collected before cross-chip transmission can begin, leading to a significant increase in transmission latency; for small data transmissions, the excessive overhead of the protocol header and footer severely reduces the effective transmission bandwidth. This inherent contradiction between latency and efficiency hinders the full realization of the potential of chip technology. Summary of the Invention

[0004] This invention provides a data transmission device to solve the problem of balancing high bandwidth and low latency in existing chip interconnect technologies.

[0005] According to one aspect of the present invention, a data transmission apparatus is provided, comprising: an on-chip network interface module, an interconnection control main module, and a physical transport layer module; wherein:

[0006] The on-chip network interface module is used to receive messages sent by the first chip in real time, in units of data sub-packets, and classify each data sub-packet into the virtual channel matched by the on-chip network interface module according to the message type in each cycle. The on-chip network interface module includes multiple parallel virtual channels.

[0007] The interconnection control module is used to arbitrate among multiple virtual channels of the on-chip network interface module in each cycle to obtain the target virtual channel, and after obtaining a data sub-packet from the target virtual channel, encapsulate it into a message frame and send the encapsulated message frame to the physical transport layer module. Each message frame is transmitted independently.

[0008] The physical transport layer module is used to send the message frames received in real time to the second core.

[0009] According to another aspect of the present invention, bidirectional data transmission hardware is also provided, comprising: two data transmission devices as described in any embodiment of the present invention, the two data transmission devices including a first data transmission device and a second data transmission device, wherein:

[0010] The on-chip network interface module in the first data transmission device and the physical transmission layer module of the second data transmission device are respectively used to connect to one chip, and the on-chip network interface module in the second data transmission device and the physical transmission layer module in the first data transmission device are respectively used to connect to another chip.

[0011] According to another aspect of the present invention, a system-on-a-chip is also provided, characterized in that a communication connection is established between two chips via bidirectional data transmission hardware as described in claim .

[0012] An embodiment of the present invention provides a data transmission device comprising: an on-chip network interface module (ISP) for receiving messages sent by a first chip in real time, in units of data sub-packets, and classifying each data sub-packet into a virtual channel matched by the ISP according to message type in each cycle, wherein the ISP includes multiple parallel virtual channels; an interconnection control module for arbitrarily obtaining a target virtual channel from the multiple virtual channels of the ISP in each cycle, and encapsulating a message frame based on a data sub-packet obtained from the target virtual channel, and sending the encapsulated message frame to a physical transport layer module, wherein each message frame is transmitted independently, greatly improving transmission efficiency; and a physical transport layer module for sending the real-time received message frames to a second chip. This novel data transmission device can split complete messages into fine-grained data sub-packets for encapsulation and transmission, thereby significantly reducing the end-to-end transmission latency of a single message. Simultaneously, through parallel processing of virtual channels and a periodic arbitration encapsulation mechanism, the bandwidth utilization efficiency of the physical link is effectively improved, ultimately achieving a synergistic optimization of high bandwidth and low latency.

[0013] It should be understood that the description in this section is not intended to identify key or essential features of the embodiments of the present invention, nor is it intended to limit the scope of the invention. Other features of the invention will become readily apparent from the following description. Attached Figure Description

[0014] To more clearly illustrate the technical solutions in the embodiments of the present invention, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0015] Figure 1 This is a schematic diagram of a data transmission device according to Embodiment 1 of the present invention;

[0016] Figure 2 This is a schematic diagram of the state machine transition of an on-chip network interface transmitter according to Embodiment 1 of the present invention;

[0017] Figure 3 This is a schematic diagram of message merging according to Embodiment 1 of the present invention;

[0018] Figure 4 This is a structural diagram of an interconnection control main body provided according to Embodiment 1 of the present invention;

[0019] Figure 5 This is a schematic diagram of the structure of a bidirectional data transmission hardware according to Embodiment 2 of the present invention;

[0020] Figure 6 This is a schematic diagram of the structure of a bidirectional data transmission on-chip system provided in Embodiment 3 of the present invention. Detailed Implementation

[0021] To enable those skilled in the art to better understand the present invention, the technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings of the embodiments of the present invention. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort should fall within the scope of protection of the present invention.

[0022] It should be noted that the terms "first," "second," etc., in the specification, claims, and accompanying drawings of this invention are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that the embodiments of the invention described herein can be implemented in orders other than those illustrated or described herein. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion; for example, a process, method, system, product, or apparatus that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus.

[0023] Example 1

[0024] Figure 1 This is a schematic diagram of a data transmission device provided in Embodiment 1 of the present invention. This embodiment is applicable to situations requiring high bandwidth and low latency inter-chip data transmission.

[0025] Correspondingly, such as Figure 1 As shown, the device includes: an on-chip network interface module 110, an interconnect control main module 120, and a physical transport layer module 130. The on-chip network interface module 110 is connected to the interconnect control main module 120, and the interconnect control main module 120 is connected to the physical transport layer module 130, wherein:

[0026] The on-chip network interface module 110 is used to receive messages sent by the first chip in real time in units of data sub-packets, and classify each data sub-packet into the virtual channel matched by the on-chip network interface module according to the message type in each cycle. The on-chip network interface module includes multiple parallel virtual channels.

[0027] A data sub-packet can be understood as the smallest transmission unit formed by breaking down a complete message. When a complete communication request is transmitted in the chip's internal network, it is divided into multiple smaller, fixed-size data sub-packets.

[0028] In this embodiment, the on-chip network interface module serves as the connection interface between the device and the internal computing or storage units of the chip, and is responsible for receiving various communication requests generated within the chip. The core function of the on-chip network interface module is to perform real-time parsing and classification of the received data stream. Based on the transactional characteristics of the message itself—such as whether it is a request to access an external device, a response to a previous request, or a notification message used to maintain cache consistency—it is routed to different corresponding virtual channels within the chip. This classification mechanism ensures that data with the same characteristics or priority requirements can flow orderly within logically independent channels, laying the foundation for subsequent refined management.

[0029] Optionally, based on the above embodiments, the on-chip network interface module may include a message classification unit, multiple virtual channels, and multiple state machine units, with one state machine unit corresponding to each virtual channel, wherein:

[0030] The message classification unit is used to classify data sub-packets into virtual channels that match the message type of the received data sub-packets when receiving data sub-packets in each cycle.

[0031] Virtual channels are used to aggregate and store data sub-packets of the matching message type that are to be sent to the second core.

[0032] The state machine unit is used to update the state of the next cycle and / or add matching data tags to the new data sub-packet when a new data sub-packet is detected on the set virtual channel in a cycle, based on the state of the current cycle and the data type of the new data sub-packet.

[0033] Generally, the message classification unit, as the entry point for data transmission, is responsible for the real-time parsing and distribution of data sub-packets delivered each clock cycle. Its core function is to precisely guide the data sub-packet to a dedicated virtual channel pre-configured for that message type based on the inherent category attributes of the message it belongs to—such as an input / output request, an interrupt signal, or buffer coherence communication. This initial classification ensures logical separation of data streams of different natures from the entry point, laying the foundation for subsequent differentiated scheduling.

[0034] Generally, virtual channels are not physically independent links, but rather a logical queue management mechanism. Each virtual channel corresponds to a specific message type, serving as a collection point and buffer for data sub-packets of that type. All data sub-packets classified into this channel will queue up in order, thus creating independent and non-interfering transmission paths for service flows with different service requirements on shared physical transmission resources. This effectively avoids the situation where low-priority or high-volume data blocks high-priority messages.

[0035] In a specific example, when a chip system is processing AI analysis of medical images, the computing chip is continuously receiving a large-scale image data stream from the memory chip through a shared physical link. If the I / O management chip suddenly issues an emergency stop command (interrupt request), the virtual channel mechanism can ensure that the command is processed first, automatically classifying the interrupt request into a dedicated high-priority virtual channel, while the massive image data stream is kept in the ordinary data channel. When the interconnect control module arbitrates in each transmission cycle, it interrupts the current data transmission and prioritizes the encapsulation and transmission of the emergency command in the high-priority virtual channel.

[0036] Generally, the state machine unit maintains a dynamic state identifier for each virtual channel. The state machine unit continuously monitors the inflow of data sub-packets within the channel and updates the state identifier for the next cycle based on the current state (e.g., receiving the beginning of a message, intermediate data, or waiting for an end marker) and the characteristics of newly arriving data sub-packets (e.g., whether they are special packets marking the start or end of a message). Simultaneously, it adds corresponding internal tags to the data sub-packets to indicate their position within the complete message sequence, thereby ensuring that the receiving end can correctly identify and reassemble the message regardless of how many fragments it is broken into.

[0037] Optionally, based on the above embodiments, the state machine unit is specifically used for:

[0038] If the current period's state is header receiving state and the data type of the new data sub-packet is header, determine the state of the next period to maintain header receiving state, and add the header flag to the new data sub-packet;

[0039] When the current period's state is header reception state and the new data sub-packet's data type is data, determine the next period's state as data reception state; obtain and record the total number of data sub-packets associated with the new data sub-packet, and update the current data sub-packet counter; wherein, a matching data sub-packet counter is set within each state machine unit;

[0040] If the current period's state is data receiving and the new data sub-packet's data type is data, update the current data sub-packet counter. If the updated data sub-packet counter has not reached the total number of data sub-packets, determine the next period's state to be data receiving. If the updated data sub-packet counter reaches the total number of data sub-packets, determine the next period's state to be header receiving and add a tail flag to the new data sub-packet.

[0041] Figure 2 This is a schematic diagram of the state machine transition at the transmitting end of an on-chip network interface, such as... Figure 2 As shown, in the initial header receiving state, the state machine unit continuously monitors newly arrived data sub-packets. When it recognizes that the sub-packet is a header that marks the start of a message, the state machine does not change its operating phase, but remains in the header receiving state to prepare for processing the next possible new message. At the same time, it marks the header sub-packet with a specific identifier to indicate its attribute as the start of a message.

[0042] Generally, if the state machine receives a data sub-packet carrying the actual content during the header waiting phase, it means that a new message with a data payload has begun transmission. The state machine will immediately switch to the data receiving state, obtain the total number of data sub-packets contained in the message from the information carried in the header, and initialize an internal counting mechanism to track the subsequent reception progress.

[0043] Generally, after entering the data receiving state, the state machine updates its counter mechanism for each valid data packet received. If the updated count value has not yet reached the predetermined total, the state machine will continue to maintain the current state to wait for subsequent data. When the count value confirms that all data packets have been received, the state machine completes the current message receiving cycle, automatically jumps back to the initial packet header receiving state, prepares to receive the next message, and simultaneously marks the last received data packet with a message end marker, thus completely defining the boundary of a message unit.

[0044] In an optional implementation of this embodiment, when the computing chip needs to read a specific piece of data from the memory chip, the request is assembled into a complete message containing a header and several data sub-packets. The state machine unit initially enters the header receiving state. The first arriving header sub-packet, after parsing, is confirmed as the start marker of the read request, and the header explicitly indicates that five data sub-packets will follow. The state machine immediately switches to the data receiving state, sets its internal counter to five, and marks the header with a start marker. Subsequently, the counter decrements with each arriving data sub-packet: when the third data sub-packet is received, the counter shows two remaining, and the state machine remains in the data receiving state; when the fifth data sub-packet arrives, the counter returns to zero, the state machine automatically resets to the header receiving state, and adds an end marker to this last sub-packet, thus forming a complete and processable read request message submitted to subsequent modules.

[0045] Optionally, based on the above embodiments, the message types received by the on-chip network interface module include at least one:

[0046] I / O request, I / O response, interrupt request, interrupt response, host owner message (HOM) request, cache listener snoop message, no data response, direct memory access (DMA) request, direct memory access (DMA) response.

[0047] Generally, on-chip network interface modules can handle various core message types, including I / O requests and responses for initiating data exchange with external devices, interrupt requests and acknowledgments for handling emergency event notifications, listener messages and host owner queries for maintaining cache consistency, no-data responses indicating operation completion, and direct memory access requests and responses for efficient large-volume data transfer. These messages collectively constitute the basic communication set for control signaling transmission, data handling, and state synchronization in a multi-core collaborative environment. For example, a computing core can obtain data through direct memory access requests, coordinate tasks through interrupt requests during processing, ensure data consistency across multiple cores using cache listener messages, and finally complete the entire operation process through response messages.

[0048] The interconnection control main module 120 is used to arbitrate and obtain the target virtual channel from multiple virtual channels of the on-chip network interface module in each cycle, and after obtaining a data sub-packet from the target virtual channel, encapsulate it into a message frame and send the encapsulated message frame to the physical transport layer module. Each message frame is transmitted independently.

[0049] In this context, a virtual channel can be understood as a non-physically independent transmission path, but rather a logical isolation mechanism based on queue management. Its core function is to allocate independent logical queues to data streams with different characteristics according to message type or priority, thereby achieving the classification, arrangement, and orderly transmission of data packets.

[0050] In this embodiment, the interconnection control module undertakes the core scheduling and encapsulation responsibilities within the device. The interconnection control module continuously monitors the data status of all virtual channels and, based on a preset arbitration strategy (e.g., prioritizing high-priority channels or employing a fair polling mechanism), selects a channel from among many waiting channels to acquire the right to send within the current period. Subsequently, it extracts the data unit to be sent from the selected channel and encapsulates it according to a predefined frame format, forming a uniformly formatted independent message frame containing necessary control information. The core advantage of this design is that each message frame carries complete transmission semantics, and its content parsing and processing do not depend on any previous or subsequent frames. Therefore, each message frame is transmitted independently, without relying on the context of preceding or following frames, thus achieving decoupling of the transmission process.

[0051] Optionally, based on the above embodiments, the interconnection control main module specifically includes a transmitting controller, wherein the transmitting controller is specifically used for:

[0052] In each cycle, the target virtual channel is obtained through arbitration from multiple virtual channels, and a target data sub-packet is obtained sequentially from the target virtual channels;

[0053] Detect whether the data payload length of the target data sub-packet is less than or equal to half the maximum capacity of a single message frame;

[0054] If so, the preset secondary arbitration strategy is followed to traverse and detect in other virtual channels. If there is an associated data sub-packet in other virtual channels that is less than or equal to half the maximum capacity of a single message frame, the target data sub-packet and the associated data sub-packet are merged and encapsulated to obtain a merged and encapsulated message frame, which is then sent to the physical transport layer module.

[0055] Otherwise, the target data sub-packet is encapsulated separately to obtain an encapsulated message frame, which is then sent to the physical transport layer module.

[0056] Generally, at the beginning of each work cycle, the sending controller first arbitrates all sending requests from virtual channels, selects a target channel that can obtain sending permission in the current cycle according to a preset strategy, and then takes out a data sub-packet to be sent from that channel in sequence.

[0057] Generally, the controller immediately detects the actual data size of the selected data sub-packet and determines whether it is less than or equal to half of the maximum capacity that a single message frame can carry. This step is a crucial judgment in determining whether message merging can be performed, thereby improving link utilization.

[0058] Generally, if the judgment result is yes, the controller will initiate a secondary arbitration process, scanning other virtual channels that have not obtained primary sending privileges to look for a similarly small data sub-packet to be sent. If found, it will select one according to the secondary strategy and package it together with the initially selected target data sub-packet into the same physical message frame to form a merged frame for transmission. If the initial data sub-packet is too large to be merged, the controller will encapsulate it separately into a complete message frame and send it out.

[0059] Correspondingly, Figure 3 This is a schematic diagram of message merging, such as... Figure 3 As shown, when the arbitrator selects message header Head0 from virtual channel 1, it determines that its data volume is small (less than half the capacity of a single frame). At this time, the message merging unit will scan other virtual channels in parallel and find that message header Head1 in virtual channel 3 also meets the merging conditions. Therefore, the two message headers, Head0 and Head1, are rearranged: Head0 occupies the standard header field position at the beginning of the frame, and Head1 is embedded in the reserved bit field (i.e., RSV), while a merging flag is set in the frame header. Conversely, if the target message data volume is too large, exceeding half the capacity of a single frame, or if there are no related messages that meet the merging conditions in other virtual channels at that time, the transmitter will use a non-mergeable separate encapsulation method to encapsulate the message independently into a frame for transmission to ensure the timeliness of data transmission. This design allows the merged frame to carry the control information of two independent messages simultaneously, while the data area can be filled with the payload of the corresponding message as needed.

[0060] In an optional implementation of this embodiment, when the sending controller of the interconnect control main module selects a data sub-packet (carrying only 8 bytes of acknowledgment information) from the virtual channel handling direct memory access responses within an arbitration cycle, and determines that it is much smaller than half the capacity of a single frame, it will immediately scan other virtual channels. Assuming that there happens to be a 4-byte configuration read command waiting to be sent in the input / output request channel at this time, the sending controller selects this command through secondary arbitration, merges and encapsulates these two small data sub-packets from different service flows into the payload area of ​​the same message frame, sets a merging flag, and finally sends it to the peer core as a single physical frame.

[0061] Furthermore, based on the above embodiments, the interconnection control main module may further include a link controller, a flow controller, and a message receiver, wherein:

[0062] The link controller is used to prevent the on-chip network interface module from receiving data sub-packets sent by the first core before establishing a link connection with the second core or when a link failure occurs in an already established link; to construct a handshake command and send it to the physical transport layer module to attempt to establish a communication link with the second core; and to allow the on-chip network interface module to receive data sub-packets sent by the first core after successfully establishing a communication link.

[0063] The flow controller is used to periodically send flow notification instructions to the first core, informing the first core of the number of messages that the second core can currently receive, as well as to receive flow control instructions sent by the second core, and to control whether the first core can currently send messages to the second core according to the flow control instructions.

[0064] The message receiver is used to receive each feedback data frame transmitted by the second chip via the physical transport layer module, and after parsing the feedback data frame, write the payload data in the feedback data frame into the receive buffer in the matching virtual channel; monitor the non-empty state of each receive buffer, and when the on-chip network interface module is in the ready state, immediately initiate a read operation to forward the payload data cached in the receive buffer to the first chip.

[0065] Generally, the link controller is responsible for managing the connection status of the physical link. When the channel is not established or an anomaly occurs, it will prevent the front end from receiving new data to prevent data loss, while continuously sending negotiation signals to the other end to try to establish a stable connection. Once it is confirmed that the link has returned to normal and the other end is ready, the controller will reopen the data transmission permission to ensure that all communication is based on a reliable connection.

[0066] Generally, flow controllers achieve precise flow management through a credit mechanism. The local end periodically informs the peer of its remaining receive buffer space and receives and parses the capacity status sent by the peer. By comparing the capacity of both parties in real time, the local end dynamically controls its sending behavior. When the peer's buffer is insufficient, sending is suspended, thereby achieving flow control while avoiding data overflow or channel idleness.

[0067] Generally, the message receiver is responsible for processing feedback data from the other end. It parses the received data frames and stores the valid data into the corresponding type of receive buffer queue according to the frame header information. The receiver continuously monitors the data backlog in each buffer. Once it detects that the front-end processing unit is ready and the buffer contains data, it immediately starts the forwarding process and sends the data to the target processing unit.

[0068] Furthermore, based on the above embodiments, the interconnection control main module may also include a correctness controller, which is used to realize message error detection and message retransmission between the first core and the second core;

[0069] The correctness controller specifically includes: a retransmission buffer unit, a message number generation unit, a CRC generation unit, a CRC verification unit, a correctness message generation unit, and a correctness message receiving unit, wherein:

[0070] The retransmission buffer unit is used to store copies of frame data that have been sent but for which no acknowledgment message has been received from the other end, and to delete the corresponding copy after receiving the acknowledgment message, or to provide the copy data when a retransmission request is received;

[0071] The message number generation unit is used to generate and assign a globally unique sequence number to each message frame to be sent, and add the sequence number to the frame header;

[0072] The CRC generation unit is used to calculate the cyclic redundancy check code for each message frame to be sent and append the check code to the end of the frame.

[0073] The CRC check unit is used to verify the checksum of the received message frame. If the verification fails, the frame is discarded and the error handling process is triggered.

[0074] The correctness message generation unit is used to periodically or event-triggered generate status messages containing a range of confirmed sequence numbers, or to generate confirmation or denial messages for specific sequence numbers;

[0075] The correctness message receiving unit is used to receive and parse the status messages sent by the peer, update the local confirmation status according to the message content, and trigger the corresponding retransmission buffer management operation.

[0076] Generally, the core function of the retransmission buffer unit is to act as a temporary insurance for data, completely saving copies of all message frames that have been sent but have not yet received a successful acknowledgment from the receiver. These data copies will be properly stored until the corresponding acknowledgment signal is successfully returned before being cleared and released. If a retransmission instruction is received from the receiver midway, the retransmission buffer unit can immediately and accurately provide a copy of the specified message for retransmission, thereby ensuring that the data is not lost due to accidents during transmission.

[0077] Generally speaking, the main function of the message number generation unit is to establish the traceability of data frames, assign a globally unique sequence identifier to each message frame to be sent, and clearly mark this sequence number in a specific position in the frame header. This enables both communicating parties to clearly identify and track each independent data frame, laying a solid foundation for orderly transmission and accurate retransmission.

[0078] Generally, before data is sent, the CRC generation unit performs a complex calculation algorithm on the entire message frame to generate a unique check code. This check code, which is like a data fingerprint, is then appended to the end of the frame. Together with the data, it forms a complete transmission unit. Any minor error that occurs during transmission will cause this fingerprint to become invalid.

[0079] Generally, when a message frame arrives, the CRC check unit immediately uses the same algorithm as the sender to recalculate the checksum of the data content in the frame and strictly compares it with the original checksum carried at the end of the frame. If the two are found to be inconsistent, it will determine that an error has occurred in the transmission process, and then discard the problematic frame and trigger the subsequent error handling mechanism.

[0080] Generally, the correctness message generation unit automatically generates a status report message based on a preset time period or a specific event (such as detecting a discontinuous frame sequence). This message may contain the sequence number range of frames that have been successfully received consecutively to achieve batch confirmation, or it may generate specific denial information for detected lost or erroneous frames, thereby providing clear reception status feedback to the sender.

[0081] Generally, the correctness message receiving unit is dedicated to receiving and parsing various status messages from the receiving end. By interpreting the message content, it updates the local transmission acknowledgment status diagram and issues explicit management instructions to the retransmission buffer unit accordingly—either clearing the copy of the acknowledged frame to release space or initiating the retransmission process of the specified sequence number frame.

[0082] Specifically, Figure 4 This is a diagram of an interconnected control main structure, such as... Figure 4 As shown, this module comprises five core components: a link controller, a flow controller, a message transmitter (i.e., a sending controller), a message receiver (i.e., a message selector), and a correctness controller. The message transmitter integrates an arbitrator and a message merging unit, responsible for dynamically arbitrating and scheduling N virtual channels (VC0 to VCn, where VC represents a virtual channel), and merging eligible small data packets for transmission through a message merging mechanism. The message receiver distributes inbound data to the corresponding virtual channel's receive buffer via a frame parser. The correctness controller implements end-to-end error control using a CRC check unit, a retransmission buffer unit, and a correctness message processing unit. The link controller and flow controller, through physical link status maintenance and credit counting mechanisms respectively, collaboratively ensure the reliability and real-time performance of data transmission, ultimately forming a high-bandwidth, low-latency inter-chip interconnection solution.

[0083] The physical transport layer module 130 is used to send the message frames received in real time to the second core.

[0084] In this embodiment, the physical transport layer module serves as the interface between the device and the external physical link, responsible for converting logical-level message frames into signal forms that can be transmitted over the actual physical medium. The physical transport layer module receives the encapsulated message frames, converts the digital information into waveforms conforming to electrical or optical signal specifications through its internal signal processing unit, and drives reliable transmission over the inter-chip transmission channel. The module's design fully considers compatibility with different underlying physical interface standards, enabling it to adapt to various mature industrial standard high-speed interface technologies, ensuring the flexibility and feasibility of the entire device in practical applications.

[0085] Optionally, based on the above embodiments, the transmission method of the physical transport layer module includes at least one of the following:

[0086] Electrical interconnects based on serializers and / or deserializers (SerDes), advanced packaged interconnects based on silicon interposers, packaged interconnects based on redistribution layers, embedded silicon bridge interconnects, optical interconnects, and wireless inter-chip interconnects, with specific protocol compatibility with industry standards such as Express UCIe, Compute Fast Link (CXL), Bunch of Wires (BoW), or High-Speed ​​Peripheral Component Interconnect (PCIe).

[0087] Generally, the physical transport layer module supports a variety of cutting-edge interconnect solutions, including electrical signal transmission based on serializers / deserializers, high-density wiring within advanced packages using silicon interposers or redistribution layers, local high-speed interconnects via embedded silicon bridges, and future-oriented optical signal transmission and wireless inter-chip communication technologies. It is also compatible with mainstream industry standard protocols. This flexible design ensures that inter-chip communication achieves optimal configuration in terms of bandwidth, latency, and compatibility.

[0088] Example 2

[0089] Figure 5 This diagram illustrates a bidirectional data transmission hardware according to Embodiment 2 of the present invention, comprising two data transmission devices as described in any one of the embodiments of the present invention. The two data transmission devices include a first data transmission device 501 and a second data transmission device 502, wherein:

[0090] The on-chip network interface module 5011 in the first data transmission device 501 and the physical transmission layer module 5022 in the second data transmission device 502 are respectively used to connect to one chip (i.e. chip A), and the on-chip network interface module 5021 in the second data transmission device and the physical transmission layer module 5012 in the first data transmission device are respectively used to connect to another chip (i.e. chip B).

[0091] Example 3

[0092] Figure 6This is a schematic diagram of a system-on-a-chip provided in Embodiment 3 of the present invention. Figure 6 As shown, the system-on-a-chip includes multiple chips, and communication connections are established between each pair of chips through the bidirectional data transmission hardware 601 described in any one of the embodiments of the present invention.

[0093] It should be understood that the various forms of processes shown above can be used, with steps reordered, added, or deleted. For example, the steps described in this invention can be executed in parallel, sequentially, or in different orders, as long as the desired result of the technical solution of this invention can be achieved, and this is not limited herein.

[0094] The specific embodiments described above do not constitute a limitation on the scope of protection of this invention. Those skilled in the art should understand that various modifications, combinations, sub-combinations, and substitutions can be made according to design requirements and other factors. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of this invention should be included within the scope of protection of this invention.

Claims

1. A data transmission apparatus, characterized by comprising: The network-on-chip interface module, the interconnection control main module and the physical transmission layer module are connected, the network-on-chip interface module is used for connecting the first core grain, and the physical transmission layer module is used for connecting the second core grain, wherein: The network-on-chip interface module is used for receiving messages sent by the first core grain in real time in units of data sub-packets, and classifying each data sub-packet into a virtual channel matched with the network-on-chip interface module according to the message type in each cycle, wherein the network-on-chip interface module internally comprises a plurality of parallel virtual channels; The interconnection control main module is used for arbitrating a target virtual channel in the plurality of virtual channels of the network-on-chip interface module in each cycle, and encapsulating a message frame after obtaining a data sub-packet from the target virtual channel, and then sending the encapsulated message frame to the physical transmission layer module, wherein each message frame is transmitted independently; The physical transmission layer module is used for sending the real-time received message frame to the second core grain.

2. The data transmission device according to claim 1, characterized in that, The network-on-chip interface module comprises a message classification unit, a plurality of virtual channels and a plurality of state machine units, and one state machine unit is arranged on one virtual channel, wherein: The message classification unit is used for classifying the data sub-packet into a virtual channel matched with the message type according to the message type of the message to which the received data sub-packet belongs when receiving the data sub-packet in each cycle; The virtual channel is used for collecting and storing the data sub-packet of the matched message type to be sent to the second core grain; The state machine unit is used for updating the state of the next cycle and / or adding a data flag to the new data sub-packet when detecting that a new data sub-packet is added to the set virtual channel in a cycle according to the current cycle state and the data type of the new data sub-packet.

3. The data transmission apparatus according to claim 2, wherein The state machine unit is specifically used for: When the state of the current cycle is a header receiving state and the data type of the new data sub-packet is a header, determining that the state of the next cycle is a header receiving state, and adding a header flag to the new data sub-packet; When the state of the current cycle is a header receiving state and the data type of the new data sub-packet is data, determining that the state of the next cycle is a data receiving state, obtaining and recording the total number of data sub-packets associated with the new data sub-packet, and updating the current data sub-packet counter; wherein one state machine unit internally sets one matched data sub-packet counter; When the state of the current cycle is a data receiving state and the data type of the new data sub-packet is data, updating the current data sub-packet counter; when the updated data sub-packet counter does not reach the total number of data sub-packets, determining that the state of the next cycle is a data receiving state; when the updated data sub-packet counter reaches the total number of data sub-packets, determining that the state of the next cycle is a header receiving state, and adding a tail flag to the new data sub-packet.

4. The data transmission apparatus of claim 1, wherein The interconnection control main module specifically comprises a sending controller, wherein the sending controller is specifically used for: Arbitrating a target virtual channel from the plurality of virtual channels in each cycle, and sequentially obtaining a target data sub-packet from the target virtual channel; detecting whether a data payload length of the target data sub-packet is less than or equal to half of a maximum capacity of a single message frame; if yes, traversing detection is performed in other virtual channels according to a preset secondary arbitration strategy, and when there is an associated data sub-packet less than or equal to half of the maximum capacity of the single message frame in the other virtual channels, the target data sub-packet is merged and encapsulated with the associated data sub-packet to obtain a merged and encapsulated message frame, which is sent to the physical transmission layer module; otherwise, the target data sub-packet is encapsulated alone to obtain an encapsulated message frame, which is sent to the physical transmission layer module.

5. The data transmission apparatus according to claim 4, wherein The interconnection control main module further comprises a link controller, a flow controller and a message receiver, wherein: the link controller is configured to prohibit the on-chip network interface module from receiving the data sub-packet sent by the first core grain before establishing a link connection with the second core grain or when a link abnormality occurs in the established link, construct a handshake instruction and send the same to the physical transmission layer module to attempt to establish a communication link with the second core grain, and start allowing the on-chip network interface module to receive the data sub-packet sent by the first core grain after successfully establishing the communication link; the flow controller is configured to periodically send a flow notification instruction to the first core grain to inform the first core grain of a number of messages that can be received by the second core grain at present, and receive a flow control instruction sent by the second core grain and control whether the first core grain can send a message to the second core grain at present according to the flow control instruction; the message receiver is configured to receive each feedback data frame transmitted by the second core grain via the physical transmission layer module, write payload data in the feedback data frame into a receiving buffer in a matching virtual channel after analyzing the feedback data frame, monitor a non-empty state of each receiving buffer, and initiate a read operation to forward the payload data cached in the receiving buffer to the first core grain when the on-chip network interface module is in a ready state.

6. The data transmission apparatus according to claim 5, wherein The interconnection control main module further comprises a correctness controller configured to implement message error detection and message retransmission between the first core grain and the second core grain. The correctness controller specifically comprises a retransmission buffer unit, a message number generation unit, a CRC generation unit, a CRC inspection unit, a correctness message generation unit and a correctness message receiving unit, wherein: the retransmission buffer unit is configured to store a copy of frame data of a message that has been sent but for which no acknowledgement message has been received from the opposite end, and delete the corresponding copy after receiving the acknowledgement message or provide the copy data when a retransmission request is received; the message number generation unit is configured to generate and assign a globally unique sequence number to each message frame to be sent, and add the sequence number to a frame header; the CRC generation unit is configured to calculate a cyclic redundancy check code for each message frame to be sent, and attach the check code to a frame tail; the CRC inspection unit is configured to perform check code verification on a received message frame, and discard the frame and trigger an error handling process if the verification fails; the correctness message generation unit is configured to periodically or eventually trigger generation of a status message containing a confirmed sequence number range, or generate an acknowledgement or denial message for a specific sequence number. The correctness message receiving unit is configured to receive and parse a state message sent by the opposite end, update a local confirmation state according to a message content, and trigger a corresponding retransmission buffer management operation.

7. The data transmission device according to any one of claims 1 to 6, characterized in that, The message types received by the network-on-chip interface module include at least one of: I / O request, I / O response, interrupt request, interrupt response, host owner message (HOM) request, cache snoop message, dataless answer, direct memory access (DMA) request, and DMA response.

8. The data transmission device according to any one of claims 1 to 6, characterized in that The transmission modes of the physical transmission layer module include at least one of: electrical interconnection based on a serializer and / or deserializer (SerDes), advanced package interconnection based on a silicon interposer, package interconnection based on a re-distribution layer, embedded silicon bridge interconnection, optical interconnection, and wireless inter-chip interconnection, and specific protocol compatibility includes universal chip interconnection (Express UCIe), computing express link (CXL), bunch of wires (BoW), or peripheral component interconnect express (PCIe) industry standard.

9. Bidirectional data transfer hardware, characterized by The two data transmission devices include a first data transmission device and a second data transmission device, wherein: the network-on-chip interface module in the first data transmission device and the physical transmission layer module of the second data transmission device are respectively configured to be connected to one dielet, and the network-on-chip interface module in the second data transmission device and the physical transmission layer module in the first data transmission device are respectively configured to be connected to another dielet. Communication connections are established between the two dielets through the bidirectional data transmission hardware according to any one of claims 1-8.

10. A system on a chip comprising a plurality of corelets, characterized in that, ​

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