Assessment test and decision-making method for regression use of domestic plastic package layered device

Abstract

The invention discloses an assessment test and decision-making method for regression use of a domestic plastic package layered device based on layering characteristics, and relates to the field of reliability assessment and test of plastic package layered devices. The process comprises the following steps: obtaining a screened plastic package layered device, and determining an initial state and basic parameters of a to-be-tested device; extracting hierarchical feature data; classifying the devices based on the hierarchical features; designing a multi-stress assessment test, and carrying out the multi-stress assessment test on different layered devices to obtain reliability layered characteristic changes and test data of the devices; and judging the regression use qualification of the device. The hierarchical feature data is obtained through an acoustic scanning microscope and a computer vision algorithm based on OpenCV; the design method of the multi-stress assessment test is an iterative test framework comprising configurable environmental stress (such as high temperature and high humidity, temperature cycle) and synchronous electrical stress (such as dynamic / static signals); the regression use decision-making method is a comprehensive decision in combination with the category of the device, the electrical parameter state after examination, the layering proportion change trend and whether reliability improvement measures such as coating and the like are added or not; according to the method, the screened layered devices can be scientifically evaluated and recycled, and the accuracy and economical efficiency of screening decisions are remarkably improved.

Description

Technical Field

[0001] This invention relates to the field of reliability testing technology for plastic-encapsulated layered devices, and in particular to a regression testing and decision-making method for domestically produced plastic-encapsulated layered devices based on layered feature extraction. Background Technology

[0002] Plastic-encapsulated devices are devices that use molding compound to encapsulate the carrier supporting the integrated chip, the lead frame, the integrated chip, and the bonding wires, thereby providing protection for the integrated chip. Delamination in plastic-encapsulated devices refers to the separation of the interface between the molding compound and the internal structure such as the chip and lead frame. This defect can lead to moisture intrusion, thermal stress concentration, and in turn, trigger a chain reaction of electromigration, bonding failure, and ultimately cause the device to lose its function.

[0003] In recent years, against the backdrop of cost reduction and efficiency improvement, molded plastic (PVC) devices have occupied an important position in the electronics and information industry due to their cost advantages and integration characteristics. However, the delamination of domestically produced PVC devices has always been a core bottleneck restricting their reliability and use. Only a small number of domestically produced PVC devices can pass the N-level screening of GJB-7400. Even under the relatively lenient N1-level requirements of GJB-7400A, many domestically produced PVC devices still fail the screening, resulting in the direct discarding of a large number of domestically produced devices with intact electrical performance but delamination in many situations.

[0004] Currently, domestically produced plastic-encapsulated devices face the following challenges in reliability testing. On one hand, existing screening standards adopt a "zero-tolerance" strategy for delamination defects, directly classifying many devices with good electrical performance but slight delamination as defective, leading to resource waste and increased costs. On the other hand, while traditional delamination detection methods (such as ultrasonic scanning microscopy and X-ray inspection) can identify delamination defects, they cannot quantitatively assess the degradation trend of delamination and its potential impact on device reliability. Because the relationship between delamination defects and device electrical performance degradation is unclear, it is difficult to establish an accurate remaining lifetime prediction model, severely restricting the reuse efficiency of delamination devices. How to overcome existing technological bottlenecks and develop a strategy for reusing delamination devices that combines reliability and economy, based on the laws of delamination degradation, has become a key challenge for ensuring the long-term stable operation of electronic systems and promoting efficient resource utilization. Summary of the Invention

[0005] To address the shortcomings of the existing technologies, the purpose of this application is to provide a method for evaluation and decision-making regarding the re-use of domestically produced plastic-encapsulated layered devices based on layering characteristics. This method is designed for domestically produced plastic-encapsulated devices of the same model that have passed functional and parameter tests in the conventional screening process but have been rejected due to encapsulation layering discovered by ultrasonic scanning. The application proposes an evaluation test method and a re-use strategy to improve the accuracy and economy of screening decisions for plastic-encapsulated layered devices.

[0006] To achieve the above objectives, this application provides the following solutions, including: determination of the initial state and basic parameters of the device under test; non-destructive testing and classification of the preliminary layered features of the device; extraction and quantification of layered feature data based on OpenCV; design of multi-stress test for layered devices; grouping and implementation of multi-stress test; determination and decision-making regarding the eligibility of plastic-encapsulated layered devices for re-use.

[0007] Step 1: Determine the initial state and basic parameters of the device under test. Collect plastic-encapsulated devices of the same model that have passed the functional and parameter tests in the routine screening process but were screened out due to encapsulation delamination found by ultrasonic scanning as devices under test. Determine the basic parameters of the devices based on the device product manual and the screening results.

[0008] Step 2: Non-destructive testing and classification of initial layering features of the device. This includes non-destructive testing of layered acoustic images and layering feature division. The molded device under test is subjected to non-destructive testing using an acoustic scanning microscope to obtain layered acoustic images. Based on the layering location, the molded device under test is divided into layers of chip and molding compound, layers of substrate and molding compound, and layers of lead frame and molding compound.

[0009] Step 3: Hierarchical Feature Data Extraction and Quantification. This includes hierarchical feature data extraction and hierarchical feature quantification. Specifically, it includes:

[0010] The OpenCV-based feature extraction method is used to automatically process the image of each layered plastic-encapsulated device, extract the layer position and layer ratio to generate initial layer feature data, and calculate the total area of ​​the layered region and the total area of ​​the reference region.

[0011] Based on the aforementioned steps, the ratio of the two (i.e., the layering ratio = (total area of ​​the layered region / total area of ​​the reference region) × 100%) is used to finally obtain a layering ratio value that quantitatively characterizes the severity of device layering.

[0012] Optionally, the main steps of the OpenCV-based layered feature extraction method for plastic-encapsulated devices include:

[0013] The layered acoustic images of the layered plastic-encapsulated device under test, acquired by acoustic scanning microscopy, are used as the processing object. A denoising algorithm is employed to eliminate image noise while effectively preserving key edge information in the layered regions.

[0014] The color acoustic image is converted into a single-channel grayscale image, and the local contrast of the grayscale image is enhanced to improve the distinguishability of layered and non-layered areas.

[0015] After image preprocessing is completed, the process moves on to the identification and area calculation of key regions.

[0016] Optionally, this stage includes layered image thresholding and layered image contour detection:

[0017] Layered image thresholding uses an adaptive thresholding technique to redistribute the grayscale value of each pixel, making the grayscale value in the output image as uniform as possible; misjudged regions are improved by adjusting the grayscale segmentation value.

[0018] Layered image contour detection automatically identifies and extracts the contour boundaries representing the contact between all internal structures of the device (including the chip, substrate, and lead frame) and the molding compound. The total area of ​​the layered regions enclosed by these contours, as well as the total area of ​​the reference region, are calculated.

[0019] Step 4: Design of multi-stress testing for layered devices. This includes analysis of the influence mechanism of molding compound and delamination stress, design of stress conditions and cycles for multi-stress testing.

[0020] The analysis of the influence mechanism of molding compound and delamination stress considers that thermal stress and wet stress are the main stresses that cause delamination of molded devices. The analysis comprehensively analyzes the influence of these two types of stress and the combined effect of electrical stress.

[0021] The multi-stress test design for the layered device considers three types of stress: thermal, humid, and electrical. Its core method is to place the device under test in a comprehensive environment composed of preset constant high temperature, constant high humidity, and electrical stress simulating the actual working environment, so as to apply thermal stress, humid stress, and electrical stress to the device.

[0022] Optionally, depending on the specific test facilities and requirements, damp heat test items, electrical stress modes and test rounds can be selected, and the test conditions for different rounds can be fine-tuned based on the results of each round of multi-stress accelerated test, so as to achieve effective screening of layered devices.

[0023] Optionally, the damp heat assessment test can be selected from steady-state damp heat test (THB), high accelerated stress test (HAST), and temperature cycling test (TCT). THB and HAST are high temperature and high humidity tests to evaluate the combined effects of humidity and heat on the device. The THB test conditions can refer to GB / T 4937.5, which can be determined as 85℃ and 85%RH; the HAST test conditions can refer to GB / T4937.4, which can be determined as 130℃ and 85%RH; the TCT test evaluates the device's resistance to thermal stress fatigue by setting preset low temperature and high temperature thresholds and performing a predetermined number of cycles. The TCT conditions can refer to method 1010 in GJB-548.

[0024] During the test, electrical stress can be applied to the molded device under test simultaneously to simulate its load under actual working conditions.

[0025] Step 5: Assessment Test Grouping and Implementation. This includes test grouping, environment setup and test implementation, electrical characteristic testing, and stratified feature data extraction. Specifically:

[0026] Based on the intended application scenarios and reliability requirements of the molded devices under test, devices with delamination at the chip-molding interface were marked as Group 1, devices with delamination between the substrate and the molding compound were marked as Group 2, and devices with delamination between the lead frame and the molding compound were marked as Group 3. Meanwhile, normal undelamination devices were selected as the control group and marked as Group 0.

[0027] During the setup of the test environment, ensure that the heating source and humidification source do not come into direct contact with the device, and that the device remains in a sealed space throughout the entire test. Then, apply preset multi-stress test conditions and preset test times to groups 0-3 respectively; apply bias and electrical signals simultaneously to the plastic-encapsulated device under test, with the bias power supply and electrical signals introduced into the test chamber through the interface reserved in the test chamber;

[0028] Optionally, the device under test (DUT) is mounted on a test circuit board, which has multiple power-on positions and can provide a complete bias power supply and electrical signal application scheme for each DUT; the test circuit board should be designed with decoupling capacitors for power supply filtering to ensure power supply quality.

[0029] After the environment described above is set up, the assessment test will be carried out according to the preset conditions.

[0030] After the assessment test, electrical characteristic tests and delamination feature data extraction were performed. Based on the basic device parameters determined in step 1, the electrical characteristics of the molded delamination devices under test were tested one by one. Based on step 2, delamination data features of the chip-molding interface delamination devices, the substrate-molding interface delamination devices, the lead frame-molding interface delamination devices, and the control group devices were extracted respectively. Based on step 3, the delamination ratio of the devices in different groups was calculated to obtain the delamination ratio evolution data at different locations.

[0031] The propagation rate of the delamination ratio conforms to the classical dynamic model of crack propagation, and the crack growth rate da / dN has a power function relationship with the magnitude of the stress intensity factor K:

[0032]

[0033] In equation (1), C and m are material constants, and ΔK is the stress intensity factor amplitude. During the propagation of a delamination crack, the crack driving force gradually weakens. As the crack extends, the rate of increase of ΔK slows down, and the crack growth rate exhibits a nonlinear decreasing trend.

[0034] As can be seen from equation (1), the early expansion rate is relatively fast, and it gradually slows down in the later stage. Correspondingly, the device has a higher proportion of layered expansion in the early stage. As time goes by, the layered crack expansion of the device will gradually become more gradual and may eventually reach a stable layered state.

[0035] Based on the above pattern, after each round of testing, layered feature extraction and parameter testing are performed, and test and layered ratio degradation data are recorded. If the device test does not fail, the next round of multi-stress assessment test is continued until the layered ratio change trend basically stabilizes and the electrical characteristic test shows no failure. The test ends and the qualification for return to use is determined.

[0036] Step 6: Determining and deciding on the eligibility of plastic-encapsulated layered devices for reuse.

[0037] The electrical parameters determining reentry eligibility can be categorized into two aspects: functional failure and parameter deviation. Regardless of the group, molded layered devices that fail the electrical characteristic test are not eligible for reentry. If a molded layered device passes the electrical characteristic test after the assessment, its reentry eligibility is divided into two types based on the device's layering category:

[0038] After the evaluation test, the delamination evolution ratio of Group 1 and Group 2 layered devices tended to stabilize, and their reliability performance showed a high degree of consistency with that of Group 0 devices. This indicates that this type of delamination did not constitute a direct, short-distance channel for moisture or other harmful media to penetrate the active area of ​​the chip. Since the diffusion path of moisture is relatively tortuous and lengthy, the electrochemical corrosion of the chip surface, which is the main failure mechanism, is difficult to be effectively triggered in the short term. Therefore, they are determined to be qualified for direct return to use, meaning that in subsequent board-level applications, the devices can be considered to have the same reliability level as qualified devices that have passed conventional screening, without the need for additional protective measures or special treatment. Conversely, if any electrical parameter fails to meet the requirements, the device is deemed not qualified for return to use and should be discarded.

[0039] If the third layered device passes the electrical characteristic test after passing the assessment test, it is still considered to have qualified for conditional return to use only. This is because the layering provides a direct channel to the core of the chip for failure-driving factors such as moisture and stress, which is the primary risk source for early and accidental failure of the device. There are still significant and non-negligible reliability risks inside. External physical protection and risk assessment must be implemented to reduce the potential failure risk of the device to an acceptable range for engineering applications before it can be finally approved for use in actual applications.

[0040] Optionally, for chip-molded devices that have passed the evaluation test and are encapsulated at the molding compound interface, external physical protection and risk assessment can be carried out by implementing board-level conformal coating (three-proof coating). The specific steps are as follows:

[0041] STEP1 selects chips and molding compound layered devices that have passed all the aforementioned assessments and are eligible for conditional regression in a proportional manner, and solders them onto the target circuit board (PCB) according to their intended application design.

[0042] STEP 2: Based on the target circuit board's final application environment (e.g., operating temperature range, chemical environment, vibration level, etc.), select one or more conformal coatings with matching performance—such as acrylic, polyurethane, or silicone-based coatings. Ensure the coating meets relevant industry standards (e.g., IPC-CC-830) and perform necessary dilution and stirring.

[0043] STEP 3 employs standard processes such as spraying, dip coating, or brush coating to uniformly and completely coat the chip and molding compound layered devices and their surrounding PCB areas on a pre-soldered circuit board. The coating layer must meet the preset thickness standard, ensuring no defects such as missed coating, bubbles, or pinholes, and completely covering the surface of the device package and the roots of its pins.

[0044] STEP 4 places the coated circuit board in a suitable curing environment (such as a heated oven or room temperature) to allow it to fully cure according to the process curve recommended by the coating supplier until the coating layer forms a tough, dense and well-adhesive protective film.

[0045] STEP 5 conducts a comprehensive risk assessment of its eligibility for re-entry into service, including storage reliability and mission reliability assessments. Storage reliability focuses on verifying the long-term effectiveness of the protective measures in non-operating states, while mission reliability focuses on assessing its performance and failure probability under application profiles. This assessment can be conducted through a combination of testing and simulation to analyze the risks introduced by the layered device. If the risks are acceptable, the device is eligible for re-entry into service after the protective measures are in place; otherwise, re-entry into service will not be permitted if the risk assessment after the protective measures are inadequate.

[0046] According to the specific embodiments provided in this application, this application has the following technical effects:

[0047] This application provides a regression testing method and strategy for domestically produced plastic-encapsulated layered devices based on layered characteristics. It aims to address the problem that current screening criteria are too stringent, leading to the direct rejection of many electrically sound devices with encapsulation layering, resulting in resource waste and increased costs. First, the rejected layered devices are categorized based on the layering location. Reliability assessment and screening are conducted through accelerated testing under thermal, humidity, and electrical stresses closely resembling real-world application scenarios. Qualitative layering images are converted into quantitative layering ratio data, providing a precise basis for assessment and decision-making. Finally, based on the assessment results, this application provides differentiated decision-making strategies for devices with different layering types, including direct regression, regression after protective measures, or no regression. Compared with existing technologies, this not only improves the scientific rigor of screening decisions but also provides a practical solution for improving existing screening standards and promoting the reliable application of low-cost components, possessing significant economic value and industry promotion significance. Attached Figure Description

[0048] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0049] Figure 1 Implementation process for re-entry evaluation testing and decision-making methods for plastic-encapsulated layered devices

[0050] Figure 2 Hierarchical feature extraction steps based on OpenCV

[0051] Figure 3 Scheme for applying electrical stress to a single device

[0052] Figure 4 Schematic diagram of the multi-stress test environment setup

[0053] Figure 5 Multi-stress test procedure

[0054] Figure 6 The graph shows the expansion rate of the layer ratio of the chip and molding compound layered device as a function of the test time.

[0055] Figure 7 The effect of conformal coating on the expansion ratio of the layer (chip and molding compound layered device). Detailed Implementation

[0056] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. The described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those of ordinary skill in the art without creative effort are within the scope of protection of this application.

[0057] In an exemplary embodiment, such as Figure 1 As shown, this paper provides an implementation process for the evaluation and decision-making method of domestically produced plastic-encapsulated devices returning to use. In this embodiment, a certain type of SOP plastic-encapsulated domestic interface circuit is used as an example for illustration, including the following steps.

[0058] Step 1: Determine the initial state and basic parameters of the device under test.

[0059] Fifty-five identical devices from ten different production batches of the same model, which met electrical characteristics but failed ultrasonic scanning, were collected as controls. An additional ten qualified devices of the same model that passed the same screening process were also selected. These 65 devices are all CAN bus transmitters in a small outline package (SOP) with eight pins. The operating conditions of this device are:

[0060] Power supply voltage V CC 3.0V~3.6V; Input logic high level V IH : 2.0V~5.5V;

[0061] Input logic low level V IL 0V~0.8V; Operating temperature T A -55℃~125℃.

[0062] Power supply voltage V CC Input logic level V IH / V IL All parameters conform to its detailed specifications.

[0063] Based on the device datasheet and application requirements, its basic parameters are determined to be the bus dominant / recessive output voltage V. O(D) / V O Input current I at terminal D IH / I IL Output short-circuit current I OS and the power supply current I in dominant / recessive modes CC(D) / I CC(R) The test results of the parameters showed that they were qualified.

[0064] Step 2: Initial non-destructive testing of delamination characteristics was performed on all devices under test. A SAM302HD scanning acoustic microscope from PVA Tepla (Germany) was used to perform C-mode ultrasonic scanning on each of the 65 collected devices to obtain internal delamination acoustic images. For devices with misjudged or unclear delamination, waveform analysis or coloring tools were used to assist in identification using the "Move to position" function. Based on the degree of influence of delamination location on moisture intrusion path and stress concentration, the devices were divided into three categories: delamination devices at the chip-molding interface (labeled 1), delamination devices at the substrate-molding interface (labeled 2), and delamination devices at the lead frame-molding interface (labeled 3). Among these, 42 devices had delamination at the chip-molding interface (numbered A1#~A42#), 8 devices had delamination at the substrate-molding interface (numbered B1#~B8#), 5 devices had delamination at the lead frame-molding interface (numbered C1#~C5#), and 10 devices were without delamination (numbered 1#~10#).

[0065] Step 3: Using OpenCV-based feature extraction methods, the image of each layered device is automatically processed to accurately calculate its layering location (chip / substrate / lead frame) and layering ratio (%). The steps of the OpenCV-based layered feature extraction are as follows: Figure 2 As shown, it specifically includes:

[0066] Step 3.1 Preprocessing of layered images. This includes three steps: noise reduction, grayscale conversion, and contrast enhancement.

[0067] The cv2.fastNlMeansDenoising() function in the OpenCV library is used to remove noise while preserving important features in the image.

[0068] Call the cv2.cvtColor() function to convert the RGB image to a grayscale image to reduce data volume and complexity;

[0069] Calling the cv2.createCLAHE() function improves the local contrast of the image, avoiding the noise amplification and over-enhancement problems caused by traditional histogram equalization.

[0070] Step 3.2 Layered Image Thresholding. All found layered pixels are marked in red on the image. This step includes two processes: histogram equalization and adaptive histogram equalization. The specific steps are as follows:

[0071] Calling the cv2.equalizeHist() function redistributes the gray values ​​of each pixel by calculating the cumulative distribution function (CDF) of the image's gray-level histogram, so that the gray values ​​in the output image are distributed as evenly as possible.

[0072] The functions cv2.threshold(), cv2.getStructuringElement(), and cv2.morphologyEx() are called in sequence to divide the image into multiple small blocks. Then, histogram equalization is performed on each small block to make the grayscale image more refined and reduce the influence of artifacts.

[0073] The `np.zeros_like()` function is called to find all the layered pixels and calculate the total area of ​​each layer, making the layered regions more obvious. The layered pixels can be marked in red on the image. Misidentified areas can be improved by adjusting the grayscale segmentation values.

[0074] Step 3.3 Layered Image Contour Detection. The cv2.findContours() function is called to perform contour detection on the layered image, identify and segment the structural contours of the chip, substrate, and lead frame in contact with the molding compound inside the device, and obtain the layered area.

[0075] Step 3.4 Quantification of Layered Image Feature Data. The acoustic image set acquired by ultrasonic scanning is compressed into a dataset. The degree of layering of the device is intuitively obtained by dividing the layered area by the total area. Taking device #2 as an example, the final calculated layering ratio is 5.87%, and the calculated layering range between the chip and the molding compound is 4.01% to 8.53%. The average layering ratio is shown in Table 1.

[0076] Table 1. Statistics on the delamination characteristics of plastic-encapsulated delaminated devices

[0077]

[0078] Step 4: Design of multi-stress test conditions.

[0079] Step 4.1 Analysis based on the influence mechanism of molding compound and delamination stress

[0080] Thermal stress caused by temperature is one of the main factors affecting the delamination of molded devices. The molding compound for this device is epoxy resin, whose coefficient of thermal expansion (CTE) is typically around 25 × 10⁻⁶. -6 The current chips are mainly composed of silicon, with a CTE of approximately 3.5 × 10⁻⁶ K. -6 The CTE of gold, commonly used in bonding wires, is approximately 14.2 × 10⁻⁶ K; -6 / K; The molding compound has a much larger CTE than the silicon wafer and metal bonding wire. There is internal stress at the interface of different materials. Excessive internal stress will lead to delamination.

[0081] Furthermore, moisture stress caused by moisture intrusion is also one of the main factors leading to encapsulation delamination in molded devices. Molding materials are non-hermetic materials; according to Fick's law, moisture diffusion within the molding compound can be described as follows:

[0082]

[0083] Where C is the moisture concentration, D is the diffusion coefficient, t is time, and x, y, z are Cartesian coordinates. The diffusion coefficient D is a function of temperature and follows the Arrhenius relation:

[0084]

[0085] Where E d D is the activation energy of the diffusion coefficient, D0 is the pre-exponential factor, K is the Boltzmann constant, and T is the absolute temperature. As the temperature increases, D will increase exponentially.

[0086] Based on the analysis of the influence mechanism of molding compound and delamination stress, thermal stress and wet stress are the main stresses that cause delamination of molded devices. Usually, these two types of stresses occur simultaneously, resulting in a combined effect. Therefore, the test design should focus on these two types of stresses.

[0087] This embodiment uses the THB or HAST experiment as an example. According to the Hallberg-Peck model, the acceleration factor AF is expressed as:

[0088]

[0089] In the formula, RH tj RH refers to the relative humidity of the device in the operating environment. uj To accelerate the process of adjusting the relative humidity of the device in the environment, E a The activation energy is typically taken in the range of 0.65 eV to 0.90 eV, and k is the Boltzmann constant, which is taken as 8.617 × 10⁻⁶. -5 eV / K, T tj T represents the absolute temperature of the device under operating conditions. uj U represents the absolute temperature of the device under accelerated conditions, where U is the bias voltage applied under accelerated conditions. n This is the nominal value of the device bias voltage.

[0090] The THB test conditions are 85℃ and 85%RH, and the HAST test conditions are 130℃ and 85%RH. Under the same power-on conditions, according to the Hallberg-Peck model (4), the acceleration factor AF of HAST relative to THB is approximately 10.46, meaning that 1 hour of HAST testing is equivalent to 10.458 hours of THB testing. The acceleration factor of the THB test is lower, while the acceleration factor of the HAST test is higher.

[0091] Step 4.2 Accelerated Assessment Test Design. Based on the case study of devices under test undergoing stratified screening without any further screening tests, this embodiment initially designs four rounds of assessment tests to expedite the understanding of the reliability level of the devices and expose early failure defects. Specifically:

[0092] The first round of testing involved HAST with increased stress, employing a dynamic power-on method to accelerate the exposure of early failure defects. During the test, dynamic electrical stress (1kHz, 50% duty cycle square wave) was applied simultaneously, causing the device to continuously switch between two typical operating modes: dominant load mode and stealth load mode. The electrical stress application scheme for a single device was as follows: Figure 3 As shown. Temperature and humidity conditions were 130℃, 85%RH, for 96 hours;

[0093] The second round of experiments was designed as a THB static bias static signal test, with temperature and humidity conditions of 85℃, 85%RH, and 400 hours. The power-on conditions were reduced to a static signal, while the bias conditions and test time remained unchanged. A portion of the devices were randomly selected for conformal coating.

[0094] The third round of testing kept the THB test conditions and test time unchanged, and observed the device delamination and failure.

[0095] The fourth round of THB testing remained at 85℃ and 85% RH for 240 hours. For 50% of the samples, the heating and humidification process was stopped before powering on, and the results were used to assess the impact of the power-on sequence on reliability. Specific stress conditions are shown in Table 2.

[0096] Table 2 Design of Multi-Stress Test Conditions

[0097]

[0098] Step 5: Multi-stress assessment tests are conducted in groups. The test environment is set up as follows: Figure 4 As shown, the test environment was set up for the assessment test. After the assessment test, electrical characteristic tests and layered feature data extraction were performed. The overall process of the assessment test is as follows: Figure 5 As shown.

[0099] Step 5.1 First round of testing

[0100] A total of 65 devices were used, and layered feature data extraction and electrical parameter testing were performed according to the aforementioned steps. The results are shown in Table 3.

[0101] Table 3. Changes in stratification characteristics and distribution of failed devices after the first round of testing.

[0102]

[0103]

[0104] Of the 65 devices tested in the HAST test, 14 failed. One group of devices failed 11 after the first round of testing, exhibiting the highest variation in the layering expansion rate, ranging from 8.41% to 11.73%, with an average expansion rate of 4.67%. The evaluation indicates that the failure rate of the layered devices in this SOP package was too high in the early stages, making them unsuitable for direct reuse. After removing the early-failure devices, a second round of testing was conducted.

[0105] Step 5.2 Second round of testing

[0106] 51 samples were used. The electrical stress mode was static electrical stress (constant high / low level), which kept the device operating in either the dominant or hidden load mode. In the THB test, 50% of the devices were subjected to a low-level signal (L) to keep them in the hidden load mode; 50% of the devices were subjected to a high-level signal (H) to keep them in the dominant load mode.

[0107] In addition, 9 devices were selected for protective coating treatment. Specifically, the distribution is as follows: 4 devices with chip and molding compound layered (numbered A3#, A10#, A19#, A39#), 2 devices with substrate and molding compound layered (numbered B2#, B5#), 1 device with lead frame and molding compound layered (C1#), and 2 unlayered devices (1#, 7#).

[0108] After setting the conditions, parameters, and running time, the experiment was conducted. Following the experiment, electrical parameter tests and stratification characteristic data extraction were performed on the device under test. The stratification characteristics and failure distribution are shown in Table 4.

[0109] Table 4. Changes in stratification characteristics and distribution of failed devices after the second round of testing.

[0110]

[0111]

[0112] Five devices failed in the second round of THB testing, and all of them were from the same group. However, the expansion rate of the stratification ratio of this group was smaller than that of the previous round, and the stratification ratio was more concentrated in the range of 9.32% to 13.76%, with an average change rate of 2.02%. It can be seen that as the stratification ratio expands, the device failure rate decreases significantly.

[0113] Step 5.3 Third round of testing.

[0114] The THB test conditions remained at 85℃ and 85% RH, with a duration of 400 hours. Forty-six unfailed samples were used. All electrical conditions were uniformly applied under static electrical stress (constant low level).

[0115] After setting the conditions, parameters, and running time, the experiment was conducted. Following the experiment, electrical parameter tests and stratification characteristic data extraction were performed on the device under test. The failure distribution and stratification ratio change rate in the third round of experiments are shown in Table 5.

[0116] Table 5. Changes in stratification characteristics and distribution of failed devices after the third round of testing.

[0117]

[0118] According to the test results, the stratification rate was concentrated in the range of 10% to 14%, and the number of failed devices was generally much smaller than the number of non-failed devices. The stratification rate expansion rate and device failure probability decreased significantly.

[0119] Step 5.4 Fourth round of testing.

[0120] In this embodiment, the test selected for this round of testing is still the THB test, the test conditions remain unchanged, and the duration is 240 hours. 22 devices were used that were immediately powered off after the high temperature and humidity period ended.

[0121] After setting the conditions, parameters, and running time, the experiment was conducted. After the experiment, electrical parameter tests and stratification characteristic data extraction were performed on the device under test. The failure distribution and stratification ratio change rate in the fourth round of experiments are shown in Table 6.

[0122] Table 6. Changes in stratification characteristics and distribution of failed devices after the fourth round of testing.

[0123]

[0124] According to the test results, in the fourth round of testing, the delamination ratio of the chip and molding compound in the delamination devices fell within the range of 11% to 15%, and the number of failed devices was extremely low, indicating that as the delamination ratio increased, the device failure probability decreased to a low level. Furthermore, the results show that improper "post-power-down" operations can cause additional instantaneous failures due to condensation, thus interfering with the actual results.

[0125] After four rounds of testing, the layering ratio expansion rate of the chip and molding compound layered device changed with the test time as follows: Figure 6 As shown, the experimental results are consistent with formula (1), indicating that the stratification expansion rate decreases exponentially over time and basically stabilizes.

[0126] Step 6: Make a decision on eligibility for re-application based on the results of the assessment test.

[0127] Step 6.1: Decision on substrate layering and lead frame layering devices.

[0128] Throughout the rigorous evaluation process, the lower-risk stratified devices in groups 2 and 3 exhibited cumulative failure rates comparable to the unstratified control group, demonstrating good reliability. Therefore, the reliability of the 11 lower-risk devices after the evaluation tests has been fully verified, and they are deemed qualified for direct return to use without any additional processing.

[0129] Step 6.2: Chip and molding compound layered device decision.

[0130] Of the high-risk "chip layering" devices, 22 passed the evaluation tests, but continued to fail in each round of testing, indicating that there are still significant reliability risks within them. Therefore, this group of devices that passed the evaluation tests was conditionally qualified for return to service.

[0131] In this embodiment, the risk assessment method employed was to randomly select a portion of devices for conformal coating before the start of the second round of testing. Through continuous monitoring and observation of the coated devices in subsequent tests, the seven delaminated devices that underwent conformal coating before the second round of testing did not fail in the subsequent three rounds of testing. The impact of conformal coating on the delamination ratio expansion rate is as follows: Figure 7 As shown, conformal coating can effectively suppress delamination and prevent device failure, which indicates that its reliability is improved. In this case, it is considered to have passed the reliability assessment.

[0132] For the remaining devices that have not undergone conformal coating and have passed the evaluation, the next step of the preventive measures and risk assessment process must be carried out. In subsequent board-level applications, conformal coating (triple protection coating) should be applied according to standard processes to form a dense physical protective film to prevent moisture intrusion, thereby inhibiting the most important failure mechanism—electrochemical corrosion of the chip surface. Risk assessments should then be conducted according to the aforementioned storage reliability and mission reliability requirements.

[0133] Beneficial effects:

[0134] 1) This application addresses the problem that existing screening test standards are too stringent and cannot effectively evaluate the reliability of plastic-encapsulated layered devices under real service conditions. By designing an iterative multi-stress assessment test framework, it proposes a differentiated SOP plastic-encapsulated layered device return-to-use strategy. Under the premise of ensuring system safety, it maximizes the utilization of the value of this type of device and provides support for solving the problems of resource waste and increased costs caused by existing screening standards.

[0135] 2) This application establishes a multi-stress testing procedure, enabling reliability assessment of SOP-encapsulated layered devices. This framework allows users to flexibly select tests (HAST / THB / temperature cycling), electrical stress modes, and test cycles according to specific needs. Through optimized testing, early failure screening can be efficiently completed in a much shorter time than standard requirements, solving the problems of long cycles and high costs associated with traditional fixed testing procedures. It provides the industry with a scientific assessment approach that combines accuracy and economy.

[0136] 3) By constructing an automated hierarchical feature extraction method based on OpenCV, qualitative acoustic scanning images are transformed into quantitative hierarchical ratio data, providing accurate hierarchical ratio and other feature quantities with objective quantitative basis for regression application strategies. This provides high-precision data input for failure physics modeling and improving more refined screening criteria, solving the defects of traditional manual interpretation, which is highly subjective and inefficient.

[0137] 4) The method mentioned in this application has a certain degree of universality. The established assessment framework, test conditions, and decision-making model are not only applicable to SOP packaging, but can also be applied to other types of plastic-encapsulated devices (such as QFP, BGA, etc.) with appropriate adjustments. It can realize the reliability assessment and regression usage decision of different types of plastic-encapsulated layered devices in different application scenarios.

[0138] The data processing and image analysis involved in the various embodiments provided in this application can be implemented based on various computing software or programming languages, such as, but not limited to, executing image processing algorithms in a programming environment that supports the OpenCV function library. The hardware devices and testing instruments involved in the various embodiments provided in this application may include, but are not limited to: scanning acoustic microscopes (SAM) for acquiring layered acoustic images, such as the SAM 302HD from PVA Tepla, Germany; automated test equipment (ATE) for comprehensive electrical parameter testing; regulated DC power supplies and signal sources for providing stable power and signals; high accelerated stress test chambers (HAST test chambers), steady-state damp heat test chambers (THB test chambers), or high and low temperature test chambers for building multi-stress environments; and test circuit boards specially designed for carrying and loading the device under test, integrating high-temperature resistant components and test sockets.

[0139] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0140] This document uses specific examples (such as 64 SOP devices of a specific model, layered feature extraction, and four rounds of specific accelerated testing) to illustrate the principles and implementation methods of this application. The descriptions of the above embodiments are only for the purpose of helping to understand the regression testing and decision-making method and its core ideas. Furthermore, for those skilled in the art, based on the ideas of this application, there will be changes in the specific implementation methods (e.g., the selection of test items, the adjustment of testing rounds, and the applicability of different package types of devices) and the scope of application. Therefore, the content of this specification should not be construed as a limitation of this application.

Claims

1. A method for evaluating and deciding the use of a domestic plastic package delaminated device, characterized in that, The examination test and decision method for returning the domestic plastic package layered device to use, comprising: determining the initial state and basic parameters of the device to be tested; the device to be tested is a domestic plastic package device that is determined to be unqualified in the conventional screening process due to package layering, and the device basic parameters are determined according to the device product manual and the screening situation; extracting and classifying the layering characteristics of the device; obtaining a layering acoustic image by using an acoustic scanning microscope, and extracting the layering position and layering proportion based on a computer vision algorithm; according to the layering position, the plastic package device is divided into a chip and plastic material interface layered device, a substrate and plastic material layered device, and a lead frame and plastic material layered device; designing a multi-stress examination test, and applying an acceleration examination test including environmental stress and synchronous electrical stress to the layered device; determining the final return-to-use qualification of the device according to the test results of each electrical parameter and the change trend of the layering proportion after the acceleration examination test; wherein the other substrate and plastic material layered device and the lead frame and plastic material layered device that pass the examination and have a change trend to stability have direct return-to-use qualification, and the chip and plastic material layered device that pass the examination and have a change trend to stability has return-to-use qualification after additional coating treatment, and the risk assessment is within an acceptable range.

2. The device layering characteristic extraction and classification of claim 1, wherein: non-destructive testing of the plastic package device to be tested is performed by using an acoustic scanning microscope to obtain a layering acoustic image; the layering acoustic image is preprocessed, threshold segmented, contour detected and feature data quantified to identify and calculate the total area of the reference region where the internal structure of the device contacts the plastic material; based on the total area of the layering region and the total area of the reference region, the layering proportion of the plastic package device is calculated, and the layering position and layering proportion are used as the basis for classification.

3. The layered features extraction and classification of plastic devices according to claim 2, characterized in that, The threshold segmentation and contour detection of the preprocessed image are implemented by using an OpenCV-based computer vision algorithm, specifically including: image preprocessing, including noise reduction, grayscale and contrast enhancement; the threshold segmentation algorithm uses histogram equalization and adaptive histogram equalization to obtain layering pixel points and calculate layering area; the contour detection algorithm identifies and extracts the contour boundary representing the contact between the internal structure of the device and the plastic material; the threshold segmentation calculates the total area of the layering region, and the contour detection calculates the ratio of the total area of the internal structure of the device contacting the plastic material to obtain the layering proportion.

4. The regression usage multi-stress screening test design for a plastic package delaminated device of claim 1, wherein, The test condition design based on the multi-stress acceleration examination environmental stress influence analysis is performed by applying a preset test condition to the device for examination, including: determining the actual test condition based on the environmental stress influence analysis, and at least one of a high temperature and high humidity examination test and a temperature cycle examination test can be selected; synchronously applying an electrical stress condition during the execution of the environmental stress condition, considering at least one of a dynamic electrical stress mode and a static electrical stress mode; wherein the dynamic electrical stress mode simulates the switching of the device working mode, and the static electrical stress mode simulates the steady state working of the device.

5. The method of claim 4, wherein the method further comprises: The multi-stress accelerated evaluation step specifically includes: Setting test rounds: according to the evaluation target, one or more test rounds are set; Performing single-round evaluation: in each round, the preset environmental stress condition and the synchronous electrical stress condition are applied; Performing intermediate evaluation: after the end of each round, the electrical parameter test and hierarchical feature extraction are performed on the test device, and only the device that passes the current round evaluation is used as the test object for the next round evaluation; Performing evaluation test termination evaluation: after the end of the multi-round test, the hierarchical proportion change trend is basically stable and the electrical characteristic test has no failure, the test is ended and the regression use qualification is determined. The determination idea of the test conditions applied in the multi-stress evaluation test step needs to be based on the regression use evaluation method of the certain type of plastic package hierarchical device according to claim 4 or 5, characterized by stress scene consideration: comprehensive economy, time cost and equipment restriction; temperature stress and electrical stress configuration: preliminary calculation according to device structure, failure mode and failure mechanism formula, dynamic optimization and adjustment of related parameters of test setting.

6. The plastic-bumped delayered device return-to-use assessment decision of claim 1, wherein: In the regression use decision step, for the additional coating treatment of the chip and plastic package hierarchical device, specifically includes: The chip and plastic package hierarchical device that passes the evaluation is soldered on the target circuit board; Uniform and complete coating is performed on the chip and plastic package hierarchical device and its surrounding area by using standard process; The circuit board after coating is fully solidified, and risk assessment of storage reliability and task reliability can be performed to confirm that it meets the preset reliability requirements.

7. The regression usage qualification strategy for a plastic-bumped delayered device of claim 1, wherein, For the decision path of the substrate and plastic package hierarchical device and the lead frame and plastic package hierarchical device with low failure rate: if the hierarchical device passes the multi-stress accelerated evaluation step, the electrical parameter test result is qualified, and it is directly determined that it has direct regression use qualification, without any additional treatment measures.

8. An evaluation system for implementing the evaluation method of the return-to-use of the plastic package delaminated device according to claims 1 to 6, characterized in that, The evaluation system includes: One or more configurable test circuit boards, which have the following characteristics: Complete power-on scheme needs to provide independent bias power supply, signal power supply and connection path of on-board load resistance for each plastic package device to be tested, and has the ability to simulate the actual load working state of the device; Power supply quality guarantee: integrated on-board decoupling capacitor and filtered power supply; High density and isolation design: multiple device power-on positions are provided, and power supply parallel isolation design is adopted, and fault isolation must be provided between each test position.

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