Memory device and semiconductor device

Abstract

The invention discloses a memory device and a semiconductor device. The memory device includes a logic die configured to output a control signal based on temperature data; and a first core die. The first core die includes: a first plurality of memory cells configured to store data; a first temperature sensor configured to measure temperatures of the first plurality of memory cells and output first temperature data based on the temperatures of the first plurality of memory cells; and a first heating circuit configured to generate heat based on the control signal and the first temperature data.

Description

[0001] This application claims priority and benefit to Korean Patent Application No. 10-2024-0113121, filed on August 22, 2024, with the Korean Intellectual Property Office, the entire contents of which are incorporated herein by reference. Technical Field

[0002] This application relates to memory devices and semiconductor devices. Background Technology

[0003] Stacked memories, such as high-bandwidth memory (HBM), with multiple dies stacked on a substrate, have been commercialized. Therefore, techniques for controlling the temperature of each of the multiple dies have been investigated.

[0004] Each of the multiple wafers may have a different temperature, for example, depending on the degree of operation. However, when the temperature of each wafer is different, properties such as band gap can be altered, which can lead to stress problems due to the temperature difference between the wafers. Summary of the Invention

[0005] This disclosure relates to a memory device capable of heating a low-temperature die among a plurality of dies included in a stacked memory and increasing the temperature of the die.

[0006] In some embodiments, a memory device includes: a logic die configured to output a control signal based on temperature data; and a first core die including a first plurality of memory cells configured to store data, a first temperature sensor configured to measure the temperature of the first plurality of memory cells and output first temperature data based on the temperature of the first plurality of memory cells, and a first heating circuit configured to generate heat based on the control signal and the first temperature data.

[0007] In some embodiments, a memory device includes: a plurality of core dies stacked in a first direction and configured to provide temperature data, the plurality of core dies including a first core die, a second core die, and a third core die; and a logic die configured to output a control signal based on the temperature data, wherein the plurality of core dies are configured to provide temperature data through a first through-silicon via (TSV) extending through the plurality of core dies in the first direction, and wherein a second core die includes a heating circuit configured to heat the second core die based on first temperature data of the first core die, second temperature data of the second core die, third temperature data of the third core die, and the control signal.

[0008] In some embodiments, a semiconductor device includes: a host device; and a memory device including a logic die configured to output a control signal based on first temperature data and second temperature data, and a core die stacked on the logic die in a first direction, wherein the core die includes a first memory region and a second memory region, the first memory region including a plurality of first memory cells, a first temperature sensor configured to measure the temperature of the plurality of first memory cells and output first temperature data based on the temperature of the plurality of first memory cells, and a first heating circuit configured to heat the plurality of first memory cells based on the control signal and the first temperature data, the first heating circuit being disposed adjacent to the host device, the second memory region including a plurality of second memory cells, a second temperature sensor configured to measure the temperature of the plurality of second memory cells and output second temperature data based on the temperature of the plurality of second memory cells, and a second heating circuit configured to heat the plurality of second memory cells based on the control signal and the second temperature data, the second heating circuit being disposed opposite to the host device relative to the first memory region, and wherein the control signal is configured to turn off the first heating circuit and turn on the second heating circuit. Attached Figure Description

[0009] Figure 1 This is a schematic block diagram of an example of a semiconductor device.

[0010] Figure 2 This is a schematic block diagram of an example memory system.

[0011] Figure 3 This is a diagram illustrating an example of a semiconductor device.

[0012] Figure 4 This is a diagram illustrating an example of a semiconductor device.

[0013] Figure 5 This is an example diagram of the core die.

[0014] Figure 6 This is a circuit diagram of an example heating circuit.

[0015] Figure 7 This is a circuit diagram of an example heating circuit.

[0016] Figure 8 This is a diagram illustrating an example of how a multiplexer operates.

[0017] Figure 9 This is a flowchart illustrating an example of a method for controlling the temperature of the core die.

[0018] Figure 10 This is a flowchart illustrating an example of a method for controlling the temperature of the core die.

[0019] Figure 11 This is a flowchart illustrating an example of a method for controlling the temperature of the core die.

[0020] Figure 12 This is a flowchart illustrating an example of a method for controlling the temperature of the core die.

[0021] Figure 13 This is a flowchart illustrating an example of a method for controlling the temperature of the core die.

[0022] Figure 14 This is an example diagram of the core die.

[0023] Figure 15 This is an example diagram of the core die.

[0024] Figure 16 This is a perspective view showing an example of a semiconductor device.

[0025] Figure 17 This is a perspective view showing an example of a semiconductor device.

[0026] Figure 18 This is a schematic block diagram of an example computing device. Detailed Implementation

[0027] Referring to the accompanying drawings, the disclosed embodiments will be described in detail below, enabling those skilled in the art to readily implement this disclosure. However, the disclosure can be implemented in many different forms and is not limited to the embodiments described herein.

[0028] Furthermore, to clearly explain this disclosure in the accompanying drawings, parts irrelevant to the description have been omitted, and similar parts are given similar reference numerals throughout the specification. In the flowcharts described with reference to the accompanying drawings, the order of operations may be changed, several operations may be combined, specific operations may be divided, and specific operations may not be performed.

[0029] Furthermore, unless explicitly stated as “a” or “single,” a singular description may be interpreted as either singular or plural. Terms including ordinal numbers (such as first, second, etc.) may be used to describe various components, but components are not limited by these terms. These terms may be used for the purpose of distinguishing one component from another.

[0030] The present disclosure will be described in more detail below by way of examples. These examples are intended to illustrate the present disclosure only, and the scope of protection of the rights of the present disclosure is not limited by these examples.

[0031] Figure 1 This is a schematic block diagram of an example of a semiconductor device.

[0032] Reference Figure 1The semiconductor device 1 can be implemented as a personal computer (PC), a data server, a laptop computer, or a portable device. The portable device can be implemented as a mobile phone, smartphone, tablet PC, wearable device, personal digital assistant (PDA), enterprise digital assistant (EDA), digital camera, digital camcorder, portable multimedia player (PMP), personal navigation device or portable navigation device (PND), handheld game console, or e-reader. Furthermore, the semiconductor device 1 can be implemented as a system-on-a-chip (SoC).

[0033] Semiconductor device 1 may include host device 10 and storage device 20. Host device 10 may communicate with storage device 20 through various interfaces. Host device 10 may request data processing operations (e.g., data read operations, data programming (write) operations, data erasure operations, etc.) from storage device 20. For example, host device 10 may be a central processing unit (CPU), graphics processing unit (GPU), microprocessor, or application processor (AP).

[0034] The host device 10 may include a host controller 110 and a host memory 120. The host memory 120 may be used as a buffer memory for temporarily storing data to be sent to or from the storage device 20.

[0035] Storage device 20 may include storage controller 210 and non-volatile memory (NVM) 220. Storage device 20 may include storage media for storing data in response to a request from host device 10. For example, storage device 20 may be implemented in various types, such as solid-state drives (SSDs), embedded multimedia cards (eMMCs), universal flash memory (UFS), compact flash memory (CF), secure digital (SDs), micro SDs, mini SDs, extreme digital (xDs), or memory sticks.

[0036] When storage device 20 is an SSD, it can be a device compliant with the Non-Volatile Memory Faster (NVMe) standard. When storage device 20 is embedded memory or external memory, it can be a device compliant with the UFS or eMMC standard. Host device 10 and storage device 20 can generate and send packets according to their respective standard protocols.

[0037] When the non-volatile memory 220 of storage device 20 includes flash memory, the flash memory may include a 2D NAND memory array or a 3D NAND memory array. As another example, storage device 20 may include various other types of non-volatile memory. For example, various other types of memory (such as magnetoresistive random access memory (MRAM), spin-transfer torque random access memory (STT-RAM), conductive bridged random access memory (CBRAM), ferroelectric random access memory (FeRAM), phase-change random access memory (PRAM), and resistive random access memory (RRAM)) may be applied to storage device 20.

[0038] In some implementations, the host controller 110 and the host memory 120 may be implemented as separate semiconductor chips. Alternatively, in some implementations, the host controller 110 and the host memory 120 may be integrated into the same semiconductor chip. For example, the host controller 110 may be any one of multiple modules disposed in the AP, and the AP may be implemented as a SoC. Furthermore, the host memory 120 may be embedded memory disposed in the AP, non-volatile memory disposed outside the AP, or a memory module.

[0039] The host controller 110 can manage operations that store data in the buffer area (e.g., programming data) in the non-volatile memory 220 or store data in the non-volatile memory 220 (e.g., read data) in the buffer area.

[0040] The storage controller 210 may include a host interface (I / F) 211, a memory interface 212, and a CPU 213. In addition, the storage controller 210 may also include a flash translation layer (FTL) 214, a packet manager 215, a buffer memory 216, an error correction code (ECC) engine 217, and an Advanced Encryption Standard (AES) engine 218.

[0041] The storage controller 210 may also include working memory, into which the FTL 214 is loaded, and where data programming and reading operations on the non-volatile memory 220 may be controlled by the CPU 213 executing the FTL 214.

[0042] Host interface 211 can send packets to host device 10 and receive packets from host device 10. Packets sent from host device 10 to host interface 211 may include commands or data to be programmed in non-volatile memory 220, and packets sent from host interface 211 to host device 10 may include responses to commands or data read from non-volatile memory 220.

[0043] The memory interface 212 can send data to be programmed in the non-volatile memory 220 to the non-volatile memory 220, or can receive data read from the non-volatile memory 220. The memory interface 212 can be implemented to conform to standard protocols (such as toggle or Open NAND Flash Interface (ONFI)).

[0044] The FTL214 can perform several functions, such as address mapping, wear leveling, and garbage collection. Address mapping is the process of translating logical addresses received from the host into physical addresses used to actually store data in the non-volatile memory 220. Wear leveling is a technique used to prevent excessive degradation of specific blocks by using blocks in the non-volatile memory 220 evenly, and can be implemented through firmware techniques that balance the erase counts of physical blocks. Garbage collection is a technique used to ensure available capacity in the non-volatile memory 220 by copying valid data from existing blocks to new blocks and then erasing the existing blocks.

[0045] The packet manager 215 can generate packets according to the protocol of the interface negotiated with the host device 10, or parse various types of information from packets received from the host device 10. Furthermore, the buffer memory 216 can temporarily store data to be programmed in the non-volatile memory 220 or data to be read from the non-volatile memory 220. The buffer memory 216 can be a component located within the storage controller 210, but it can also be located externally to the storage controller 210.

[0046] ECC engine 217 performs error detection and correction functions on read data to be read from non-volatile memory 220. More specifically, ECC engine 217 generates parity bits for the write data to be written to non-volatile memory 220, and the generated parity bits are stored in non-volatile memory 220 along with the write data. When reading data from non-volatile memory 220, ECC engine 217 can correct errors in the read data by using the parity bits read from non-volatile memory 220 along with the read data, and outputs the error-corrected read data.

[0047] The AES engine 218 can perform at least one of encryption and decryption operations on the data input to the storage controller 210 by using a symmetric key algorithm.

[0048] Figure 2 This is a schematic block diagram of an example memory system.

[0049] Reference Figure 2 The memory system 30 may include a memory controller 310 and a memory device 320.

[0050] The memory controller 310 can be configured to access the memory device 320 in response to a request from the host device. The memory controller 310 can be configured to provide an interface between the memory device 320 and the host device. Furthermore, the memory controller 310 can be configured to drive firmware for controlling the memory device 320.

[0051] The memory controller 310 can control the operation of the memory device 320. Specifically, the memory controller 310 can provide at least one of the following along the input / output lines connected to the memory device 320: address ADDR, command CMD, data DATA, and control signal CTRL.

[0052] The memory controller 310 can write data to, erase data from, or read data from the memory device 320 using at least one of the address ADDR, command CMD, and control signal CTRL. The control signal CTRL may include chip enable CE, write enable WE, read enable RE, etc.

[0053] The memory device 320 can be operated under the control of the memory controller 310. The memory device 320 can be a volatile memory (such as static random access memory (SRAM) and dynamic random access memory (DRAM)) or a non-volatile memory device (such as NAND flash memory, vertical NAND (VNAND) flash memory, bonded vertical NAND (BVNAND) flash memory, NOR flash memory, resistive random access memory (RRAM), phase change RAM (PRAM), magnetoresistive RAM (MRAM), ferroelectric RAM (FRAM), spin-transfer torque RAM (STT-RAM), conductive bridged RAM (CBRAM), etc.).

[0054] Figure 3 This is a diagram illustrating an example of a semiconductor device.

[0055] Reference Figure 3 The semiconductor device 40 may include a host device 41, a memory device 42, middleware 43, and a printed circuit board (PCB) 44. Here, the host device 41 may be connected to... Figure 1 The host device 10 shown is essentially the same in construction. Furthermore, the memory device 42 can be connected to... Figure 1 The storage device 20 shown in the figure or Figure 2 The memory device 320 shown is substantially the same in construction, or may be included in Figure 1 The storage device 20 shown in the figure or Figure 2 The configuration of the memory device 320 shown in the figure.

[0056] The memory device 42 may include four core dies CD1 to CD4 and a logic die LD stacked in a first direction Z. A plurality of bumps MB may be formed between the stacked core dies CD1 to CD4 and the logic die LD, and through-silicon vias (TSVs) penetrating the core dies CD1 to CD3 may be formed between the stacked bumps MB. As described below, temperature data for each of the core dies CD1 to CD4 and control signals for controlling each of the core dies CD1 to CD4 may be transmitted via the TSVs. The plurality of bumps MB may also be disposed on the lower surface of the logic die LD relative to the first direction Z.

[0057] Each of the core dies CD1 to CD4 can be an HBM DRAM die, but the implementation is not limited to this. Each of the core dies CD1 to CD4 may include multiple memory cells for storing data, a temperature sensor, and a heating circuit. The temperature sensor measures the temperature of the multiple memory cells and outputs temperature data. The heating circuit generates heat based on the temperature data and a control signal output from the logic die LD. The following will refer to... Figure 5 Describe the details.

[0058] at the same time, Figure 3 The memory device 42 shown includes four stacked core dies CD1 to CD4, and a logic die LD is disposed below the stacked core dies CD1 to CD4. However, the implementation is not limited to this. For example, the memory device 42 may include five or more stacked core dies, and the logic die LD may be stacked above the stacked core dies CD1 to CD4 rather than below them.

[0059] Figure 3 Each of the core dies CD1 to CD4 shown can be manufactured as a memory device that, in response to commands and addresses applied via command and address terminals, stores data input via data terminals in a selected memory cell among a plurality of memory cells in a memory cell array, or outputs data stored in a selected memory cell via data terminals.

[0060] Multiple bumps (MBs) may be disposed on the lower surface of the host device 41, and the multiple bumps (MBs) may be microbumps. Multiple bumps (MBs) may be disposed on the lower surface of the intermediate component 43, and the intermediate component 43 may include command and address lines and control signal lines connecting the multiple bumps (MBs). Multiple balls may be disposed on the lower surface of the PCB 44, and the multiple bumps (MBs) and multiple balls may be connected to each other in the PCB 44.

[0061] Figure 4 This is a diagram illustrating an example of a semiconductor device.

[0062] Reference Figure 4 ,and Figure 3 Different from the implementation shown, the memory device 42 may also include a first through-silicon via (TSV_1) penetrating the stacked core dies CD1 to CD3, and a second through-silicon via (TSV_2) that is distinct from the first through-silicon via (TSV_1) and penetrates the stacked core dies CD1 to CD3.

[0063] Each of the core dies CD1 to CD4 can provide temperature data, measured by a temperature sensor included in each of the core dies CD1 to CD4, and logic die LD, through a first through-silicon via TSV_1.

[0064] For example, the first core die CD1 can provide temperature data measured by an internal temperature sensor to the second core die CD2 through the fourth core die CD4 and the logic die LD through the first through-silicon via TSV_1.

[0065] In addition, the second core die CD2 can provide temperature data measured by an internal temperature sensor to the first core die CD1, the third core die CD3, the fourth core die CD4 and the logic die LD through the first through-silicon via TSV_1.

[0066] In addition, the third core die CD3 can provide temperature data measured by the internal temperature sensor to the first core die CD1, the second core die CD2, the fourth core die CD4 and the logic die LD through the first through-silicon via TSV_1.

[0067] In addition, the fourth core die CD4 can provide temperature data measured by an internal temperature sensor to the first core die CD1 through the first through-silicon via TSV_1 and the logic die LD.

[0068] The logic die LD can provide control signals to the core dies CD1 to CD4 through the second through-silicon via TSV_2.

[0069] For example, the logic die LD can output a control signal for turning on the heating circuit included in the first core die CD1 through the second through-silicon via TSV_2.

[0070] In addition, the logic die LD can output a control signal for turning on the heating circuit included in the second core die CD2 through the second through silicon via TSV_2.

[0071] In addition, the logic die LD can output a control signal for turning on the heating circuit included in the third core die CD3 through the second through silicon via TSV_2.

[0072] In addition, the logic die LD can output a control signal for turning on the heating circuit included in the fourth core die CD4 through the second through silicon via TSV_2.

[0073] Optionally, the logic die LD can output a control signal to the first core die CD1 through the fourth core die CD4 to activate all the heating circuits included in the first core die CD1 through the fourth core die CD4. In this case, the first core die CD1 through the fourth core die CD4 can send and receive temperature data to each other, and based on the temperature data, the heating circuit included in each of the first core die CD1 through the fourth core die CD4 can adjust the degree of radiated heat.

[0074] In other words, the temperature data measured for each of the core dies CD1 to CD4 and the control signals output from the logic die LD can be sent through different through-silicon vias.

[0075] Figure 5 This is an example diagram of the core die.

[0076] Reference Figure 5 Core bare CD (e.g., Figure 3 and 4 The core die CD1 to CD4 shown may include multiple memory units 51, a temperature sensor 52, and a heating circuit 53.

[0077] Multiple memory units 51 can store data. For example, multiple memory units 51 can store input data or output stored data in response to commands and addresses input to the core die CD.

[0078] Temperature sensor 52 can measure the temperature of multiple memory cells 51 in real time. Temperature sensor 52 can measure the temperature of multiple memory cells 51 and output temperature data TD. Temperature sensor 52 can provide the output temperature data TD to heating circuit 53 and logic die (e.g., Figure 3 and Figure 4 (The logic die LD is shown in the figure). Here, "temperature of multiple memory cells 51 included in a specific core die CD" can have the same meaning as "temperature of a specific core die CD".

[0079] The temperature data TD can indicate which of a plurality of temperature ranges belongs to the temperature of the plurality of memory cells 51 measured by the temperature sensor 52. For example, when the temperature of the plurality of memory cells 51 is in a first range (e.g., less than or equal to 25°C), the temperature sensor 52 can output temperature data TD with a first value, and when the temperature of the plurality of memory cells 51 is in a second range (e.g., greater than 25°C and less than or equal to 100°C), the temperature sensor 52 can output temperature data TD with a second value, and when the temperature of the plurality of memory cells 51 is in a third range (e.g., greater than 100°C), the temperature sensor 52 can output temperature data TD with a third value.

[0080] The first to third values ​​of the temperature data TD can have different values. For example, as the temperature of the multiple memory cells 51 decreases, the temperature data TD can have a smaller value; therefore, the second value can be greater than the first value but less than the third value.

[0081] The value of the temperature data TD can be represented by a voltage. Here, for ease of description, it is described that the temperature data TD has a relatively high voltage as the temperature measured by the multiple memory cells 51 increases, and a relatively low voltage as the temperature measured by the multiple memory cells 51 decreases.

[0082] However, the implementation is not limited to this, and the measured temperatures of the plurality of memory cells 51 may be implemented to be included in any one of three or more temperature ranges, and the relationship between the measured temperatures of the plurality of memory cells 51 and the values ​​of the temperature data TD corresponding to the measured temperatures of the plurality of memory cells 51 may also be implemented differently depending on the implementation.

[0083] Heating circuit 53 may be configured to surround multiple memory cells 51. Heating circuit 53 may be based on temperature data TD provided from temperature sensor 52 and data from logic die (e.g., ...). Figure 3 and Figure 4 The control signal CONT provided by the logic die LD shown in the diagram generates heat. Specifically, the heating circuit 53 can be turned on or off based on the control signal CONT, and the degree of radiated heat can vary according to the value of the temperature data TD.

[0084] The heating circuit 53 can heat multiple memory cells 51 (more specifically, the core die CD of the heating circuit 53) by using heat generated by the Joule heating mechanism. The heating circuit 53 may be composed of at least one of, for example, polycrystalline materials and metals (such as tungsten, aluminum, copper, etc.), but the implementation is not limited thereto, and the heating circuit 53 may include any other suitable materials for heating operation.

[0085] Figure 6 and Figure 7 This is a circuit diagram of an example heating circuit.

[0086] Reference Figure 6 The heating circuit 53 may include a transistor TR and multiple resistors PR.

[0087] The transistor TR can be connected to the point where temperature data is applied (e.g., Figure 5 The diagram shows a first node N1 of a transistor TR connected to multiple resistors PR. Multiple resistors PR can be connected between a transistor TR and a second node N2. The second node N2 can be grounded. The transistor TR and multiple resistors PR can be connected in series. When the transistor TR is on, multiple resistors PR can be connected between the first node N1 and the second node N2.

[0088] From logic bare metal (e.g., Figure 3 and Figure 4 The control signal CONT provided by the logic die LD shown in the figure can be applied to the gate of the transistor TR.

[0089] When the control signal CONT is high (e.g., logic 1), the transistor TR is turned on, and thus current flows through multiple resistors PR according to the temperature data applied to the first node N1. The magnitude of the current flowing through the multiple resistors PR can vary according to the voltage level of the temperature data applied to the first node N1. The current flowing through the multiple resistors PR generates heat through a Joule heating mechanism.

[0090] On the other hand, when the control signal CONT is low (e.g., logic value 0), the transistor TR can be turned off, so the heating circuit 53 can not operate.

[0091] Simultaneously, when the temperature data received from the core die exceeds a certain value, the logic die can output a control signal CONT with a bias voltage to break down transistor TR. For example, when the core die temperature is too high, the logic die can apply the control signal CONT with a bias voltage to the transistors of the heating circuit included in the core die to control the heating circuit to not operate.

[0092] Reference Figure 7The heating circuit 53 may further include at least one voltage amplifier VA connected between the plurality of resistors PR and the second node N2. When the length of the line between the first node N1 and the second node N2 is greater than or equal to a certain length, the heating caused by the plurality of resistors PR may not occur sufficiently due to current leakage, etc. To compensate for this, the voltage amplifier VA can amplify the voltage at a specific point in the heating circuit 53, thereby ensuring sufficient heating by the plurality of resistors PR. The heating circuit 53 may include a corresponding number of voltage amplifiers VA depending on the length of the line.

[0093] Figure 8 This is a diagram illustrating an example of how a multiplexer operates.

[0094] Reference Figure 8 The core die may also include a multiplexer 54. The multiplexer 54 may be based on a logic die (e.g., Figure 3 and Figure 4 The selection signal SEL provided by the logic die LD shown in the figure outputs either the first temperature data TD1 provided by the first temperature sensor 52_1 or the second temperature data TD2 provided by the second temperature sensor 52_2.

[0095] Multiplexer 54 may be included in the first core die CD1 or in the second core die CD2. Optionally, multiplexer 54 may be included in both the first core die CD1 and the second core die CD2. Figure 8 The text describes how multiplexer 54 is included in the first core die CD1.

[0096] A first temperature sensor 52_1 may be included in a first core die CD1, and the first temperature sensor 52_1 may output first temperature data TD1 regarding the first core die CD1. A second temperature sensor 52_2 may be included in a second core die CD2, and the second temperature sensor 52_2 may output second temperature data TD2 regarding the second core die CD2.

[0097] For example, when the temperature of the first core die CD1 is lower than the temperature of the second core die CD2, the value of the first temperature data TD1 can be less than the value of the second temperature data TD2.

[0098] Multiplexer 54 can output the second temperature data TD2, which has the larger value between the first temperature data TD1 and the second temperature data TD2, to the first heating circuit 53_1 (e.g., the input terminal (e.g., the source or drain of the transistor in the first heating circuit 53_1) included in the first core die CD1, based on the selection signal SEL provided from the logic die.

[0099] Here, the selection signal SEL can be a signal used to determine a specific input of the multiplexer 54 output from a plurality of inputs based on "the result of the logic die receiving first temperature data TD1 and second temperature data TD2 and comparing the corresponding values ​​of the first temperature data TD1 and the second temperature data TD2". The selection signal SEL can be a control signal included in the output from the logic die (e.g., Figure 5 The signals shown in the control signals (CONT) are examples of the signals, but the implementation is not limited to these.

[0100] Instead of the previously received first temperature data TD1, the first heating circuit 53_1 can receive second temperature data TD2, the value of which is greater than the value of the first temperature data TD1. Therefore, compared to the input of the first temperature data TD1, the first heating circuit 53_1 can generate more heat, and the temperature of the first core die CD1 can increase and become substantially the same as the temperature of the second core die CD2.

[0101] Figure 9 This is a flowchart illustrating an example of a method for controlling the temperature of the core die.

[0102] Reference Figure 9 The method S10 for controlling the temperature of the core die may include: step S11, measuring the temperature of multiple memory cells. For example, referring to... Figure 5 The temperature sensor 52 included in the core die CD can measure the temperature of multiple memory cells 51 and output temperature data TD.

[0103] The method S10 for controlling the temperature of the core die may include: step S12, determining whether the measured temperature is less than or equal to a predetermined specific temperature (T). s For example, refer to Figures 3 to 5 The logic die LD can receive temperature data TD about the corresponding core die CD from the temperature sensor 52 included in the core die CD, and can determine whether the value of the temperature data TD is less than or equal to a predetermined specific value.

[0104] The method S10 for controlling the temperature of the core die may include: step S13, outputting a control signal for turning on the transistor when the measured temperature is below a predetermined specific temperature ("yes" in step S12). For example, refer to... Figures 3 to 7 The logic die LD can output a control signal CONT to turn on the transistor TR of the heating circuit 53 included in the core die CD, so as to control the operation of the heating circuit 53 to increase the temperature of the core die CD.

[0105] When the measured temperature is higher than the predetermined specific temperature (No in step S12), step S12, which determines whether the measured temperature is less than or equal to the predetermined specific temperature, can be executed again.

[0106] At the same time, refer to Figure 3 and Figure 4 The predetermined specific temperature (i.e., the pre-defined specific temperature) for each of the first core dies CD1 to the fourth core dies CD4, and the corresponding temperature data, may differ from each other. For example, when all the heating circuits included in the first core dies CD1 to the fourth core dies CD4 are not turned on, the first core die CD1, stacked on the logic die LD, may typically have a higher temperature than the fourth core die CD4 due to the heat generated by the operation of the logic die LD. Therefore, the temperature at which the heating circuit included in the fourth core die CD4 begins to turn on may be lower than the temperature at which the heating circuit included in the first core die CD1 begins to turn on.

[0107] In other words, the predetermined specific temperature for the first core die CD1 can be higher than the predetermined specific temperature for the second core die CD2, the predetermined specific temperature for the second core die CD2 can be higher than the predetermined specific temperature for the third core die CD3, and the predetermined specific temperature for the third core die CD3 can be higher than the predetermined specific temperature for the fourth core die CD4.

[0108] Furthermore, in order to correspond with this, the temperature data value corresponding to the predetermined specific temperature of the first core die CD1 can be greater than the temperature data value corresponding to the predetermined specific temperature of the second core die CD2, the temperature data value corresponding to the predetermined specific temperature of the second core die CD2 can be greater than the temperature data value corresponding to the predetermined specific temperature of the third core die CD3, and the temperature data value corresponding to the predetermined specific temperature of the third core die CD3 can be greater than the temperature data value corresponding to the predetermined specific temperature of the fourth core die CD4.

[0109] Therefore, when the temperature data of the first core die CD1 is less than or equal to the temperature data corresponding to a predetermined specific temperature of the first core die CD1, the logic die LD can output a control signal CONT to activate the heating circuit included in the first core die CD1, so as to heat the first core die CD1.

[0110] Similarly, when the temperature data value of the second core die CD2 is less than or equal to the temperature data value corresponding to a predetermined specific temperature of the second core die CD2, the logic die LD can output a control signal CONT to activate the heating circuit included in the second core die CD2 in order to heat the second core die CD2.

[0111] Similarly, when the temperature data value of the third core die CD3 is less than or equal to the temperature data value corresponding to a predetermined specific temperature of the third core die CD3, the logic die LD can output a control signal CONT to turn on the heating circuit included in the third core die CD3 so as to heat the third core die CD3.

[0112] Similarly, when the temperature data value of the fourth core die CD4 is less than or equal to the temperature data value corresponding to a predetermined specific temperature of the fourth core die CD4, the logic die LD can output a control signal CONT to turn on the heating circuit included in the fourth core die CD4 so as to heat the fourth core die CD4.

[0113] Figure 10 This is a flowchart illustrating an example of a method for controlling the temperature of the core die.

[0114] Reference Figure 10 The method S20 for controlling the temperature of the core die may include: step S21, measuring the temperature of the Nth core die. For example, referring to... Figures 3 to 5 The temperature sensor 52 included in the second core die CD2 can measure the temperature of the second core die CD2 by measuring the temperature of the multiple memory cells 51 included in the second core die CD2, and can output temperature data TD.

[0115] The method S20 for controlling the temperature of the core die may include: step S22, determining whether the temperature of the Nth core die is lower than the temperature of the (N-1)th core die (T). 第N-1 And below the temperature of the N+1th core die (T) 第N+1 ).

[0116] For example, refer to Figures 3 to 5 The logic die LD can receive temperature data TD about each of the first core die CD1 to the third core die CD3 from the temperature sensor included in each of the first core die CD1 to the third core die CD3.

[0117] The logic die LD can determine whether the temperature data of the second core die CD2 is less than the temperature data of the first core die CD1 and the temperature data of the third core die CD3, and determine whether the temperature of the second core die CD2 is lower than the temperature of the first core die CD1 and lower than the temperature of the third core die CD3.

[0118] The method S20 for controlling the temperature of the core die may include: step S23, when the temperature of the Nth core die is lower than the temperature of the (N-1)th core die and lower than the temperature of the (N+1)th core die ("Yes" in step S22), outputting a control signal for turning on the transistor.

[0119] For example, refer to Figures 3 to 7 The logic die LD can output the control signal CONT of the transistor TR used to turn on the heating circuit 53 included in the second core die CD2 to the second core die CD2 to control the operation of the heating circuit 53 included in the second core die CD2 so as to increase the temperature of the second core die CD2, which is lower than the temperature of the first core die CD1 and the third core die CD3.

[0120] When the temperature of the Nth core die is higher than or equal to the temperature of the (N-1)th core die or higher than or equal to the temperature of the (N+1)th core die (No in step S22), step S22, which determines whether the temperature of the Nth core die is lower than the temperature of the (N-1)th core die and lower than the temperature of the (N+1)th core die, can be executed again.

[0121] Figure 11 This is a flowchart illustrating an example of a method for controlling the temperature of the core die.

[0122] Reference Figure 11 The method S30 for controlling the temperature of the core die may include: step S31, outputting a control signal for turning on the transistor. For example, refer to... Figures 3 to 7 The logic die LD can output a control signal CONT to turn on the transistor TR of the heating circuit 53 included in the core die CD, so as to control the operation of the heating circuit 53 to increase the temperature of the core die CD.

[0123] The method S30 for controlling the temperature of the core die may include: step S32, comparing the measured temperature of the memory cell with a predetermined specific temperature. For example, referring to... Figures 3 to 5 The logic die LD can receive temperature data TD about the core die CD from the temperature sensor 52 included in the core die CD, and can compare the value of the temperature data TD with the value of temperature data corresponding to a predetermined specific temperature.

[0124] The method S30 for controlling the temperature of the core die may include: step S33, adjusting the voltage applied to the first node. For example, refer to... Figures 3 to 8 When the temperature of the corresponding core die CD is lower than a predetermined specific temperature (e.g., the temperature of other core dies), the logic die LD can output the following selection signal SEL to the multiplexer 54: the selection signal SEL causes a higher voltage to be applied to the first node N1 of the heating circuit 53 and causes the heating circuit 53 to generate heat relatively strongly.

[0125] Conversely, when the temperature of the corresponding core die CD is higher than a predetermined specific temperature (e.g., the temperature of other core dies), the logic die LD can output a selection signal SEL to the multiplexer 54 such that a lower voltage is applied to the first node N1 of the heating circuit 53 and the heating circuit 53 generates heat relatively weakly.

[0126] Figure 12 This is a flowchart illustrating an example of a method for controlling the temperature of the core die.

[0127] Reference Figure 12 The method S40 for controlling the temperature of the core die may include: step S41, outputting a control signal for turning on the transistor. For example, refer to... Figures 3 to 7 The logic die LD can output a control signal CONT to turn on the transistor TR of the heating circuit 53 included in the corresponding core die CD, so as to control the operation of the heating circuit 53 to increase the temperature of the core die CD.

[0128] The method S40 for controlling the temperature of the core die may include: step S42, determining whether the measured temperature of the memory cell is within a predetermined specific temperature range. For example, referring to... Figures 3 to 5 The logic die LD can receive temperature data TD about the corresponding core die CD from the temperature sensor 52 included in the core die CD, and can determine whether the value of the temperature data TD is included in the range of temperature data values ​​corresponding to a predetermined specific temperature range.

[0129] The method S40 for controlling the temperature of the core die may include: step S43, adjusting the voltage applied to the first node. For example, refer to... Figures 3 to 8 When the temperature of the corresponding core die CD is lower than a predetermined specific temperature range, the logic die LD can output the following selection signal SEL to the multiplexer 54: the selection signal SEL causes a higher voltage to be applied to the first node N1 of the heating circuit 53 and causes the heating circuit 53 to generate heat relatively strongly.

[0130] Conversely, when the temperature of the corresponding core die CD is higher than a predetermined specific temperature range, the logic die LD can output the following selection signal SEL to the multiplexer 54: the selection signal SEL causes a lower voltage to be applied to the first node N1 of the heating circuit 53 and causes the heating circuit 53 to generate heat relatively weakly.

[0131] Figure 13 This is a flowchart illustrating an example of a method for controlling the temperature of the core die.

[0132] Reference Figure 13 The method S50 for controlling the temperature of the core die may include: step S51, outputting a control signal for turning on the transistor. For example, refer to... Figures 3 to 7 The logic die LD can output a control signal CONT to turn on the transistor TR of the heating circuit 53 included in the corresponding core die CD, so as to control the operation of the heating circuit 53 to increase the temperature of the core die CD.

[0133] The method S50 for controlling the temperature of the core die may include: step S52, adjusting the voltage applied to the first node. For example, refer to... Figures 3 to 7 The higher the measured temperature of the core die CD, the lower the voltage of the temperature data TD output from the temperature sensor 52 can be set to a relatively small value, and the lower the measured temperature of the core die CD, the higher the voltage of the temperature data TD output from the temperature sensor 52 can be set to a relatively large value.

[0134] For example, when the temperature of the first core die CD1 is high, the heating amount of the heating circuit 53 can be relatively small because the voltage of the temperature data TD input to the first node N1 has a relatively small value. Specifically, the temperature sensor 52 can output a first voltage when the temperature of the first core die CD1 is in a first range that is a low temperature range, output a second voltage lower than the first voltage when the temperature is in a second range that is an intermediate temperature range, and output a third voltage lower than the second voltage when the temperature is in a third range that is a high temperature range.

[0135] When the third voltage is applied to the heating circuit ( Figure 5 When the first node N1 of the heating circuit 53 is also subjected to the same voltage as the third voltage, and the second node N2 is also subjected to the same voltage, no current can flow through the multiple resistors PR. Therefore, when the temperature of the first core die CD1 is in the high temperature range, the heating circuit 53 does not generate heat.

[0136] When a second voltage is applied to the first node N1 of the heating circuit 53 and the same voltage as the third voltage is applied to the second node N2, a relatively low current can flow through multiple resistors PR due to the relatively small voltage difference between the second and third voltages. Therefore, when the temperature of the first core die CD1 is within the intermediate temperature range, the heating amount of the heating circuit 53 can be relatively small.

[0137] When a first voltage is applied to the first node N1 of the heating circuit 53 and the same voltage as the third voltage is applied to the second node N2, a relatively high current can flow through multiple resistors PR due to the relatively large voltage difference between the first and third voltages. Therefore, when the temperature of the first core die CD1 is in a low temperature range, the heating amount of the heating circuit 53 can be relatively large.

[0138] In other words, when the temperatures of multiple core dies CD1 to CD4 are compared through the logic die LD and no corresponding control is performed, the temperatures of the first core die CD1 and the second core die CD2 can be substantially the same.

[0139] The method S50 for controlling the temperature of the core die may include: step S53, determining whether the temperature of the core die is greater than a predetermined specific temperature (T). s For example, refer to Figures 3 to 5 The logic die LD can determine whether the temperature of the core die CD is greater than a predetermined specific temperature based on the temperature data TD of the corresponding core die CD from the temperature sensor 52 included in the core die CD.

[0140] The method S50 for controlling the temperature of the core die may include: step S54, when the temperature of the core die is greater than a predetermined specific temperature ("Yes" in step 53), outputting a control signal with a bias voltage to break down the transistor. For example, refer to Figures 3 to 7 When the temperature of the core die CD is higher than a predetermined specific temperature, the logic die LD can output a control signal CONT with a bias voltage to break down the transistor TR of the heating circuit 53 included in the core die CD, thereby controlling the heating circuit 53 to not operate.

[0141] When the measured temperature is lower than the predetermined specific temperature (No in step 53), step S53, which determines whether the temperature of the core die is greater than the predetermined specific temperature, can be performed again.

[0142] Figures 9 to 13 The method for controlling the temperature of the core die shown is illustrated as being performed alone, but the implementation is not limited thereto. Figures 9 to 12 The methods for controlling the temperature of the core die shown can be organically combined and implemented so that the temperatures of multiple core dies remain substantially the same.

[0143] Figure 14 This is an example diagram of the core die.

[0144] Reference Figure 14 The core die CD can be mounted on the same substrate as the host device 10 and implemented as a semiconductor device. The core die CD may include a first memory region 55_1 and a second memory region 55_2, which are distinguished according to their arrangement with the host device 10.

[0145] Specifically, the first memory region 55_1 may be a memory region of the core CD that is disposed adjacent to the host device 10, and the second memory region 55_2 may be a memory region opposite to the host device 10 relative to the first memory region 55_1 (that is, the first memory region 55_1 may be disposed between the second memory region 55_2 and the host device 10). In this respect, the area of ​​the first memory region 55_1 may be the same as the area of ​​the second memory region 55_2, but the implementation is not limited to this.

[0146] The first memory region 55_1 may include a plurality of first memory cells 51_1, a first temperature sensor 52_1 and a first heating circuit 53_1. The first temperature sensor 52_1 measures the temperature of the plurality of first memory cells 51_1 to output first temperature data TD1. The first heating circuit 53_1 heats the plurality of first memory cells 51_1 based on the control signal CONT and the first temperature data TD1.

[0147] The second memory region 55_2 may include a plurality of second memory cells 51_2, a second temperature sensor 52_2, and a second heating circuit 53_2. The second temperature sensor 52_2 measures the temperature of the plurality of second memory cells 51_2 to output second temperature data TD2. The second heating circuit 53_2 heats the plurality of second memory cells 51_2 based on the control signal CONT and the second temperature data TD2.

[0148] When neither the first heating circuit 53_1 nor the second heating circuit 53_2 is activated, the temperature of the first memory region 55_1 is typically higher than the temperature of the second memory region 55_2 due to the heat generated by the operation of the host device 10. Therefore, temperature control for the core die CD can be performed to keep the temperature of the second memory region 55_2 the same as the temperature of the first memory region 55_1.

[0149] Specifically, logic dies (e.g., Figure 3 and Figure 4The logic die LD shown can receive first temperature data TD1 about the first memory region 55_1 from the first temperature sensor 52_1, and second temperature data TD2 about the second memory region 55_2 from the second temperature sensor 52_2.

[0150] Because the temperature of the first memory region 55_1 is higher than the temperature of the second memory region 55_2, the value of the first temperature data TD1 can be greater than the value of the second temperature data TD2. The logic die LD can determine that the temperature of the second memory region 55_2 is lower than the temperature of the first memory region 55_1 based on the values ​​of the first temperature data TD1 and the second temperature data TD2.

[0151] The logic die LD can provide a control signal CONT to the first heating circuit 53_1 to turn off the first heating circuit 53_1, and can provide a control signal CONT to the second heating circuit 53_2 to turn on the second heating circuit 53_2, so that the temperature of the first memory region 55_1 and the second memory region 55_2 remains the same.

[0152] Figure 15 This is an example diagram of the core die.

[0153] Reference Figure 15 The core die CD can be mounted on the same substrate as the host device 10 and implemented as a semiconductor device. The core die CD may include a first memory region 55_1, a second memory region 55_2, a third memory region 55_3, and a fourth memory region 55_4, which are distinguished according to their arrangement with the host device 10.

[0154] Specifically, the first memory region 55_1 and the third memory region 55_3 can be memory regions of the core bare CD that are disposed adjacent to the host device 10, and the second memory region 55_2 and the fourth memory region 55_4 can be memory regions that are opposite to the host device 10 relative to the first memory region 55_1 and the third memory region 55_3 (that is, the first memory region 55_1 and the third memory region 55_3 can be disposed between the second memory region 55_2 and the fourth memory region 55_4 and the host device 10). In this respect, the areas of the first memory region 55_1, the second memory region 55_2, the third memory region 55_3 and the fourth memory region 55_4 can be the same, but the implementation is not limited to this.

[0155] The first memory region 55_1 may include a plurality of first memory cells 51_1, a first temperature sensor 52_1 and a first heating circuit 53_1. The first temperature sensor 52_1 measures the temperature of the plurality of first memory cells 51_1 to output first temperature data TD1. The first heating circuit 53_1 heats the plurality of first memory cells 51_1 based on the control signal CONT and the first temperature data TD1.

[0156] The second memory region 55_2 may include a plurality of second memory cells 51_2, a second temperature sensor 52_2, and a second heating circuit 53_2. The second temperature sensor 52_2 measures the temperature of the plurality of second memory cells 51_2 to output second temperature data TD2. The second heating circuit 53_2 heats the plurality of second memory cells 51_2 based on the control signal CONT and the second temperature data TD2.

[0157] The third memory region 55_3 may include multiple third memory cells 51_3, a third temperature sensor 52_3, and a third heating circuit 53_3. The third temperature sensor 52_3 measures the temperature of the multiple third memory cells 51_3 to output third temperature data TD3. The third heating circuit 53_3 heats the multiple third memory cells 51_3 based on the control signal CONT and the third temperature data TD3.

[0158] The fourth memory region 55_4 may include a plurality of fourth memory cells 51_4, a fourth temperature sensor 52_4, and a fourth heating circuit 53_4. The fourth temperature sensor 52_4 measures the temperature of the plurality of fourth memory cells 51_4 to output fourth temperature data TD4. The fourth heating circuit 53_4 heats the plurality of fourth memory cells 51_4 based on the control signal CONT and the fourth temperature data TD4.

[0159] When the first heating circuit 53_1, the second heating circuit 53_2, the third heating circuit 53_3, and the fourth heating circuit 53_4 are all off, the temperatures of the first memory region 55_1 and the third memory region 55_3 are typically higher than the temperatures of the second memory region 55_2 and the fourth memory region 55_4 due to the heat generated by the operation of the host device 10. Therefore, temperature control for the core die CD can be performed to maintain the temperatures of the second memory region 55_2 and the fourth memory region 55_4 at the same level as the temperatures of the first memory region 55_1 and the third memory region 55_3.

[0160] Specifically, logic dies (e.g., Figure 3 and Figure 4The logic die LD shown can receive first temperature data TD1 about the first memory region 55_1 from the first temperature sensor 52_1, second temperature data TD2 about the second memory region 55_2 from the second temperature sensor 52_2, third temperature data TD3 about the third memory region 55_3 from the third temperature sensor 52_3, and fourth temperature data TD4 about the fourth memory region 55_4 from the fourth temperature sensor 52_4.

[0161] Because the temperatures of the first memory region 55_1 and the third memory region 55_3 are higher than the temperatures of the second memory region 55_2 and the fourth memory region 55_4, the values ​​of the first temperature data TD1 and the third temperature data TD3 can be greater than the values ​​of the second temperature data TD2 and the fourth temperature data TD4. The logic die LD can determine that the temperatures of the second memory region 55_2 and the fourth memory region 55_4 are lower than the temperatures of the first memory region 55_1 and the third memory region 55_3 based on the values ​​of the first temperature data TD1, the second temperature data TD2, the third temperature data TD3, and the fourth temperature data TD4.

[0162] The logic die LD can provide the control signal CONT for turning off the first heating circuit 53_1 and the third heating circuit 53_3 to the first heating circuit 53_1 and the third heating circuit 53_3, and can provide the control signal CONT for turning on the second heating circuit 53_2 and the fourth heating circuit 53_4 to the second heating circuit 53_2 and the fourth heating circuit 53_4, so that the temperature of the first memory region 55_1, the second memory region 55_2, the third memory region 55_3 and the fourth memory region 55_4 remains the same.

[0163] Figure 16 This is a perspective view showing an example of a semiconductor device.

[0164] Reference Figure 16 The semiconductor device 1000, as a semiconductor package, may be a memory module including at least one memory device 1010 and a system-on-a-chip (SoC) 1020 mounted on a package substrate 1040 (such as a printed circuit board). In some embodiments, reference is made to... Figures 1 to 15 The described memory device can be applied to memory device 1010.

[0165] The middleware 1030 may be further selectively disposed on the package substrate 1040. The memory device 1010 may be formed as a chip-on-a-chip (CoC). The memory device 1010 may include a memory die 1100 comprising at least one core die stacked on a logic die 1200. The memory die 1100 and the logic die 1200 may be interconnected through through-silicon vias (TSVs).

[0166] In some implementations, the memory device 1010 may be a high-bandwidth memory with a bandwidth of 500 gigabytes (GB) / second to 1 terabyte (TB) / second or higher.

[0167] Figure 17 This is a perspective view showing an example of a semiconductor device.

[0168] Reference Figure 17 Semiconductor device 2000 is a dual in-line memory module (DIMM) system in which semiconductor chips are mounted on both sides of a printed circuit board, and may include a memory controller 2020 and a memory module 2002 including at least one PCB 2030. The memory controller 2020 may be mounted on a motherboard 2040, and the PCB 2030 may be electrically connected to the motherboard 2040 via a plurality of connection sockets 2070.

[0169] The memory device 2010 may be formed as a CoC and may be mounted on both sides of the PCB 2030. The memory controller 2020 and the memory device 2010 may be electrically connected to the PCB 2030 via a bus in the motherboard 2040. In some embodiments, the memory device 2010 may include a stacked structure of memory dies and logic dies. In some embodiments, refer to... Figures 1 to 15 The described memory device can be applied to memory device 2010.

[0170] In some implementations, the memory device 2010 may be a high-bandwidth memory of 500 GB / s to 1 TB / s or higher.

[0171] Figure 18 This is a schematic block diagram of an example computing device.

[0172] Reference Figure 18 The computing device 3000 includes a processor 3010, a memory 3020, a memory controller 3030, a storage device 3040, a communication interface 3050, and a bus 3060. The computing device 3000 may also include other general-purpose components.

[0173] The processor 3010 controls the overall operation of each component of the computing device 3000. The processor 3010 may be implemented as at least one of various processing units, such as CPU, AP, and GPU.

[0174] The memory 3020 stores various types of data and commands. The memory 3020 can be implemented as a reference. Figures 1 to 15The memory device described. Memory controller 3030 controls the transfer of data or commands to and from memory 3020. In some embodiments, memory controller 3030 may be configured as a separate chip from processor 3010. In some embodiments, memory controller 3030 may be integrated into the internal structure of processor 3010.

[0175] Storage device 3040 stores programs and data non-transitory. In some embodiments, storage device 3040 may be implemented as non-volatile memory. Communication interface 3050 supports wired / wireless Internet communication of computing device 3000. Furthermore, communication interface 3050 may support various communication methods other than Internet communication. Bus 3060 provides communication functionality between components of computing device 3000. Bus 3060 may include at least one type of bus according to a communication protocol between components.

[0176] In some implementations, refer to Figures 1 to 15 Each component described, or a combination of two or more components, can be implemented as a digital circuit, a programmable or non-programmable logic device or array, an application-specific integrated circuit (ASIC), etc.

[0177] While this specification contains numerous specific details of implementation, these details should not be construed as limiting the scope of any invention or the scope that may be claimed, but rather as descriptions of features specific to particular embodiments of a particular invention. Specific features described in the context of individual embodiments in this specification may also be implemented in combination in a single embodiment. Conversely, various features described in the context of a single embodiment may also be implemented individually or in any suitable sub-combination in multiple embodiments. Furthermore, although features may be described above as functioning in a particular combination, in some cases one or more features from the combination may be removed from the combination, and a combination may refer to a sub-combination or a variation of a sub-combination.

[0178] Although the disclosed embodiments have been described in detail above, the scope of the disclosure is not limited thereto, and various modifications and improvements made by those skilled in the art are also within the scope of the disclosure.

Claims

1. A memory device comprising: a logic die configured to output a control signal based on temperature data; and a first core die including: a first plurality of memory cells configured to store data; a first temperature sensor configured to measure a temperature of the first plurality of memory cells and output first temperature data based on the temperature of the first plurality of memory cells; and a first heating circuit configured to generate heat based on the control signal and the first temperature data.

2. The memory device of claim 1, wherein, The first heating circuit includes: a resistor connected between a first node and a second node, the first node and the second node configured to receive the first temperature data, a transistor connected between the first node and the resistor, the transistor including a gate configured to receive the control signal, and a voltage amplifier connected between the resistor and the second node. 3.The memory device of claim 2, wherein: the logic die is further configured to output the control signal to turn on the transistor based on the first temperature data being equal to or less than a certain value. 4.The memory device of claim 2, wherein: the logic die is further configured to output the control signal with a bias voltage to break down the transistor based on the first temperature data being greater than the certain value. 5.The memory device of claim 2, further comprising: a second core die including: a second plurality of memory cells configured to store data; a second temperature sensor configured to measure a temperature of the second plurality of memory cells and output second temperature data based on the temperature of the second plurality of memory cells; and a second heating circuit configured to generate heat based on the control signal and the second temperature data, wherein the first core die further includes: a multiplexer configured to output the first temperature data or the second temperature data to an input terminal of the transistor. 6.The memory device of claim 5, wherein: the first core die and the second core die are stacked in a first direction. 7.The memory device of claim 5, wherein: the logic die is further configured to output a selection signal configured to cause the multiplexer to output the second temperature data to the multiplexer based on a value of the first temperature data being less than a value of the second temperature data. 8.The memory device of claim 6, wherein: the first core die is configured to receive the second temperature data through a first through silicon via extending through the first core die and the second core die in the first direction. 9.The memory device of claim 8, wherein: the logic die and the first core die are stacked in the first direction, the logic die is further configured to provide the control signal to the first core die through a second through silicon via different from the first through silicon via, and the second through silicon via extends through the first core die and the second core die in the first direction. 10.The memory device of any one of claims 1 to 9, wherein: the first heating circuit is configured to surround the first plurality of memory cells. 11.The memory device of any one of claims 1 to 9, wherein: the first plurality of memory cells includes a first memory cell and a second memory cell, and the first memory cell is configured to store data and the second memory cell is configured to store metadata. The first heating circuit includes a third heating circuit surrounding the first memory cell and a fourth heating circuit surrounding the second memory cell.

12. The memory device of any one of claims 1 to 9, wherein: The first heating circuit includes at least one of a polycrystalline material, tungsten, aluminum, and copper.

13. A memory device, comprising: a plurality of core dies stacked in a first direction and configured to provide temperature data, the plurality of core dies including a first core die, a second core die, and a third core die; and a logic die configured to output a control signal based on the temperature data, wherein the plurality of core dies are configured to provide the temperature data through a first through-silicon via extending through the plurality of core dies in the first direction, and wherein the second core die includes a heating circuit configured to heat the second core die based on first temperature data of the first core die, second temperature data of the second core die, third temperature data of the third core die, and the control signal.

14. The memory device of claim 13, wherein, The heating circuit includes: a resistor connected between a first node and a second node, the first node and the second node configured to receive at least a portion of the temperature data, a transistor connected between the first node and the resistor, the transistor including a gate configured to receive the control signal, and a voltage amplifier connected between the resistor and the second node.

15. The memory device of claim 14, wherein: the logic die is further configured to output the control signal to turn on the transistor based on a value of the temperature data of the second core die being less than a value of the temperature data of the first core die and a value of the temperature data of the third core die.

16. The memory device of claim 14, wherein: the logic die is further configured to output the control signal with a bias voltage to turn on the transistor based on the temperature data of the second core die being greater than a particular value.

17. The memory device of claim 13, wherein, the logic die is further configured to: output the control signal to turn on the heating circuit of the first core die based on the temperature data of the first core die being less than or equal to a first value, output the control signal to turn on the heating circuit of the second core die based on the temperature data of the second core die being less than or equal to a second value different from the first value, and output the control signal to turn on the heating circuit of the third core die based on the temperature data of the third core die being less than or equal to a third value different from the first value and the second value.

18. The memory device of claim 17, wherein: the second value is less than the first value and greater than the third value.

19. The memory device of claim 18, wherein: the logic die, the first core die, the second core die, and the third core die are stacked in the first direction, and the logic die is further configured to provide the control signal to the first core die, the second core die, and the third core die through a second through-silicon via different from the first through-silicon via, the second through-silicon via extending through the first core die, the second core die, and the third core die in the first direction.

20. A semiconductor device, comprising: a host device; and a memory device according to any one of claims 1 to 19. A memory device includes a logic die configured to output a control signal based on first temperature data and second temperature data, and a core die stacked on the logic die in a first direction, wherein the core die includes: a first memory region including a plurality of first memory cells, a first temperature sensor configured to measure a temperature of the plurality of first memory cells and output the first temperature data based on the temperature of the plurality of first memory cells, and a first heating circuit configured to heat the plurality of first memory cells based on the control signal and the first temperature data, the first heating circuit being disposed adjacent to a host device, and a second memory region including a plurality of second memory cells, a second temperature sensor configured to measure a temperature of the plurality of second memory cells and output the second temperature data based on the temperature of the plurality of second memory cells, and a second heating circuit configured to heat the plurality of second memory cells based on the control signal and the second temperature data, the second heating circuit being disposed opposite to the host device with respect to the first memory region, and wherein the control signal is configured to cause the first heating circuit to be turned off and the second heating circuit to be turned on.

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