Tail current biasing for sense operations in memory devices

Abstract

The invention relates to tail current biasing for sense operations in memory devices. A memory device includes a memory array having a plurality of memory cells formed at respective intersections of a plurality of word lines and a plurality of bit lines. The memory device further includes a page buffer circuit coupled to the memory array, the page buffer circuit including sensing circuitry for measuring a cell current read from a bit line of the plurality of bit lines and tail current bias circuitry coupled to the bit line, wherein the tail current bias circuitry includes a tail current capacitor having a first terminal coupled to the bit line, the tail current capacitor to generate a tail current in the bit line during a signal accumulation period when the sensing circuitry measures the cell current read from the bit line.

Description

Technical Field

[0001] Embodiments of this disclosure generally relate to memory subsystems, and more specifically, to tail current biasing for sensing operations in memory devices of memory subsystems. Background Technology

[0002] The memory subsystem may include one or more memory devices for storing data. For example, the memory devices may be non-volatile memory devices and volatile memory devices. Generally, the host system can utilize the memory subsystem to store data at the memory devices and retrieve data from the memory devices. Summary of the Invention

[0003] One aspect of this disclosure discloses a memory device comprising: a memory array including a plurality of memory cells formed at corresponding intersections of a plurality of word lines and a plurality of bit lines; and a page buffer circuit coupled to the memory array, the page buffer circuit including a sensing circuit system for measuring cell current read from a bit line among the plurality of bit lines and a tail current biasing circuit system coupled to the bit lines, wherein the tail current biasing circuit system includes a tail current capacitor having a first terminal coupled to the bit lines, the tail current capacitor being used to generate a tail current in the bit lines during a signal accumulation period when the sensing circuit system measures the cell current read from the bit lines.

[0004] Another aspect of this disclosure discloses a page buffer circuit comprising: a sensing circuit system for measuring cell current read from a bit line of a plurality of bit lines of a memory array; and a tail current biasing circuit system coupled to the bit line, wherein the tail current biasing circuit system includes a tail current capacitor having a first terminal coupled to the bit line, the tail current capacitor being used to generate a tail current in the bit line during a signal accumulation period when the sensing circuit system measures the cell current read from the bit line.

[0005] Another aspect of this disclosure discloses a memory device comprising: a memory array including a plurality of memory cells formed at corresponding intersections of a plurality of word lines and a plurality of bit lines; a page buffer circuit coupled to the memory array, the page buffer circuit including a sensing circuit system for measuring cell current read from a bit line among the plurality of bit lines and a tail current bias circuit system coupled to the bit line, wherein the tail current bias circuit system includes a tail current capacitor having a first terminal coupled to the bit line, the tail current capacitor being used to generate a tail current in the bit line during a signal accumulation period when the sensing circuit system measures the cell current read from the bit line; and control logic operatively coupled to the memory array and the page buffer circuit to perform operations including: causing the bit line to be precharged; causing a read voltage to be applied to a word line among the plurality of word lines; and causing a bias voltage applied to a second terminal of the tail current capacitor to slope down over time to generate the tail current in the bit line. Attached Figure Description

[0006] This disclosure will be more fully understood from the detailed description given below and from the accompanying drawings of various embodiments thereof.

[0007] Figure 1A This describes an example computing system including a memory subsystem according to some embodiments of the present disclosure.

[0008] Figure 1B This is a block diagram of a memory device communicating with a memory subsystem controller of a memory subsystem according to some embodiments of the present disclosure.

[0009] Figure 2 Some embodiments of this disclosure may be used for reference. Figure 1B A schematic diagram of a portion of the memory cell array in the described type of memory.

[0010] According to some embodiments of this disclosure Figure 3A This is a schematic diagram illustrating part of the page buffer circuit of a system with tail current biasing circuit. Figure 3B This is its timing diagram.

[0011] According to some embodiments of this disclosure Figure 4A This is a schematic diagram illustrating part of the page buffer circuit of a system with tail current biasing circuit. Figure 4B This is its timing diagram.

[0012] Figure 5 This is a flowchart of an example method for performing a sensing operation in a memory device using tail current bias according to some embodiments of the present disclosure.

[0013] According to some embodiments of this disclosure Figure 6AThis is a schematic diagram illustrating part of the page buffer circuit in a system with a switching tail current bias circuit. Figure 6B This is its timing diagram.

[0014] According to some embodiments of this disclosure Figure 7A This is a schematic diagram illustrating part of the page buffer circuit in a system with a switching tail current bias circuit. Figure 7B This is its timing diagram.

[0015] According to some embodiments of this disclosure Figure 8A This is a schematic diagram illustrating part of the page buffer circuit in a system with a switching tail current bias circuit. Figure 8B This is its timing diagram.

[0016] According to some embodiments of this disclosure Figure 9A This is a schematic diagram illustrating part of the page buffer circuit in a system with a switching tail current bias circuit. Figure 9B This is its timing diagram.

[0017] According to some embodiments of this disclosure Figure 10A This is a schematic diagram illustrating part of the page buffer circuit in a system with a switching tail current bias circuit. Figure 10B This is its timing diagram.

[0018] Figure 11 This is a block diagram of an example computer system in which embodiments of this disclosure may be operated. Detailed Implementation

[0019] This disclosure relates to tail current biasing for sensing operations in a memory device for a memory subsystem. The memory subsystem may be a memory device, a memory module, or a hybrid of a memory device and a memory module. The following is combined with… Figure 1A Describe examples of storage devices and memory modules. Generally, a host system may utilize a memory subsystem that includes one or more components, such as a memory device for storing data. The host system can provide data stored in the memory subsystem and can request data to be retrieved from the memory subsystem.

[0020] A memory subsystem may contain high-density non-volatile memory devices in which it is desirable to retain data when no power is supplied to the memory device. For example, NAND memory (e.g., 3D flash NAND memory) provides storage in a compact, high-density configuration. A non-volatile memory device is a package of one or more dies, each comprising one or more planes. For some types of non-volatile memory devices (e.g., NAND memory), each plane contains a set of physical blocks. Each block contains a set of pages. Each page contains a set of memory cells (“cells”). A cell is an electronic circuit that stores information. Depending on the cell type, a cell may store one or more bits of binary information and have various logic states related to the number of bits stored. Logic states may be represented by binary values, such as “0” and “1” or combinations of such values.

[0021] Memory devices can consist of bits arranged in a two-dimensional or three-dimensional grid. Memory cells are formed on a silicon wafer in arrays of columns (hereinafter also referred to as bit lines) and rows (hereinafter also referred to as word lines). A word line can refer to one or more rows of memory cells in a memory device, which, together with one or more bit lines, is used to generate the address of each memory cell. The intersection of a bit line and a word line constitutes the address of the memory cell. The term "block" below refers to a unit of memory device used for storing data and can include groups of memory cells, groups of word lines, word lines, or individual memory cells. One or more blocks can be grouped together to form separate partitions (e.g., planes) of the memory device to allow concurrent operation on each plane. Memory devices can include circuitry that performs concurrent memory page accesses on two or more memory planes. For example, a memory device can include multiple access line driver circuits and power supply circuitry that can be shared by planes of the memory device to facilitate concurrent access to pages containing different page types on two or more memory planes. For ease of description, these circuits can be collectively referred to as independent plane driver circuitry. Depending on the storage architecture used, data can be stored across memory planes (i.e., in stripes). Therefore, a request to read a data segment (e.g., corresponding to one or more data addresses) can result in a read operation on two or more of the memory planes of the memory device.

[0022] As part of a read operation, a page buffer circuit in the memory device can be used to sense the charge level in selected memory cells stored in the memory array. The page buffer circuit can first precharge the bit line to a known voltage, and then, when a read voltage is applied to the selected word line, the page buffer circuit can sense the bit line voltage, which can remain high or discharge based on a threshold voltage of the memory cell being read. For example, to sense the bit line voltage, a temporary cache capacitor can be used to accumulate the current flowing on the bit line over time. As the current flows, it charges or discharges the capacitor, and this change corresponds to a change in the bit line voltage. The page buffer circuit compares the bit line voltage with a reference voltage to determine whether the cell is in a programmed state (e.g., '0') or an erased state (e.g., '1'), and the result can be temporarily stored in a latch until it is transferred out or further processed.

[0023] Sensing operations performed in the page buffer are sensitive to many factors that can negatively impact accuracy, including noise, interference, and process variations. For example, pattern noise can be caused by the influence of data patterns stored in neighboring cells or nearby memory pages in the array. This noise can be caused by coupling between cells (i.e., inter-cell interference), variations in the cell's threshold voltage, or read / write interference caused by repetitive operations in nearby cells. Pattern noise introduces variability into the threshold voltage of memory cells, and bit line voltages can be affected by noise from neighboring cells, leading to incorrect voltage reads during sensing. Therefore, the page buffer circuitry may fail to accurately distinguish between programming and erase states, resulting in bit errors and incorrect reads of stored data.

[0024] This disclosure addresses the aforementioned and other drawbacks by implementing tail current biasing for sensing operations in a memory device for a memory subsystem. For example, a page buffer circuit may include a tail current capacitor or a network of one or more capacitors and / or switches (e.g., transistors) coupled to the bit line and used to generate a tail current during sensing operations (e.g., as part of a read or program verification operation). In one embodiment, one or more tail current capacitors are biased with a voltage signal that can slope down during the signal accumulation time, thereby generating a tail current on the bit line. From a sensing perspective, adding the tail current to the cell current during the sensing phase improves sensing accuracy. When sensing reads a cell programmed as logic 0 (i.e., a cell that does not absorb current), the convergence of the bit line becomes faster. Once the bit line reaches a steady state, both the cell current from the bit line and the tail current can accumulate at a temporary cache capacitor, resulting in a voltage drop at the temporary cache node. The rate of voltage drop can be used to identify the state of the cell read from the bit line. The presence of a tail current stabilizes the bit line, thereby reducing variability, improving the signal-to-noise ratio, and allowing detectors in the page buffer to more accurately distinguish between programming states (e.g., '0') and erase states (e.g., '1'). In other embodiments, a switched tail current capacitor is used to generate a tail current on the bit line. In these embodiments, a switching network controlled by alternating control signals alternately charges and discharges the tail current capacitor from the bit line to the source node (e.g., ground). The frequency of the switches can be used to more accurately control the magnitude of the tail current, which further improves the accuracy of sensing operations in the page buffer circuitry.

[0025] The advantages of the methods described herein include (but are not limited to) improved performance of the page buffer circuitry of the memory device. In any embodiment, the use of tail current bias improves the accuracy of sensing operations. When used in conjunction with a ramp bias signal, the tail current capacitor allows for lower precharge time, higher edge immunity, and lower dynamic margin compared to sensing operations performed without this tail current. Switched capacitor solutions offer additional advantages such as increased flexibility in tail current generation, reduced area (because a ramp generator is not required and a smaller tail current capacitor can be used), and increased read window due to interference cancellation effects.

[0026] Figure 1A This description describes an example computing system 100 including a memory subsystem 110 according to some embodiments of the present disclosure. The memory subsystem 110 may include media such as one or more volatile memory devices (e.g., memory device 140), one or more non-volatile memory devices (e.g., memory device 130), or combinations thereof.

[0027] The memory subsystem 110 may be a storage device, a memory module, or a combination of a storage device and a memory module. Examples of storage devices include solid-state drives (SSDs), flash drives, universal serial bus (USB) flash drives, embedded multimedia controller (eMMC) drives, universal flash memory (UFS) drives, secure digital cards (SD cards), and hard disk drives (HDDs). Examples of memory modules include dual in-line memory modules (DIMMs), small form factor DIMMs (SO-DIMMs), and various types of non-volatile dual in-line memory modules (NVDIMMs).

[0028] The computing system 100 may be a computing device, such as a desktop computer, laptop computer, web server, mobile device, vehicle (e.g., airplane, drone, train, car or other means of transportation), Internet of Things (IoT) enabled device, embedded computer (e.g., embedded computer contained in a vehicle, industrial equipment or networked business device), or such computing device containing memory and processing devices.

[0029] The computing system 100 may include a host system 120 coupled to one or more memory subsystems 110. In some embodiments, the host system 120 is coupled to different types of memory subsystems 110. Figure 1A This describes an example of a host system 120 coupled to a memory subsystem 110. As used herein, “coupled to” or “coupled with” generally refers to a connection between components, which can be an indirect or direct communication connection (e.g., without an intermediary component), whether wired or wireless, and includes connections such as electrical, optical, magnetic, etc.

[0030] Host system 120 may include a processor chipset and a software stack executed by the processor chipset. The processor chipset may include one or more cores, one or more caches, a memory controller (e.g., an NVDIMM controller), and a storage protocol controller (e.g., a PCIe controller, a SATA controller, a CXL controller). Host system 120, for example, uses memory subsystem 110 to write data to and read data from memory subsystem 110.

[0031] Host system 120 can be coupled to memory subsystem 110 via a physical host interface. Examples of physical host interfaces include (but are not limited to) Serial Advanced Technology Attachment (SATA) interfaces, Compute Fast Link (CXL) interfaces, Peripheral Component Interconnect Fast (PCIe) interfaces, Universal Serial Bus (USB) interfaces, Fibre Channel, Serial Attached SCSI (SAS), Double Data Rate (DDR) memory bus, Small Computer System Interface (SCSI), Dual In-line Memory Module (DIMM) interfaces (e.g., DIMM slot interfaces supporting Double Data Rate (DDR)), etc. The physical host interface can be used to transfer data between host system 120 and memory subsystem 110. When memory subsystem 110 is coupled to host system 120 via a physical host interface (e.g., a PCIe or CXL interface), host system 120 can further utilize an NVM Fast (NVMe) interface to access memory components (e.g., memory device 130). The physical host interface provides an interface for passing control, address, data, and other signals between memory subsystem 110 and host system 120. Figure 1A The memory subsystem 110 is described as an example. Generally, the host system 120 can access multiple memory subsystems via the same communication connection, multiple individual communication connections, and / or combinations of communication connections.

[0032] Memory devices 130 and 140 may comprise any combination of different types of non-volatile memory devices and / or volatile memory devices. Volatile memory devices (such as memory device 140) may be (but are not limited to) random access memory (RAM), such as dynamic random access memory (DRAM) and synchronous dynamic random access memory (SDRAM).

[0033] Some examples of non-volatile memory devices (such as memory device 130) include NAND flash memory and in-situ write memory, such as three-dimensional crosspoint (“3D crosspoint”) memory devices. The crosspoint array of non-volatile memory can perform bit storage based on changes in volume resistance combined with a stackable cross-network data access array. Furthermore, compared to many flash-based memories, crosspoint non-volatile memory can perform in-situ write operations, where non-volatile memory cells can be programmed without prior erasing of the non-volatile memory cells. NAND flash memory includes, for example, two-dimensional NAND (2D NAND) and three-dimensional NAND (3D NAND).

[0034] Each of the memory devices 130 may include one or more arrays of memory cells. One type of memory cell (e.g., single-level cell (SLC)) may store one bit per cell. Other types of memory cells (e.g., multi-level cell (MLC), three-level cell (TLC), and four-level cell (QLC)) may store multiple bits per cell. In some embodiments, each of the memory devices 130 may include one or more arrays of memory cells, such as SLC, MLC, TLC, QLC, or any combination thereof. In some embodiments, a particular memory device may include SLC portions and MLC portions, TLC portions, or QLC portions of memory cells. The memory cells of the memory device 130 may be grouped into pages, which may refer to logical cells of the memory device used for storing data. For some types of memory (e.g., NAND), pages may be grouped to form blocks.

[0035] Although non-volatile memory components such as 3D cross-point arrays of non-volatile memory cells and NAND flash memories (e.g., 2D NAND, 3D NAND) are described, memory device 130 may be based on any other type of non-volatile memory, such as read-only memory (ROM), phase-change memory (PCM), self-select memory, other chalcogenide-based memories, ferroelectric transistor random access memory (FeTRAM), ferroelectric random access memory (FeRAM), magnetic random access memory (MRAM), spin-transfer torque (STT)-MRAM, conductive bridged RAM (CBRAM), resistive random access memory (RRAM), oxide-based RRAM (OxRAM), NOR flash memory, and electrically erasable programmable read-only memory (EEPROM).

[0036] The memory subsystem controller 115 (or simply controller 115) can communicate with the memory device 130 to perform operations such as reading data, writing data, erasing data, and other such operations at the memory device 130. The memory subsystem controller 115 may include hardware such as one or more integrated circuits and / or discrete components, buffer memories, or combinations thereof. The hardware may include a digital circuit system having dedicated (i.e., hard-coded) logic for performing the operations described herein. The memory subsystem controller 115 may be a microcontroller, a dedicated logic circuit system (e.g., a field-programmable gate array (FPGA), an application-specific integrated circuit (ASIC), etc.), or other suitable processor.

[0037] The memory subsystem controller 115 may include a processor 117 (e.g., a processing device) configured to execute instructions stored in local memory 119. In the illustrated example, the local memory 119 of the memory subsystem controller 115 includes embedded memory configured to store instructions for performing various processes, operations, logical flows, and routines for controlling the operation of the memory subsystem 110 (including handling communication between the memory subsystem 110 and the host system 120).

[0038] In some embodiments, local memory 119 may include memory registers for storing memory pointers, fetch data, etc. Local memory 119 may also include read-only memory (ROM) for storing microcode. Although Figure 1A The instance memory subsystem 110 has been described as including a memory subsystem controller 115, but in another embodiment of this disclosure, the memory subsystem 110 does not include a memory subsystem controller 115, but may rely on external control (e.g., provided by an external host or by a processor or controller separate from the memory subsystem).

[0039] Generally, the memory subsystem controller 115 can receive commands or operations from the host system 120 and can translate these commands or operations into instructions or appropriate commands to achieve the desired access to the memory device 130. The memory subsystem controller 115 may be responsible for other operations, such as wear leveling, discard item collection, error detection and error correction code (ECC) operations, encryption, caching, and address translation between logical addresses (e.g., logical block addresses, namespaces) and physical addresses (e.g., physical block addresses) associated with the memory device 130. The memory subsystem controller 115 may further include a host interface circuitry for communicating with the host system 120 via a physical host interface. The host interface circuitry can translate commands received from the host system into command instructions to access the memory device 130 and translate responses associated with the memory device 130 into information for the host system 120.

[0040] The memory subsystem 110 may also include additional circuitry or components not described. In some embodiments, the memory subsystem 110 may include caches or buffers (e.g., DRAM) and address circuitry (e.g., row decoders and column decoders) that can receive and decode addresses from the memory subsystem controller 115 to access the memory device 130.

[0041] In some embodiments, memory device 130 includes a local media controller 135 that operates in conjunction with memory subsystem controller 115 to perform operations on one or more memory cells of memory device 130. An external controller (e.g., memory subsystem controller 115) can manage memory device 130 from an external source (e.g., perform media management operations on memory device 130). In some embodiments, memory device 130 is a managed memory device, which is a raw memory device 130 having on-die control logic (e.g., local controller 135) and a controller (e.g., memory subsystem controller 115) for media management within the same memory device package. An example of a managed memory device is a managed NAND (MNAND) device. For example, memory device 130 may represent a single die on which some control logic (e.g., local media controller 135) is embodied. In some embodiments, one or more components of memory subsystem 110 may be omitted.

[0042] In one embodiment, memory subsystem 110 includes memory interface 113, which handles interactions between memory subsystem controller 115 and memory devices (e.g., memory device 130) of memory subsystem 110. For example, memory interface 113 may send memory access commands, such as programming commands, read commands, or other commands, to memory device 130 in response to a request received from host system 120. Additionally, memory interface 113 may receive data from memory device 130, such as data retrieved in response to confirmation that a read command or programming command has been successfully executed. In some embodiments, memory subsystem controller 115 includes at least a portion of memory interface 113. For example, memory subsystem controller 115 may include processor 117 (processing means) configured to execute instructions stored in local memory 119 for performing the operations described herein.

[0043] In one embodiment, a local media controller 135 of the memory device 130 may manage memory access operations performed on memory cells in the memory array 104 of the memory device 130. For example, the local media controller 135 may provide control signals to a driver or other circuitry associated with the memory array 104, including page buffer circuitry 160. In one embodiment, as part of a read operation or a program verification operation, page buffer circuitry 160 may include a sensing circuitry system that can sense the charge level stored in selected memory cells of the memory array 104. The page buffer circuitry may first precharge selected bit lines of the memory array 104 to a known voltage, and then, when a read voltage is applied to the selected word line of the memory array 104, page buffer circuitry 160 may sense the bit line voltage, which may remain high or discharge based on a threshold voltage of the read memory cell. In one embodiment, page buffer circuitry 160 includes a tail current biasing circuitry system 162 to improve sensing operations in the memory device 130. For example, as described in more detail below, tail current biasing circuitry system 162 may include a tail current capacitor or a network of one or more capacitors and / or switches (e.g., transistors) coupled to the bit line and used to generate a tail current during sensing operations (e.g., as part of a read or program verification operation). In one embodiment, one or more tail current capacitors are biased with a voltage signal that can ramp down during signal accumulation time, thereby generating a tail current on the bit line. Once the bit line reaches a steady state, both the cell current from the bit line and the tail current can accumulate at a temporary cache capacitor, resulting in a voltage drop at the temporary cache node. The rate of voltage drop can be used to identify the state of the cell read from the bit line. The presence of the tail current stabilizes the bit line, thereby reducing variability, improving the signal-to-noise ratio, and allowing detectors in the page buffer to more accurately distinguish between programming states (e.g., '0') and erase states (e.g., '1'). In other embodiments, the tail current capacitor is switched to generate a tail current on the bit line. In these embodiments, a switching network controlled by an alternating control signal alternately charges and discharges the tail current capacitor from the bit line to the source node (e.g., ground). The switching frequency can be used to more accurately control the magnitude of the tail current, which further improves the accuracy of the sensing operation in the page buffer circuit. Further details regarding the operation of the local media controller 135, the page buffer circuit 160, and the tail current biasing circuit system 162 are described below.

[0044] Figure 1B It is a memory subsystem according to an embodiment (e.g.) Figure 1AThis is a simplified block diagram of a first device in the form of a memory device 130 communicating with a second device in the form of a memory subsystem controller 115 (of a memory subsystem 110). Examples of electronic systems include personal computers, personal digital assistants (PDAs), digital cameras, digital media players, digital recorders, game consoles, home appliances, vehicles, wireless devices, mobile phones, and the like. The memory subsystem controller 115 (e.g., a controller external to the memory device 130) may be a memory controller or other external host device. In one embodiment, the memory subsystem controller 115 includes a memory interface 113.

[0045] Memory device 130 includes a memory cell array 104 logically arranged in rows and columns. Memory cells in logical rows are typically connected to the same access line (e.g., a word line), while memory cells in logical columns are typically selectively connected to the same data line (e.g., a bit line). A single access line may be associated with more than one logical row of memory cells, and a single data line may be associated with more than one logical column. At least a portion of the memory cells in memory cell array 104 ( Figure 1B (Not shown in the text) can be programmed to be one of at least two target data states.

[0046] Row decoding circuitry 108 and column decoding circuitry 109 are provided to decode address signals. Address signals are received and decoded to access memory cell array 104. Memory device 130 also includes input / output (I / O) control circuitry 180 to manage command, address, and data inputs to and from memory device 130. Address register 114 communicates with I / O control circuitry 180, row decoding circuitry 108, and column decoding circuitry 109 to latch address signals before decoding. Command register 124 communicates with I / O control circuitry 180 and local media controller 135 to latch incoming commands.

[0047] A controller (e.g., a local media controller 135 within memory device 130) controls access to memory cell array 104 in response to commands and generates status information for external memory subsystem controller 115. Specifically, the local media controller 135 is configured to perform access operations (e.g., read operations, program operations, and / or erase operations) on memory cell array 104. The local media controller 135 communicates with row decoding circuitry 108 and column decoding circuitry 109 to control them in response to addresses.

[0048] The local media controller 135 also communicates with cache register 172. Under the guidance of the local media controller 135, cache register 172 latches incoming or outgoing data to temporarily store data while memory cell array 104 is busy writing or reading other data. During programming operations (e.g., write operations), data can be transferred from cache register 172 to data register 170 for transfer to memory cell array 104; then, new data can be latched from I / O control circuitry system 180 into cache register 172. During read operations, data can be transferred from cache register 172 to I / O control circuitry system 180 for output to memory subsystem controller 115; then, new data can be transferred from data register 170 to cache register 172. Cache register 172 and / or data register 170 may form a page buffer 160 of memory device 130 (e.g., may form part of page buffer 160 of memory device 130). Page buffer 160 may further include sensing devices (e.g., included within page buffer 160) to sense the data state of memory cells in memory cell array 104 (e.g., by sensing the state of data lines (i.e., bit lines) connected to that memory cell). Status register 122 may communicate with I / O control circuitry system 180 and local memory controller 135 to latch status information for output to memory subsystem controller 115. Additionally, page buffer 160 may include tail current biasing circuitry system 162, which can generate tail current on the bit lines during sensing operations to improve the accuracy of sensing a given data state from memory cells in array 104.

[0049] Memory device 130 receives control signals from memory subsystem controller 115 via control link 182 at local media controller 135. For example, control signals may include a chip enable signal CE#, a command latch enable signal CLE, an address latch enable signal ALE, a write enable signal WE#, a read enable signal RE#, and a write protect signal WP#. Depending on the nature of memory device 130, additional or alternative control signals (not shown) may be received via control link 182. In one embodiment, memory device 130 receives command signals (representing commands), address signals (representing addresses), and data signals (representing data) from memory subsystem controller 115 via multiplexed input / output (I / O) bus 184 and outputs data to memory subsystem controller 115 via I / O bus 184.

[0050] For example, commands can be received at I / O control circuitry 180 via the input / output (I / O) pins [7:0] of I / O bus 184 and then written to command register 124. Addresses can be received at I / O control circuitry 180 via the input / output (I / O) pins [7:0] of I / O bus 184 and then written to address register 114. Data can be received at I / O control circuitry 180 via the input / output (I / O) pins [7:0] for 8-bit devices or the input / output (I / O) pins [15:0] for 16-bit devices and then written to cache register 172. The data can then be written to data register 170 for programming memory cell array 104.

[0051] In this embodiment, cache register 172 may be omitted, and data may be written directly to data register 170. Data may also be output via input / output (I / O) pins [7:0] for 8-bit devices or input / output (I / O) pins [15:0] for 16-bit devices. Although references may be made to I / O pins, they may include any conductive nodes, such as commonly used conductive pads or conductive bumps, that provide electrical connections to memory device 130 via external devices, such as memory subsystem controller 115.

[0052] Those skilled in the art will understand that additional circuitry and signals can be provided, and the system has been simplified. Figure 1B The memory device 130. It should be understood that, reference Figure 1B The functionality of the various block components described may not necessarily have to be separated into different components or component portions of the integrated circuit device. For example, a single component or component portion of the integrated circuit device may be adapted to perform... Figure 1B The functionality of more than one block component. Alternatively, one or more components or component portions of an integrated circuit device can be combined to perform... Figure 1B The functionality of a single block component. Additionally, while specific I / O pins have been described according to popular conventions for receiving and outputting various signals, it should be noted that other combinations or numbers of I / O pins (or other I / O node structures) may be used in various embodiments.

[0053] Figure 2 According to the embodiments, see reference Figure 1B A schematic diagram of a portion of a memory cell array 104 (e.g., a NAND memory array) used in a memory of the described type. The memory array 104 includes access lines (e.g., word lines 2020 to 202). N ) and data lines (e.g., bit lines 2040 to 204) M Word line 202 can be connected to global access lines (e.g., global word lines) in a many-to-one relationship. Figure 2(Not shown in the text). In some embodiments, the memory array 104 may be formed on a semiconductor, which may be conductively doped to have a conductivity type, such as p-type conductivity for forming a p-well or n-type conductivity for forming an n-well.

[0054] The memory array 104 can be arranged in rows (each corresponding to a word line 202) and columns (each corresponding to a bit line 204). Each column can contain a series of serially connected memory cells (e.g., non-volatile memory cells), such as NAND strings 2060 to 206. M One of them. Each NAND string 206 can be connected (e.g., selectively connected) to the common source (SRC) 216 and can contain memory cells 2080 to 208. N Memory cell 208 may represent a non-volatile memory cell used for data storage. The memory cells 208 of each NAND string 206 may be connected in series with select gate 210 (e.g., field-effect transistors) (e.g., select gates 2100 to 210). M One of them (e.g., it could be a source-select transistor, often referred to as a select-gate-source) and select gate 212 (e.g., a field-effect transistor) (e.g., select gates 2120 to 212) M Between one of them (for example, it could be a drain-select transistor, often referred to as a select gate-drain). Select gates 2100 to 210 M They can be connected together to select line 214 (e.g., source select line (SGS)), and select gates 2120 to 212. M They can be connected together to select line 215 (e.g., drain select line (SGD)). Although depicted as conventional field-effect transistors, select gates 210 and 212 can utilize a structure similar to (e.g., identical to) memory cell 208. Select gates 210 and 212 can represent several select gates connected in series, wherein each select gate is configured in series to receive the same or independent control signal.

[0055] The source of each select gate 210 can be connected to the common source 216. The drain of each select gate 210 can be connected to the memory cell 2080 of the corresponding NAND string 206. For example, the drain of select gate 2100 can be connected to the memory cell 2080 of the corresponding NAND string 2060. Therefore, each select gate 210 can be configured to selectively connect the corresponding NAND string 206 to the common source 216. The control gate of each select gate 210 can be connected to the select line 214.

[0056] The drain of each select gate 212 can be connected to bit line 204 for the corresponding NAND string 206. For example, the drain of select gate 2120 can be connected to bit line 2040 for the corresponding NAND string 2060. The source of each select gate 212 can be connected to memory cell 208 for the corresponding NAND string 206. N For example, the source of select gate 2120 can be connected to the memory cell 208 of the corresponding NAND string 2060. N Therefore, each select gate 212 can be configured to selectively connect the corresponding NAND string 206 to the corresponding bit line 204. The control gate of each select gate 212 can be connected to the select line 215.

[0057] Figure 2 The memory array 104 can be a quasi-two-dimensional memory array and can have a generally planar structure, for example, in which the common source 216, NAND string 206, and bit line 204 extend in a generally parallel plane. Alternatively, Figure 2 The memory array 104 in the memory array can be a three-dimensional memory array, for example, in which the NAND string 206 can extend substantially perpendicular to the plane containing the common source 216 and the plane containing the bit line 204, and the bit line 204 can extend substantially parallel to the plane containing the common source 216.

[0058] A typical configuration of memory cell 208 includes a data storage structure 234 (e.g., a floating gate, charge trap, or similar) and a control gate 236, such as a threshold voltage variation, which determine the data state of the memory cell. Figure 2 As shown in the diagram. Data storage structure 234 may include both conductive and dielectric structures, while control gate 236 is typically formed of one or more conductive materials. In some cases, memory cell 208 may further have a source / drain defining electrode (e.g., source) 230 and a source / drain defining electrode (e.g., drain) 232. Memory cell 208 connects its control gate 236 to (and in some cases forms) word line 202.

[0059] A row of memory cells 208 may be a NAND string 206 or several NAND strings 206 selectively connected to a given word line 204. A row of memory cells 208 may be memory cells 208 commonly connected to a given word line 202. A row of memory cells 208 may (but is not required to) contain all memory cells 208 commonly connected to a given word line 202. Several rows of memory cells 208 may typically be divided into one or more physical page groups of memory cells 208, and the physical pages of memory cells 208 typically contain every other memory cell 208 commonly connected to a given word line 202. For example, commonly connected to word line 202 NFurthermore, memory cells 208 selectively connected to even-numbered bit lines 204 (e.g., bit lines 2040, 2042, 2044, etc.) can be a physical page of memory cell 208 (e.g., an even-numbered memory cell), while those commonly connected to word line 202... N Furthermore, the memory cell 208 selectively connected to the odd bit line 204 (e.g., bit line 2041, 2043, 2045, etc.) can be another physical page of the memory cell 208 (e.g., an odd memory cell).

[0060] although Figure 2 Although bit lines 2043 to 2045 are not explicitly depicted in the figure, it is evident from the figure that bit lines 204 of the memory cell array 104 can be connected from bit line 2040 to bit line 2045. M Sequential numbering. Other groups of memory cells 208 commonly connected to a given word line 202 may also define physical pages of memory cells 208. For some memory devices, all memory cells commonly connected to a given word line may be considered physical pages of the memory cell. A portion of the physical page of a memory cell read during a single read operation or programmed during a single programmable operation (which in some embodiments may still be an entire line) (e.g., the upper or lower page of the memory cell) may be considered a logical page of the memory cell. A block of memory cells may contain those memory cells configured to be erased together, such as those connected to word lines 2020 to 202. N All memory cells (e.g., all NAND strings 206 sharing a common word line 202). Unless explicitly distinguished, a page memory cell in this document refers to a memory cell that is a logical page of the memory cell. Although discussed in conjunction with NAND flash memory. Figure 2 Examples are provided, but the embodiments and concepts described herein are not limited to a specific array architecture or structure, but may include other structures (e.g., SONOS, phase-change, ferroelectric, etc.) and other architectures (e.g., AND arrays, NOR arrays, etc.).

[0061] According to some embodiments of this disclosure Figure 3A This is a schematic diagram illustrating part of the page buffer circuit of a system with tail current biasing circuit. Figure 3B This is its timing diagram. For example, a page buffer 160 associated with the memory array 104 of memory device 130 may include a tail current biasing circuit system 162 corresponding to each bit line in array 104 and therefore to each vertical string of memory cells. In the illustrated embodiment, the tail current biasing circuit system 162 includes a tail current capacitor 302 having one terminal connected to a bit line 310 in memory array 104 and another terminal biased with a voltage signal (vbias). In one embodiment, this voltage signal is received from a signal generator (not shown) and may slope down from an initial voltage level to a lower voltage level over time, such as... Figure 3BAs shown in the timing diagram. In one embodiment, the page buffer circuit 160 further includes a sensing circuitry to sense the voltage read from bit line 310 based on the cell current (icell). In one embodiment, the sensing circuitry includes a series transistor, several switches, a temporary cache capacitor (ctc), and a detector transistor 342. When the first switch (sw1) is activated, bit line 310 can initially be pre-charged via a voltage signal received from the voltage source (vcc) via the series transistor 332 (which is controlled by a control signal (vcasc)). As the voltage signal (vbias) slopes down, a tail current (itail) is generated in bit line 310 to charge tail current capacitor 302. As the voltage on bit line 310 reaches a steady state, the first switch (sw1) can be deactivated, while the second switch (swtc) remains active to begin a signal accumulation period. During the signal accumulation period, both the cell current (icell) and tail current (itail) from the bit line can accumulate at the temporary cache capacitor (ctc), resulting in a voltage drop at the temporary cache (tc) node. The detector transistor 342 can be used to sample the voltage at the temporary cache (TC) node during the signal accumulation period. For example... Figure 3B As explained, the rate of voltage drop at the temporary cache (TC) node can be used to identify the state of the cell read from bit line 310. A lower voltage (cell 1) indicates a cell programmed with logic '1' and a higher voltage (cell 0) indicates a cell programmed with logic '0'. Deactivating the second switch (SWTC) ends the signal accumulation period.

[0062] According to some embodiments of this disclosure Figure 4A This is a schematic diagram illustrating part of the page buffer circuit of a system with tail current biasing circuit. Figure 4B This is its timing diagram. For example, a page buffer 160 associated with the memory array 104 of memory device 130 may include a tail current biasing circuit system 162 corresponding to each bit line in array 104 and therefore to each vertical string of memory cells. In the illustrated embodiment, the tail current biasing circuit system 162 includes two tail current capacitors 402 and 404. One terminal of capacitor 402 is connected to bit line 410 in memory array 104, and the other terminal is biased with a voltage signal (vbias). One terminal of capacitor 404 is connected to a temporary cache (TC) node, and the other terminal is biased with a voltage signal (vbias). As described above, this voltage signal is received from a signal generator (not shown) and may slope down from an initial voltage level to a lower voltage level over time, such as... Figure 4BAs shown in the timing diagram. Bit line 410 is initially precharged via a voltage signal received from the voltage source (VCC) via a series transistor 432 (which is controlled by a control signal (VCASC)). As the voltage signal (Vbias) slopes down, a tail current (itail) is generated in bit line 410 to charge tail current capacitor 402 and a tail current (itail) is drawn from the temporary cache (TC) node to charge tail current capacitor 404. As the voltage on bit line 410 reaches a steady state, a switch (SW) can be activated to begin the signal accumulation period. During the signal accumulation period, current accumulates at the temporary cache (TC) node, resulting in an increase in the voltage at the temporary cache (TC) node. This current at the temporary cache (TC) node represents the cell current (icell) from bit line 410, as the tail current (itail) from the second capacitor 404 compensates for the cell current (icell) added by the first capacitor 402. Detector transistor 442 can be used to sample the voltage at the temporary cache (tc) node during the signal accumulation period. For example... Figure 4B As explained, the rate of voltage increase at the temporary cache (TC) node can be used to identify the state of the cell read from bit line 310. A lower voltage (cell 0) indicates a cell programmed as logic '0' and a higher voltage (cell 1) indicates a cell programmed as logic '1'. The deactivation switch (SW) ends the signal accumulation period.

[0063] Figure 5 This is a flowchart illustrating an example method of performing a sensing operation in a memory device using tail current bias according to some embodiments of the present disclosure. Method 500 can be executed by processing logic, which may include hardware (e.g., processing device, circuitry, dedicated logic, programmable logic, microcode, device hardware, integrated circuits, etc.), software (e.g., instructions that run or execute on the processing device), or a combination thereof. In some embodiments, method 500 is performed by… Figure 1A and Figure 1B The process is executed by one or more of the memory subsystem controller 115, local media controller 135, and page buffer circuitry 160. Although shown in a specific sequence or order, the order of the processes may be modified unless otherwise specified. Therefore, the illustrated embodiments should be understood as examples only, and the illustrated processes may be executed in different orders, and some processes may be executed in parallel. In addition, one or more processes may be omitted in various embodiments. Therefore, not all processes are required in every embodiment. Other process flows are possible.

[0064] At operation 505, a read operation is initiated. For example, processing logic (e.g., memory subsystem controller 115) may initiate a read operation on the memory array 104 of memory device 130. Depending on the embodiment, the read operation may be initiated in response to a received request (e.g., from host system 120) or may be a programming verification operation (i.e., to verify that data has been correctly programmed into memory array 104). The read operation may point to a specific memory address in memory array 104, such as one or more memory cells located at the intersection of one or more word lines and one or more bit lines in memory array 104.

[0065] At operation 510, the bit lines are precharged. For example, processing logic (e.g., local media controller 135) may send a control signal (e.g., vcasc) to page buffer circuit 160 to activate a cascaded transistor (e.g., 332 or 432), which allows a voltage signal to precharge the selected bit lines (e.g., 310 or 410) associated with one or more memory cells to be read.

[0066] At operation 515, a read voltage is applied. For example, processing logic (e.g., local media controller 135) may send a control signal to an associated signal driver to cause a read voltage signal to be applied to a selected word line of the memory array 104 associated with one or more memory cells to be read.

[0067] At operation 520, the voltage signal is ramped. For example, processing logic (e.g., local media controller 135) may send a control signal to an associated signal driver to cause the voltage signal (vbias) applied to a terminal of a tail current capacitor (e.g., 302, 402, and / or 404) coupled to bit lines 310 or 410 to ramp down from an initial voltage level to a lower voltage level over time. As the voltage signal (vbias) ramps down, a tail current (itail) is generated in bit line 310 to charge tail current capacitor 302, or a tail voltage (itail) is generated in bit line 410 to charge tail current capacitor 402 and a tail voltage (itail) is drawn from a temporary cache (tc) node to charge tail current capacitor 404.

[0068] At operation 525, signal accumulation is performed. For example, processing logic (e.g., local media controller 135) may send a control signal to page buffer circuit 160 to deactivate switch (sw1) (e.g.) Figure 3A (as shown in the image) or activate the switch (sw) (e.g.) Figure 4A(As shown in the diagram) to initiate a signal accumulation period. In one embodiment, during the signal accumulation period, both the cell current (icell) and tail current (itail) from the bit line can accumulate at the temporary cache capacitor (ctc), resulting in a voltage drop at the temporary cache (tc) node. In another embodiment, current is accumulated at the temporary cache (tc) node, resulting in an increase in the voltage at the temporary cache (tc) node.

[0069] In operation 530, the voltage is sampled. For example, processing logic (e.g., local media controller 135) may send a control signal to page buffer circuit 160 to cause detector transistors (e.g., 342 or 442) to sample the voltage at the temporary cache (TC) node during the signal accumulation period. Figure 3B As explained, the rate of voltage drop at the temporary cache (TC) node can be used to identify the state of the cell read from bit line 310. A lower voltage (cell 1) indicates a cell programmed with logic '1' and a higher voltage (cell 0) indicates a cell programmed with logic '0'. Figure 4B As explained, the rate of voltage increase at the temporary cache (TC) node can be used to identify the state of the cell read from bit line 310. A lower voltage (cell 0) will indicate a cell programmed as logic '0' and a higher voltage (cell 1) will indicate a cell programmed as logic '1'.

[0070] According to some embodiments of this disclosure Figure 6A This is a schematic diagram illustrating part of the page buffer circuit in a system with a switching tail current bias circuit. Figure 6B This is its timing diagram. For example, a page buffer 160 associated with the memory array 104 of memory device 130 may include a tail current biasing circuit system 162 corresponding to each bit line in array 104 and thus to each vertical string of memory cells. In the illustrated embodiment, the tail current biasing circuit system 162 includes a tail current capacitor 602 having one terminal connected to the bit line 610 in memory array 104 via a switching network (e.g., a transistor) and another terminal coupled to ground (gnd). In one embodiment, the tail current capacitor 602 is coupled to the switching of the bit line via which is controlled by alternating control signals (P and Q), such as... Figure 6BAs shown in the timing diagram, bit line 610 can initially be pre-charged via voltage signals received from the voltage source (VCC) via transistors 632 and 634 (which are controlled by control signals bl_clamp and bl_clamp2, respectively). Switches controlled by control signals P and Q alternately charge and discharge tail current capacitor 602 from bit line 610 to the source node (e.g., ground), thereby generating a tail current (itail) in bit line 610. For example, when control signal P is activated, a tail current (itail) is generated in bit line 610 to charge tail current capacitor 602, and when control signal Q is activated, tail current capacitor 602 discharges to the source node. The switching frequencies of P and Q can be used to control the magnitude of the tail current (itail). Once the voltage on bit line 610 reaches a steady state, the signal accumulation period can begin. During this period, both the cell current (icell) and tail current (itail) from the bit line can accumulate at the temporary cache capacitor (ctc), causing a voltage drop at the temporary cache (tc) node. The voltage at the temporary cache (tc) node can be sampled during the signal accumulation period to determine the state of the read cell. For example... Figure 6B As explained, the rate of voltage drop at the temporary cache (TC) node can be used to identify the state of the cell read from bit line 610. A lower voltage (cell 1) indicates a cell programmed with logic '1' and a higher voltage (cell 0) indicates a cell programmed with logic '0'.

[0071] According to some embodiments of this disclosure Figure 7A This is a schematic diagram illustrating part of the page buffer circuit in a system with a switching tail current bias circuit. Figure 7B This is its timing diagram. For example, a page buffer 160 associated with the memory array 104 of memory device 130 may include a tail current biasing circuit system 162 corresponding to each bit line in array 104 and therefore to each vertical memory cell string. In the illustrated embodiment, the tail current biasing circuit system 162 includes two tail current capacitors 702 and 704. One terminal of capacitor 702 is connected to bit line 710, and the other terminal is coupled to the opposite side of a first switch controlled by control signal P. One terminal of capacitor 704 is connected to a source node (e.g., ground), and the other terminal is coupled to the opposite side of a second switch controlled by control signal Q. In one embodiment, the switch is controlled by alternating control signals (P and Q), such as Figure 7BAs shown in the timing diagram, bit line 710 is initially precharged via voltage signals received from the voltage source (VCC) via transistors 732 and 734 (which are controlled by control signals bl_clamp and bl_clamp2, respectively). Switches controlled by control signals P and Q alternately charge and discharge tail current capacitors 702 and 704 from bit line 710 to their source nodes (e.g., ground), thereby generating a tail current (itail) in bit line 710. For example, when control signal P is activated, a tail current (itail) is generated in bit line 710 to charge tail current capacitors 702 and 704, and when control signal Q is activated, tail current capacitors 702 and 704 discharge to their source nodes. In this way, tail current capacitors 702 and 704 are short-circuited one at a time to avoid interference to the bit line due to discharge occurring between the two pins. The switching frequency of P and Q can be used to control the magnitude of the tail current (itail). As the voltage on bit line 710 reaches a steady state, the signal accumulation period can begin. During this period, both the cell current (icell) and tail current (itail) from the bit line can accumulate at the temporary cache capacitor (ctc), causing a voltage drop at the temporary cache (tc) node. The voltage at the temporary cache (tc) node can be sampled during the signal accumulation period to determine the state of the read cell. For example... Figure 7B As explained, the rate of voltage drop at the temporary cache (TC) node can be used to identify the state of the cell read from bit line 710. A lower voltage (cell 1) will indicate a cell programmed as logic '1' and a higher voltage (cell 0) will indicate a cell programmed as logic '0'.

[0072] According to some embodiments of this disclosure Figure 8A This is a schematic diagram illustrating part of the page buffer circuit in a system with a switching tail current bias circuit. Figure 8B This is its timing diagram. For example, a page buffer 160 associated with the memory array 104 of memory device 130 may include a tail current biasing circuit system 162 corresponding to a pair of bit lines in array 104 and thus to a pair of vertical memory cell strings. In the illustrated embodiment, the tail current biasing circuit system 162 includes a tail current capacitor 802 having one terminal connected to bit line 810 (i.e., bit line a) in memory array 104 via a switching network (e.g., a transistor) and another terminal coupled to bit line 820 (i.e., bit line b) in memory array 104 via a separate switching network (e.g., a transistor). In one embodiment, bit line a is adjacent to bit line b. In one embodiment, the switching of the two networks is controlled by alternating control signals (P and Q), such as Figure 8BAs shown in the timing diagram. Bit lines 810 and 820 can initially be pre-charged via voltage signals received via transistors 832 and 834 (which are controlled by a shared control signal (vcasc)). Switches controlled by control signals P and Q alternately charge and discharge tail current capacitor 802 from bit line 810 to the source node (e.g., ground), thereby generating a tail current (itaila) in bit line 810. In a later cycle, tail current capacitor 802 is charged from bit line 820 to generate a tail voltage (itailb) in bit line 820. For example, when control signal P is activated, a tail current (itaila) is generated in bit line 810 to charge tail current capacitor 802, and when control signal Q is activated, a tail current (itailb) is generated in bit line 820 to charge tail current capacitor 802. The switching frequencies of P and Q can be used to control the magnitudes of the tail currents (itaila and itailb). Once the voltages on bit lines 810 and 820 reach a steady state, a signal accumulation period can begin, during which corresponding sensing capacitors (ca and cb) can be used to accumulate the corresponding current. The voltage can be sampled during the signal accumulation period to determine the state of the cell read on each corresponding word line. Through this arrangement of the tail current biasing circuitry system 162, a single tail current capacitor can be shared by multiple word lines, thereby reducing the total area of ​​the page buffer dedicated to tail current biasing and allowing data to be read from two word lines in a single operation.

[0073] According to some embodiments of this disclosure Figure 9A This is a schematic diagram illustrating part of the page buffer circuit in a system with a switching tail current bias circuit. Figure 9B This is its timing diagram. For example, a page buffer 160 associated with the memory array 104 of memory device 130 may include a tail current biasing circuit system 162 corresponding to a pair of bit lines in array 104 and thus to a pair of vertical memory cell strings. In the illustrated embodiment, the tail current biasing circuit system 162 includes a tail current capacitor 902 having one terminal connected to bit line a in memory array 104 via a switching network (e.g., a transistor) and another terminal coupled to bit line b in memory array 104 via a separate switching network (e.g., a transistor). In one embodiment, bit line a is adjacent to bit line b. In one embodiment, the switching of the two networks is controlled by alternating control signals (P and Q), such as... Figure 9BAs shown in the timing diagram, the bit lines are initially pre-charged via voltage signals received via transistors 932 and 934 (which are controlled by a shared control signal (vcasc)). Switches controlled by control signals P and Q alternately charge and discharge tail current capacitor 902 from the bit lines to the source node (e.g., ground), thereby generating a tail current (itaila) in bit line a. In a later cycle, the tail current capacitor is charged from bit line b to generate a tail current (itailb) in bit line b. For example, when control signal P is activated, a tail current (itaila) is generated in bit line a to charge tail current capacitor 902, and when control signal Q is activated, a tail current (itailb) is generated in bit line b to charge tail current capacitor 902. The switching frequencies of P and Q can be used to control the magnitudes of the tail currents (itaila and itailb). As the voltage on the bit lines reaches a steady state, a signal accumulation period can begin, during which corresponding sensing capacitors (ca and cb) can be used to accumulate the corresponding current. Voltage can be sampled during the signal accumulation period to determine the state of the cell read on each corresponding word line. Additionally, the tail current bias circuitry 162 is connected to bit line a via a separate switch 942 and to bit line b via a separate switch 944. Switches 942 and 944 are controlled using separate control signals from P and Q to provide self-reference capability and can be used to independently disconnect the sensing circuitry and tail current bias circuitry from the bit lines. In this way, the tail current bias circuitry 162 can be used to independently perform sensing operations on bit line a or bit line b without having to read data from both bit lines. Therefore, the voltage from the corresponding sensing capacitor can be sampled during the signal accumulation period to determine the state of the cell read. Figure 9B As explained, the voltage drop rate can be used to identify the state of a cell read from a bit line. A lower voltage (cell 1) will indicate a cell programmed as logic '1' and a higher voltage (cell 0) will indicate a cell programmed as logic '0'. In one embodiment, when a cell associated with bit line a is sensed, the tail current bias circuitry 162 introduces a voltage shift on bit line b to move the voltage between the voltages of cell 0 and cell 1 and generate a reference voltage that can be used to distinguish what data is being written using a differential method. The voltage shift on bit line a can be substituted when a cell associated with bit line b is sensed.

[0074] According to some embodiments of this disclosure Figure 10A This is a schematic diagram illustrating part of the page buffer circuit in a system with a switching tail current bias circuit. Figure 10BThis is its timing diagram. For example, a page buffer 160 associated with the memory array 104 of memory device 130 may include a tail current biasing circuit system 162 corresponding to a pair of bit lines in array 104 and thus to a pair of vertical memory cell strings. In the illustrated embodiment, the tail current biasing circuit system 162 includes a tail current capacitor 1002 having a terminal connected via a shared switching network (e.g., a transistor) to bit lines 1010 (i.e., bit line a) and 1020 (i.e., bit line b) in memory array 104. In one embodiment, bit line a is adjacent to bit line b. In one embodiment, the switch is controlled by alternating control signals (P1, P2, and Q), such as Figure 10B As shown in the timing diagram. Bit lines 1010 and 1020 can initially be pre-charged via voltage signals received via transistors 1032 and 1034 (which are controlled by a shared control signal (vcasc)). Switches controlled by control signals P1, P2, and Q alternately charge and discharge tail current capacitor 1002 from bit line 1010 to the source node (e.g., ground), thereby generating a tail current (itaila) in bit line 1010. In a later cycle, tail current capacitor 1002 is charged from bit line 1020 to generate a tail voltage (itailb) in bit line 1020. For example, when control signal P1 is activated, a tail current (itaila) is generated in bit line 1010 to charge tail current capacitor 1002, and when control signal P2 is activated, a tail current (itailb) is generated in bit line 1020 to charge tail current capacitor 1002. When control signal Q is activated, tail current capacitor 1002 discharges to the source node (e.g., ground). The switching frequencies of P1, P2, and Q can be used to control the magnitude of the tail currents (itaila and itailb). For example, the frequency of control signal Q can be twice as fast as the frequencies of control signals P1 and P2, such as... Figure 10B As shown in the timing diagram, the signal accumulation period can begin as the voltages on bit lines 1010 and 1020 reach a steady state, during which corresponding sensing capacitors (ca and cb) can be used to accumulate the corresponding current. The voltage can be sampled during the signal accumulation period to determine the state of the cell read on each corresponding word line. Through this arrangement of the tail current bias circuitry system 162, a single tail current capacitor can be shared by multiple word lines, thereby reducing the total area of ​​the page buffer dedicated to tail current bias and allowing data to be read from two word lines in a single operation.

[0075] Figure 11 An example machine illustrating computer system 1100 is described, within which a set of instructions is executable to cause the machine to perform any or more of the methods discussed herein. In some embodiments, computer system 500 may correspond to a host system (e.g., Figure 1AThe host system 120 includes, is coupled to, or utilizes a memory subsystem (e.g., a memory subsystem). Figure 1A The memory subsystem 110) or can be used to perform controller operations (e.g., to execute an operating system to perform operations corresponding to...). Figure 1A (Operation of the memory subsystem controller 115 or local media controller 135). In alternative embodiments, the machine may be connected (e.g., networked) to other machines in a LAN, intranet, extranet, and / or the Internet. The machine may operate as a server or client machine in a client-server network environment, as a peer machine in a peer-to-peer (or distributed) network environment, or as a server or client machine in a cloud computing infrastructure or environment.

[0076] The machine may be a personal computer (PC), tablet PC, set-top box (STB), personal digital assistant (PDA), cellular phone, network device, server, network router, switch, or bridge, or any machine capable of executing a set of instructions (sequentially or otherwise) specifying actions to be taken by the machine. Furthermore, although a single machine is described, the term "machine" should also be considered as encompassing any collection of machines that individually or collectively execute a set (or more) of instructions to perform any or more of the methods discussed herein.

[0077] The example computer system 1100 includes a processing device 1102, a main memory 1104 (e.g., read-only memory (ROM), flash memory, dynamic random access memory (DRAM) (e.g., synchronous DRAM (SDRAM) or Rambus DRAM (RDRAM)), etc.), a static memory 1106 (e.g., flash memory, static random access memory (SRAM), etc.), and a data storage system 1118, which communicate with each other via a bus 1130.

[0078] Processing device 1102 represents one or more general-purpose processing devices, such as a microprocessor, central processing unit, or the like. More specifically, the processing device may be a Complex Instruction Set Computing (CISC) microprocessor, a Reduced Instruction Set Computing (RISC) microprocessor, a Very Long Instruction Word (VLIW) microprocessor, or a processor implementing other instruction sets, or several processors implementing combinations of instruction sets. Processing device 1102 may also be one or more special-purpose processing devices, such as application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), digital signal processors (DSPs), network processors, or the like. Processing device 1102 is configured to execute instructions 1126 for performing the operations and steps discussed herein. Computer system 1100 may further include a network interface device 1108 for communication via network 1120.

[0079] Data storage system 1118 may include machine-readable storage medium 1124 (also referred to as computer-readable medium) storing one or more sets of instructions 1126 or software embodying any or more of the methods or functions described herein. Instructions 1126 may also reside wholly or at least partially within main memory 1104 and / or processing device 1102 during execution by computer system 1100, which also constitute machine-readable storage medium. Machine-readable storage medium 1124, data storage system 1118, and / or main memory 1104 may correspond to... Figure 1A The memory subsystem 110.

[0080] In one embodiment, instruction 1126 includes instructions for implementing the corresponding Figure 1A The memory subsystem controller 115 or local media controller 135 provides functional instructions. Although the machine-readable storage medium 1124 is shown as a single medium in the exemplary embodiment, the term "machine-readable storage medium" should be considered as a single medium or multiple media containing one or more sets of instructions. The term "machine-readable storage medium" should also be considered as any medium capable of storing or encoding a set of instructions for machine execution and causing the machine to perform any or more of the methods of this disclosure. Therefore, the term "machine-readable storage medium" should be considered as including (but not limited to) solid-state memory, optical media, and magnetic media.

[0081] Some parts of the foregoing detailed description have been presented based on the algorithms and symbolic representations of operations on data bits within computer memory. These algorithmic descriptions and representations are the means by which those skilled in the art of data processing most effectively communicate the essence of their work to others skilled in the art. Algorithms are generally conceived herein as self-consistent sequences of operations that lead to desired results. Operations are operations that require the physical manipulation of physical quantities. Usually, but not always, these quantities take the form of electrical or magnetic signals that can be stored, combined, compared, and otherwise manipulated. It has proven convenient, sometimes primarily for general reasons, to refer to these signals as bits, values, elements, symbols, characters, items, numbers, or the like.

[0082] However, it should be remembered that all these and similar terms should be associated with appropriate physical quantities and are merely convenient labels for application to those quantities. This disclosure may relate to the operation and processes of a computer system or similar electronic computing device that manipulate and transform data representing physical (electronic) quantities in the registers and memories of the computer system into other data similarly represented in the memory or registers of the computer system or other such information storage systems.

[0083] This disclosure also relates to apparatus for performing the operations described herein. Such apparatus may be specifically constructed for its intended purpose, or may comprise a general-purpose computer selectively activated or reconfigured by a computer program stored in a computer. This computer program may be stored in a computer-readable storage medium, such as (but not limited to) any type of disk (including floppy disks, optical disks, CD-ROMs, and magneto-optical disks), read-only memory (ROM), random access memory (RAM), EPROM, EEPROM, magnetic cards, or optical cards, or any type of media suitable for storing electronic instructions, each coupled to a computer system bus.

[0084] The algorithms and displays presented herein are not inherently related to any particular computer or other device. Various general-purpose systems can be used with programs based on the teachings herein, or it may prove convenient to construct more specialized devices to perform the methods. The structures of various such systems will appear as set forth in the appended claims. Furthermore, this disclosure is described without reference to any particular programming language. It should be understood that the teachings of this disclosure described herein can be implemented using various programming languages.

[0085] This disclosure may be provided as a computer program product or software, which may include a machine-readable medium having instructions stored thereon, the instructions being usable to program a computer system (or other electronic device) to perform processes according to this disclosure. The machine-readable medium includes any mechanism for storing information in a form readable by a machine (e.g., a computer). In some embodiments, the machine-readable (e.g., computer-readable) medium includes machine-readable storage media, such as read-only memory (“ROM”), random access memory (“RAM”), disk storage media, optical storage media, flash memory components, etc.

[0086] In the foregoing description, embodiments of the present disclosure have been described with reference to specific examples. It will be apparent that various modifications can be made to the embodiments of the present disclosure without departing from the broader spirit and scope set forth in the appended claims. Therefore, the specification and drawings should be considered illustrative rather than limiting.

Claims

1. A memory device comprising: a memory array comprising a plurality of memory cells formed at respective intersections of a plurality of word lines and a plurality of bit lines; and a page buffer circuit coupled to the memory array, the page buffer circuit comprising sensing circuitry for measuring a cell current read from a bit line of the plurality of bit lines and tail current biasing circuitry coupled to the bit line, wherein the tail current biasing circuitry comprises a tail current capacitor having a first terminal coupled to the bit line, the tail current capacitor for generating a tail current in the bit line when the sensing circuitry measures the cell current read from the bit line during a signal accumulation period.

2. The memory device of claim 1, wherein the sensing circuitry comprises a series transistor coupled to the bit line, a temporary cache capacitor coupled to a temporary cache node, and a detector transistor coupled to the temporary cache node, and wherein the temporary cache transistor is for accumulating the cell current measured from the bit line during the signal accumulation period.

3. The memory device of claim 2, wherein a bias voltage applied to a second terminal of the tail current capacitor is ramped down over time to generate the tail current in the bit line.

4. The memory device of claim 3, wherein the tail current biasing circuitry comprises a second tail current capacitor having a first terminal coupled to the temporary cache node and a second terminal for receiving the bias voltage, wherein the second tail current capacitor is for generating a second tail current in the bit line during the signal accumulation period.

5. The memory device of claim 2, wherein the tail current capacitor is coupled to the bit line through a plurality of switches, and wherein the plurality of switches are controlled by alternating control signals to alternately generate the tail current in the bit line to charge the tail current capacitor and discharge the tail current capacitor to a source node.

6. The memory device of claim 5, wherein the tail current biasing circuitry comprises a plurality of tail current capacitors coupled to the bit line through the plurality of switches.

7. The memory device of claim 5, wherein the tail current capacitor is coupled between the bit line and an adjacent bit line through the plurality of switches.

8. The memory device of claim 7, wherein the bit line and the adjacent bit line comprise respective self-reference switches to independently disconnect the sensing circuitry from the tail current biasing circuitry.

9. A page buffer circuit comprising: sensing circuitry for measuring a cell current read from a bit line of a plurality of bit lines of a memory array; and tail current biasing circuitry coupled to the bit line, wherein the tail current biasing circuitry comprises a tail current capacitor having a first terminal coupled to the bit line, the tail current capacitor for generating a tail current in the bit line when the sensing circuitry measures the cell current read from the bit line during a signal accumulation period.

10. The page buffer circuit of claim 9, wherein the sense circuitry comprises a string transistor coupled to the bit line, a temporary cache capacitor coupled to a temporary cache node, and a detector transistor coupled to the temporary cache node, and wherein the temporary cache transistor is to accumulate the cell current measured from the bit line during the signal accumulation period.

11. The page buffer circuit of claim 10, wherein a bias voltage applied to a second terminal of the tail current capacitor is ramped down over time to generate the tail current in the bit line.

12. The page buffer circuit of claim 11, wherein the tail current bias circuitry comprises a second tail current capacitor having a first terminal coupled to the temporary cache node and a second terminal to receive the bias voltage, wherein the second tail current capacitor is to generate a second tail current in the bit line during the signal accumulation period.

13. The page buffer circuit of claim 10, wherein the tail current capacitor is coupled to the bit line through a plurality of switches, and wherein the plurality of switches are controlled by alternating control signals to alternately generate the tail current in the bit line to charge the tail current capacitor and discharge the tail current capacitor to a source node.

14. The page buffer circuit of claim 13, wherein the tail current bias circuitry comprises a plurality of tail current capacitors coupled to the bit line through the plurality of switches.

15. The page buffer circuit of claim 13, wherein the tail current capacitor is coupled between the bit line and a neighboring bit line through the plurality of switches.

16. The page buffer circuit of claim 15, wherein the bit line and the neighboring bit line comprise respective self-referencing switches to independently disconnect the sense circuitry from the tail current bias circuitry.

17. A memory device comprising: a memory array comprising a plurality of memory cells formed at respective intersections of a plurality of word lines and a plurality of bit lines; a page buffer circuit coupled to the memory array, the page buffer circuit comprising sense circuitry to measure a cell current read from a bit line of the plurality of bit lines and tail current bias circuitry coupled to the bit line, wherein the tail current bias circuitry comprises a tail current capacitor having a first terminal coupled to the bit line, the tail current capacitor to generate a tail current in the bit line when the sense circuitry measures the cell current read from the bit line during a signal accumulation period; and control logic operably coupled to the memory array and the page buffer circuit to perform operations comprising: causing the bit line to be pre-charged; causing a read voltage to be applied to a word line of the plurality of word lines; and causing a bias voltage applied to a second terminal of the tail current capacitor to be ramped down over time to generate the tail current in the bit line. ​ 18. The memory device of claim 17, wherein the sense circuitry comprises a string transistor coupled to the bit line, a temporary cache capacitor coupled to a temporary cache node, and a detector transistor coupled to the temporary cache node.

19. The memory device of claim 18, wherein the control logic is to perform operations further comprising: causing the temporary cache transistor to accumulate the cell current measured from the bit line during the signal accumulation period.

20. The memory device of claim 19, wherein the tail current bias circuitry comprises a second tail current capacitor having a first terminal coupled to the temporary cache node and a second terminal to receive the bias voltage, wherein the second tail current capacitor is to generate a second tail current in the bit line during the signal accumulation period.

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