Memory array driving circuit and operating method thereof

Abstract

The invention provides a memory array driving circuit and an operation method thereof, the memory array driving circuit comprises a first N-type transistor and a second N-type transistor, the grid electrode of the first N-type transistor is connected with a selected turn-on voltage, the drain electrode of the first N-type transistor is connected with a write operation voltage or a read operation voltage, and the source electrode of the first N-type transistor is connected with a control line and / or an address line of a memory; the grid electrode of the second N-type transistor is connected with non-selected turn-on voltage, the drain electrode is connected with the source electrode of the first N-type transistor, and the source electrode is connected with non-selected voltage; the write-in operation voltage and the read-out operation voltage are conducted by adopting the same N-type driving transistor, and a higher voltage can be applied to the grid electrode of the N-type driving transistor, so that the on-resistance can be reduced; the circuit area is small; in write and read operations, the gate of the first N-type transistor is made to have the ability to turn on a higher write operation voltage and a lower read operation voltage at the same time by applying a high voltage to the gate of the first N-type transistor.

Description

Technical Field

[0001] This application relates to the field of semiconductor storage technology, and in particular to a storage array driving circuit and its operation method. Background Technology

[0002] A memory array typically refers to an array of a certain number of rows and columns based on a specific type of memory device, such as SRAM arrays, DRAM arrays, RRAM arrays, and Flash arrays. Memory arrays generally have word lines and bit lines, and some memory arrays also have source lines. Word lines and bit lines are perpendicular to each other. The intersection of each word line and each bit line corresponds to a memory device. For each word line and each bit line, a driver circuit structure is required to connect to the operating voltage when selected and to the non-selected voltage when not selected.

[0003] During write operations, the voltage applied to the word lines and bit lines (and in some memory arrays, the source lines) of a memory array is typically much higher than that applied during read operations. For example, in an RRAM array, the voltage applied to the word lines and bit lines during write operations is typically greater than 2V, while during read operations, the voltage applied to the word lines and bit lines is typically less than 1V. Traditional array driver circuits fall into two categories: one uses P-type transistors to transmit the write and read operation voltages, and the other uses separate P-type and N-type transistors to transmit the write and read operation voltages. The first method has the disadvantage that, during read operations, the P-type transistor has a weak turn-on amplitude due to the lower voltage, resulting in higher on-resistance. The second method has the disadvantage that using both P-type and N-type transistors increases the area of ​​the array driver circuit. Summary of the Invention

[0004] This application provides a memory array driving circuit and its operation method to at least partially solve one of the technical problems in the related art. The technical solution of this disclosure is as follows: In a first aspect, embodiments of this application propose a memory array driving circuit, including a first N-type transistor and a second N-type transistor. The gate of the first N-type transistor is connected to a selection enable voltage, the drain of the first N-type transistor is connected to a write operation voltage or a read operation voltage, and the source of the first N-type transistor is connected to the memory's control line and / or address line. The gate of the second N-type transistor is connected to a non-selection enable voltage, the drain of the second N-type transistor is connected to the source of the first N-type transistor, and the source of the second N-type transistor is connected to a non-selection voltage. Secondly, embodiments of this application propose an operation method for a memory array driving circuit, wherein the memory array driving circuit is the memory array driving circuit described in the first aspect, and the method includes: When a write operation is in progress and the control line and / or address line connected to the source of the first N-type transistor are selected, the first N-type transistor is turned on by applying a first selected enable voltage to its gate, and the second N-type transistor is turned off by applying a first unselected enable voltage to its gate; wherein the first selected enable voltage is greater than the sum of the write operation voltage and the threshold voltage of the first N-type transistor.

[0005] In some implementations, the method further includes: When in a readout operation and the control line and / or address line connected to the source of the first N-type transistor are selected, the first N-type transistor is turned on by applying a second selected enable voltage to its gate, and the second N-type transistor is turned off by applying a second unselected enable voltage to its gate; wherein the second selected enable voltage is greater than the sum of the readout operation voltage and the threshold voltage of the first N-type transistor.

[0006] In some implementations, the method further includes: When the control line and / or address line connected to the source of the first N-type transistor is not selected, the first N-type transistor is turned off by applying a third selected enable voltage to the gate of the first N-type transistor, and the second N-type transistor is turned on by applying a third unselected enable voltage to the gate of the second N-type transistor; wherein the third unselected enable voltage is greater than the sum of the unselected voltage and the threshold voltage of the second N-type transistor.

[0007] In some implementations, the first selected activation voltage is greater than the second selected activation voltage.

[0008] In some implementations, the first non-selection enable voltage and the second non-selection enable voltage are both 0.

[0009] In some implementations, the third selected turn-on voltage is 0.

[0010] The memory array driving circuit and its operation method provided in this application use the same N-type driving transistor to conduct the write operation voltage and read operation voltage. The gate of the N-type driving transistor can be subjected to a higher voltage, thereby reducing the on-resistance. Furthermore, since only the same transistor type is used to conduct the write operation voltage and read operation voltage, the circuit area is smaller. During write and read operations, by applying a high voltage to the gate of the first N-type transistor, it is made capable of conducting both a higher write operation voltage and a lower read operation voltage simultaneously, thus solving the problem that the memory array driving circuit needs to simultaneously meet the write operation voltage and read operation voltage requirements while having low on-resistance and a small area.

[0011] Additional aspects and advantages of this application will be set forth in part in the description which follows, and in part will be obvious from the description, or may be learned by practice of this application. Attached Figure Description

[0012] The above and / or additional aspects and advantages of this application will become apparent and readily understood from the following description of the embodiments taken in conjunction with the accompanying drawings, wherein: Figure 1 This is a schematic diagram of the structure of a memory array driver circuit provided in an embodiment of this application; Figure 2 This is a flowchart illustrating an operation method of a memory array driver circuit provided in an embodiment of this application. Detailed Implementation

[0013] The embodiments of this application are described in detail below. Examples of these embodiments are shown in the accompanying drawings, wherein the same or similar reference numerals denote the same or similar elements or elements having the same or similar functions throughout. The embodiments described below with reference to the accompanying drawings are exemplary and intended to explain this application, and should not be construed as limiting this application.

[0014] The memory array driving circuit and its operation method according to embodiments of this application are described below with reference to the accompanying drawings.

[0015] Figure 1 This is a schematic diagram of a memory array driver circuit provided in an embodiment of this application. Figure 1As shown, the memory array driving circuit includes a first N-type transistor M0 and a second N-type transistor M1. The gate of the first N-type transistor M0 is connected to the selection enable voltage V1, the drain of the first N-type transistor M0 is connected to the write operation voltage V3 or the read operation voltage V4, and the source of the first N-type transistor M0 is connected to the memory's control lines and / or address lines. The gate of the second N-type transistor M1 is connected to the non-selection enable voltage V2, the drain of the second N-type transistor M1 is connected to the source of the first N-type transistor M0, and the source of the second N-type transistor M1 is connected to the non-selection voltage V5. The memory's control lines and / or address lines include word lines and bit lines, and may also include source lines.

[0016] This can be understood as follows: M0 is an N-type transistor that turns on when the word line / bit line / source line is selected; M1 is an N-type transistor that turns on when it is not selected. The gate of M0 is connected to the selection enable voltage V1, the drain is connected to the write operation voltage V3 or the read operation voltage V4, and the source is connected to the word line, bit line, or source line. When the word line, bit line, or source line is selected, the selector is turned on by applying the selection enable voltage V1 to the gate of M0, thus realizing the write operation or read operation. The gate of M1 is connected to the non-selection enable voltage V2. When the word line, bit line, or source line is selected, the selector M1 is turned off by applying the non-selection enable voltage V2 to the gate of M1.

[0017] The memory array driving circuit of this application embodiment uses the same N-type driving transistor to turn on the write operation voltage and read operation voltage. The gate of the N-type driving transistor can be subjected to a higher voltage, thereby reducing the on-resistance. Lower on-resistance generally means that the data written and read has stronger reliability under the same write or read operation conditions. Moreover, since only the same transistor type is used to turn on the write operation voltage and read operation voltage, the circuit area is smaller.

[0018] Based on the above embodiments, Figure 2 This is a flowchart illustrating an operation method of a memory array driver circuit provided in an embodiment of this application, as shown below. Figure 2 As shown, the operation method of the memory array drive circuit includes the following steps: Step S201: When in a write operation and the control line and / or address line connected to the source of the first N-type transistor are selected, the first N-type transistor is turned on by applying a first selected enable voltage to the gate of the first N-type transistor, and the second N-type transistor is turned off by applying a first unselected enable voltage to the gate of the second N-type transistor; wherein, the first selected enable voltage is greater than the sum of the write operation voltage and the threshold voltage of the first N-type transistor.

[0019] In some embodiments, the first non-selected turn-on voltage.

[0020] In other words, during a write operation, if the word line / bit line / source line corresponding to the first N-type transistor is selected (determined by the preceding decoding circuit based on the address signal), then M0 is turned on and M1 is turned off. The first selected enable voltage is greater than the sum of the write operation voltage and the threshold voltage of M0 to ensure that the write operation voltage is conducted to the word line / bit line / source line. The higher the first selected enable voltage, the lower the on-resistance of M0. The first unselected enable voltage needs to ensure that M1 is turned off, which is usually zero voltage.

[0021] Step S202: When in readout operation and the control line and / or address line connected to the source of the first N-type transistor are selected, the first N-type transistor is turned on by applying a second selected turn-on voltage to the gate of the first N-type transistor, and the second N-type transistor is turned off by applying a second unselected turn-on voltage to the gate of the second N-type transistor; wherein the second selected turn-on voltage is greater than the sum of the readout operation voltage and the threshold voltage of the first N-type transistor.

[0022] In some embodiments, the first selected activation voltage is greater than the second selected activation voltage.

[0023] In some embodiments, the second non-selected turn-on voltage is 0.

[0024] In other words, during a read operation, if the word line / bit line / source line corresponding to the first N-type transistor is selected, then M0 is turned on and M1 is turned off. The second selection turn-on voltage is greater than the sum of the read operation voltage and the threshold voltage of M0 to ensure that the read operation voltage is conducted to the word line / bit line / source line. The higher the second selection turn-on voltage, the lower the on-resistance of M0. The second non-selection turn-on voltage needs to ensure that M1 is turned off, and is usually zero voltage.

[0025] Step S203: When the control line and / or address line connected to the source of the first N-type transistor are not selected, the first N-type transistor is turned off by applying a third selected turn-on voltage to the gate of the first N-type transistor, and the second N-type transistor is turned on by applying a third unselected turn-on voltage to the gate of the second N-type transistor; wherein the third unselected turn-on voltage is greater than the sum of the unselected voltage and the threshold voltage of the second N-type transistor.

[0026] In some embodiments, the third selected turn-on voltage is 0.

[0027] In other words, if the word line / bit line / source line corresponding to the first N-type transistor is not selected, then M1 is turned on and M0 is turned off. The third non-selection turn-on voltage needs to exceed the sum of the non-selection voltage and the threshold voltage of M1 to ensure that the non-selection voltage is transmitted to the word line / bit line / source line. When non-selected, since no write or read operation is required, a very small on-resistance is usually not needed. The selection turn-on voltage needs to ensure that the M0 transistor is turned off, and is usually zero voltage.

[0028] The operation method of the memory array driving circuit in this application embodiment applies a high voltage to the gate of the first N-type transistor during write and read operations, enabling it to simultaneously have the ability to conduct a higher write operation voltage and a lower read operation voltage. This solves the problem that the memory array driving circuit needs to simultaneously meet the write operation voltage and read operation voltage, and has low on-resistance and small area, thereby improving the reliability of read and write operations.

[0029] In the foregoing descriptions of the embodiments, the terms "one embodiment," "some embodiments," "example," "specific example," or "some examples," etc., refer to specific features, structures, materials, or characteristics described in connection with that embodiment or example, which are included in at least one embodiment or example of this application. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples. Moreover, without contradiction, those skilled in the art can combine and integrate the different embodiments or examples described in this specification, as well as the features of different embodiments or examples.

[0030] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include at least one of that feature. In the description of this application, "multiple" means at least two, such as two, three, etc., unless otherwise explicitly specified.

[0031] Although embodiments of this application have been shown and described above, it is understood that the above embodiments are exemplary and should not be construed as limiting this application. Those skilled in the art can make changes, modifications, substitutions and variations to the above embodiments within the scope of this application.

Claims

1. A memory array drive circuit, comprising: The first N-type transistor has a gate connected to a selected-on voltage, a drain connected to a write operation voltage or a read operation voltage, and a source connected to a control line and / or an address line of a memory; the second N-type transistor has a gate connected to a non-selected-on voltage, a drain connected to the source of the first N-type transistor, and a source connected to a non-selected voltage.

2. A method of operating a memory array drive circuit, comprising: The memory array driving circuit is the memory array driving circuit of claim 1, and the method comprises: In a case where a write operation is performed and the control line and / or the address line connected to the source of the first N-type transistor is selected, the first N-type transistor is turned on by applying a first selected-on voltage to the gate of the first N-type transistor, and the second N-type transistor is turned off by applying a first non-selected-on voltage to the gate of the second N-type transistor; wherein the first selected-on voltage is greater than the sum of the write operation voltage and the threshold voltage of the first N-type transistor.

3. The method of claim 2, wherein, The method further comprises: In a case where a read operation is performed and the control line and / or the address line connected to the source of the first N-type transistor is selected, the first N-type transistor is turned on by applying a second selected-on voltage to the gate of the first N-type transistor, and the second N-type transistor is turned off by applying a second non-selected-on voltage to the gate of the second N-type transistor; wherein the second selected-on voltage is greater than the sum of the read operation voltage and the threshold voltage of the first N-type transistor.

4. The method according to claim 2 or 3, characterized in that, The method further comprises: In a case where the control line and / or the address line connected to the source of the first N-type transistor is not selected, the first N-type transistor is turned off by applying a third selected-on voltage to the gate of the first N-type transistor, and the second N-type transistor is turned on by applying a third non-selected-on voltage to the gate of the second N-type transistor; wherein the third non-selected-on voltage is greater than the sum of the non-selected voltage and the threshold voltage of the second N-type transistor.

5. The method of claim 3, wherein, The first selected-on voltage is greater than the second selected-on voltage.

6. The method of claim 3, wherein, The first non-selected-on voltage and the second non-selected-on voltage are 0.

7. The method of claim 3, wherein, The third selected-on voltage is 0.

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