Memory device with failed primary library repair using redundant libraries

Abstract

The invention relates to a memory device with failed primary library repair using redundant libraries. In certain aspects, a memory device includes an array of memory cells, an input / output (I / O) circuit, and control logic coupled to the I / O circuit. The memory cell array includes N primary banks and M redundant banks, where each of N and M is a positive integer, and N is greater than M. The I / O circuitry is coupled to the N primary libraries and the M redundant libraries, and is configured to direct the N data fragments to or from the N working libraries, respectively. The control circuit is configured to determine N working libraries from the N primary libraries and the M redundant libraries based on library failure information indicating K failed primary libraries of the N primary libraries. The N work libraries comprise K redundant libraries in the M redundant libraries, and K is a positive integer not greater than M. The control circuit is further configured to control the I / O circuit to direct K of the N data segments to the K redundancy libraries or to direct K of the N data segments from the K redundancy libraries, respectively.

Description

Case Analysis

[0001] This application is a divisional application of Chinese patent application No. 202180000863.7, filed on March 24, 2021, entitled "Memory Device with Fault Master Library Repair Using Redundant Library". Technical Field

[0002] This disclosure relates to memory devices and methods of operating thereof. Background Technology

[0003] Flash memory is a low-cost, high-density, non-volatile solid-state storage medium that can be electrically erased and reprogrammed. Flash memory includes NOR flash memory and NAND flash memory. As the number of memory cells in flash memory continues to increase, faulty (bad) memory cells may occur during the manufacturing process of memory devices.

[0004] For example, most NAND flash memory devices are shipped from foundries with a number of faulty memory cells. These cells are typically identified according to a specified faulty cell labeling policy. By allowing for some bad cells, manufacturers can achieve higher yields than would be possible if all cells had to be verified as good. This significantly reduces the cost of NAND flash memory and only slightly reduces the storage capacity of the device. Summary of the Invention

[0005] In one aspect, a memory device includes a memory cell array, input / output (I / O) circuitry, and control logic coupled to the I / O circuitry. The memory cell array includes... N individual master databases and M There are redundant libraries, among which... N and M Each of the elements is a positive integer, and N Greater than M I / O circuits are coupled to N individual master databases and M A redundant library, and configured to respectively... N A data fragment leads to N A work library or from N Work library guidance N A data segment. The control circuit is configured to be based on an indication. N In each master database K The database fault information of each faulty master database is obtained from N individual master databases and M One redundant library is determined N A work library. N The work library includes M In a redundant library K There are redundant libraries, among which...K Not greater than M Positive integers. The control circuit is also configured to control the I / O circuitry to respectively... N In the data fragments K A data fragment leads to K A redundant library or from K A redundant library boot N In the data fragments K A data fragment.

[0006] In another aspect, a system includes a memory device configured to store data and a memory controller coupled to the memory device and configured to control the memory device. The memory device includes a memory cell array, I / O circuitry, and control logic coupled to the I / O circuitry. The memory cell array includes... N individual master databases and M There are redundant libraries, among which... N and M Each of the elements is a positive integer, and N Greater than M I / O circuits are coupled to N individual master databases and M A redundant library, and configured to respectively... N A data fragment leads to N A work library or from N Work library guidance N A data segment. The control circuit is configured to be based on an indication. N In each master database K The database fault information of each faulty master database is obtained from N individual master databases and M One redundant library is determined N A work library. N The work library includes M In a redundant library K There are redundant libraries, among which... K Not greater than M Positive integers. The control circuit is also configured to control the I / O circuitry to respectively... N In the data fragments K A data fragment leads to K A redundant library or from K A redundant library boot N In the data fragments K A data fragment.

[0007] In another aspect, a method for operating a memory device is provided. The memory device includes a memory cell array, the memory cell array including... N individual master databases and M There are redundant libraries, among which...N and M Each of the elements is a positive integer, and N Greater than M Based on instructions N In each master database K The database fault information of each faulty master database is obtained from N individual master databases and M One redundant library is determined N A work library. N The work library includes M In a redundant library K There are redundant libraries, among which... K Not greater than M Positive integers. (The remaining text appears to be incomplete and requires further context.) N In the data fragments K A data fragment leads to K A redundant library or from K A redundant library boot N In the data fragments K A data fragment. Attached Figure Description

[0008] The accompanying drawings, which are incorporated herein and form part of the specification, illustrate aspects of this disclosure and, together with the description, further serve to explain the principles of this disclosure and enable those skilled in the art to make and use this disclosure.

[0009] Figure 1 A block diagram of an exemplary system having a memory device according to some aspects of this disclosure is shown.

[0010] Figure 2A An illustration of an exemplary memory card having a memory device according to some aspects of this disclosure is shown.

[0011] Figure 2B An illustration of an exemplary solid-state drive (SSD) having a memory device according to some aspects of this disclosure is shown.

[0012] Figure 3 A schematic diagram of an exemplary memory device including peripheral circuitry according to some aspects of this disclosure is shown.

[0013] Figure 4 A block diagram of an exemplary memory device including a memory cell array and peripheral circuitry according to some aspects of this disclosure is shown.

[0014] Figure 5 A block diagram of a memory device is shown, illustrating a fault master library repair scheme using a redundant library.

[0015] Figure 6A and Figure 6B It shows the use of by Figure 5 The redundant library implementation scheme for the main library fault repair of the memory devices in the system.

[0016] Figure 7 A block diagram of an exemplary memory device is shown, illustrating a fault master library repair scheme implemented using a redundant library in data input according to some aspects of this disclosure.

[0017] Figure 8 A block diagram of an exemplary memory device is shown, illustrating a fault master library repair scheme implemented using a redundant library in data output according to some aspects of this disclosure.

[0018] Figure 9 Some aspects of this disclosure are shown. Figure 7 and Figure 8 A block diagram of exemplary control logic for a memory device.

[0019] Figures 10A-10C The use of some aspects of this disclosure is shown. Figures 7-9 An exemplary fault master library repair scheme for redundant libraries implemented in memory devices.

[0020] Figure 11 A flowchart illustrating an exemplary method for operating a memory device having a faulty master library and a redundant library, according to some aspects of this disclosure, is shown.

[0021] Figure 12 A flowchart is shown of another exemplary method for operating a memory device having a faulty master library and a redundant library, according to some aspects of this disclosure.

[0022] This disclosure will be described with reference to the accompanying drawings. Detailed Implementation

[0023] Although specific constructions and arrangements have been discussed, it should be understood that this is for illustrative purposes only. Thus, other constructions and arrangements may be used without departing from the scope of this disclosure. Furthermore, it is apparent that this disclosure can also be used in a variety of other applications. The functional and structural features described in this disclosure can be combined, adjusted, and modified with each other, as well as in ways not specifically depicted in the drawings, such combinations, adjustments, and modifications are within the scope of this disclosure.

[0024] Generally, terms can be understood, at least in part, from their use in context. For example, depending at least in part on the context, the term “one or more” as used herein can be used to describe any feature, structure, or characteristic in a singular sense, or it can be used to describe a combination of features, structures, or characteristics in a plural sense. Similarly, terms such as “a” or “described” can also be understood to convey either a singular or a plural usage, depending at least in part on the context. Furthermore, the term “based on” can be understood to not necessarily convey an exclusive set of factors, and may instead allow for the presence of additional factors that are not necessarily explicitly described, again depending at least in part on the context.

[0025] As the number of memory cells continues to increase to meet the ever-growing demand for larger storage capacities, the chance of memory cell failures also increases during the manufacturing process of memory devices. One way to handle faulty memory cells is to add redundant memory cell regions (e.g., redundant banks, redundant columns, or redundant groups) in addition to the main memory cell regions (e.g., main banks, also known as main columns or main groups). For each memory device, if the number of faulty memory cell regions identified during post-manufacturing testing is below a limit (e.g., not greater than the number of redundant memory cell regions), a remediation scheme can be employed so that the redundant memory cell regions can replace the faulty memory cell regions for reading and writing data when the memory device is being operated.

[0026] Some known memory devices (e.g., NAND flash memory devices) can perform parallel data input / output (I / O) operations to write eight data segments (e.g., 8 bytes) to or read eight data segments (e.g., 8 bytes) from eight physically separate main memory cell regions (e.g., main libraries). An equal number of eight redundant memory cell regions (e.g., redundant libraries) are coupled to the main memory cell regions. According to known remediation schemes, once a main memory cell region is identified as a faulty main memory cell region, the corresponding redundant memory cell region replaces the faulty memory cell region in the data input and output. However, this remediation scheme and redundant library design have various problems. For example, a large number of redundant libraries can waste chip area because not all libraries are typically used. A relatively large number of redundant libraries can also affect the flexibility of the remediation scheme. Furthermore, the additional wiring length used to couple each main library and the corresponding redundant library can increase data line skew.

[0027] To address one or more of the aforementioned problems, this disclosure introduces a solution in which a fewer redundant libraries than the number of primary libraries and a flexible repair scheme can be used to handle faulty primary libraries in memory devices (e.g., NAND flash memory devices). Consistent with certain aspects of this disclosure, multiplexers can be used to couple adjacent libraries, allowing input or output data to be shifted between adjacent libraries (primary or redundant libraries). As a result, redundant libraries are no longer dedicated to a specific primary library but can replace any faulty primary library without being coupled to each primary library. Therefore, the total chip area of ​​redundant libraries and the chance of wasting redundant library area can be significantly reduced. Furthermore, due to the data shift-based repair scheme, each library is coupled to only one or more adjacent libraries, thus reducing skew between each data line and shortening the data line routing length. Even with a smaller number of redundant libraries compared to known methods, the redundant library design and data shift-based repair scheme disclosed herein increase repair flexibility.

[0028] Figure 1 A block diagram of an exemplary system 100 having a memory device according to some aspects of this disclosure is shown. System 100 may be a mobile phone, desktop computer, laptop computer, tablet computer, vehicle computer, game console, printer, positioning device, wearable electronic device, smart sensor, virtual reality (VR) device, augmented reality (AR) device, or any other suitable electronic device having storage therein. Figure 1 As shown, system 100 may include a host 108 and a storage system 102, the storage system 102 having one or more memory devices 104 and a memory controller 106. The host 108 may be a processor (e.g., a central processing unit (CPU)) or a system-on-a-chip (SoC) (e.g., an application processor (AP)). The host 108 may be configured to send data to or receive data from the memory device 104.

[0029] Memory device 104 can be any memory device disclosed herein. As detailed below, memory device 104 (e.g., a NAND flash memory device) may include a redundant library of fewer numbers than the primary library and implements a flexible data shift-based repair scheme in data input and output operations to handle faulty primary libraries identified during post-manufacturing testing of memory device 104.

[0030] According to some embodiments, a memory controller 106 is coupled to a memory device 104 and a host 108 and is configured to control the memory device 104. The memory controller 106 can manage data stored in the memory device 104 and communicate with the host 108. In some embodiments, the memory controller 106 is designed to operate in low-duty-cycle environments, such as Secure Digital (SD) cards, Compact Flash (CF) cards, Universal Serial Bus (USB) flash drives, or other media used in electronic devices such as personal calculators, digital cameras, mobile phones, etc. In some embodiments, the memory controller 106 is designed to operate in high-duty-cycle environments, such as SSDs or embedded multimedia cards (eMMCs), which serve as data storage for mobile devices such as smartphones, tablets, laptops, etc., and for enterprise storage arrays. The memory controller 106 can be configured to control the operation of the memory device 104, such as read, erase, and program operations. The memory controller 106 may also be configured to manage various functions relating to data stored or to be stored in the memory device 104, including but not limited to bad block management, garbage collection, logical-to-physical address translation, wear leveling, etc. In some embodiments, the memory controller 106 is also configured to process error correction codes (ECC) relating to data read from or written to the memory device 104. The memory controller 106 may also perform any other suitable functions, such as formatting the memory device 104. The memory controller 106 may communicate with external devices (e.g., host 108) according to specific communication protocols. For example, the memory controller 106 may communicate with external devices via at least one of various interface protocols, such as USB, MMC, Peripheral Component Interconnect (PCI), PCI-E, Advanced Technology Attachment (ATA), Serial ATA, Parallel ATA, Small Computer Small Interface (SCSI), Enhanced Small Disk Interface (ESDI), Integrated Drive Electronic Devices (IDE), Firewire, etc.

[0031] The memory controller 106 and one or more memory devices 104 can be integrated into various types of storage devices, for example, included in the same package (e.g., a Universal Flash Memory (UFS) package or an eMMC package). That is, the memory system 102 can be implemented and packaged into different types of end electronic products. Figure 2AIn one example shown, the memory controller 106 and a single memory device 104 can be integrated into the memory card 202. The memory card 202 can include PC cards (PCMCIA, Personal Computer Memory Card International Association), CF cards, Smart Media (SM) cards, memory sticks, multimedia cards (MMC, RS-MMC, MMCmicro), SD cards (SD, miniSD, microSD, SDHC), UFS, etc. The memory card 202 can also include a connection between the memory card 202 and a host computer (e.g., ...). Figure 1 The host 108) is coupled to the memory card connector 204. In such a... Figure 2B In another example shown, the memory controller 106 and multiple memory devices 104 may be integrated into the SSD 206. The SSD 206 may also include a connection between the SSD 206 and a host (e.g., Figure 1 The SSD connector 208 is coupled to the host 108. In some embodiments, the storage capacity and / or operating speed of the SSD 206 is greater than the storage capacity and / or operating speed of the memory card 202.

[0032] Figure 3 A schematic circuit diagram of an exemplary memory device 300, including peripheral circuitry, is shown according to some aspects of this disclosure. The memory device 300 may be... Figure 1 An example of memory device 104 is shown. Memory device 300 may include memory cell array device 301 and peripheral circuitry 302 coupled to memory cell array device 301. Memory cell array device 301 may be a NAND flash memory cell array, wherein memory cells 306 are provided in the form of an array of NAND memory strings 308, each NAND memory string 308 extending vertically above a substrate (not shown). In some embodiments, each NAND memory string 308 includes a plurality of memory cells 306 coupled in series and stacked vertically. Each memory cell 306 may hold a continuous analog value, such as voltage or charge, depending on the number of electrons trapped in the region of memory cell 306. Each memory cell 306 may be a floating-gate type memory cell including a floating-gate transistor, or a charge-trapping type memory cell including a charge-trapping transistor.

[0033] In some implementations, each memory cell 306 is a single-level cell (SLC) having two possible memory states and thus capable of storing one bit of data. For example, a first memory state "0" may correspond to a first voltage range, and a second memory state "1" may correspond to a second voltage range. In some implementations, each memory cell 306 is a multi-level cell (MLC) capable of storing more than a single bit of data in more than four memory states. For example, an MLC may store two bits per cell, three bits per cell (also known as a three-level cell (TLC)), or four bits per cell (also known as a four-level cell (QLC)). Each MLC can be programmed to take a range of possible nominal storage values. In one example, if each MLC stores two bits of data, the MLC can be programmed to take one of three possible programming levels from the erase state by writing one of the three possible nominal storage values ​​to the cell. A fourth nominal storage value can be used for the erase state.

[0034] like Figure 3 As shown, each NAND memory string 308 may include a source select gate (SSG) 310 at its source end and a drain select gate (DSG) 312 at its drain end. The SSG 310 and DSG 312 may be configured to activate the selected NAND memory string 308 (column of the array) during read and program operations. In some embodiments, the SSG 310 of the NAND memory strings 308 in the same block 304 is coupled to, for example, ground via the same source line (SL) 314 (e.g., a common SL). According to some embodiments, the DSG 312 of each NAND memory string 308 is coupled to a corresponding bit line 316, from which data can be read or written via an output bus (not shown). In some implementations, each NAND memory string 308 is configured to be selected or deselected by applying a selection voltage (e.g., higher than the threshold voltage of the transistor having DSG 312) or a deselection voltage (e.g., 0V) to the corresponding DSG 312 via one or more DSG lines 313 and / or by applying a selection voltage (e.g., higher than the threshold voltage of the transistor having SSG 310) or a deselection voltage (e.g., 0V) to the corresponding SSG 310 via one or more SSG lines 315.

[0035] like Figure 3As shown, NAND memory strings 308 can be organized into multiple blocks 304, each of which may have a common source line 314. In some embodiments, each block 304 is a basic data unit for erase operations, i.e., all memory cells 306 on the same block 304 are erased simultaneously. Memory cells 306 of adjacent NAND memory strings 308 can be coupled via word lines 318, which select which row of memory cells 306 is affected by read and program operations. In some embodiments, each word line 318 is coupled to a page 320 of memory cells 306, which is a basic data unit for programming operations. The size of a page 320, in bits, can be related to the number of NAND memory strings 308 coupled by word lines 318 in a block 304. Each word line 318 may include multiple control gates (gate electrodes) at each memory cell 306 in the corresponding page 320, as well as gate lines coupling the control gates.

[0036] Peripheral circuitry 302 can be coupled to memory cell array 301 via bit line 316, word line 318, source line 314, SSG line 315, and DSG line 313. Peripheral circuitry 302 can include any suitable analog, digital, and mixed-signal circuitry to facilitate operation of memory cell array 301 by applying voltage and / or current signals to each target memory cell 306 via bit line 316, word line 318, source line 314, SSG line 315, and DSG line 313, and sensing voltage and / or current signals from each target memory cell 306. Peripheral circuitry 302 can include various types of peripheral circuitry formed using metal-oxide-semiconductor (MOS) technology. For example, Figure 4 Some exemplary peripheral circuitry 302 is shown, including a page buffer / sensor amplifier 404, a column decoder / bit line driver 406, I / O circuitry 407, a row decoder / word line driver 408, a voltage generator 410, control logic 412, a register 414, an interface 416, and a data bus 418. It should be understood that in some examples, additional peripheral circuitry may be included. Figure 4 Additional peripheral circuitry not shown.

[0037] Page buffer / sensor amplifier 404 can be configured to read data from memory cell array 301 and program (write) data to memory cell array 301 according to control signals from control logic 412. In one example, page buffer / sensor amplifier 404 can store a page of programming data (write data) to be programmed into a page 320 of memory cell array 301. In another example, page buffer / sensor amplifier 404 can perform a programming verification operation to ensure that data has been correctly programmed into memory cell 306 coupled to selected word line 318. In yet another example, page buffer / sensor amplifier 404 can also sense a low-power signal from bit line 316 representing a data bit stored in memory cell 306 and amplify a small voltage swing to a recognizable logic level during a read operation.

[0038] The column decoder / bit line driver 406 can be configured to be controlled by control logic 412 and to select one or more NAND memory strings 308 by applying a bit line voltage generated from voltage generator 410. I / O circuitry 407 can be coupled to page buffer / sensor amplifier 404 and / or column decoder / bit line driver 406 and is configured to route data input from data bus 418 to desired memory cell regions (e.g., libraries) of memory cell array 301, and to route data output from desired memory cell regions to data bus 418. As described in detail below, I / O circuitry 407 may include a multiplexer (MUX) array to implement flexible data shift-based repair schemes disclosed herein, as controlled by control logic 412.

[0039] The line decoder / word line driver 408 can be configured to be controlled by control logic 412 and to select block 304 of the memory cell array 301 and the word line 318 of the selected block 304. The line decoder / word line driver 408 can also be configured to drive the selected word line 318 using a word line voltage generated from a voltage generator 410. The voltage generator 410 can be configured to be controlled by control logic 412 and to generate word line voltages (e.g., read voltage, programming voltage, pass voltage, local voltage, and verification voltage) to be supplied to the memory cell array 301.

[0040] Control logic 412 can be coupled to each of the peripheral circuits described above and is configured to control the operation of each peripheral circuit. Register 414 can be coupled to control logic 412 and includes a status register, a command register, and an address register for storing status information, command opcodes (OP codes), and command addresses for controlling the operation of each peripheral circuit. Interface 416 can be coupled to control logic 412 and acts as a control buffer to buffer control commands received from the host (not shown) and forward them to control logic 412, and to buffer status information received from control logic 412 and forward it to the host. Interface 416 can also be coupled to I / O circuit 407 via data bus 418 and acts as a data I / O interface and data buffer to buffer write data received from the host (not shown) and forward it to I / O circuit 407, and to buffer read data from I / O circuit 407 and forward it to the host. For example, interface 416 may include data I / O 417 coupled to data bus 418.

[0041] Figure 5 A block diagram of a memory device 500 implementing a faulty master library repair scheme using a redundant library is shown. The memory cell array 301 in the memory device 500 includes... i Group 8 master databases 502 ( <0> …and <7> )as well as j Group 8 redundant databases 504 ( <0> …and <7> ), and each master database 502 is connected via the corresponding data line (L <0> … or L <7> The memory device 500 is coupled to a corresponding redundant library 504. That is, if a primary library 502 is identified as a faulty primary library during post-manufacturing testing, each primary library 502 has its own dedicated redundant library 504 as a backup. The memory device 500 is capable of inputting or outputting eight data segments (e.g., eight bytes) to or from the eight primary libraries 502 in parallel. The memory device 500 includes... i Group 8 master databases 502 and j Group 8 redundant databases 504.

[0042] The column decoder / bit line driver 406 of the memory device 500 includes components coupled to... i Group 8 master databases 502 i Each main decoder 510 and each coupled to j Group 8 redundant libraries 504 j A redundant decoder 511. The column decoder / bit line driver 406 of the memory device 500 also includes a driver coupled to... i The main pre-decoder 506 of the main decoder 510 and coupled to jA redundant (RED) pre-decoder 508 of a redundant decoder 511. The control logic 412 of the memory device 500 implements a fault master library repair scheme by controlling the master pre-decoder 506 and the redundant pre-decoder 508 via control signals (e.g., a redundancy enable signal (RED_EN)). Based on the control signals from the control logic 412, the master pre-decoder 506 uses a select / deselect signal (YSEL) to perform a selection / deselection. <0> …and YSEL< i >) make i Each of the eight master libraries in the corresponding master library group 502 that is disabled in the master decoder 510 is any one of the failed master libraries. On the other hand, based on the control signals from the control logic 412, the redundant pre-decoder 508 uses the select / deselect signal (YREDSEL) <0> …and YREDSEL< j >) make j Each of the redundant decoders 511 enables any one of the eight redundant libraries 504 in the corresponding redundant library group, which is coupled to the corresponding faulty master library via a corresponding bit line. The page buffer / sensor amplifier 404 of the memory device 500 is shared by the master library 502 and the redundant libraries 504 for read and write operations.

[0043] Figure 6A and Figure 6B It shows the use of by Figure 5 The memory device 500 implements a fault master library repair scheme for the redundant library. Figure 6A and Figure 6B The diagram illustrates a set of eight primary databases 502 and a set of eight redundant databases 504. The eight primary databases 502 include Database 0 Low (B0_L), Database 0 High (B0_H), Database 1 Low (B1_L), Database 1 High (B1_H), Database 2 Low (B2_L), Database 2 High (B2_H), Database 3 Low (B3_L), and Database 3 High (B3_H). The eight primary databases 502 are isolated from each other, meaning that data segments routed to one primary database 502 cannot be routed to another primary database 502 because they are not coupled via data lines. Instead, each primary database 502 is coupled to a corresponding redundant database 504 (e.g., ...). Figure 6A and Figure 6B As shown, the data lines between the adjacent ones on the right (e.g., Figure 5 L in <0> … or L <7> ) is coupled to the corresponding redundant library 504.

[0044] Figure 6AThe diagram illustrates a scenario where all eight primary databases 502 are working databases, meaning that post-manufacturing testing did not identify any faulty primary databases. In this case, the first eight data segments (0…, and 7) are either directed to or from the eight primary databases 502, without using any of the eight redundant databases 504, i.e., no data is displayed (marked as "x"). Similarly, the second eight data segments (8…, and 15) are again directed to or from the eight primary databases 502, while all eight redundant databases 504 remain unused, i.e., no data is displayed (marked as "x").

[0045] Figure 6B The illustration shows a case where one of the eight master libraries 502 is a faulty master library identified through post-manufacturing testing. In one example where B2_H is the faulty master library, seven of the first eight data segments (0, 1, 2, 3, 4, 6, and 7) are either routed to or from the seven working master libraries 502 (excluding B2_H), while data (5) is routed back to or from B2_H. That is, the faulty master library B2_H is replaced by a dedicated backup redundant library 504 coupled to B2_H for data input and output. In another example where B0_L is the faulty master library, seven data segments (9..., and 15) of the second 8th data segment are either directed to or from the seven working masters 502 (other than B0_L), while data (8) is redirected to or from the redundant library 504 coupled to B0_L. That is, the faulty master library B0_L is replaced by a dedicated backup redundant library 504 coupled to B0_L for data input and output.

[0046] As mentioned above, Figure 5 , Figure 6A and Figure 6B The redundant library design and associated repair scheme shown have various problems. First, seven of the eight redundant libraries 504 are wasted, and only one of the redundant libraries 504 is used to repair a faulty primary library. Second, the repair scheme lacks flexibility because the faulty primary library can only be replaced by a pre-assigned dedicated redundant library 504. Third, each primary library 502 needs to be coupled to the corresponding redundant library 504 via a data cable, which increases the wiring length and skewness of the data cables.

[0047] To overcome one or more of these problems, this disclosure provides an improved redundant library design with a smaller number of redundant libraries and an associated flexible data shift-based repair scheme. Consistent with the scope of this disclosure, memory devices may include memory cell arrays (e.g., Figure 3 and Figure 4The memory cell array 301 in the memory cell array), and the I / O circuits (e.g., Figure 4 The I / O circuit 407 in the middle) and the control logic (e.g., Figure 4 The control logic 412 in the memory cell array may include... N individual master databases and M There are redundant libraries, among which... N and M Each of the elements is a positive integer, and N Greater than M In other words, a memory cell array can have fewer redundant libraries than the main library. It should be understood that, compared to... Figure 5 Similar to the memory device 500 in the memory, the memory cell array can include multiple groups N Individual master databases and multiple groups M A redundant library. However, N This refers to the number of data segments that can be input (written / programmed) to and output (read) from the memory cell array in parallel. It should also be understood that the term "library" as used herein (in the context of "primary library," "redundant library," or "working library") may refer to... N One of the parallel data segments is guided to its or N A library is a region of memory cells that is guided from a parallel data segment. For example, a library can be a portion of a page, block, or face in an array of memory cells.

[0048] I / O circuits can be coupled to N individual master databases and M A redundant library, and configured to respectively... N A data fragment leads to N A work library or from N Work library guidance N A data segment. In some implementations, the I / O circuitry is coupled to... N individual master databases and M For each pair of adjacent libraries in the redundant libraries, the I / O circuitry is configured to... N One data segment can be routed to or from either of a pair of adjacent databases. N One of the data segments.

[0049] In some implementations... M It equals 1. In other words, a single redundant library can be used to repair a set of... N (2, 3, 4, 5, etc.) master libraries can significantly reduce the chip area of ​​redundant libraries and the waste of unused redundant libraries. For example, Figure 7 and Figure 8A block diagram of an exemplary memory device 700 is shown, illustrating an implementation of a fault master library repair scheme using a redundant library at both data input and data output, according to some aspects of this disclosure. The memory device 700 may be... Figure 3 and Figure 4 An example of memory device 300 is provided. For ease of description, details of the components in memory device 300 may be omitted when describing memory device 700, and similarly, this can be applied to memory device 700. For example... Figure 7 and Figure 8 As shown, the memory device 700 may include a memory cell array 301 having eight main libraries 702 (B0_L, B0_H, B1_L, B1_H, B2_L, B2_H, B3_L, and B3_H) and one redundant library 704 (RED). That is, in the memory device 700, N It equals 8, and M It equals 1. In other words, according to some implementations, the memory cell array 301 includes 9 libraries, which include 8 main libraries 702 and 1 redundant library 704.

[0050] I / O circuitry 407 can be coupled, for example, to eight main libraries 702 and one redundant library 704 via page buffer / sensor amplifier 404 and column decoder / bit line driver 406. Figure 7 In some specific implementations shown, during data input (e.g., write operations), the page buffer / sensor amplifier 404 and the column decoder / bit line driver 406 include nine drivers 706, respectively coupled to eight main libraries 702 and one redundant library 704. Figure 8 In some of the embodiments shown, during data output (e.g., read operations), the page buffer / sensor amplifier 404 and the column decoder / bit line driver 406 include nine sense amplifiers 802 coupled to eight main libraries 702 and one redundant library 704, respectively.

[0051] I / O circuit 407 can be configured to boot eight data segments to or from eight working libraries, respectively. Figure 7 In some embodiments shown, during data input, I / O circuitry 407 is configured to direct eight input data segments (e.g., write data: gwd<7:0>, gwd<15:8>, gwd<23:16>, gwd<31:24>, gwd<39:32>, gwd<47:40>, gwd<55:48>, and gwd<63:56>) to eight working libraries (e.g., seven primary libraries 702 and one redundant library 704) out of nine libraries (i.e., eight primary libraries 702 and one redundant library 704). Figure 8In some embodiments shown, in the data output, I / O circuitry 407 is configured to boot eight output data segments (e.g., read data: grd<7:0>, grd<15:8>, grd<23:16>, grd<31:24>, grd<39:32>, grd<47:40>, grd<55:48>, and grd<63:56>) from eight working libraries out of nine libraries (e.g., seven main libraries 702 and one redundant library 704). Figure 7 and Figure 8 As shown, in some embodiments, I / O circuitry 407 is coupled to each pair of adjacent libraries such that I / O circuitry 407 is configured to direct a write data segment (gwd) to either library in a pair of adjacent libraries, or to direct a read data segment (grd) from either library in a pair of adjacent libraries. A pair of adjacent libraries may be two primary libraries 702, or it may be one primary library 702 and a redundant library 704. In some embodiments, redundant library 704 is coupled to two primary libraries 702 via I / O circuitry 407. It should be understood that although redundant library 704 is coupled to two primary libraries 702 (B1_H and B2_L) respectively via I / O circuitry 407 in the middle of the eight primary libraries 702, as... Figure 7 and Figure 8 As shown, however, in some examples, the redundant library 704 can be coupled to any two main libraries 702 via I / O circuit 407, or coupled to only one main library 702 at the end of the eight main libraries 702 (e.g., B0_L or B3_H).

[0052] The I / O circuit 407 can be implemented using a MUX array. Figure 7In some embodiments shown, the I / O circuitry 407 of the memory device 700 includes a set of nine write MUXs 708 coupled to eight main libraries 702 and one redundant library 704 for data input. Each write MUX 708 may include an output (Out), two inputs (A and B), and a select port (S). The output of each write MUX 708 is coupled to a corresponding library 702 or 704. The select port of the write MUX 708 can be configured to receive a write select signal (red_en_b0_l_wt…, red_en_b12_wt…, or red_en_b3_h_wt) indicating the selection of an input (A or B). For example, a positive bias write select signal (i.e., an enable write select signal) can select input B. In some implementations, in addition to the write MUX 708 coupled at the ends to two master libraries 702 (B0_L and B3_H) (i.e., coupled only to one other master library 702), each write MUX 708 coupled to a respective master library 702 has two inputs configured to input two data segments, each including a write data segment intended for the respective master library 702 and another write data segment intended for an adjacent master library 702. For example, the write MUX 708 coupled to B0_H may have input A configured to input write data gwd<15:8> and input B configured to input write data gwd<7:0>. As for the write MUX 708 coupled to the redundant library 704, it may have two inputs configured to input two data segments, each including a write data segment intended for one adjacent master library 702 and another write data segment intended for another adjacent master library 702. For example, a write MUX 708 coupled to RED can have input A configured to input write data gwd<31:24> and input B configured to input write data gwd<39:32>. In other words, each write data segment can be coupled to both inputs of two adjacent libraries and can be input to either input of the two adjacent libraries. As for the write MUX 708 coupled at the ends to two master libraries 702 (B0_L and B3_H), one of its inputs can be configured to input a write data segment intended for the corresponding master library 702, and the other of its inputs can be configured to input a signal indicating data inactivation due to a library failure (e.g., system voltage Vdd).

[0053] exist Figure 8In some embodiments shown, the I / O circuitry 407 of the memory device 700 includes a set of eight read MUX 804s coupled to one redundant library 704 of eight main libraries 702 for data output. Each read MUX 804 may include an output (Out), two inputs (A and B), and a select port (S). The select port of the read MUX 804 can be configured to receive a read select signal (red_en_b0_l_rd…, or red_en_b3_h_rd) indicating the selection of an input (A or B). For example, a positive bias read select signal (i.e., an enable read select signal) can select input B. In some embodiments, each read MUX 804 has two inputs coupled to two adjacent libraries. For example, the leftmost read MUX 804 may have input A coupled to B0_L and input B coupled to B0_H; the middle read MUX 804 may have input A coupled to B1_H and input B coupled to RED. In other words, in addition to the two master libraries 702 (B0_L and B3_H) at the ends, each library 702 or 704 can be coupled to the inputs of two read MUX 804s respectively. The output of each read MUX 804 can be configured to output a data segment from input A or input B based on a corresponding read selection signal, i.e., any data segment stored in the two adjacent libraries. For example, the read data gwd<7:0> output from the leftmost read MUX 804 can come from B0_L or B0_H; the read data gwd<31:24> output from the middle read MUX 804 can come from B1_H or RED.

[0054] As mentioned above Figure 7 and Figure 8 The I / O circuit 407 can be coupled to each pair of adjacent libraries and is configured to direct data segments to or from any library in each pair of adjacent libraries. It should be understood that although the above description of an exemplary design of the MUX array in the I / O circuit 407 with respect to a memory device 700 having eight primary libraries 702 and one redundant library 704 is an example of such an design, similar designs can generally be applied to memory devices with... M individual master databases and N The memory devices of the redundant library, among which... N and M Each of the elements is a positive integer, and N Greater than M The design, based on redundant libraries in the memory cell array and MUX arrays in the I / O circuitry, allows for flexible data shift-based repair schemes. Control logic can be coupled to the I / O circuitry and configured based on indications. N In each master database K The database fault information of each faulty master database is obtained fromN individual master databases and M One redundant library is determined N A work library. N A work library can include M In a redundant library K There are redundant libraries, among which... K Not greater than M Positive integers. The control logic can also be configured to control the I / O circuitry to respectively... N In the data fragments K A data fragment leads to K A redundant library or from K A redundant library boot N In the data fragments K A data fragment.

[0055] For example, such as Figure 9 As shown, control logic 412 may include read redundancy enable logic 902, write redundancy enable logic 904, and working library logic 906. Each logic 902, 904, or 906 may be implemented by a microprocessor, microcontroller (also known as a microcontroller unit (MCU)), digital signal processor (DSP), application-specific integrated circuit (ASIC), field-programmable gate array (FPGA), programmable logic device (PLD), state machine, gating logic, discrete hardware circuitry, and other suitable hardware, firmware, and / or software configured to perform the various functions described in detail below. In some embodiments, one or more of the read redundancy enable logic 902, write redundancy enable logic 904, and working library logic 906 are implemented using content-addressable memory (CAM).

[0056] In some implementations, the working library logic 906 is coupled to register 414 and configured to obtain library fault information indicating one or more faulty master libraries in the master library of the memory device (e.g., memory device 700), for example, N In each master database K Each memory device has a fault master library. During post-manufacturing testing, bad (non-functional) memory cells can be detected from the memory device, and each master library containing at least one bad memory cell can be identified as a fault master library. In some implementations, library fault information indicates each of the fault master libraries of the memory device and is stored in the memory device (e.g., in register 414). Thus, each memory device can have its own library fault information. Before operating the memory device, the working library logic 906 can obtain the library fault information from register 414 and determine the memory device's available data input and output. N The number of working libraries. According to some implementations, the number of working libraries ( N) and the number of parallel input / output data segments ( N (For example, 8 in memory device 700) are the same. That is, the working library logic 906 can be used with the same number ( K Redundant library replacement K A faulty master database, making N A work library can include K A redundant library and N - K In memory device 700, one of the eight master libraries 702 can be replaced by a redundant library 704 to form eight working libraries, as determined by working library logic 906 of control logic 412.

[0057] Based on certainty N Each working library, read redundancy enable logic 902 and write redundancy enable logic 904 can be configured to control I / O circuit 407 to respectively... N In the data fragments K A data fragment leads to K A redundant library or from K A redundant library boot N In the data fragments K A data segment. In some embodiments, for data input, write redundancy enable logic 904 is coupled to write MUX 708 of I / O circuitry 407 and configured to provide nine write select signals (e.g., red_en_b0_l_wt…, red_en_b12_wt…, and red_en_b3_h_wt) to nine write MUX 708 respectively based on eight determined working libraries. In some embodiments, for data output, read redundancy enable logic 902 is coupled to read MUX 804 of I / O circuitry 407 and configured to provide eight read select signals (e.g., red_en_b0_l_rd…, and red_en_b3_h_rd) to eight read MUX 804 respectively based on eight determined working libraries. In some implementations, read redundancy enable logic 902 and write redundancy enable logic 904 also provide synchronization signals to the strobe clocks of read MUX 804 and write MUX 708, respectively, to align data and selection signals.

[0058] Based on K Each faulty master library is enabled (e.g., positively biased) or disabled (e.g., negatively biased) by each selection signal. In some implementations, if the first library in a pair of adjacent libraries is KIf one of the faulty master libraries is a faulty master library, then read redundancy enable logic 902 and write redundancy enable logic 904 are configured to control I / O circuit 407 to direct data segments to or from the second library in the pair of adjacent libraries. That is, according to some implementations, control logic 412 is configured to select one library in each pair of adjacent libraries based on library fault information, and control I / O circuit 407 to direct data segments to or from the selected library in each pair of adjacent libraries.

[0059] Now for reference Figure 7 In the data input, write redundancy enable logic 904 can be configured to control the first write MUX 708 coupled to the first library (i.e., the faulty master library) to disable input of data segments from input A of the first write MUX 708 and disable output of data segments to the first library. Conversely, write redundancy enable logic 904 can be configured to control the second write MUX 708 coupled to the second library (e.g., the master library 702 or the redundant library 704 adjacent to the first library) to enable input of data segments from input B of the second write MUX 708 and enable output of data segments to the second library. That is, as controlled by write redundancy enable logic 904, data segments intended for the faulty master library can be redirected by the write MUX 708 coupled to the faulty master library to its adjacent library (master library 702 or redundant library 704). The same operation can be applied to each pair of adjacent libraries, causing data input to be shifted between adjacent libraries.

[0060] For example, assuming B0_L is the faulty master library, writing redundancy enable logic 904 enables red_en_b0_l_wt and red_en_b0_h_wt, causing Vdd to be input from input B to B0_L, and gwd<7:0> to be redirected and input from input B to B0_H. To shift the data input, writing redundancy enable logic 904 can also enable red_en_b1_l_wt and red_en_b1_h_wt, causing gwd<15:8> to be redirected and input from input B to B1_L, and gwd<23:16> to be redirected and input from input B to B1_H. Writing redundancy enable logic 904 can also disable red_en_b12_wt, causing gwd<31:24> to be redirected and input from input A to RED. In other words, input data can therefore be shifted from the faulty master library B0_L to the redundant library RED. For the other master databases B2_L, B2_H, B3_L, and B3_H, no input data shifting is required, allowing the write redundancy enable logic 904 to disable red_en_b2_l_wt, red_en_b2_h_wt, red_en_b3_l_wt, and red_en_b3_h_wt. As a result, each of B2_L, B2_H, B3_L, and B3_H can still receive data from input A without data shifting.

[0061] Now for reference Figure 8 In data output, read redundancy enable logic 902 can be configured to control read MUX 804 coupled to the first and second libraries (i.e., the faulty primary library and the primary library 702 or redundant library 704 adjacent to the faulty primary library) to enable the output of data segments from the second library (e.g., the primary library 702 or redundant library 704 adjacent to the faulty primary library). That is, as controlled by read redundancy enable logic 902, data segments intended for the faulty primary library can be redirected from their adjacent libraries (primary library 702 or redundant library) by read MUX 804. The same operation can be applied to each pair of adjacent libraries, causing the data output to shift between the adjacent libraries.

[0062] For example, assuming B0_L is the faulty master library, read redundancy enable logic 902 can enable red_en_b0_l_rd, causing grd<7:0> to be redirected and output from B0_H, which is coupled to input B. To shift the data output, read redundancy enable logic 902 can also enable red_en_b0_h_rd, red_en_b1_l_rd, and red_en_b1_h_rd, causing grd<15:8> to be redirected and output from B1_L, coupled to input B; grd<23:16> to be redirected and output from B1_H, coupled to input B; and grd<31:24> to be redirected and output from RED, coupled to input B. In other words, output data can therefore be shifted from the faulty master library B0_L to the redundant library RED. For the other master libraries B2_L, B2_H, B3_L, and B3_H, no output data shift is required, allowing the read redundancy enable logic 902 to disable red_en_b2_l_rd, red_en_b2_h_rd, red_en_b3_l_rd, and red_en_b3_h_rd. As a result, data can still be output from input A to B2_L, B2_H, B3_L, and B3_H without data shifting.

[0063] Figures 10A-10C Further examples of fault master library repair schemes using a redundant library 704 implemented by memory device 700, according to some aspects of this disclosure, are shown. Figure 10A The diagram illustrates a scenario where all eight master libraries 702 are working libraries, meaning no faulty master libraries were identified during post-manufacturing testing. In this case, the first eight data segments (0…, and 7) can be routed to or from any of the eight master libraries 702, without using the redundant library 704, i.e., without data (marked as "x"). Similarly, the second eight data segments (8…, and 15) can again be routed to or from the eight master libraries 702, while the redundant library 704 remains unused, i.e., without data (marked as "x").

[0064] Figure 10B and Figure 10C This illustrates a case where one of the eight master libraries 702 was identified as a faulty master library through post-manufacturing testing. For example... Figure 10BAs shown in the example where B2_H is a faulty master database, the first four data segments (1, 2, 3, and 4) of the first eight data segments can be redirected to or from the four corresponding working masters B0_L, B0_H, B1_L, and B1_H (which are separated from B2_H via the redundant database 704). Data (5) intended for B2_H can be redirected to the adjacent working master database B2_L, and data (4) intended for B2_L can be redirected to the redundant database 704 (data shifted to the left). B2_H can become unused. That is, data shifting can occur between B2_H and the redundant database 704. The last two data segments (6 and 7) of the first eight data segments can be redirected to or from the corresponding working masters B3_L and B3_H, respectively, without data shifting. In another example where B0_L is the faulty master database, the first four data segments (8, 9, 10, and 11) of the second 8th data segment can be redirected to or from adjacent working masters B0_H, B1_L, and B1_H, and the redundant database 704, respectively (data shifted to the right). B0_L can become unused. That is, data shifting can occur between B0_L and the redundant database 704. The last four data segments (12, 13, 14, and 15) of the second 8th data segment can be redirected to or from the four corresponding working masters B2_L, B2_H, B3_L, and B3_H, respectively, without data shifting.

[0065] like Figure 10CAs shown in the example where B1_L is the faulty master database, the first two data segments (0 and 1) of the first eight data segments can be redirected to or from the corresponding working masters B0_L and B0_H, respectively. The next two data segments (2 and 3) of the first eight data segments can be redirected to or from the adjacent working master database B1_H and the redundant database 704, respectively (data shifted to the right). B1_L can become unused. That is, data shifting can occur between B1_L and the redundant database 704. The last four data segments (4, 5, 6, and 7) of the first eight data segments can be redirected to or from the corresponding working masters B2_L, B2_H, B3_L, and B3_H, respectively, without data shifting. In another example where B2_L is the faulty master library, the first four data segments (8, 9, 10, and 11) of the second eight data segments can be redirected to or from the corresponding working masters B0_L, B0_H, B1_L, and B1_H (which are separated from B2_L via the redundant library 704), respectively. Data (12) intended for B2_L can be redirected to or from the redundant library 704 (data shifted to the left), and B2_L can become unused. That is, data shifting can occur between B2_L and the redundant library 704. The last three data segments (13, 14, and 15) in the second 8th data segment can be directed to or from the three corresponding working master libraries B2_H, B3_L, and B3_H, respectively, without data shifting.

[0066] Figure 11 A flowchart of an exemplary method 1100 for operating a memory device having a faulty primary library and a redundant library, according to some aspects of this disclosure, is shown. The memory device can be any suitable memory device disclosed herein. Method 1100 can be implemented by control logic 412. It should be understood that the operations shown in method 1100 are not exhaustive, and other operations may be performed before, after, or between any of the operations shown. Furthermore, some operations may be performed simultaneously or in conjunction with... Figure 11 The different execution sequences are shown.

[0067] refer to Figure 11Method 1100 begins at operation 1102, wherein library fault information indicating a faulty master library among multiple master libraries is obtained. Faulty master libraries can be identified through post-manufacturing testing of the memory device. For example, before operating the memory device, the working library logic 906 can obtain the library fault information from register 414.

[0068] Method 1100 proceeds to operation 1104, such as Figure 11 As shown, multiple working databases are determined from multiple primary databases and redundant databases based on database fault information. These multiple working databases may include redundant databases. For example, working database logic 906 can determine working databases that include redundant databases and remaining primary databases.

[0069] Method 1100 proceeds to operation 1106, such as Figure 11 As shown, one library from each pair of adjacent libraries is selected based on library fault information. According to some implementations, the selected library is the working library. For example, working library logic 906 can select one working library from each pair of adjacent libraries based on library fault information.

[0070] Method 1100 proceeds to operation 1108, such as Figure 11 As shown, control directs data fragments to or from a selected library in each pair of adjacent libraries. According to some implementations, to control the routing of data fragments, a first library in a pair of adjacent libraries is determined to be the faulty master library, and control directing data fragments to or from a second library in that pair of adjacent libraries. In one example, write redundancy enable logic 904 can control a first write MUX 708 to disable the output of data fragments to the first library, and control a second write MUX 708 to enable the output of data fragments to the second library. In another example, read redundancy enable logic 902 can control a read MUX 804 to enable the output of data fragments from the second library.

[0071] Figure 12 A flowchart of another exemplary method 1200 for operating a memory device having a faulty primary library and a redundant library, according to some aspects of this disclosure, is shown. The memory device can be any suitable memory device disclosed herein. Method 1200 can be implemented by control logic 412. It should be understood that the operations shown in method 1200 are not exhaustive, and other operations may be performed before, after, or between any of the operations shown. Furthermore, some operations may be performed simultaneously or in conjunction with... Figure 12 The different execution sequences are shown.

[0072] refer to Figure 12 Method 1200 begins at operation 1202, where an instruction is obtained. N In each master databaseK Database failure information for each faulty master database. K It can be no greater than N Positive integers. These can be identified through post-manufacturing testing of memory devices. K A faulty master library. For example, before operating memory devices, the working library logic 906 can obtain library fault information from register 414.

[0073] Method 1200 proceeds to operation 1204, such as Figure 12 As shown in the figure, based on library fault information from N individual master databases and M One redundant library is determined N A work library. N A work library can include M In a redundant library K A redundant library. For example, working library logic 906 can determine that it includes... K One redundant database and a remaining primary database N A working library. In some implementations, M It equals 1, and is based on library fault information from N For each pair of adjacent databases in the primary and redundant databases, a working database is selected.

[0074] Method 1200 proceeds to operation 1206, such as... Figure 12 As shown in the figure, respectively, N In the data fragments K A data fragment leads to K A redundant library or from K A redundant library boot N In the data fragments K A data segment. In some implementations, M It equals 1, and will K One of the data segments leads to... N Select the working database or the source database from each pair of adjacent databases in the primary and redundant databases. N The selected working database in each pair of adjacent databases in the primary and redundant databases guides the selection of the working database. K One of the data segments.

[0075] According to one aspect of this disclosure, a memory device includes a memory cell array, I / O circuitry, and control logic coupled to the I / O circuitry. The memory cell array includes... N individual master databases and M There are redundant libraries, among which... N and M Each of the elements is a positive integer, and N Greater than M I / O circuits are coupled toN individual master databases and M A redundant library, and configured to respectively... N A data fragment leads to N A work library or from N Work library guidance N A data segment. The control circuit is configured to be based on an indication. N In each master database K The database fault information of each faulty master database is obtained from N individual master databases and M One redundant library is determined N A work library. N The work library includes M In a redundant library K There are redundant libraries, among which... K Not greater than M Positive integers. The control circuit is also configured to control the I / O circuitry to respectively... N In the data fragments K A data fragment leads to K A redundant library or from K A redundant library boot N In the data fragments K A data fragment.

[0076] In some implementations, the I / O circuitry is coupled to N individual master databases and M For each pair of adjacent libraries in the redundant libraries, the I / O circuitry is configured to... N One data segment can be routed to or from either of a pair of adjacent databases. N One of the data segments.

[0077] In some implementations, at least one pair of adjacent repositories is the master repository.

[0078] In some implementations, the first library in a pair of adjacent libraries is K One of the faulty master libraries is a faulty master library, and the control logic is configured to control the I / O circuitry to direct data segments to or from the second library in a pair of adjacent libraries.

[0079] In some implementations, the I / O circuitry includes circuits coupled to... N individual master databases and MA set of write MUXs for a redundant library. In some implementations, a set of write MUXs includes: a first write MUX having two inputs and an output coupled to a first library, one of the two inputs being configured to input a data segment; and a second write MUX having two inputs and an output coupled to a second library, the two inputs being configured to input a data segment and another data segment, respectively.

[0080] In some implementations, the control logic is also configured to control the first write MUX to prevent data fragments from being output to the first library, and to control the second write MUX to enable data fragments to be output to the second library.

[0081] In some implementations, the I / O circuitry includes coupling to N individual master databases and M A set of read MUXs for a redundant library, and the set of read MUXs includes a read MUX having two inputs respectively coupled to a first library and a second library, and an output configured to output data fragments.

[0082] In some implementations, the control logic is also configured to control the reading of the MUX to enable the output of data fragments from the second library.

[0083] In some implementations... M It equals 1.

[0084] In some implementations, the redundant library is coupled to I / O circuitry. N Two master databases in one master database.

[0085] In some implementations, the memory device includes a 3D NAND memory device.

[0086] According to another aspect of this disclosure, a system includes a memory device configured to store data and a memory controller coupled to the memory device and configured to control the memory device. The memory device includes a memory cell array, I / O circuitry, and control logic coupled to the I / O circuitry. The memory cell array includes... N individual master databases and M There are redundant libraries, among which... N and M Each of the elements is a positive integer, and N Greater than M I / O circuits are coupled to N individual master databases and M A redundant library, and configured to respectively... N A data fragment leads to N A work library or from N Work library guidance NA data segment. The control circuit is configured to be based on an indication. N In each master database K The database fault information of each faulty master database is obtained from N individual master databases and M One redundant library is determined N A work library. N The work library includes M In a redundant library K There are redundant libraries, among which... K Not greater than M Positive integers. The control circuit is also configured to control the I / O circuitry to respectively... N In the data fragments K A data fragment leads to K A redundant library or from K A redundant library boot N In the data fragments K A data fragment.

[0087] In some implementations, the system also includes a host coupled to the memory controller and configured to send or receive data.

[0088] In some implementations, the I / O circuitry is coupled to N individual master databases and M For each pair of adjacent libraries in the redundant libraries, the I / O circuitry is configured to... N One data segment can be routed to or from either of a pair of adjacent databases. N One of the data segments.

[0089] In some implementations, at least one pair of adjacent repositories is the master repository.

[0090] In some implementations, the first library in a pair of adjacent libraries is K One of the faulty master libraries is a faulty master library, and the control logic is configured to control the I / O circuitry to direct data segments to or from the second library in a pair of adjacent libraries.

[0091] In some implementations, the I / O circuitry includes circuits coupled to... N individual master databases and M A set of write MUXs for a redundant library. In some implementations, a set of write MUXs includes: a first write MUX having two inputs and an output coupled to a first library, one of the two inputs being configured to input a data segment; and a second write MUX having an output coupled to a second library with the two inputs, the two inputs being configured to input a data segment and another data segment, respectively.

[0092] In some implementations, the control logic is also configured to control the first write MUX to prevent data fragments from being output to the first library, and to control the second write MUX to enable data fragments to be output to the second library.

[0093] In some implementations, the I / O circuitry includes coupling to N individual master databases and M A set of read MUXs for a redundant library, and the set of read MUXs includes a read MUX having two inputs respectively coupled to a first library and a second library, and an output configured to output data fragments.

[0094] In some implementations, the control logic is also configured to control the reading of the MUX to enable the output of data fragments from the second library.

[0095] In some implementations... M It equals 1.

[0096] In some implementations, the redundant library is coupled to I / O circuitry. N Two master databases in one master database.

[0097] According to another aspect of this disclosure, a method for operating a memory device is provided. The memory device includes a memory cell array, the memory cell array comprising... N individual master databases and M There are redundant libraries, among which... N and M Each of the elements is a positive integer, and N Greater than M Based on instructions N In each master database K The database fault information of each faulty master database is obtained from N individual master databases and M One redundant library is determined N A work library. N The work library includes M In a redundant library K There are redundant libraries, among which... K Not greater than M Positive integers. (The remaining text appears to be incomplete and requires further context.) N In the data fragments K A data fragment leads to K A redundant library or from K A redundant library boot N In the data fragments K A data fragment.

[0098] In some implementations, an instruction is obtained. N In each master database K Database failure information for each faulty master database.

[0099] In some implementations... M It equals 1.

[0100] In some implementations, to determine, based on library fault information from N For each pair of adjacent databases in the primary and redundant databases, a working database is selected.

[0101] In some implementations, for the purpose of guiding, K One of the data segments leads to... N Selected working database or bootstrap from each pair of adjacent databases in the primary and redundant databases. K One of the data segments.

[0102] The foregoing description of the specific embodiments can be readily modified and / or adapted to various applications. Therefore, based on the teachings and guidance presented herein, such adaptations and modifications are intended to fall within the meaning and scope of equivalents of the disclosed embodiments.

[0103] The breadth and scope of this disclosure should not be limited by any of the exemplary embodiments described above, but should be defined solely by the appended claims and their equivalents.

Claims

1. A memory device, comprising: an array of memory cells, the array of memory cells comprising N one primary bank and M one redundant bank, wherein N and M each of n, m, p, and q is a positive integer, and N p is greater than M q. Input / output (I / O) circuitry including a plurality of write multiplexers respectively coupled to the N primary banks and the M redundant banks; wherein one of the M redundant banks is coupled to one of the plurality of write multiplexers and one of the N main banks is coupled to one of the plurality of write multiplexers.

2. The memory device of claim 1, wherein, The M is equal to 1.

3. The memory device of claim 2, wherein, The N is even, the redundant bank is located between two main banks of the N main banks, and the number of main banks on one side of the redundant bank is equal to the number of main banks on the other side.

4. The memory device of claim 1, further comprising N+M drive circuits, wherein the input / output (I / O) circuit is coupled to the N main banks and M redundant banks through the N+M drive circuits.

5. The memory device of claim 1, wherein: one of the plurality of write multiplexers comprises: one output coupled to one main bank or one redundant bank; two inputs; and one select port configured to receive a write select signal, the write select signal indicating to select one of the two inputs.

6. The memory device of claim 1, wherein: the plurality of write multiplexers comprises: a first write multiplexer coupled to one failed main bank of the N main banks; a second write multiplexer coupled to one main bank or one redundant bank adjacent to the one failed main bank; the memory device further comprises control logic configured to: control the first write multiplexer to disable outputting a piece of data to the one failed main bank; and 7. The memory device of claim 6, wherein, control the second write multiplexer to enable outputting the piece of data to one main bank or one redundant bank adjacent to the one failed main bank.

8. The memory device of claim 1, further comprising N+M sense amplifiers, wherein, The second write multiplexer is in a first direction from the first multiplexer, and the failed main bank is in a second direction from the redundant bank, the second direction being opposite to the first direction.

9. The memory device of claim 5, wherein, The input / output (I / O) circuit is coupled to the N main banks and the M redundant banks through the N+M sense amplifiers, respectively. The input / output (I / O) circuit further comprises a plurality of read multiplexers coupled to the N main banks and the M redundant banks, respectively; 10. The memory device of claim 1, wherein, one read multiplexer of the plurality of read multiplexers comprises two inputs and one output, the two inputs coupled to two adjacent banks of the N main banks and the M redundant banks, respectively.

11. The memory device of claim 10, further comprising control logic configured to obtain the bank failure information from the register and determine N working banks, the N working banks comprising K redundant banks of the M redundant banks and N-K primary banks of the N primary banks, wherein, The memory device further comprises a register configured to hold bank failure information, the bank failure information indicating a failed main bank of the N main banks.

12. The memory device of claim 1, wherein, K is a positive integer no greater than M.

13. The memory device of claim 1, wherein, one of the M redundant banks is coupled to two of the N main banks through the input / output (I / O) circuit. The memory device comprises a three-dimensional (3D) NAND memory device.

14. A memory system, comprising: a memory device, the memory device comprising the memory device of any one of claims 1-13; and a memory controller coupled to the memory device and configured to control the memory device.

15. A method for operating a memory device, the memory device comprising an array of memory cells, the array of memory cells comprising N one main bank and M one redundant bank, N and M each being a positive integer, and N being greater than M the method comprising: based on the library failure information indicating the K number of failed primary libraries N K based on the library failure information indicating the K number of failed primary libraries​ 16. The method of claim 15, wherein, The M One of the redundant banks is located between two of the N master banks.

17. The method of claim 15, further comprising determining, based on library failure information indicating a number of failed primary libraries of the number of primary libraries, a number of working libraries from the number of primary libraries and the number of redundant libraries, the number of working libraries comprising a number of redundant libraries of the number of redundant libraries, wherein N K N M N N M K K is a positive integer not greater than M is a positive integer not greater than ​​​​​​​​ 18. The method of claim 17, further comprising obtaining the library failure information indicative of the N one failed primary library in the K one primary library.

19. The method of claim 15, wherein, M is equal to 1.

20. The method of claim 17, further comprising directing N data segments from the N working banks.

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