Three-dimensional phase change memory and preparation method thereof

Abstract

The invention discloses a three-dimensional phase change memory and a preparation method thereof, and the method comprises the steps: sequentially depositing a dielectric layer and a metal layer on a substrate, and constructing a multilayer film structure which is periodically and alternately stacked; performing photoetching and developing on the top of the alternately stacked multi-layer film structure to form a circular hole array pattern; taking a circular hole formed by photoetching as a mask, and vertically and downwards etching to the bottom dielectric layer to obtain a deep hole etching structure; performing transverse etching on the metal layer exposed in the deep hole etching structure, wherein a groove structure is arranged between every two adjacent dielectric layers; performing plasma activation on the inner side wall of the hole in the groove structure to obtain a metal layer with high surface active site density and a dielectric layer with a relatively inert surface state; depositing a functional layer in the groove structure; and backfilling a metal material to form a top electrode. According to the invention, the chemical state of the surface of the substrate is activated in a differentiated manner, and the self-aligned deposition of the heterogeneous surface is realized in combination with the low-saturation precursor pulse, so that the stability of the three-dimensional phase change memory is improved.

Description

Technical Field

[0001] This invention belongs to the field of semiconductor device manufacturing technology, specifically relating to three-dimensional phase-change memory and its preparation method. Background Technology

[0002] Atomic layer deposition (ALD) technology, with its ability to control thickness at the single-atom level and excellent thin film uniformity, has become one of the core processes in semiconductor manufacturing and nanodevice fabrication. However, traditional ALD is essentially a uniform deposition method across the entire surface, unable to distinguish between different material regions on the substrate. This limitation is gradually becoming apparent as micro- and nanoelectronics technology moves towards three-dimensional integration and heterogeneous fusion. Taking integrated circuit manufacturing as an example, as device dimensions approach physical limits, the material waste and process complexity caused by traditional uniform deposition characteristics are becoming increasingly prominent. For instance, in the fabrication of the dielectric layer of dynamic random access memory (DRAM) capacitors, the deposited film requires multiple photolithography and etching steps to remove non-target areas, resulting in a material utilization rate of less than 30%, significantly increasing manufacturing costs. In high-density memory devices such as three-dimensional phase-change memories (3D phase-change memories), while traditional techniques can achieve uniform coverage of high aspect ratio structures, they cannot selectively distinguish between electrode and dielectric regions, leading to extreme leakage current densities between adjacent memory cells and a sharp reduction in the resistance window at high temperatures.

[0003] To overcome this bottleneck, the industry has attempted to achieve region-selective deposition using auxiliary methods such as photolithography, physical masks, or chemical modification. However, these methods all have significant drawbacks. While photolithography can define the deposition area through patterning, its multi-step process significantly extends the production cycle, and the roughness of the photoresist edges blurs the deposition boundaries, making it difficult to meet the precision requirements at advanced process nodes. More seriously, photoresist residues decompose during high-temperature processes, introducing impurities and significantly degrading the film's conductivity. Physical masking avoids chemical contamination, but the precise control requirements for the mask-substrate spacing make it difficult to adapt to complex three-dimensional structures, and mechanical contact can easily damage the device surface, leading to drift in key electrical parameters. Chemical modification inhibits deposition through molecular selectivity, but its thermal stability is insufficient, and it is prone to decomposition at typical process temperatures, leading to selective failure. Furthermore, existing technologies generally face poor compatibility with three-dimensional structures; for example, material differentiation cannot be achieved within high aspect ratio channels, leading to increased interface defect density and severely restricting device reliability.

[0004] The manufacturing demands of 3D phase-change memories further highlight the urgency of region-selective deposition technology. In traditional unconstrained vertical electrode structures, electric field coupling and thermal diffusion issues caused by multilayer stacking lead to a sharp degradation in device performance. While existing improvements propose using chemical vapor deposition (CVD) for selective deposition, its process temperature exceeds the process thermal budget limit, and the deposition rate control precision is insufficient, making it difficult to meet the integration requirements of advanced nodes. More importantly, existing technologies struggle to achieve high-precision region selectivity without complex masks or photolithography, resulting in manufacturing costs increasing exponentially with structural complexity. Summary of the Invention

[0005] To address the shortcomings and improvement needs of existing technologies, this invention provides a three-dimensional phase change memory and its fabrication method. The purpose is to improve the stability of the three-dimensional phase change memory by differentially activating the chemical state of the substrate surface and combining it with low-saturation precursor pulses to achieve self-aligned deposition on heterogeneous surfaces.

[0006] To achieve the above objectives, according to one aspect of the present invention, a method for fabricating a three-dimensional phase-change memory is provided, comprising: S1: A dielectric layer and a metal layer are sequentially deposited on a substrate to construct a multilayer film structure with periodically alternating stacks, wherein the top layer is a dielectric layer; S2: A circular hole array pattern is formed on top of the above-mentioned alternately stacked multilayer film structure by photolithography and development; S3: Using the circular hole formed by photolithography as a mask, vertical etching is performed to penetrate the dielectric layer and the metal layer down to the bottom dielectric layer to obtain a deep hole etching structure. S4: Lateral etching of the exposed metal layer in the deep hole etching structure to form a groove structure at the metal of the hole wall, wherein the groove structure is between adjacent dielectric layers, and each two adjacent dielectric layers include one groove structure. S5: Plasma activation is performed on the inner wall of the exposed metal layer and dielectric layer in the groove structure to obtain a metal layer with a high density of surface active sites and a dielectric layer with relatively inert surface states. S6: Selectively deposit functional layers in the groove structure; S7: After the functional layer deposition is completed, metal material is backfilled into the deep hole to form the top electrode.

[0007] In summary, the above-described technical solutions conceived in this invention can achieve the following beneficial effects: 1. In-situ selectivity: By differentially activating the chemical state of the substrate surface, combined with low-saturation precursor pulses, self-aligned deposition on heterogeneous surfaces is achieved without the need for back etching, avoiding sidewall damage / residue; the process is simplified, self-aligned, and BEOL compatible.

[0008] 2. The interlayer insulation resistance of the dielectric layer of the three-dimensional memory is ≥10¹² Ω, leakage is reduced by about six orders of magnitude, thermal crosstalk is significantly suppressed, and cycle life can be improved by hundreds of times.

[0009] 3. High selectivity and strong robustness: ≥98% selectivity after 2000 cycles, <1nm dielectric side deposition, maintaining selectivity even within submicron characteristics.

[0010] 4. Scalability: The functional layer in this invention can be extended to various chalcogenide material systems such as GeTe, Sb2Te3, and GST, and is suitable for high-level stacking. Attached Figure Description

[0011] Figure 1 The diagram shown is a flowchart of a method for fabricating a three-dimensional phase-change memory according to an embodiment of the present invention; Figure 2 The image shown is a front view of a three-dimensional phase-change memory according to an embodiment of the present invention; Figure 3 The image shown is a front view of another three-dimensional phase-change memory provided according to an embodiment of the present invention; Figure 4 The figure shown is a schematic diagram of a cross-section high-resolution transmission electron microscope (HRTEM) and corresponding energy dispersive spectroscopy (EDS) of a three-dimensional phase change memory provided according to an embodiment of the present invention. Figure 5 The diagram shown illustrates the material versatility of the SAM-ALD strategy in a three-dimensional phase change memory provided by an embodiment of the present invention. Figure 6 The image shown is a three-dimensional schematic diagram of a cross-section of a three-dimensional phase-change memory provided according to an embodiment of the present invention. Detailed Implementation

[0012] To make the objectives, technical solutions, and advantages of this invention clearer, the invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the invention. Furthermore, the technical features involved in the various embodiments of this invention described below can be combined with each other as long as they do not conflict with each other.

[0013] In this invention, the terms "first," "second," etc. (if present) in the invention and the accompanying drawings are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence.

[0014] Example 1: This invention discloses a method for fabricating a three-dimensional phase-change memory, such as... Figure 1 As shown, it includes: S1: A dielectric layer and a metal layer are sequentially deposited on a substrate to construct a periodically alternating multilayer film structure, with the top layer being the dielectric layer; see details [link to documentation]. Figure 1 and Figure 2 As shown, a dielectric layer and a metal layer are deposited sequentially on the substrate. The dielectric layer in contact with the substrate is the bottom dielectric layer. After periodically depositing dielectric and metal layers, the top dielectric layer is deposited. Figure 2 and 3 As shown, blue represents the dielectric layer and gray represents the metal layer. In one optional embodiment, a silicon substrate with good electrical insulation and flatness is selected as the basic structure of the three-phase memory. A silicon dioxide layer with a thickness of approximately 200 to 300 nanometers is thermally grown on its surface to achieve electrical insulation and structural support. In the actual fabrication process, to ensure the interface quality of subsequent film stacking, the substrate undergoes rigorous surface cleaning. The standard RCA process or a multi-step organic / inorganic impurity removal method is preferred, i.e., ultrasonic cleaning in acetone, isopropanol, or ethanol to remove surface organic contaminants; followed by thorough rinsing with deionized water and drying with high-purity nitrogen. If necessary, to further improve surface roughness, diluted hydrofluoric acid (DHF) can be used to lightly etch the surface to remove the natural oxide layer before regrowing a dense oxide film, resulting in a smooth, clean surface with excellent film formation conditions. Furthermore, on the surface-cleaned and pretreated substrate, dielectric and metal layers are sequentially deposited to construct a periodically alternating multilayer film structure, such as... Figure 2 and 3 As shown. In one embodiment, a silicon dioxide thin film is deposited on the substrate surface as a dielectric layer using chemical vapor deposition (CVD) or atomic layer deposition (ALD) techniques. Besides the silicon dioxide dielectric layer, other insulating materials can be used as the dielectric layer, with the thickness generally controlled between 30 and 50 nanometers, forming the first insulating dielectric layer. Subsequently, a metal layer of similar thickness, such as tungsten, gold, or copper, is deposited as the bottom electrode layer using sputtering or metal-organic chemical vapor deposition (MOCVD). By controlling the deposition rate and temperature, a tight interface bond and excellent flatness are ensured. This process is then repeated multiple times, such as 8 to 12 cycles, to achieve a periodic multilayer structure with alternating metal / dielectric layers. The entire multilayer system ends with a dielectric layer, which serves as insulation protection and pattern definition support. This alternating multilayer film structure provides the basis for the vertical electrode distribution for the subsequent formation of vertical electrode channels and phase change unit arrays.

[0015] S2: A circular aperture array pattern is formed on top of the aforementioned alternatingly stacked multilayer film structure using photolithography and development. Specifically, a layer of photoresist (PR), approximately 1 to 2 micrometers thick, is spin-coated onto the top of the formed alternatingly stacked multilayer film structure. Using ultraviolet lithography or electron beam lithography, a series of circular patterns arranged according to the design are defined on the photoresist surface. These circular areas correspond to the positions of the vertical phase-change memory cell channels that will be formed in the future. After exposure, the photoresist in the exposed areas is removed by a development process, resulting in a structure with periodic circular openings on the top. These openings will serve as etching windows for the subsequent formation of deep-hole channel structures that penetrate the alternatingly stacked multilayer film structure. Through the precise pattern definition in this step, the dimensional uniformity and array periodicity of the subsequent deep holes are ensured, thereby ensuring the geometric symmetry and repeatability of the device array in both the vertical and lateral directions.

[0016] S3: Using the circular aperture formed by photolithography as a mask, vertical etching is performed downwards, penetrating the dielectric and metal layers until reaching the bottom dielectric layer, resulting in a deep-hole etched structure. Specifically, using the circular opening formed by photolithography as a mask, reactive ion etching (RIE) or deep silicon etching (ICP) processes are employed to vertically etch downwards through the dielectric / metal layers, such as alternating SiO2 / W stacked layers, until approaching the bottom dielectric layer. During the etching process, the gas ratio and energy density are controlled to maintain high verticality, smooth sidewalls, and precise etching endpoints. After etching, the photoresist can be removed using organic solvents or oxygen plasma. This etching step forms a series of high aspect ratio cylindrical deep-hole structures with apertures approximately in the hundreds of nanometers range. The sidewalls of the holes consist of alternating exposed metal and dielectric layers arranged periodically. At this point, the entire structure has the rudiments of a three-dimensional electrode array, providing a spatial basis for subsequent selective sidewall etching and functional layer deposition.

[0017] S4: Lateral etching of the exposed metal layer in the deep hole etching structure forms a groove structure at the metal of the hole wall, wherein the groove structure is between adjacent dielectric layers, and there is one groove structure between every two adjacent dielectric layers; Reference Figure 2 and Figure 3As shown, based on the deep hole etching structure obtained in step S3, selective etching is performed on the hole walls to form periodic grooves. These grooves are placed in the metal layer, between adjacent dielectric layers. Due to the significant difference in etching rates between the metal and the dielectric, such as tungsten (W) and silicon dioxide (SiO2), by using chemically selective etching solutions, such as H2O2 solution or amino complex etching systems, the lateral etching rate of the metal layer can be much higher than that of the silicon dioxide layer. Under precise control of etching time and solution concentration, each metal layer undergoes a small amount of lateral erosion, while the dielectric layer remains almost uncorroded, thus forming a periodically arranged W-shaped groove structure on the sidewall of the deep hole. These grooves are alternately distributed along the vertical direction, forming confined functional regions, and are encapsulated and isolated by the upper and lower dielectric layers. The formation of this structure is a key step in the entire process, effectively defining the growth area of ​​subsequent functional materials, such as the PCM phase change layer and the OTS gate layer, so that they form functional units with confined volumes only within the W-shaped grooves.

[0018] S5: Plasma activation is performed on the inner sidewalls of the exposed metal and dielectric layers in the groove structure to obtain a metal layer with a high density of surface active sites and a dielectric layer with relatively inert surface states. The plasma gas includes monatomic, diatomic, or polyatomic gases. In one optional implementation, a SAM-free AS-ALD method is proposed. Through surface reactivity gating and a combined strategy of undersaturated pulse / extended purge, the functional layer nucleates and grows continuously only towards the metal layer within the groove in the three-dimensional vertical hole, while maintaining a long incubation period and extremely low deposition on the sidewalls of the dielectric layer. This allows for the acquisition of a confined structure without etch-back, solving the problems of leakage and thermal crosstalk between functional layers, and possessing BEOL compatibility and stackability. It should be noted that the functional layer here includes a self-gated material layer, or a functional layer composed of a gate material layer and a phase change material layer, which is used to store data.

[0019] Furthermore, surface reactivity gating specifically involves O2 plasma activation of the exposed metal / dielectric layer (e.g., W / SiO2) within the groove, using parameters such as 140 W, 20 sccm, 100 Pa, and 0–240 s. Plasma activation significantly increases the density of active sites on the metal layer surface while maintaining the relative inertness of the dielectric layer's surface states. This relative inertness refers to the exponential increase in activation effect on the metal layer compared to the dielectric layer. During activation, surface treatment parameters are selected corresponding to the point where the metal surface activity reaches its maximum. These parameters include plasma RF power, gas flow rate, chamber pressure, and processing time. In addition to plasma activation, undersaturated precursor pulses and extended purging are further employed, such as feeding with low saturation and extending purging at 80–120°C, to amplify the difference in incubation period between the metal layer and the dielectric layer, enabling rapid chemical adsorption nucleation at the metal layer and long-term incubation at the dielectric layer. The precursors used are GeCl2C4H8O2, Sb(OEt)3, and (Et3Si)2Te; N2 is used as the carrier / purge gas, for example, 600 sccm, 0.9 mbar.

[0020] S6: Selectively deposit functional layers in the groove structure. It should be noted that when the functional layer is a gate material layer, selective atomic layer deposition (SLD) is used to deposit it in the groove. When the functional layer is a gate material layer and a phase change material layer, the phase change material layer is deposited first, preferably a chalcogenide material such as Ge2Sb2Te5 (GST) or GeTe. The groove after step S5 exhibits atomic-level conformality and chemisorption selectivity; the material is deposited only in the groove with the metal surface, and hardly grows on the dielectric layer surface, achieving spatially selective coverage. Subsequently, a gate layer, such as an Ovonic Threshold Switch (OTS), is deposited in the same groove. Commonly used materials are As2S3, GeSe, or SiTe. Optimized processes achieve good interfacial bonding with the PCM phase change material layer. The two layers form a local PCM / OTS dual-functional stacked unit within the groove. This process step realizes the construction of a three-dimensional multilayer array of cells and ensures uniform functional layer thickness and a smooth interface.

[0021] S7: After functional layer deposition, metal material is backfilled into the deep holes to form the top electrode, completing the fabrication of the three-dimensional phase-change memory (PCM). Specifically, after functional layer deposition, metal material is backfilled into the deep holes using physical vapor deposition (PVD) or chemical vapor deposition (CVD) to form the top electrode. Commonly used top electrode materials are highly conductive metals such as TiN, W, or Pt. The backfilling process must ensure that the metal fully fills to the bottom of the hole to avoid voids. Subsequently, chemical mechanical polishing (CMP) is used to remove excess metal from the surface, ensuring the top electrode surface is flush with the SiO2 layer at the top of the multilayer structure. Next, photolithography and etching processes are used to define the top electrode interconnects, enabling array addressing functionality. Finally, a passivation layer (such as SiN or Al2O3) is deposited on the entire structure surface to isolate it from environmental moisture and oxidation reactions, enhancing the long-term reliability of the device. At this point, the entire confined three-dimensional vertical electrode structure of the PCM / OTS cell array is fabricated. Multiple PCM / OTS cells in the structure are connected in series along the vertical direction, sharing a single top electrode, achieving high-density three-dimensional integration and excellent electrical consistency.

[0022] To further illustrate the effectiveness of the three-dimensional memory fabricated using the above method Figure 4 The image shows a cross-sectional high-resolution transmission electron microscope (HRTEM) and corresponding energy dispersive spectroscopy (EDS) diagram of a three-dimensional phase-change memory provided according to an embodiment of the present invention; as shown. Figure 4 As shown, in the lateral metal grooves / receding cavities formed after etching, taking W / SiO2 as an example, the grooves are continuously and densely filled with the phase change material PCM; conversely, no discernible PCM deposition is observed in the adjacent SiO2 sidewalls and interstitial regions. HRTEM images reveal a sharp and regular W–SiO2 interface, with no obvious diffusion layer or blurred transition zone at the cavity boundary, demonstrating spatial selectivity and interface integrity of the deposition. In EDS mapping, Ge and Te signals are highly co-located with the W groove region in space, while Si signals are mainly distributed in adjacent insulating layers; the three almost do not overlap in space, further confirming that the phase change material is selectively deposited only in the W region. Observing along the depth direction, the thickness and morphology of the phase change film inside the cavity are basically consistent, without significant thinning or interruption with depth, indicating that at the approximately 1:1 aspect ratio used in this invention, the deposition on the target surface (activated W) still maintains good sidewall consistency and conformity; at the same time, SiO2 does not undergo nucleation and growth due to its limited incubation state. In conclusion, Figure 4 The red area in the middle visually demonstrates the high selectivity brought about by the surface activity regulation and low saturation pulse coupling strategy of this invention: the phase change film is effectively confined inside the W cavity and a sharp interface is formed at the W–SiO2 boundary, which lays the structural foundation for the thermal / electric localization and reliability improvement of subsequent devices.

[0023] Figure 5The diagram illustrates the material versatility of the SAM-free AS-ALD strategy in a three-dimensional phase change memory provided by an embodiment of the present invention. This invention can be extended to other technically relevant phase change materials, particularly Sb₂Te₃ and GeSbTe, which, like GeTe, are widely used in phase change materials due to their excellent electrical switching properties and thermal stability. The successful selective deposition of these multi-component phase change materials further demonstrates the robustness and versatility of the developed AS-ALD process.

[0024] Specifically, Figure 5 The left image shows SEM and EDS elemental mapping of photolithographically patterned W / SiO2 structures after Sb2Te3 deposition using AS-ALD technology. The same scheme as for GeTe optimization was employed: oxygen plasma pretreatment, such as 30 seconds and a low-saturation precursor pulse. EDS mapping reveals that Sb and Te signals are confined to the W regions, while no signals are detected in the adjacent SiO2 regions, indicating their chemical inertness. The surface morphology also shows uniform and continuous coverage on the W, consistent with successful nucleation and uniform film growth.

[0025] Figure 5 The right figure in the image shows similar results for GeSbTe films deposited under the same AS-ALD conditions. EDS mapping confirms that germanium, antimony, and tellurium selectively concentrate on the tungsten surface, while no measurable deposition is observed on silica. These findings further confirm the reliability of plasma-activated tungsten surfaces in promoting selective nucleation and growth, even in more complex ternary systems. Importantly, they demonstrate the broad applicability of the selective mechanism based on the thermodynamic advantage of precursor adsorption and the modulation of surface defect density, and are not limited to single materials or precursor combinations.

[0026] In summary, these results demonstrate that the atomic layer deposition (ALD) strategy for self-assembled monolayer SAMs developed in this study is applicable to a wide range of chalcogenide phase change memory (PCM) materials. The ability to selectively deposit multiple compositions on metal electrodes while excluding dielectric regions is crucial for the fabrication of heterostructures, the tuning of alloy compositions, and the design of multi-bit storage in advanced 3D-PCMs. Furthermore, this method enables the integration of chemically diverse materials into nanoscale architectures requiring precise spatial control.

[0027] Example 2: This invention discloses a three-dimensional phase-change memory fabricated using the method described in Example 1. For example... Figure 2 , Figure 3 as well as Figure 6As shown, adjacent dielectric layers include groove structures, in which functional layers are deposited. Each groove structure is independent, and the functional layers within each groove structure do not contact each other. The three-dimensional phase-change memory disclosed in this invention isolates the functional layers, effectively avoiding mutual interference and influence between them, and improving the stability of the memory.

[0028] In summary, the method for fabricating three-dimensional memory using SAM-free AS-ALD disclosed in this invention employs a surface reactive gating and undersaturated pulse / extended purge synergistic strategy. This allows the functional layer to nucleate and grow continuously only in the lateral recesses of the metal within the three-dimensional vertical aperture, while maintaining a long incubation period and extremely low deposition rate on the dielectric sidewall. This eliminates the need for etching back to obtain a confined structure, solves the problems of interlayer leakage and thermal crosstalk, and possesses BEOL compatibility and stackability.

[0029] Secondly, in the fabrication of the three-dimensional memory in this invention, selective loop closure and quantitative criteria can be used: under the same number of cycles M (e.g., 200–2000), the film thickness ratio of W / SiO2 in the same cycle is measured to be ≥50, preferably with a selectivity of ≥98% (2000 cycles); alternatively, the core density ratio or "total dielectric thickness ≤1nm (2000 cycles)" can be used as the selectivity criterion. Finally, in terms of structural integration, in the multilayer W / SiO2 stack, a lateral recess of approximately 10–80nm (e.g., ~30 nm) is formed by selective lateral etching of W with SF6 / O2, and PCM is grown only at the recess using the aforementioned AS-ALD; subsequently, the top electrode is backfilled to complete the device, without the need for sidewall etchback of the phase change material layer.

[0030] In one alternative embodiment, taking a phase change material layer and a gate material layer as examples, a (W 50 nm / SiO2 50 nm) × 6 stack is prepared on a Si substrate, with patterned openings exposing the sidewalls. The exposed W layer is laterally etched using SF6 / O2 plasma to form a ~30 nm depression. Surface activation is performed using O2 plasma at 140 W, 20 sccm, 100 Pa, and 30 s to enhance the active sites on the W surface while maintaining the inertia difference of SiO2. During AS-ALD, multi-component PCM (e.g., GeTe) deposition is performed at 90°C using undersaturated pulse and extended purge, with precursors: GeCl2C4H8O2, Sb(OEt)3, (Et3Si)2Te, N2 600 sccm, and 0.9 mbar. Selective loop closure: The selectivity of the W / SiO2 film thickness ratio is ≥98% after 2000 cycles; the total SiO2 deposition is ≤1 nm; this can also be confirmed by a core density ratio ≥100 (same cycle). After the structure is completed: the W top electrode is backfilled to complete the fabrication; the sidewall etchback step to remove the PCM is not performed. The three-dimensional phase change memory fabricated above has functional layers that are isolated from each other to avoid mutual interference.

[0031] In summary, this invention utilizes region-selective atomic layer deposition based on surface energy regulation. By differentially activating the chemical state of the substrate surface and combining it with low-saturation precursor pulses, it achieves self-aligned deposition on heterogeneous surfaces, eliminating traditional photolithography or masking processes and controlling nucleation behavior using the intrinsic properties of the material. In the fabrication of three-dimensional phase-change memory, this one-step selective film deposition method reduces more than half of the photolithography-etching steps, significantly lowering manufacturing costs. Simultaneously, it achieves sidewall deposition uniformity exceeding 98% in high aspect ratio structures. Inter-cell leakage current is reduced to extremely low levels, cycle life exceeds the million-cycle mark, thermal diffusion distance is limited to within 150 nanometers, and resistance window retention is improved to 95% at high temperatures. The method disclosed in this invention solves the region-selectivity defects of traditional deposition methods and provides a scalable manufacturing solution for high-density integration of three-dimensional memory, laying the foundation for the development of next-generation high-performance memory devices.

[0032] Those skilled in the art will readily understand that the above description is merely a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of the present invention should be included within the scope of protection of the present invention.

Claims

1. A method of fabricating a three-dimensional phase change memory, comprising: The method comprises the following steps: ​ S1: sequentially depositing a dielectric layer and a metal layer on a substrate to construct a periodic alternating multilayer film structure, wherein the top layer is the dielectric layer; S2: forming a circular hole array pattern on the top of the alternating multilayer film structure by photolithography and development; S3: vertically etching downward through the dielectric layer and the metal layer to the bottom dielectric layer to obtain a deep hole etching structure, using the circular hole formed by photolithography as a mask; S4: laterally etching the exposed metal layer in the deep hole etching structure to form a groove structure at the metal on the hole wall, wherein the groove structure is between adjacent dielectric layers, and each two adjacent dielectric layers comprise one groove structure; S5: plasma activating the exposed metal layer and the inner sidewall of the dielectric layer in the groove structure to obtain a metal layer with a high surface active site density and a dielectric layer with a relatively inert surface state; S6: selectively depositing a functional layer in the groove structure; S7: after the deposition of the functional layer is completed, backfilling a metal material in the deep hole to form a top electrode.

2. The method of claim 1, wherein the method further comprises: When the inner wall is plasma activated, the metal layer with a high surface active site density and the dielectric layer with a relatively inert surface state are obtained by using a low-saturation precursor pulse and prolonging the purge to cause preferential chemical adsorption-nucleation on the surface of the metal layer and maintain the incubation period on the surface of the dielectric layer.

3. The method of claim 1, wherein the method further comprises: When the inner wall is plasma activated, the activation parameters of the plasma include plasma radio frequency power, gas flow, cavity pressure, and processing time.

4. The method of claim 3, wherein the method further comprises: The plasma gas includes a monatomic gas, a diatomic gas, or a polyatomic gas.

5. The method of claim 1, wherein the method further comprises: When the dielectric layer and the metal layer are etched, a reactive ion etching or a deep silicon etching process is used.

6. The method of claim 1, wherein the method further comprises: The lateral etching of the exposed metal layer in the deep hole etching structure to obtain the groove structure comprises using a chemical selective etching solution H2O2 solution or an amino complex etching system for etching.

7. The method of claim 1, wherein the method further comprises: The functional layer is a self-selected material layer.

8. The method of claim 1, wherein the method further comprises: The functional layer comprises a phase change material layer and a selector material layer, and the phase change material layer is arranged between the metal layer and the selector material layer in the groove structure, wherein the phase change material layer comprises one or more of GeTe, Sb2Te3 or GST.

9. The method of claim 2, wherein the method further comprises: The precursor in the low-saturation precursor pulse comprises one or more of GeCl2C4H8O2, Sb(OEt)3 and (Et3Si)2Te, and the purge gas is N2.

10. A three-dimensional phase change memory prepared based on the preparation method of any one of claims 1-9, wherein adjacent dielectric layers comprise groove structures, a functional layer is deposited in the groove structures, each groove structure is independent of each other, and the functional layers in each groove structure are not in contact with each other.

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