Image sensor

Abstract

An image sensor includes: a first substrate having a first surface and a second surface opposite the first surface, and including a plurality of pixel region groups, each pixel region group including a plurality of pixel regions, the pixel regions oriented in a first direction and a second direction parallel to the first surface, the second direction intersecting the first direction; a first bond pad on the first surface and the pixel region group; a first shielding conductive pattern on the first surface, on each boundary of the pixel block parallel to the first direction, and oriented in the form of a matrix along the first direction and the second direction, columns of the matrix being separated from each other; and a first pickup region in at least one of the pixel regions, wherein each first shielding conductive pattern is electrically connected to the first pickup region in the corresponding pixel region.

Description

Technical Field

[0001] The inventive concept relates to image sensors and / or methods of manufacturing them. Background Technology

[0002] Image sensors can be or include semiconductor elements that convert optical images into electrical signals. Recently, with the development of the computer and communications industries, the demand for image sensors with improved performance has increased in various fields such as digital cameras, camcorders, personal communication systems (PCS), gaming devices, security cameras, and medical miniature cameras. Image sensors can be classified, for example, as charge-coupled device (CCD) type and complementary metal-oxide-semiconductor (CMOS) type. CMOS image sensors can provide multiple pixels arranged in a two-dimensional manner. Each pixel can include a photodiode (PD). The photodiode can be used to convert incident light into an electrical signal. Summary of the Invention

[0003] At least some example implementations relate to an image sensor that includes shielding conductive patterns spaced apart from each other and having short line patterns.

[0004] An image sensor may include: a first substrate having a first surface and a second surface opposite to the first surface, the first substrate including a plurality of pixel groups, each pixel group including a plurality of pixel regions oriented in a first direction and a second direction intersecting the first direction, the first and second directions being parallel to the first surface; a first bonding pad on the first surface of the first substrate and individually on each pixel group; a first shielding conductive pattern on the first surface of the first substrate, the first shielding conductive pattern being individually on each boundary of the pixel group parallel to the first direction, the first shielding conductive pattern being in the form of a matrix along the first and second directions, each column of the first shielding conductive pattern being spaced apart from each other; and a first pickup area in at least one pixel region of each pixel group, wherein each first shielding conductive pattern is electrically connected to the first pickup area in the first pickup area in the corresponding pixel region of the pixel group.

[0005] An image sensor may include: a first substrate having a first surface and a second surface opposite to the first surface, the first substrate including a plurality of pixel groups, each pixel group including a plurality of pixel regions, the pixel regions being oriented in a first direction and a second direction intersecting the first direction, the first direction and the second direction being parallel to the first surface; a first bonding pad on the first surface of the first substrate and individually on each pixel group; a first shielding conductive pattern on the first surface of the first substrate, the first shielding conductive pattern being individually on each boundary of the pixel group parallel to the first direction, the first shielding conductive pattern being in the form of a matrix along the first direction and the second direction, each column of the matrix being a first shielding conductive pattern. The electrical patterns are spaced apart from each other; a first pickup area, in at least one pixel area of ​​each pixel area group; a second substrate, having a third surface and a fourth surface, the third surface facing the first surface and the fourth surface opposite to the third surface; a second bonding pad on the third surface of the second substrate; a second shielding conductive pattern on the third surface of the second substrate, the second shielding conductive pattern being individually bonded to each first shielding conductive pattern; and a second pickup area in the second substrate, wherein each first shielding conductive pattern is electrically connected to a first pickup area in a corresponding pixel area of ​​the pixel area group, and each second shielding conductive pattern is electrically connected to a corresponding pickup area in the second pickup area. Each of the first and second shielding conductive patterns may have a strip shape extending in a first direction. Attached Figure Description

[0006] Figure 1 This is a block diagram of an image sensor according to some example implementations.

[0007] Figure 2 This is a circuit diagram of a pixel array of an image sensor according to some example implementations.

[0008] Figure 3A and Figure 3B This is a circuit diagram of a pixel group of an image sensor according to some example implementations.

[0009] Figure 4 This is a plan view of an image sensor according to some example implementations.

[0010] Figure 5 This is a plan view of an image sensor according to some example implementations.

[0011] Figures 6 to 8 An image sensor according to some example embodiments is shown. Figures 6 to 8 It corresponds to Figure 4 A magnified cross-sectional view of part of 'PXRG'.

[0012] Figure 9 Is with Figure 6The cross-sectional view corresponding to line I-I'.

[0013] Figure 10 Is with Figure 6 The cross-sectional view corresponding to line II-II'.

[0014] Figure 11 Is with Figure 6 The cross-sectional view corresponding to line III-III'.

[0015] Figure 12 Is with Figure 6 The cross-sectional view corresponding to line IV-IV'.

[0016] Figure 13 An image sensor according to some example embodiments is shown. Figure 13 It corresponds to Figure 8 The cross-sectional view of line II-II'.

[0017] Figure 14 This is a cross-sectional view of an image sensor according to some example implementations.

[0018] Figure 15 This is a plan view of an image sensor according to some example implementations.

[0019] Figure 16 Is with Figure 15 The cross-sectional view corresponding to line I-I'. Detailed Implementation

[0020] In the following, some exemplary embodiments of the inventive concept are described in detail with reference to the accompanying drawings.

[0021] Figure 1 This is a block diagram of an image sensor according to some example implementations.

[0022] Reference Figure 1 An image sensor according to some example implementations may include a pixel array 1, a row decoder 2, a row driver 3, a column decoder 4, a timing generator 5, a correlated double sampler (CDS) 6, an analog-to-digital converter (ADC) 7, and an input / output buffer (I / O buffer) 8.

[0023] Pixel array 1 may include a plurality of pixels arranged in a two-dimensional manner. According to some example embodiments, some of the pixels may form pixel groups, and multiple pixel groups may be arranged in pixel array 1 in a two-dimensional manner. Pixels can convert optical signals into electrical signals. Pixel array 1 may be driven by a plurality of drive signals (e.g., pixel selection signals, reset signals, and / or charge transfer signals) transmitted from row driver 3. The converted electrical signals may be provided to the associated dual sampler 6.

[0024] The row driver 3 can provide multiple drive signals to the pixel array 1 to drive multiple pixels based on the decoding results in the row decoder 2. When the pixels are arranged in a matrix, the drive signals can be provided on a row-by-row basis.

[0025] The timing generator 5 can provide timing and control signals to the row decoder 2 and the column decoder 4.

[0026] The correlated double sampler 6 can receive electrical signals generated from the pixel array 1, and can hold and sample the received signals. The correlated double sampler 6 can double sample a specific noise level and a signal level caused by the electrical signal to output a differential level corresponding to the difference between the noise level and the signal level.

[0027] The analog-to-digital converter 7 can convert the analog signal corresponding to the differential level output from the correlated dual sampler 6 into a digital signal, and can output a digital signal.

[0028] The input / output buffer 8 can latch digital signals and output the latched signals sequentially to the image signal processor (not shown) based on the decoding results in the column decoder 4.

[0029] Figure 2 It is a circuit diagram of pixels included in a pixel array of an image sensor according to some example implementations.

[0030] Reference Figure 2 The pixel array may include multiple pixels PXL, and the pixels PXL may be arranged in a matrix. Each pixel PXL may include a transfer transistor TX and logic transistors CX, SX, and SFX. The logic transistors CX, SX, and SFX may include a control transistor CX, a selection transistor SX, and a source follower transistor SFX. The transfer gate of the transfer transistor TX may be connected to a transfer gate line TGL. Each pixel PXL may further include, for example, a photodiode PD and a floating diffusion region FD.

[0031] A photodiode (PD) can generate and accumulate photocharge in proportion to the amount of light incident from the outside. A photodiode (PD) can include, for example, a photoelectric conversion element, a phototransistor, a photogate, a pinned photodiode, or a combination thereof. A transfer transistor (TX) can transfer the photocharge generated from the photodiode (PD) to a floating diffusion region (FD). The floating diffusion region (FD) can receive and accumulate the photocharge generated from the photodiode (PD).

[0032] The gate of a source follower transistor (SFX) can be connected to the floating diffusion region (FD). One source / drain electrode of the source follower transistor (SFX) can be connected to the power supply voltage node V. DDThe source follower transistor SFX can be controlled based on the amount of photocharge accumulated in the floating diffusion region FD.

[0033] The control transistor CX can be used as a reset transistor RX to periodically reset the photocharge accumulated in the floating diffusion region FD. The gate of the control transistor CX can be connected to the reset gate line RGL. Each source / drain electrode of the control transistor CX can be connected to the floating diffusion region FD and the power supply voltage node V. DD Each of these (e.g., the source / drain electrodes of the control transistor CX) can be individually or separately connected to the floating diffusion region FD and the power supply voltage node V. DD Each of them). For example, the power supply source / drain electrodes of the control transistor CX can be connected to the power supply voltage node V. DD Furthermore, the control source / drain electrodes of the control transistor CX can be connected to the floating diffusion region FD. When the control transistor CX is turned on, the charge accumulated in the floating diffusion region FD can be released through the power supply voltage node V. DD The power supply voltage is discharged, thereby resetting the floating diffusion region FD.

[0034] A source follower transistor (SFX) can be used as a source follower buffer amplifier. The SFX amplifies the potential change in the floating diffuser region (FD) and outputs the amplified potential change to the output line V. OUT .

[0035] The gate of the selector transistor SX can be connected to the select gate line SGL. Each of the source / drain electrodes of the selector transistor SX can be connected to the other source / drain electrodes of the source follower transistor SFX and the output line V. OUT Each pixel PXL to be read in rows can be selected by the selection transistor SX via a selection signal applied through the corresponding selection gate line SGL. When the selection transistor SX is turned on, the potential change amplified by the source follower transistor SFX can be output to the output line V through the selection transistor SX. OUT .

[0036] Figure 3A and Figure 3B This is a circuit diagram of a pixel group of an image sensor according to some example implementations.

[0037] Reference Figure 3A and Figure 3B A pixel array can include pixel groups PXLG, and each pixel group PXLG can include multiple pixels. Figure 3A and Figure 3B Each of the diagrams shows a circuit diagram of a single pixel group PXLG.

[0038] Reference Figure 3A In some example implementations, the pixel group PXLG may include four pixels (e.g., first to fourth pixels). The first pixel may include a first transmission transistor TX1 and a first photodiode PD1, the second pixel may include a second transmission transistor TX2 and a second photodiode PD2, the third pixel may include a third transmission transistor TX3 and a third photodiode PD3, and the fourth pixel may include a fourth transmission transistor TX4 and a fourth photodiode PD4. The gates of the first to fourth transmission transistors TX1 and TX4 may be connected to the first transmission gate line TGL1, the first transmission gate line TGL2, the first transmission gate line TGL3, and the fourth transmission gate line TGL4, respectively. In some example implementations, the first to fourth pixels of the pixel group PXLG may share the previously described reset transistor RX, source follower transistor SFX, and select transistor SX.

[0039] Reference Figure 3B In some example embodiments, the pixel group PXLG may include, for example, eight pixels. The first to eighth pixels may respectively include a first transmission transistor TX1, a second transmission transistor TX2, a third transmission transistor TX3, a fourth transmission transistor TX4, a fifth transmission transistor TX5, a first transmission transistor TX6, a first transmission transistor TX7, and an eighth transmission transistor TX8, and a first photodiode PD1, a second photodiode PD2, a third photodiode PD3, a fourth photodiode PD4, a fifth photodiode PD5, a sixth photodiode PD6, a seventh photodiode PD7, and an eighth photodiode PD8. The gates of the first to eighth transmission transistors TX1 may be connected to the first transmission gate line TGL1, the second transmission gate line TGL2, the third transmission gate line TGL3, the fourth transmission gate line TGL4, the fifth transmission gate line TGL5, the sixth transmission gate line TGL6, the seventh transmission gate line TGL7, and the eighth transmission gate line TGL8, respectively. In some example embodiments, the first to eighth pixels may share the previously described reset transistor RX, source follower transistor SFX, and select transistor SX.

[0040] In Figure 3A and Figure 3B In some exemplary embodiments, the pixel group PXLG may include, for example, four or eight pixels. However, the exemplary embodiments of the inventive concept are not limited to this, and the number of pixels in the pixel group PXLG may vary.

[0041] Figure 4 This is a plan view of an image sensor according to some example implementations. Figure 5 This is a plan view of an image sensor according to some example implementations. Figures 6 to 8An image sensor according to some example embodiments is shown. Figures 6 to 8 It corresponds to Figure 4 A magnified cross-sectional view of part of 'PXRG'. Specifically, for ease of explanation and illustration, in Figures 6 to 8 Some components have been omitted. For example, in Figure 6 The shielding conductive pattern and bonding pads are omitted in the text. Figure 7 The shielding conductive pattern, bonding pads, and some wiring layers are omitted in the text. Figure 8 The shielding conductive pattern, bonding pads, and wiring layers are omitted. Figure 9 Is with Figure 6 The cross-sectional view corresponding to line I-I'. Figure 10 Is with Figure 6 The cross-sectional view corresponding to line II-II'. Figure 11 Is with Figure 6 The cross-sectional view corresponding to line III-III'. Figure 12 Is with Figure 6 The cross-sectional view corresponding to line IV-IV'.

[0042] Reference Figure 4 and Figures 6 to 12 An image sensor according to some example embodiments may include a photoelectric conversion structure 100. The photoelectric conversion structure 100 may be referred to as a first structure 100 and may include a photoelectric conversion layer 10, a first wiring layer 20a, and a light control layer 30. An intermediate structure 200 may be referred to as a second structure 200 and may include a second wiring layer 20b and an intermediate layer 40. The first structure 100 may be stacked on the second structure 200.

[0043] The photoelectric conversion layer 10 can be disposed between the first wiring layer 20a and the light control layer 30, and can include a first substrate 110, a photodiode 120, a first deep element isolation pattern DTI1, a second deep element isolation pattern DTI2, a first shallow element isolation pattern STI1, a floating diffusion region FD, a transmission gate TG, a first pickup region 130 and a gate insulating film 140.

[0044] The first substrate 110 may have a first surface 111 and a second surface 113 opposite to the first surface 111. The first surface 111 may be the front surface of the first substrate 110, and the second surface 113 may be the rear surface of the first substrate 110. Light may be incident on the second surface 113 of the first substrate 110. In other words, the second surface 113 of the first substrate 110 may be a light incident surface.

[0045] The first substrate 110 may be, for example, a silicon (Si) substrate, a germanium (Ge) substrate, a silicon-germanium (Si-Ge) substrate, a group II-VI compound semiconductor substrate, a group III-V compound semiconductor substrate, or a silicon-on-insulator (SOI) substrate, but the exemplary embodiments are not limited thereto. The first substrate 110 may include impurities of a first conductivity type, and therefore, the first substrate 110 may have a first conductivity type. For example, the impurities of the first conductivity type may be group III elements. For example, the impurities of the first conductivity type may include p-type impurities, such as, for example, aluminum (Al), boron (B), indium (In), and / or gallium (Ga).

[0046] A photodiode 120 may be provided in the first substrate 110. In some example embodiments, the photodiode 120 may include impurities having a second conductivity type different from the first conductivity type; therefore, the photodiode 120 may have a second conductivity type. For example, the impurities of the second conductivity type may be or include group V elements. For example, the impurities of the second conductivity type may include N-type impurities, such as, for example, phosphorus, arsenic, bismuth, and / or antimony.

[0047] The first substrate 110 and the photodiode 120 can form the aforementioned photodiode PD by forming a PN junction between them.

[0048] In some example embodiments, a first deep element isolation pattern (DTI1) is provided in the first substrate 110 to define a pixel region group (PXRG) in the first substrate 110. In some example embodiments, the first deep element isolation pattern (DTI1) may extend through the first substrate 110. For example, the first deep element isolation pattern (DTI1) may extend through the first surface 111 and the second surface 113 of the first substrate 110 and the substrate body between the first surface 111 and the second surface 113 of the first substrate 110.

[0049] In some example embodiments, a first deep element isolation pattern (DTI1) may be formed in the first substrate 110 to surround each pixel group PXRG in a planar view. For example, the first deep element isolation pattern (DTI1) may be formed by filling deep trenches formed by patterning in the first substrate 110 with an insulating material (e.g., by deep trench isolation (DTI) technology). In some example embodiments, the pixel groups PXRG may be arranged in two dimensions.

[0050] Each pixel region group PXRG may have at least two pixel regions PXR. In some example embodiments, the at least two pixel regions PXR may be separated by at least one of various isolation techniques. For example, the at least two pixel regions PXR may be separated from each other by a doped isolation technique. For example, a doped isolation region may be provided between the at least two pixel regions PXR. Alternatively, the at least two pixel regions PXR may be separated from each other by a second deep element isolation pattern DTI2. In other words, the second deep element isolation pattern DTI2 may be formed in the first substrate 110 between the at least two pixel regions PXR. Alternatively, a doped isolation region and the second deep element isolation pattern DTI2 may be formed in the first substrate 110 between the at least two pixel regions PXR.

[0051] In other words, each pixel region PXR may be defined by a first deep element isolation pattern DTI1 and a second deep element isolation pattern DTI2. According to some example embodiments, in a plan view, each pixel region PXR may be a portion of the first substrate 110 surrounded or at least partially surrounded by the first deep element isolation pattern DTI1 and the second deep element isolation pattern DTI2, or may be included in the portion of the first substrate 110 surrounded or at least partially surrounded by the first deep element isolation pattern DTI1 and the second deep element isolation pattern DTI2. The pixel regions PXR of the pixel region group PXRG may be arranged in a matrix along a first direction D1 and a second direction D2. In some example embodiments, the first direction D1 and the second direction D2 may be parallel to the first surface 111 of the first substrate 110 and may intersect each other. For example, the first direction D1 and the second direction D2 may be perpendicular to each other. The first deep element isolation pattern DTI1 and the second deep element isolation pattern DTI2 may extend in a direction perpendicular to the first surface 111 of the first substrate 110 (e.g., a third direction D3).

[0052] A first shallow element isolation pattern STI1 may be provided in the first substrate 110 to define an active region. The first shallow element isolation pattern STI1 may be adjacent to a first surface 111 of the first substrate 110. The first shallow element isolation pattern STI1 may be provided between active regions to electrically isolate the active regions from each other. In some example embodiments, the first shallow element isolation pattern STI1 may define at least one active region in each pixel region.

[0053] In some example implementations, the first deep element isolation pattern DTI1 may overlap or at least partially overlap with the first shallow element isolation pattern STI1. For example, the first deep element isolation pattern DTI1 may extend through a portion of the first shallow element isolation pattern STI1. The overlapping portion of the first deep element isolation pattern DTI1 and the first shallow element isolation pattern STI1 may correspond to a portion of the first shallow element isolation pattern STI1 or a portion of the first deep element isolation pattern DTI1.

[0054] A transfer gate TG can be disposed on a first surface 111 of the first substrate 110. The transfer gate TG can be disposed on a corresponding active region (hereinafter referred to as the first active region) of each pixel region. A gate insulating film 140 can be disposed between the transfer gate TG and the first active region.

[0055] The floating diffusion region FD can be located in the first active region on one side of the transfer gate TG. In some example embodiments, the floating diffusion region FD can be, for example, a region doped with impurities having a second conductivity type.

[0056] like Figures 4 to 9 As shown, floating diffusion regions FD provided in each of two adjacent pixel regions PXR can be connected to each other to form a single floating diffusion region FD.

[0057] The first pickup region 130 may be provided in a second active region spaced apart from the first active region. In some example embodiments, the first pickup region 130 may be, for example, a region doped with an impurity of a second conductivity type.

[0058] In some example embodiments, a gate spacer (not shown) may be provided on the side surface of the transmission gate TG. The gate spacer may, for example, comprise an insulating material different from the insulating material of the first shallow element isolation pattern STI1. For example, when the first shallow element isolation pattern STI1 comprises silicon oxide, the gate spacer may comprise silicon nitride and / or silicon oxide nitride, but the example embodiments are not limited thereto.

[0059] The first wiring layer 20a may include a first interlayer insulating film 150, a first contact plug 160, a first wiring 170, a first bonding pad 410, and a first shielding conductive pattern 510.

[0060] A first interlayer insulating film 150 may be provided on a first surface 111 of the first substrate 110. The first interlayer insulating film 150 may cover the first surface 111, the floating diffusion region FD, and the transport gate. For example, each first interlayer insulating film 150 may include at least one of silicon oxide, silicon oxide nitride, and silicon nitride, but the exemplary embodiments are not limited thereto. In some exemplary embodiments, the first interlayer insulating films 150 may be sequentially stacked on the first surface 111 of the first substrate 110. A first contact plug 160 and a first wiring 170 may be provided in the first interlayer insulating film 150.

[0061] The first bonding pad 410 may be provided on the first surface 111 of the first substrate 110, and may be provided on any or each of the pixel region groups PXRG. In some example embodiments, the first bonding pad 410 may be disposed in the lowest layer of the first interlayer insulating film 150 (e.g., the lowest first interlayer insulating film in the first interlayer insulating film 150) and / or at its level, but the example embodiments are not limited thereto.

[0062] In some example embodiments, each first bonding pad 410 may be electrically connected to one of the floating diffusion regions FD provided in a corresponding one of the pixel region groups PXRG. In some example embodiments, the first bonding pad 410 may include, for example, copper, but the example embodiments are not limited thereto.

[0063] Each first shielding conductive pattern 510 may be provided on a first surface 111 of the first substrate 110, and may be provided on each of the boundaries of the pixel region group PXRG parallel to the first direction D1 (e.g., the first shielding conductive pattern 510 may be individually or separately on each of the boundaries of the pixel region group PXRG). In some example embodiments, the first shielding conductive pattern 510 may be located within the lowest layer of the first interlayer insulating film 150 (e.g., the lowest first interlayer insulating film 150 of the first interlayer insulating films 150) and / or at its level.

[0064] The first shielding conductive pattern 510 may be arranged in a matrix (e.g., oriented) along a first direction D1 and a second direction D2. In some example embodiments, the first shielding conductive patterns 510 forming each column of the matrix (e.g., each column of the matrix) may be spaced apart from each other. For example, the first shielding conductive patterns 510 may be physically spaced apart from each other.

[0065] In some example embodiments, each first shielding conductive pattern 510 may be electrically connected to a first pickup area 130 provided in a corresponding one of the pixel area groups PXRG. Furthermore, each first shielding conductive pattern 510 may have a strip shape extending along a first direction D1. Figure 4 and Figure 5 As shown, the length of each first shielding conductive pattern 510 in the first direction D1 may be greater than (e.g., greater than) or equal to the width of each first bonding pad 410 in the first direction D1. In some example embodiments, the first shielding conductive pattern 510 may not be provided on the boundary of the pixel group PXRG parallel to the second direction D2.

[0066] Reference Figures 6 to 9For example, in some example embodiments, each pixel region group PXRG may include eight pixel regions PXR, and the first pickup area 130 and the transmission gate TG may be provided in and / or on each pixel region PXR. However, the example embodiments are not limited thereto. In some example embodiments, the number of pixel regions PXR in the pixel region group PXRG may vary (e.g., may be different). In some example embodiments, the first pickup area 130 may be provided in at least one of the pixel regions PXR in the pixel region group PXRG.

[0067] In some example implementations, the first bonding pad 410 can be electrically connected to the floating diffusion region FD in each pixel group PXRG via a corresponding first wiring in the first wiring 170 and a corresponding first contact plug in the first contact plug 160. Similarly, each first shielding conductive pattern 510 can be electrically connected to the first pickup region 130 in the corresponding pixel group PXRG via (e.g., through) a corresponding first wiring in the first wiring 170 and a corresponding first contact plug in the first contact plug 160.

[0068] The intermediate layer 40 may include a second substrate 210, a second shallow element isolation pattern STI2, a second pickup area 230, a gate, and a second gate insulating film 240. The second wiring layer 20b may include a second interlayer insulating film 250, a second contact plug 260, a second wiring 270, a second bonding pad 420, and a second shielding conductive pattern 520.

[0069] The second substrate 210 may have a third surface 211 facing the first surface 111 of the first substrate 110 and a fourth surface 213 opposite to the third surface 211.

[0070] The second shallow element isolation pattern STI2 may be disposed in a shallow trench recessed to a certain depth from (e.g., relative to) the third surface 211 of the second substrate 210. In other words, the second shallow element isolation pattern STI2 may be adjacent to the third surface 211 of the second substrate 210. In some example embodiments, the second shallow element isolation pattern STI2 may define an active region (e.g., a third active region, a fourth active region, etc.) in the second substrate 210.

[0071] Gates (e.g., reset gate, select gate, source follower gate SFG, etc.) may be disposed on corresponding third active regions of the second substrate 210. In some example embodiments, the reset gate (not shown), select gate (not shown), and source follower gate SFG may be disposed on the third surface 211 of the second substrate 210. A second gate insulating film 240 may be disposed between each of the corresponding third active regions of the reset gate, select gate, and source follower gate SFG. Source / drain regions may be disposed in the corresponding third active regions on both sides of each gate.

[0072] The second pickup region 230 may be provided in a fourth active region spaced apart from the third active region. In some example embodiments, the second pickup region 230 may be a region doped with an impurity of a second conductivity type. In some example embodiments, a plurality of fourth active regions may be defined in the second substrate 210, and each of the plurality of second pickup regions 230 may be provided in each of the plurality of fourth active regions (e.g., the second pickup region 230 may be in each of the fourth active regions). Each of the plurality of second pickup regions 230 may correspond to each of the plurality of second shielding conductive patterns 520 (e.g., one).

[0073] The second wiring layer 20b may include a second interlayer insulating film 250, a second contact plug 260, a second wiring 270, a second bonding pad 420, and a second shielding conductive pattern 520.

[0074] A second interlayer insulating film 250 may be provided on the third surface 211 of the second substrate 210. The second interlayer insulating film 250 may cover the third surface 211, the gate, and the second pickup region 230. In some example embodiments, each second interlayer insulating film 250 may include at least one of silicon oxide, silicon oxide nitride, or silicon nitride, but the example embodiments are not limited thereto. In some example embodiments, the second interlayer insulating films 250 may be sequentially stacked on the third surface 211 of the second substrate 210. A second contact plug 260 and a second wiring 270 may be provided in the second interlayer insulating film 250.

[0075] Each second bonding pad 420 may be provided on the third surface 211 of the second substrate 210 and may be provided on each pixel group PXRG (e.g., each pixel group PXRG may have a second bonding pad 420 thereon). In some example embodiments, the second bonding pad 420 may be disposed in the uppermost layer of the second interlayer insulating film 250.

[0076] In some example embodiments, each second bonding pad 420 may be electrically connected to a source follower gate SFG provided on a third surface 211 of the second substrate 210. In some example embodiments, the second bonding pad 420 may include copper.

[0077] The first bonding pad 410 and the second bonding pad 420 can be electrically connected to structures 100 and 200. In other words, the floating diffusion region FD and the source follower gate SFG in the image sensor can be electrically connected. In this case, the first bonding pad 410 and the second bonding pad 420 can be bonded to each other, for example, by copper-copper bonding technology. The bonded bonding pads 410 and 420 can, for example, be formed as a single body with no boundary surface therebetween. In some example embodiments, the lowermost layer of the first interlayer insulating film 150 (e.g., the lowermost first interlayer insulating film) can be covalently bonded to the uppermost layer of the second interlayer insulating film 250 (e.g., the uppermost second interlayer insulating film).

[0078] Each second shielding conductive pattern 520 may be provided on the third surface 211 of the second substrate 210, and may be provided on each of the boundaries of the pixel group PXRG parallel to the first direction D1 (e.g., each of the boundaries of the pixel group PXRG parallel to the first direction D1 may have one of the second shielding conductive patterns 520 thereon). In some example embodiments, the second shielding conductive pattern 520 may be located in the uppermost layer of the second interlayer insulating film 250 (e.g., the uppermost second interlayer insulating film).

[0079] The second shielding conductive pattern 520 can be arranged in a matrix along the first direction D1 and the second direction D2. In some example embodiments, each column of the second shielding conductive pattern 520 forming the matrix can be spaced apart from each other. For example, the second shielding conductive patterns 520 can be physically spaced apart from each other.

[0080] In some example embodiments, each second shielding conductive pattern 520 may be electrically connected to a second pickup area 230 provided in the second substrate 210. Furthermore, each second shielding conductive pattern 520 may have a strip shape extending in the first direction D1. For example, the length of each second shielding conductive pattern 520 in the first direction D1 may be longer than (e.g., greater than) or equal to the width of each second bonding pad 420 in the first direction D1. In some example embodiments, the second shielding conductive pattern 520 may not be provided on the boundary of the pixel group PXRG parallel to the second direction D2.

[0081] In some example implementations, each second shielding conductive pattern 520 may be bonded to each first shielding conductive pattern 510 (e.g., the second shielding pattern 520 may be individually bonded to each first shielding conductive pattern 510).

[0082] The light control layer 30 may include a light-transmitting film 180, a grid 190, a color filter CF, and a microlens ML.

[0083] A light-transmitting film 180 may be provided on the second surface 113 of the first substrate 110. The light-transmitting film 180 may cover the second surface 113 of the first substrate 110 and the upper surfaces of the first deep element isolation pattern DTI1 and the second deep element isolation pattern DTI2. The light-transmitting film 180 may include a transparent insulating material.

[0084] A grid 190 may be provided on the second surface 113 of the first substrate 110, with a light-transmitting film 180 interposed therebetween. In other words, the grid 190 may be provided on the light-transmitting film 180. The grid 180 may define an opening. A color filter array comprising two-dimensionally arranged color filters CF may be provided on the second surface 113 of the first substrate 110. The color filter array may be provided on the light-transmitting film 180, and each color filter CF may fill a corresponding opening in the opening of the grid 190. A lens array comprising two-dimensionally arranged microlenses ML may be provided on the second surface 113 of the first substrate 110, with the color filter array interposed therebetween. For example, the color filter array may be disposed between the lens array and the light-transmitting film 180.

[0085] In some example implementations, each color filter CF may cover or at least partially cover a corresponding pixel area within a pixel region. For example, each color filter CF may be positioned on two pixel regions PXR arranged in a 1×2 matrix in a plan view. In other words, each color filter CF may cover or at least partially cover a pair of adjacent pixel regions PXR. However, the example implementations are not limited to this. For example, each color filter CF may be positioned on four pixel regions PXR arranged in a 2×2 matrix in a plan view. Additionally, as... Figure 4 and Figure 5 As shown, each color filter CF can be set on eight pixel areas PXR arranged in a 2×4 matrix, nine pixel areas PXR arranged in a 3×3 matrix, or sixteen pixel areas PXR arranged in a 4×4 matrix.

[0086] In some example implementations, a color filter CF may include a first color filter having a first color, a second color filter having a second color, and a third color filter having a third color. For example, each color filter CF may have any one of red, green, or blue. Alternatively, each color filter CF may have any one of cyan, magenta, or yellow. In addition to the previously described red, green, blue, cyan, magenta, or yellow, color filter CF may also have other colors.

[0087] The grating 190 can guide incident light into the photodiode 120. The grating 190 can have a single-layer or multi-layer structure. The grating 190 can include metallic materials (e.g., titanium, tungsten, aluminum, tantalum, etc.), metal nitrides (e.g., titanium nitride, tantalum nitride, etc.), and / or low-refractive-index materials, but the example embodiments are not limited thereto. Low-refractive-index materials can refer to materials with a refractive index lower than that of silicon (Si). In some example embodiments, low-refractive-index materials can include metal oxides, and / or polymers, and silicon dioxide nanoparticles in the polymer. For example, low-refractive-index materials can include at least one of silicon oxide, aluminum oxide, tantalum oxide, or silicon hydrogen nitride. In some example embodiments, low-refractive-index materials can have insulating properties.

[0088] In some example embodiments, the grating 190 may at least perpendicularly overlap or at least partially overlap with the second deep element isolation pattern DTI2. In some example embodiments, although not shown, the grating 190 may also perpendicularly overlap or at least partially overlap with the first deep element isolation pattern DTI1. However, the example embodiments are not limited thereto. In some example embodiments, when the grating 190 is laterally shifted, at least a portion of the grating 190 may not perpendicularly overlap with the first deep element isolation pattern DTI1 and the second deep element isolation pattern DTI2. For example, the grating 190 may have a structure laterally offset from the first deep element isolation pattern DTI1 and the second deep element isolation pattern DTI2. The offset structure may be intentionally selected to optimize or customize the optical path, taking into account manufacturing process allowances and / or the angle of travel of incident light.

[0089] A microlens ML may be disposed on the light-transmitting film 180, with a color filter CF inserted therebetween. At least a portion of the microlens ML may perpendicularly overlap or partially overlap with the photodiode 120. The microlens ML may converge light incident toward the first substrate 110. In some example embodiments, the microlens ML may comprise organic materials, such as, for example, polymers. For example, the microlens ML may comprise a light-transmitting resin, a photoresist material, and / or a thermosetting resin, but the example embodiments are not limited thereto.

[0090] In some example embodiments, the microlens ML may include a lens pattern and a planarization portion. The planarization portion may be provided on the color filter CF, and the lens pattern may be provided on the planarization portion. The lens pattern may include, for example, the same material as the planarization portion, but the example embodiments are not limited thereto. The lens pattern and the planarization portion may be formed into a single body without a boundary surface therebetween. In some example embodiments, the planarization portion may be omitted, and the lens pattern may be directly disposed on the color filter CF.

[0091] In some example embodiments, each microlens ML may cover or at least partially cover each pixel region. In other words, each microlens ML may vertically overlap or at least partially overlap with a corresponding pixel region within a pixel region. Therefore, each microlens ML may cover or at least partially cover a pair of sub-pixel regions included in a corresponding pixel region. Each microlens ML may vertically overlap or at least partially overlap with a pair of photodiodes 120 formed in a pair of sub-pixel regions. In some example embodiments, each microlens ML in the lens array may vertically overlap or at least partially overlap with a corresponding pixel region within a pixel region. Each microlens ML may be provided to converge incident light and may include a spherical lens, an aspherical lens, or a combination thereof. For example, each microlens ML may have an upwardly convex shape in a cross-sectional view, but the example embodiments are not limited to this.

[0092] The image sensor described above may include a first shielding conductive pattern 510 and a second shielding conductive pattern 520 spaced apart from each other and having a short line shape. When a long line shape is formed in the image sensor, one or more micro-voids may be formed in one or more portions susceptible to plasma-induced damage (PID) associated with the manufacturing process. Micro-voids may cause, for example, white spots. However, according to the example embodiment, the first shielding conductive pattern 510 and the second shielding conductive pattern 520 spaced apart from each other and having a short line shape can be provided in the image sensor. Therefore, damage caused by plasma can be limited, minimized, or prevented. Furthermore, the first shielding conductive pattern 510 and the second shielding conductive pattern 520 may be connected to the first pickup area 130 and the second pickup area 230. Therefore, even when a charge is induced in the first shielding conductive pattern 510 and the second shielding conductive pattern 520 by plasma during the manufacturing process, the induced charge can be discharged relatively smoothly through the first pickup area 130 and the second pickup area 230. Therefore, damage to the first shielding conductive pattern 510 and the second shielding conductive pattern 520 can be limited, minimized, or prevented.

[0093] Figure 13 An image sensor according to some example embodiments is shown. Figure 13 It corresponds to Figure 8The cross-sectional view of line II-II' is shown below. For ease of explanation, the differences from the embodiments described above will be primarily described.

[0094] Reference Figure 13 , Figure 8 The image sensor in the image sensor comprises eight pixel regions (PXR) arranged in a 2×4 matrix, while Figure 13 The image sensor in the image sensor may include four pixel regions (PXRs) arranged in a 2×2 matrix. In other words, as described above, the number of pixel regions (PXRs) in the pixel region group (PXRG) can be varied.

[0095] Figure 14 This is a cross-sectional view of an image sensor according to some example implementations.

[0096] Reference Figure 14 An image sensor according to some example embodiments may include first to third structures 100, 200, and 300. The first structure 100 may be stacked on the second structure 200, and the second structure 200 may be stacked on the third structure 300. In other words, the second structure 200 may be disposed between the first structure 100 and the third structure 300. The third structure 300 may be referred to as a peripheral circuit structure or a third chip. The first structure 100 and the second structure 200 may be joined to each other by at least one of various joining methods and electrically connected to each other by at least one of various connection methods. Similarly, the second structure 200 and the third structure 300 may be joined to each other by at least one of various joining methods and electrically connected to each other by at least one of various connection methods.

[0097] The second structure 200 may further include a third wiring layer 20c, and an intermediate layer 40 may be disposed between the second wiring layer 20b and the third wiring layer 20c. The third wiring layer 20c may include a second interlayer insulating film 250 and a third bonding pad 430. The third bonding pad 430 may be disposed in the bottommost layer of the second interlayer insulating film 250.

[0098] The third structure 300 may include a peripheral circuit layer 50 and a fourth wiring layer 20d. The peripheral circuit layer 50 may include a third substrate 310, a third shallow element isolation pattern STI3, a third gate insulating film 340, and a peripheral circuit gate MxG. The fourth wiring layer 20d may include a third interlayer insulating film 350, a third contact plug 360, a third wiring 370, and a fourth bonding pad 440.

[0099] The third substrate 310 may have a fifth surface 311 and a sixth surface 313 opposite to the fifth surface 311. A third shallow element isolation pattern STI3 may be disposed in a shallow trench recessed to a specific depth from the fifth surface 311 of the third substrate 310, and the third shallow element isolation pattern STI3 may be adjacent to the fifth surface 311 of the third substrate 310. In some example embodiments, the third shallow element isolation pattern STI3 may define an active region in the third substrate 310.

[0100] The peripheral circuit gate MxG can be disposed on the corresponding active region of the third substrate 310. In some example embodiments, the peripheral circuit gate MxG can be disposed on the fifth surface 311 of the third substrate 310. The third gate insulating film 340 can be disposed between the peripheral circuit gate MxG and the corresponding active region. The peripheral circuit source / drain regions can be disposed in the corresponding active regions on both sides of each peripheral circuit gate MxG.

[0101] A third interlayer insulating film 350 may be disposed on the fifth surface 311 of the third substrate 310 to cover the fifth surface 311, the third gate insulating film 340, and the peripheral circuit gate MxG. The third interlayer insulating films 350 may be sequentially stacked on the fifth surface 311 of the third substrate 310. A third contact plug 360 and a third wiring 370 may be provided in the third interlayer insulating film 350. A fourth bonding pad 440 may be disposed in the uppermost layer of the third interlayer insulating film 350 (e.g., the uppermost third interlayer insulating film).

[0102] The first to fourth bonding pads 410, 420, 430, and 440 can electrically connect the first to third structures 100, 200, and 300. In some example embodiments, the first bonding pad 410 and the second bonding pad 420 can be bonded to each other to electrically connect the first structure 100 to the second structure 200. In some example embodiments, the third bonding pad 430 and the fourth bonding pad 440 can be bonded to each other to electrically connect the second structure 200 to the third structure 300.

[0103] In some exemplary embodiments, the second structure 200 can be modified by applying techniques such as upside down, upside down, left-right reversal, or 180° rotation. Figure 14 The bonding methods are different as shown. For example, the first bonding pad 410 and the third bonding pad 430 can be bonded to each other to electrically connect the first structure 100 to the third structure 200. For example, the second bonding pad 420 and the fourth bonding pad 440 can be bonded to each other to electrically connect the second structure 200 to the third structure 300.

[0104] In some example embodiments, the third bonding pad 430 and the fourth bonding pad 440 may include copper, for example, like the first bonding pad 410 and the second bonding pad 420. The pads bonded among the first to fourth bonding pads 410, 420, 430 and 440 may be bonded by, for example, copper-copper bonding technology, and the bonded pads may form a single body therebetween without boundary surfaces, but the example embodiments are not limited thereto.

[0105] In some example embodiments, the bonded films in the first to third interlayer insulating films 150, 250, and 350 can be bonded to each other, for example, by forming covalent bonds. For example, the lowest layer in the first interlayer insulating film 150 can be bonded to the highest layer in the second interlayer insulating film 250. For example, the lowest layer in the second interlayer insulating film 250 can be bonded to the highest layer in the third interlayer insulating film 350.

[0106] Figure 15 This is a plan view of an image sensor according to some example implementations. Figure 16 Is with Figure 15 The corresponding cross-sectional view of line I-I'.

[0107] Reference Figure 15 Each pixel region group PXRG can have a pair of pixel regions PXR. In some example embodiments, the pair of pixel regions PXR can be separated from each other by at least one of a doped isolation region and a second deep element isolation pattern DTI2. For example, the pair of pixel regions PXR can be separated from each other by a second deep element isolation pattern DTI2. In other words, the second deep element isolation pattern DTI2 can be formed between the pair of pixel regions PXR.

[0108] A first bonding pad 410 may be provided on a first surface 111 of the first substrate 110 and on each pixel region group PXRG. In some example embodiments, the first bonding pad 410 may be provided between the pair of pixel regions PXR, and a portion of the first bonding pad 410 may vertically overlap with a second deep element isolation pattern DTI2.

[0109] Reference Figure 15 and Figure 16 As previously described, a pixel region group PXRG may include a pair of pixel regions PXR. Furthermore, a first pickup region 130 and a transmission gate TG may be provided in one pixel region PXR, and a floating diffusion region FD may be provided in two adjacent pixel regions PXR. In such a case, the floating diffusion region FD may be provided in each pixel region PXR or in each of the pair of pixel regions PXR.

[0110] According to some example embodiments, each first contact plug 160 in the uppermost layer of the first interlayer insulating film 150 may be provided on each of a first pickup region 130, a transmission gate TG, and a floating diffusion region FD.

[0111] According to some example embodiments, each second contact plug 260 provided in the lowest layer of the second interlayer insulating film 250 (e.g., the lowest second interlayer insulating film in the second interlayer insulating film 250) may be provided on at least one second pickup region 230 and a source follower gate SFG. The second contact plug 260 provided on the second pickup region 230 is connected to a second shielding conductive pattern 520 in the uppermost layer of the second interlayer insulating film 250, such that the second contact plug 260 can be electrically connected to the second pickup region 230 and the second shielding conductive pattern 520 together with the second wiring 270. Furthermore, the second contact plug 260 provided on the source follower gate SFG is connected to a second bonding pad 420 in the uppermost layer of the second interlayer insulating film 250 (e.g., the uppermost second interlayer insulating film in the second interlayer insulating film 250), such that the second contact plug 260, together with the second wiring 270, can be electrically connected to the source follower gate SFG and the second bonding pad 420.

[0112] According to some example implementations, chip yield can be increased by forming a shielding conductive pattern with short line shapes.

[0113] Although the inventive concept has been described above with reference to exemplary embodiments, those skilled in the art will understand that the exemplary embodiments can be modified and altered in various ways without departing from the spirit and scope of the inventive concept as described in the appended claims. For example, it is self-evident that the above exemplary embodiments can be combined in various forms to a degree that they are compatible with each other.

[0114] Therefore, the spirit and scope of the inventive concept should not be limited to what is described in the detailed description of the specification.

[0115] Unless the context clearly indicates otherwise, singular expressions may include plural expressions. Terms such as “including” or “having” may be interpreted as adding features, numbers, steps, operations, components, parts, or combinations thereof described in the specification.

[0116] It will be understood that when an element or layer is referred to as being "on" another element or layer, "connected" to another element or layer, "attached" to another element or layer, or "in contact" with another element or layer, it can be directly on, directly connected to, directly attached to, directly attached to, or directly in contact with another element or layer, or there may be intermediate elements or layers present. Conversely, when an element is referred to as being "directly on" another element or layer, "directly connected" to, directly attached to, directly attached to, or directly in contact with another element or layer, there are no intermediate elements or layers present. As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items.

[0117] For ease of description, spatial relation terms (e.g., "below," "under," "below," "above," "above," etc.) are used herein to describe the relationship between one element or feature and another element or feature as shown in the figures. It should be understood that, in addition to the orientation depicted in the figures, spatial relation terms are intended to cover other different orientations of the device in use or operation. For example, if the device in the figures is flipped, an element described as "below" or "below" other elements or features would be oriented "above" other elements or features. Therefore, the term "below" can cover both above and below orientations. The device may be oriented in other ways (rotated 90 degrees or in its orientation), and the spatial relation descriptors used herein are interpreted accordingly.

[0118] One or more of the elements disclosed above may include or be implemented in processing circuitry, which is hardware such as including logic circuitry; hardware / software combinations such as a processor executing software; or combinations thereof. For example, the processing circuitry may more specifically include, but is not limited to, a central processing unit (CPU), an arithmetic logic unit (ALU), a digital signal processor, a microcomputer, a field-programmable gate array (FPGA), a system-on-a-chip (SoC), a programmable logic unit, a microprocessor, an application-specific integrated circuit (ASIC), etc.

[0119] Reference Figure 1 Any or all of the elements described may be related to the reference. Figure 1 It can communicate with any or all other components described. For example, any component can communicate with... Figure 1 Any or all other elements may communicate in one-way and / or two-way and / or broadcast manner to transmit and / or exchange and / or receive information such as, but not limited to, data and / or commands via a bus such as a wireless and / or wired bus (not shown) in a serial and / or parallel manner. The information may be in various encoded formats, such as analog and / or digital formats.

[0120] Cross-reference to related applications

[0121] This application claims priority to Korean Patent Application No. 10-2024-0111987, filed on August 21, 2024, with the Korean Intellectual Property Office, the disclosure of which is incorporated herein by reference in its entirety.

Claims

1. An image sensor, comprising: a first substrate having a first surface and a second surface opposite the first surface, the first substrate including a plurality of groups of pixel regions, each of the groups of pixel regions including a plurality of pixel regions, the pixel regions oriented in a first direction and a second direction that intersects the first direction, the first and second directions being parallel to the first surface; a first bond pad on the first surface of the first substrate and individually on each of the groups of pixel regions; a first shield conductive pattern on the first surface of the first substrate, the first shield conductive pattern individually on each boundary of the groups of pixel regions that is parallel to the first direction, the first shield conductive pattern being in a matrix form along the first and second directions, the first shield conductive pattern of each column of the matrix being physically spaced apart from one another; and a first pick-up region in at least one of the pixel regions of each of the groups of pixel regions, wherein each of the first shield conductive patterns is electrically connected to the first pick-up region in the respective pixel region of the group of pixel regions. Each of the first shield conductive patterns has a strip shape that extends in the first direction.

2. The image sensor of claim 1, wherein, 3. The image sensor of claim 1, further comprising: a floating diffusion region in each of the pixel regions, wherein each of the first bond pads is electrically connected to the floating diffusion region in the respective pixel region of the group of pixel regions. The first shield conductive pattern is not on a boundary of the group of pixel regions that is parallel to the second direction.

4. The image sensor of claim 1, wherein, A length of each of the first shield conductive patterns in the first direction is greater than or equal to a width of each of the first bond pads in the first direction.

5. The image sensor of claim 1, wherein, 6. The image sensor of claim 1, further comprising: a second substrate having a third surface facing the first surface; a source follower gate on the third surface of the second substrate; a second bond pad on the third surface of the second substrate; a second shield conductive pattern on the third surface of the second substrate, the second shield conductive pattern individually on each of the boundaries of the groups of pixel regions that is parallel to the first direction, the second shield conductive pattern being in a matrix form along the first and second directions, the second shield conductive pattern of each column of the matrix being physically spaced apart from one another; and a second pick-up region in the second substrate, wherein each of the second shield conductive patterns is electrically connected to the respective pick-up region of the second pick-up region. The second shield conductive pattern is individually bonded to each of the first shield conductive patterns. Each of the second shield conductive patterns has a strip shape that extends in the first direction.

7. The image sensor of claim 6, wherein, Each of the second bond pads is electrically connected to the respective source follower gate of the source follower gates.

8. The image sensor of claim 6, wherein, The second shield conductive pattern is not on a boundary of the group of pixel regions that is parallel to the second direction.

9. The image sensor of claim 6, wherein, A length of each of the second shield conductive patterns in the first direction is greater than or equal to a width of each of the second bond pads in the first direction.

10. The image sensor of claim 6, wherein, ​ 11. The image sensor of claim 6, wherein, ​ 12. The image sensor of claim 6, further comprising: an interlayer insulating film at least partially covering the third surface of the second substrate and the source follower gate, wherein the second bonding pad and the second shield conductive pattern are in an uppermost interlayer insulating film among the interlayer insulating films.

13. An image sensor, comprising: a first substrate having a first surface and a second surface opposite to the first surface, the first substrate including a plurality of pixel region groups, each of the pixel region groups including a plurality of pixel regions, the pixel regions oriented in a first direction and a second direction intersecting the first direction, the first direction and the second direction being parallel to the first surface; a first bonding pad on the first surface of the first substrate and individually on each of the pixel region groups; a first shield conductive pattern on the first surface of the first substrate, the first shield conductive pattern individually on each boundary of the pixel region groups parallel to the first direction, the first shield conductive pattern being in a form of a matrix along the first direction and the second direction, the first shield conductive pattern of each column of the matrix being physically spaced apart from each other; a first pickup region in at least one of the pixel regions of each of the pixel region groups, a second substrate having a third surface facing the first surface and a fourth surface opposite to the third surface; a second bonding pad on the third surface of the second substrate; a second shield conductive pattern on the third surface of the second substrate, the second shield conductive pattern individually bonded to each of the first shield conductive pattern; and a second pickup region in the second substrate, wherein each of the first shield conductive pattern is electrically connected to a first pickup region in the first pickup region in a corresponding pixel region of the pixel region groups, and each of the second shield conductive pattern is electrically connected to a corresponding pickup region in the second pickup region.

14. The image sensor of claim 13, wherein, Each of the first shield conductive pattern and each of the second shield conductive pattern has a bar shape extending in the first direction.

15. The image sensor of claim 13, wherein the first shield conductive pattern and the second shield conductive pattern are not on a boundary of the pixel region groups parallel to the second direction.

16. The image sensor of claim 13, wherein a length of each of the first shield conductive pattern in the first direction is greater than or equal to a width of each of the first bonding pad in the first direction, and a length of each of the second shield conductive pattern in the first direction is greater than or equal to a width of each of the second bonding pad in the first direction.

17. The image sensor of claim 13, further comprising: a floating diffusion region in each of the pixel regions; and a source follower gate on the third surface of the second substrate, wherein each of the first bonding pad is electrically connected to a floating diffusion region in the floating diffusion region in a corresponding pixel region of the pixel region groups, and Each of the second bonding pads is electrically connected to a respective one of the source follower gates.

18. The image sensor of claim 17, wherein, The first bonding pad and the second bonding pad are separately bonded to each other.

19. The image sensor of claim 13, further comprising: an interlayer insulating film at least partially covering the third surface of the second substrate and the source follower gates, wherein the second bonding pads and the second shield conductive pattern are in an uppermost one of the interlayer insulating films.

20. The image sensor of claim 13, further comprising: third bonding pads on the fourth surface of the second substrate; a third substrate having a fifth surface facing the fourth surface; and fourth bonding pads on the fifth surface of the third substrate, wherein the fourth bonding pads are separately bonded to each of the third bonding pads.

Images