Gallium arsenide wafer lateral erosion improvement method and wafer structure

Abstract

The invention provides a gallium arsenide wafer lateral erosion improvement method and a wafer structure. The method comprises the following steps: providing a gallium arsenide wafer; forming a protective layer on the front surface of the gallium arsenide wafer; attaching the back surface of the gallium arsenide wafer to a bearing film; cutting the front surface of the gallium arsenide wafer by using laser to divide the gallium arsenide wafer into a plurality of crystal grains, and forming a recast layer on the side surface of a cutting channel of the crystal grains; removing the protective layer on the crystal grains to enable the protective layer to take away cutting residues formed on the surfaces of the crystal grains during cutting; carrying out heat treatment on the crystal grains attached with the bearing film, so that an adhesive layer of the bearing film generates rheology and partially wraps the back surfaces and the edges of the crystal grains; and etching the side surfaces of the crystal grains by using an etching solution to remove the recast layer, and the back metal layer covered by the adhesive layer is protected in the etching process, so that the lateral erosion phenomenon is fundamentally avoided.

Description

Technical Field

[0001] This invention belongs to the field of semiconductor technology, and specifically relates to a method for improving the side etching of gallium arsenide wafers and a wafer structure. Background Technology

[0002] Cutting semiconductor wafers into individual chips or dies is an indispensable step in the fabrication of semiconductor components or integrated circuits. For fragile III-V compound semiconductor wafers such as gallium arsenide (GaAs), traditional mechanical cutting methods can easily lead to wafer breakage and microcracks. Therefore, laser cutting technology has gradually become the mainstream cutting method.

[0003] Laser cutting technology uses a high-power laser beam focused on the wafer surface, causing the material in the irradiated area to locally and instantaneously heat up, melt, or even vaporize, thereby achieving separation. However, this cutting method presents a significant technical challenge in the application of gallium arsenide (GaAs) wafers: the recasting of GaAs residue. Under the high temperature of the laser, GaAs decomposes to produce arsenic vapor and tiny GaAs particles. These particles can re-condense and adhere to the cut edges and wafer surface during the cutting process, forming a so-called "recast layer." If this recast layer is not removed, it will severely affect the electrical characteristics and reliability of the components.

[0004] To address the aforementioned issues, existing technologies typically employ a combination of protective layer and etching processes. Specifically, before laser cutting, a protective layer is coated on the front side of the wafer. This protective layer must withstand the high temperatures generated by the laser and possess good adhesion and coverage to the wafer surface. After cutting, the protective layer and any cutting residue adsorbed on it are removed using an etching solution, and the recast layer remaining on the die sides is further removed. Currently, water-soluble polyvinyl alcohol (PVA) is widely used in the industry as the protective layer material.

[0005] However, this existing technology has an inherent drawback. During the removal of the recast layer on the grain side using a mixed acid etching solution (e.g., a mixture of ammonia / hydrogen peroxide / water), the PVA protective layer, being water-soluble, is washed away after cutting, leaving the back metal layer of the grain (typically a TIW barrier layer or a TIW / Au composite layer) directly exposed to the etching solution. While the etching solution laterally corrodes the recast layer on the side, it also laterally erodes the exposed back metal layer, leading to severe side etching or undercutting. Summary of the Invention

[0006] To address the aforementioned technical problems, this invention provides a method for improving gallium arsenide wafer side etching and a wafer structure, which solves the technical problems mentioned in the background art.

[0007] On one hand, the invention provides the following technical solution: a method for improving the side etching of gallium arsenide wafers, the method comprising: Provide a gallium arsenide wafer; A protective layer is formed on the front side of the gallium arsenide wafer; The back side of the gallium arsenide wafer is attached to a carrier film; The gallium arsenide wafer is cut from the front side using a laser to divide it into multiple grains, and a recast layer is formed on the side of the cut path of the grains. Remove the protective layer on the grain so that the protective layer carries away the cutting residue formed on its surface during cutting; The grains to which the carrier film is attached are subjected to heat treatment, causing the adhesive layer of the carrier film to undergo rheological changes and partially wrap around the back side and edges of the grains, thereby covering and protecting the metal layer on the back side; The sides of the grain are etched using an etching solution to remove the recast layer, wherein the back metal layer covered by the adhesive layer is protected during the etching process.

[0008] Compared with existing technologies, the advantages of this invention are: by employing a technique of baking UV tape to cause the adhesive layer to undergo rheological changes and wrap around the back side of the grain, an effective physical barrier is established for the back metal layer (TIW / AU). This barrier can prevent the etching solution from contacting the metal layer, thereby fundamentally avoiding the occurrence of lateral etching.

[0009] Furthermore, the protective layer is a polyvinyl alcohol layer.

[0010] Furthermore, the protective layer and cutting residue are removed by washing with water.

[0011] Furthermore, the carrier film is a UV adhesive tape.

[0012] Furthermore, the thickness of the protective layer is 10μm-15μm.

[0013] Furthermore, the baking temperature for the heat treatment is 60℃-100℃, and the baking time is 5-15 minutes.

[0014] Furthermore, the heat treatment causes the grains to become embedded in the rheological adhesive layer to a depth of 3 μm to 5 μm.

[0015] Furthermore, the etching solution is a mixed solution containing ammonia, hydrogen peroxide and water in a volume ratio of 1:1:(8-12).

[0016] Furthermore, after etching the sides of the grain, the method further includes irradiating the carrier film with ultraviolet light to reduce its stickiness and removing the grain from the carrier film.

[0017] The present invention also provides a wafer structure, which is prepared according to the above-described gallium arsenide wafer side etching improvement method. Attached Figure Description

[0018] Figure 1 This is a flowchart of the preparation method of the gallium arsenide wafer side etching improvement method in the first embodiment of the present invention.

[0019] Figure 2 This is a schematic diagram of the structure of a gallium arsenide wafer according to the first embodiment of the present invention.

[0020] Figure 3 This is a schematic diagram of the structure formed in step S03 of the first embodiment of the present invention.

[0021] Figure 4 This is a schematic diagram of the structure formed in step S04 of the first embodiment of the present invention.

[0022] Figure 5 This is a schematic diagram of the structure formed in step S05 of the first embodiment of the present invention.

[0023] Figure 6 This is a schematic diagram of the structure formed in step S06 of the first embodiment of the present invention.

[0024] Figure 7 This is a schematic diagram of the structure formed in step S07 of the first embodiment of the present invention.

[0025] Figure 8 This is a test image of a gallium arsenide wafer in the eighth embodiment of the present invention.

[0026] Key component symbols: 10. Gallium arsenide wafer; 11. Protective layer; 12. Carrier film; 13. Die; 14. Recast layer; 15. Cutting residue; 16. Adhesive layer; 17. TIW barrier layer; 18. Au conductive layer.

[0027] The following detailed description, in conjunction with the accompanying drawings, will further illustrate the present invention. Detailed Implementation

[0028] To facilitate understanding of the present invention, a more complete description will be given below with reference to the accompanying drawings. Several embodiments of the invention are illustrated in the drawings. However, the invention can be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete.

[0029] It should be noted that when a component is said to be "fixed to" another component, it can be directly on the other component or there may be an intervening component. When a component is said to be "connected to" another component, it can be directly connected to the other component or there may be an intervening component. The terms "vertical," "horizontal," "left," "right," and similar expressions used in this document are for illustrative purposes only.

[0030] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention pertains. The terminology used herein in the description of the invention is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. The term "and / or" as used herein includes any and all combinations of one or more of the associated listed items.

[0031] Example 1 Please see Figure 1 The figure shows a gallium arsenide wafer side etching improvement method in the first embodiment of the present invention, the method including the following steps: step S01-step S07; S01, providing a gallium arsenide wafer 10; In this embodiment, a standardized 4-inch gallium arsenide wafer 10 is provided, on the back of which a TIW barrier layer 17 (approximately 100 nm thick) and an Au conductive layer 18 (approximately 500 nm thick) have been sequentially formed by sputtering process.

[0032] S02, a protective layer 11 is formed on the front side of the gallium arsenide wafer 10; Specifically, the protective layer 11 is a polyvinyl alcohol layer. Optionally, the thickness of the protective layer 11 is 10μm-15μm.

[0033] In this embodiment, a water-soluble polyvinyl alcohol (PVA) protective layer 11 is coated on the front side of the gallium arsenide wafer 10 using a spin-coating process. The coating parameters are set to 3000 rpm for 30 seconds, resulting in a PVA protective layer 11 with a thickness of approximately 15 μm. This PVA protective layer 11 is used to protect the front side of the wafer from contamination during subsequent laser cutting.

[0034] S03, attach the back side of the gallium arsenide wafer 10 to a carrier film 12; Specifically, the carrier film is a UV adhesive tape.

[0035] In this embodiment, the back side of the gallium arsenide wafer 10 is attached to a UV tape (e.g., the ULTRON® series from Nitto Denko Corporation). The initial thickness of the adhesive layer 16 of the UV tape is 12 μm.

[0036] S04, a laser is used to cut the gallium arsenide wafer 10 from the front side, dividing it into multiple grains 13, and a recast layer 14 is formed on the side of the cut path of the grains 13. In this embodiment, an ultraviolet laser dicing machine is used to dice the gallium arsenide wafer 10 from the front side, dividing the entire wafer into multiple independent grains 13 with a size of 1mm × 1mm. During the dicing process, the high temperature of the laser vaporizes and recasts the gallium arsenide material, forming a recast layer 14 on the side of the dicing path of the grain 13.

[0037] S05, Remove the protective layer 11 on the grain 13 so that the protective layer 11 carries away the cutting residue 15 formed on its surface during cutting; Specifically, the protective layer 11 and cutting residue 15 are removed by washing with water.

[0038] In this embodiment, the diced wafer is placed in an ultrapure water washing device, and the PVA protective layer 11 on the front side and the surface dicing residue 15 adsorbed thereon are thoroughly removed by spraying and immersion. After washing, the front side of the wafer 13 is clean, but the side recast layer 14 is still present.

[0039] S06, the grain 13 to which the carrier film is attached is subjected to heat treatment, so that the adhesive layer 16 of the carrier film undergoes rheological changes and partially wraps the back side and edge of the grain 13, thereby covering and protecting the metal layer on the back side. Optionally, the baking temperature of the heat treatment is 60℃-100℃, and the baking time is 5-15 minutes. The heat treatment causes the grains 13 to be embedded in the rheological adhesive layer 16 to a depth of 3μm to 5μm.

[0040] In this embodiment, the UV tape with the attached grains 13 is placed in an oven and baked at 80°C for 10 minutes. This heat treatment process causes the adhesive layer 16 of the UV tape to undergo rheological changes, transforming from a solid state to a semi-molten viscous flow state. Under the combined action of surface tension and gravity, the grains 13 sink and embed themselves in the semi-molten adhesive layer 16 to a depth of approximately 5 μm. As a result, the adhesive layer 16 tightly wraps around and covers the TIW / Au metal layer on the back side of the grains 13 and its edge edges, forming a physical barrier.

[0041] S07, the side surface of the grain 13 is etched using an etching solution to remove the recast layer 14, wherein the back metal layer covered by the adhesive layer 16 is protected during the etching process.

[0042] Alternatively, the etching solution may be a mixed solution containing ammonia, hydrogen peroxide and water in a volume ratio of 1:1:(8-12).

[0043] In this embodiment, the entire baked structure is immersed in an etching solution for approximately 90 seconds. The etching solution is a mixture of ammonia, hydrogen peroxide, and ultrapure water in a volume ratio of 1:1:10. This etching solution can effectively corrode and remove the gallium arsenide recast layer 14 on the side of the grain 13. However, since the metal layer on the back of the grain 13 is completely covered by the rheological adhesive layer 16, the etching solution cannot contact the metal layer, thus completely avoiding the side etching phenomenon of the TIW layer.

[0044] Alternatively, after etching the sides of the grain 13, the method may further include irradiating the carrier film with ultraviolet light to reduce its stickiness and removing the grain 13 from the carrier film 12.

[0045] In this embodiment, after etching, the die 13 is rinsed with deionized water and dried. Then, the entire UV tape is placed under ultraviolet light irradiation at an energy of 300 mJ / cm², causing the adhesive layer 16 to cross-link and lose its adhesiveness. Finally, the die 13 without side-etching defects is removed from the UV tape and proceeds to the subsequent encapsulation process.

[0046] Example 2 The difference between this embodiment and Embodiment 1 is that the parameters of the baking step in the heat treatment are adjusted to: temperature 70°C and time 12 minutes. At this time, the depth of the grains embedded in the adhesive layer is approximately 4 μm. After etching, the back metal layer is also effectively protected, and no side etching occurs.

[0047] Example 3 The difference between this embodiment and Embodiment 1 is that the parameters of the baking step in the heat treatment are adjusted to: temperature 90°C and time 8 minutes. At this time, the depth of the grains embedded in the adhesive layer is approximately 5 μm. After etching, the back metal layer is also effectively protected, and no side etching occurs.

[0048] Example 4: This embodiment aims to illustrate that variations in the thickness of the front protective layer within a certain range do not affect the effectiveness of the present invention.

[0049] This embodiment is basically the same as Embodiment 1, except that in the step of coating the front protective layer, the spin coating speed is adjusted to 1500 rpm, so that the thickness of the formed PVA protective layer is increased to about 25 μm.

[0050] Subsequent process parameters, including laser cutting, UV tape thickness (12 μm), baking conditions (80°C, 10 minutes), and etching conditions, remained unchanged. After etching, SEM observation showed that the recast layer on the grain side was completely removed, while the TIW / Au metal layer on the back side, effectively protected by the adhesive layer, showed no side etching. This indicates that the thickness of the PVA protective layer is applicable over a wide range (e.g., 10 μm to 30 μm) under the method of this invention, and the core improvement effect depends on the UV tape baking process on the back side.

[0051] Example 5: This embodiment aims to illustrate that the present invention has a protective effect on different back metal structures.

[0052] This embodiment is basically the same as Embodiment 1, except that in the wafer preparation step, the gallium arsenide wafer provided has only a single TIW layer on the back side with a thickness of 200nm, and no Au conductive layer is deposited.

[0053] Subsequent process parameters remained unchanged. Post-etching observation revealed that, despite the different metal layer structures, the rheological UV adhesive tape effectively covered and protected the edges of the single TIW metal layer, completely suppressing lateral etching. This demonstrates that the protective effect of this invention does not depend on the presence of a specific Au conductive layer and has general improvement significance for common back-plated metals (such as TIW, Ti, Pt, etc.).

[0054] Example 6: This embodiment aims to verify the lower limit requirement for UV tape thickness.

[0055] This embodiment is basically the same as Embodiment 1, except that: in the step of attaching the carrier film, a UV tape with an adhesive layer thickness of 8μm is selected (slightly lower than the preferred range).

[0056] Under the same baking conditions (80°C, 10 minutes), due to the thinner adhesive layer, the grain embedment depth was shallower, approximately 2 μm. After etching, most of the metal layer on the back of the grains was protected, but slight and unstable lateral etching (approximately 0.5-1 μm) was observed in localized areas (especially stress concentration points such as cut intersections). This comparative example illustrates that maintaining the UV tape thickness at least 10 μm is necessary to ensure the stability and consistency of the protective effect.

[0057] Example 7: This embodiment aims to verify the impact of the upper limit of UV tape thickness.

[0058] This embodiment is basically the same as Embodiment 1, except that: in the step of attaching the carrier film, a UV tape with an adhesive layer thickness of 18μm is selected (slightly higher than the preferred range).

[0059] Under the same baking conditions, excessively thick adhesive layers resulted in over-encapsulation after rheological transformation, with some adhesive climbing to the grain sides. This affected the contact between the side recast layer and the etching solution, leading to recast layer residue. Although the back metal protection was intact, the side cleaning was incomplete. This result indicates that excessively thick adhesive tape may interfere with the main process objectives; therefore, controlling the thickness to within 15 μm is preferred.

[0060] To quantitatively evaluate the improvement effect of the present invention, the grains prepared in the above embodiments and comparative examples were tested and analyzed. The specific methods are as follows: Lateral etching measurement: Cross-section observation of the etched grains was performed using a scanning electron microscope (SEM). Thirty grains were randomly selected from each experimental group, and the maximum depth of lateral etching of the TIW metal layer on the back side was measured. The average value was calculated as the lateral etching amount for that group.

[0061] Yield statistics: The pass rate of each group is calculated based on the lateral etching amount of less than 0.5μm as the acceptance standard.

[0062] The test results are summarized in Table 1 below: Based on the test data in Table 1, the following clear conclusions can be drawn: The invention demonstrates significant advantages: all embodiments (one to seven) including the "UV tape baking" step exhibited significantly better average lateral etching and product yield compared to the comparative examples that did not undergo baking. This fully proves the necessity and superior effectiveness of the core steps of the invention.

[0063] The optimal implementation method was determined as follows: As shown in the table, Example 1 (UV tape thickness 12μm, baking conditions 80℃ / 10 minutes) achieved the best overall results, with an average lateral etching amount of almost zero (0.1μm) and a product yield exceeding 99%. This indicates that this set of parameters is the preferred solution of the present invention, ensuring perfect protection of the back metal while also ensuring the complete removal of the side recast layer.

[0064] Defining the process window: Baking process: Examples 1, 2 and 3 show that the present invention can achieve excellent results (lateral etching amount <0.5μm, yield >98%) within a temperature range of 60℃-100℃ and a time range of 5-15 minutes, but 80℃ / 10 minutes is the optimal point to achieve the best results.

[0065] UV tape thickness: Examples 1, 6, and 7 collectively define the preferred thickness range for UV tape as 10 μm to 15 μm. Too thin (Example 6) will result in insufficient protection, increased lateral etching, and decreased yield; too thick (Example 7), while protecting the back side, will introduce new problems such as incomplete side cleaning.

[0066] Demonstrating the universality of the solution: Examples 4 and 5 demonstrate that the present invention is insensitive to changes in the thickness of the front PVA protective layer and the structure of the back metal layer, showcasing the robustness and broad applicability of the technical solution.

[0067] In summary, this invention, by introducing a simple UV tape baking step, can reduce the side etching depth of gallium arsenide wafer back-plated metal from over 4.2 μm to below 0.5 μm, and increase the yield from less than 5% to over 98%. The parameter combination represented by Example 1 is the optimal implementation scheme, providing the industry with an efficient, low-cost, and reliable side etching improvement solution.

[0068] Example 8: This embodiment aims to clarify the precise specifications of the UV tape used, and based on these specifications, to quantitatively demonstrate the influence of baking time on the rheological height and uniformity of the adhesive layer through experimental data, thereby refining the core process window and proving the stability and reliability of the optimized parameters.

[0069] 1. UV tape specifications; In this embodiment and the preferred embodiment of the present invention, the carrier film used is a UV tape conforming to the following specifications: Structure: A three-layer composite structure consisting of a polyvinyl chloride film, an acrylic UV-curable adhesive layer, and a polyester release film.

[0070] Base film: polyvinyl chloride, with a thickness of 80μm.

[0071] Adhesive layer: acrylic (UV cured), initial thickness 10μm.

[0072] Total thickness: 90μm (excluding release film).

[0073] Appearance: Opaque.

[0074] 2. Baking process and verification of rheological uniformity; Under the conditions of using the above-mentioned UV tape and fixing the baking temperature at 80℃, such as Figure 8 The rheological height (adhesive thickness in μm) of the adhesive layer at different locations was tested under different baking times, and the data are shown in Table 2 below:

[0075] As shown in Table 2 above, for an acrylic adhesive layer with an initial thickness of 10 μm, a baking time of 10 minutes at 80°C is required to ensure that its rheological height consistently reaches 5-6 μm at all measurement points. This height precisely ensures that the grains are embedded to a depth of approximately 5 μm, which is the ideal range for achieving effective encapsulation.

[0076] Under 10-minute conditions, the difference in the rheological height of the adhesive layer at different locations was minimal (maximum difference 1 μm). This demonstrates that the process can provide consistent and reliable protection for grains at all locations on the entire wafer, completely avoiding the risk of localized lateral etching caused by uneven protection (as revealed in Example 6).

[0077] This embodiment clarifies that the preferred embodiment of the present invention is a precise combination of "an acrylic adhesive layer with an initial thickness of 10 μm" and "an 80°C / 10-minute baking process". This combination is the core technical condition for achieving high yield and zero side-etching production.

[0078] This embodiment fully demonstrates how to controllable and uniform rheology of UV tape adhesive layers of a specific specification by clearly defining material specifications and quantitative process data, thereby providing a precise process window and experimental basis for achieving stable and reliable lateral corrosion protection.

[0079] The present invention also proposes a wafer structure, which is prepared according to the above-described gallium arsenide wafer side etching improvement method.

[0080] In summary, the gallium arsenide wafer side etching improvement method and wafer structure in the above embodiments of the present invention have the following beneficial effects: By employing a technique of baking UV tape to cause its adhesive layer to undergo rheological changes and encapsulate the back side of the die, an effective physical barrier is established for the back metal layer (TIW / AU). This barrier prevents the etchant from contacting the metal layer, thereby fundamentally avoiding lateral etching. As shown in the example data, the lateral etching depth is reduced from 4.2 μm in the comparative example to below 0.1 μm in this invention, and the product yield is increased from less than 5% to over 99%, greatly ensuring the electrical performance and long-term reliability of the device.

[0081] This invention requires no changes to existing mainstream process materials (such as PVA protective solution, TIW / Au metal layer, and ammonia / hydrogen peroxide etching solution), nor does it require the introduction of expensive additional equipment. Its core improvement lies solely in the addition of two steps: UV tape application and baking. Both steps can be performed using mature equipment already available in semiconductor manufacturing. Therefore, this invention can be seamlessly integrated into existing production lines with extremely low cost and minimal modifications, making it easily adopted and promoted by the industry.

[0082] By utilizing the rheological properties of UV tape in a semi-molten state, a protective layer is formed only on the back and edges of the grains requiring protection, without affecting the normal processing on the front and sides. This "locality" and "precision" of protection ensures that the side recast layer can be completely and cleanly removed, while the back metal is well protected, solving the problem of complex processes in traditional global protection solutions.

[0083] Through extensive experimental verification, this invention has clarified the key process parameter ranges for achieving optimal results, such as a UV tape thickness of 10-15 μm and a baking temperature of 60-100℃. These specific parameter ranges provide clear guidance for industrial production. Furthermore, as shown in Examples Six and Seven, the boundaries of the parameter ranges were verified, ensuring process stability and consistency of results in large-scale production and avoiding new problems arising from insufficient or excessive protection.

[0084] In the description of this specification, references to terms such as "one embodiment," "some embodiments," "example," "specific example," or "some examples," etc., indicate that a specific feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of the invention. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples.

[0085] The embodiments described above are merely illustrative of several implementations of the present invention, and while the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the present invention. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of the present invention, and these all fall within the protection scope of the present invention. Therefore, the protection scope of this patent should be determined by the appended claims.

Claims

1. A method for improving the side etching of a gallium arsenide wafer, comprising: The method comprises: providing a gallium arsenide wafer; forming a protective layer on the front side of the gallium arsenide wafer; attaching the back side of the gallium arsenide wafer to a carrier film; cutting the gallium arsenide wafer from the front side using a laser to divide it into multiple dies and form a recast layer on the side of the cutting path of the dies; removing the protective layer on the dies to take away the cutting residues formed on the surface of the dies during cutting; heat treating the dies attached to the carrier film to make the adhesive layer of the carrier film rheological and partially wrap the back side and edges of the dies, thereby covering and protecting the metal layer on the back side; etching the side of the dies using an etching solution to remove the recast layer, wherein the metal layer on the back side covered by the adhesive layer is protected during etching.

2. The method of claim 1, wherein the GaAs wafer is a (100) GaAs wafer. The protective layer is a polyvinyl alcohol layer.

3. The method of claim 1, wherein the GaAs wafer is a (100) GaAs wafer. The protective layer and the cutting residues are removed by water washing.

4. The method of claim 1, wherein the GaAs wafer is a (100) GaAs wafer. The carrier film is a UV adhesive tape.

5. The method of claim 1, wherein the GaAs wafer is a (100) GaAs wafer. The thickness of the protective layer is 10-15 μm.

6. The method of claim 1, wherein the GaAs wafer is a GaAs wafer having a thickness of 1000 μm or less. The baking temperature of the heat treatment is 60-100 °C, and the baking time is 5-15 minutes.

7. The method of claim 1, wherein the GaAs wafer is a GaAs substrate wafer. The depth of the heat treatment to make the dies sink into the rheological adhesive layer is 3-5 μm.

8. The method of claim 1, wherein the GaAs wafer is a GaAs wafer having a thickness of 1000 μm or less. The etching solution is a mixed solution containing ammonia, hydrogen peroxide and water, with a volume ratio of 1:1:(8-12).

9. The method of claim 1, wherein the GaAs wafer is a GaAs wafer having a thickness of 1000 μm or more. After the step of etching the side of the dies, the method further comprises the steps of irradiating the carrier film with ultraviolet light to reduce its adhesion, and removing the dies from the carrier film.

10. A wafer structure, characterized by The wafer structure is prepared by the gallium arsenide wafer side etching improvement method of any one of claims 1-9.

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