Pixel driving circuit and driving method thereof, display substrate and display device

Abstract

The invention discloses a pixel driving circuit and a driving method thereof, a display substrate and a display device, and the pixel driving circuit comprises a node control sub-circuit which is configured to control signals of a first scanning signal line (Gate1), a second scanning signal line (Gate2), a third scanning signal line (Gate3) and a fourth scanning signal line (Gate4), and a node control sub-circuit which is configured to control the signals of the first scanning signal line (Gate1), the second scanning signal line (Gate2), the third scanning signal line (Gate3) and the fourth scanning signal line (Gate4). A signal of a first node (N1) is driven by signals of a first initial signal line (INIT1), a data signal line (Data) and a first power line (VDD), a signal of a second initial signal line (INIT2) is provided to a second node (N2), and a signal of a third initial signal line (INIT3) is provided to a third node (N3); the light emission control sub-circuit is configured to provide a signal of a first power supply line (VDD) to the third node (N3) under the control of a signal of a light emission signal line (EM); the driving sub-circuit is configured to output a driving current to the second node (N2) under the control of signals of the first node (N1) and the third node (N3).

Description

Pixel driving circuit and driving method thereof, display substrate and display device Technical Field

[0001] The present disclosure relates to, but is not limited to, the field of display technology, and in particular to a pixel driving circuit and a driving method thereof, a display substrate, and a display device. Background Art

[0002] Organic Light Emitting Diodes (OLEDs) and Quantum-dot Light Emitting Diodes (QLEDs) are active light-emitting display devices with advantages such as self-luminescence, wide viewing angles, high contrast, low power consumption, extremely fast response times, thinness, flexibility, and low cost. With the continuous advancement of display technology, flexible displays using OLEDs or QLEDs as light-emitting devices and thin-film transistors (TFTs) for signal control have become mainstream products in the display field.

[0003] Summary of the Invention

[0004] The following is an overview of the subject matter described in detail in this disclosure. This overview is not intended to limit the scope of the claims.

[0005] In a first aspect, the present disclosure provides a pixel driving circuit configured to drive a light-emitting device, the pixel driving circuit comprising: a node control subcircuit, a light-emitting control subcircuit, and a driving subcircuit;

[0006] The node control subcircuit is electrically connected to the first node, the second node, the third node, the first scan signal line, the second scan signal line, the third scan signal line, the fourth scan signal line, the first initial signal line, the second initial signal line, the third initial signal line, the data signal line, and the first power line, respectively, and is configured to, under the control of the signals of the first scan signal line, the second scan signal line, the third scan signal line, and the fourth scan signal line, drive the signal of the first node through the first initial signal line, the data signal line, and the signal of the third node, provide the signal of the second initial signal line to the second node, and provide the signal of the third initial signal line to the third node;

[0007] The light control subcircuit is electrically connected to the first power line, the light signal line and the third node respectively, and is configured to provide the signal of the first power line to the third node under the control of the signal of the light signal line;

[0008] The driving sub-circuit is electrically connected to the first node, the second node and the third node respectively, and is configured to output a driving current to the second node under the control of the signals of the first node and the third node;

[0009] The light emitting device is electrically connected to the second node and the second power line respectively;

[0010] The node control subcircuit includes: an energy storage subcircuit, the energy storage subcircuit includes: a first capacitor and a second capacitor, the first capacitor and the second capacitor include: a first plate and a second plate;

[0011] The first plate of the first capacitor is electrically connected to the first power line, and the second plate of the first capacitor is electrically connected to the fourth node;

[0012] The first plate of the second capacitor is electrically connected to the first node, and the second plate of the second capacitor is electrically connected to the fourth node.

[0013] In an exemplary embodiment, the node control subcircuit further includes: a reset subcircuit, a compensation subcircuit, and a write subcircuit;

[0014] The reset subcircuit is electrically connected to the first node, the second node, the third node, the first scan signal line, the second scan signal line, the third scan signal line, the first initial signal line, the second initial signal line, and the third initial signal line, respectively, and is configured to provide the signal of the first initial signal line to the first node under the control of the signal of the first scan signal line, provide the signal of the second initial signal line to the second node under the control of the signal of the second scan signal line, and provide the signal of the third initial signal line to the third node under the control of the signal of the third scan signal line;

[0015] The compensation sub-circuit is electrically connected to the third node, the fourth node and the first scan signal line respectively, and is configured to provide the signal of the third node to the fourth node under the control of the signal of the first scan signal line to compensate for the signal of the fourth node;

[0016] The writing sub-circuit is electrically connected to the fourth node, the fourth scanning signal line and the data signal line respectively, and is configured to provide the signal of the data signal line to the fourth node under the control of the signal of the fourth scanning signal line.

[0017] In an exemplary embodiment, the reset subcircuit includes: a first transistor, a second transistor, and a third transistor;

[0018] The gate electrode of the first transistor is electrically connected to the first scan signal line, the first electrode of the first transistor is electrically connected to the first initial signal line, and the second electrode of the first transistor is electrically connected to the first node;

[0019] The gate electrode of the second transistor is electrically connected to the second scan signal line, the first electrode of the second transistor is electrically connected to the second initial signal line, and the second electrode of the second transistor is electrically connected to the second node;

[0020] A gate electrode of the third transistor is electrically connected to the third scan signal line, a first electrode of the third transistor is electrically connected to the third initial signal line, and a second electrode of the second transistor is electrically connected to the third node.

[0021] In an exemplary embodiment, the compensation sub-circuit includes: a fourth transistor, and the write transistor includes: a fifth transistor;

[0022] A gate electrode of the fourth transistor is electrically connected to the first scan signal line, a first electrode of the fourth transistor is electrically connected to the fourth node, and a second electrode of the fourth transistor is electrically connected to the third node;

[0023] A gate electrode of the fifth transistor is electrically connected to the fourth scan signal line, a first electrode of the fifth transistor is electrically connected to the data signal line, and a second electrode of the fifth transistor is electrically connected to the fourth node.

[0024] In an exemplary embodiment, the node control subcircuit further includes: first to fifth transistors, the driving subcircuit includes: a sixth transistor, and the light emission control subcircuit includes: a seventh transistor;

[0025] The gate electrode of the first transistor is electrically connected to the first scan signal line, the first electrode of the first transistor is electrically connected to the first initial signal line, and the second electrode of the first transistor is electrically connected to the first node;

[0026] The gate electrode of the second transistor is electrically connected to the second scan signal line, the first electrode of the second transistor is electrically connected to the second initial signal line, and the second electrode of the second transistor is electrically connected to the second node;

[0027] a gate electrode of the third transistor electrically connected to the third scan signal line, a first electrode of the third transistor electrically connected to the third initial signal line, and a second electrode of the second transistor electrically connected to the third node;

[0028] A gate electrode of the fourth transistor is electrically connected to the first scan signal line, a first electrode of the fourth transistor is electrically connected to the fourth node, and a second electrode of the fourth transistor is electrically connected to the third node;

[0029] A gate electrode of the fifth transistor is electrically connected to the fourth scan signal line, a first electrode of the fifth transistor is electrically connected to the data signal line, and a second electrode of the fifth transistor is electrically connected to the fourth node;

[0030] A gate electrode of the sixth transistor is electrically connected to the first node, a first electrode of the sixth transistor is electrically connected to the third node, and a second electrode of the sixth transistor is electrically connected to the second node;

[0031] A gate electrode of the seventh transistor is electrically connected to the light emitting signal line, a first electrode of the seventh transistor is electrically connected to the first power supply line, and a second electrode of the seventh transistor is electrically connected to the third node.

[0032] In an exemplary embodiment, the first transistor, the fourth transistor, and the fifth transistor are oxide transistors and are N-type transistors, and the second transistor, the third transistor, the sixth transistor, and the seventh transistor are P-type transistors;

[0033] The length of the channel region of the active layer of the sixth transistor is greater than the length of the channel region of the active layer of any one of the first to fifth transistors and the seventh transistor, the width of the channel region of the active layer of the sixth transistor is greater than the width of the channel region of the active layer of any one of the first to fifth transistors and the seventh transistor, and the width-to-length ratio of the channel region of the active layer of the sixth transistor is less than the width-to-length ratio of the channel region of the active layer of any one of the first to fifth transistors and the seventh transistor.

[0034] In an exemplary embodiment, the signal of the first scanning signal line and the signal of the second scanning signal line are inverted signals to each other;

[0035] When the signal of the third scanning signal line is a valid level signal, the signals of the first scanning signal line and the second scanning signal line are valid level signals, and the signals of the fourth scanning signal line and the light emitting signal line are invalid level signals;

[0036] When the signal of the fourth scanning signal line is a valid level signal, the signals of the first scanning signal line, the second scanning signal line, the third scanning signal line and the light emitting signal line are invalid level signals;

[0037] When the signal of the light emitting signal line is a valid level signal, the signals of the first scanning signal line, the second scanning signal line, the third scanning signal line and the fourth scanning signal line are invalid level signals;

[0038] A duration in which a signal of any one of the first scan signal line and the second scan signal line is a valid level signal is longer than a duration in which a signal of any one of the third scan signal line and the fourth scan signal line is a valid level signal.

[0039] In an exemplary embodiment, the signal of the first initial signal line and the signal of the second initial signal line are the same signal, and a voltage value of the signal of the first initial signal line is smaller than a voltage value of the signal of the third initial signal line;

[0040] A voltage value of a signal on the second initial signal line is greater than a voltage value of a signal on the second power line.

[0041] In a second aspect, the present disclosure further provides a display substrate, comprising: a substrate and a plurality of sub-pixels arranged on the substrate, at least one sub-pixel comprising: the above-mentioned pixel driving circuit and a light-emitting device driven by the pixel driving circuit.

[0042] In an exemplary embodiment, the present invention further comprises: a driving circuit layer and a light emitting structure layer sequentially stacked on the substrate, the driving circuit layer comprising: a plurality of pixel driving circuits, a plurality of light emitting signal lines, a plurality of first initial signal lines, a plurality of second initial signal lines, a plurality of third initial signal lines, a plurality of first scanning signal lines, a plurality of second scanning signal lines, a plurality of third scanning signal lines, a plurality of fourth scanning signal lines, a plurality of first power supply lines, and a plurality of data signal lines; the light emitting structure layer comprising: a light emitting device;

[0043] Any one of the light-emitting signal line, the first initial signal line, the second initial signal line, the third initial signal line, the first scanning signal line, the second scanning signal line, the third scanning signal line and the fourth scanning signal line extends at least partially along the first direction, and any one of the first power line and the data signal line extends at least partially along the second direction, and the first direction and the second direction intersect.

[0044] In an exemplary embodiment, the driving circuit layer further includes: a plurality of power connection lines extending at least partially along the first direction;

[0045] At least one power connection line is connected to the pixel driving circuit and the at least one first power line respectively.

[0046] In an exemplary embodiment, the driving circuit layer further includes: a first connecting electrode;

[0047] The first connecting electrodes are respectively connected to the pixel driving circuit, the power connection line and the first power line;

[0048] The orthographic projection of the first connecting electrode on the substrate at least partially overlaps with the orthographic projections of the power connection line and the first power line on the substrate.

[0049] In an exemplary embodiment, the first initial signal line and the second initial signal line are the same signal line, and the driving circuit layer further includes: a plurality of initial connection lines extending at least partially along the second direction;

[0050] at least one initial connection line, connected to the pixel driving circuit and the at least one first initial signal line respectively;

[0051] The orthographic projection of the initial connection line on the substrate is located between the orthographic projections of the data signal lines connected to two adjacent columns of sub-pixels connected by the initial connection line on the substrate.

[0052] In an exemplary embodiment, the first scan signal line includes: a first sub-signal line and a second sub-signal line electrically connected to each other, and the fourth scan signal line includes: a third sub-signal line and a fourth sub-signal line electrically connected to each other;

[0053] The orthographic projection of the first sub-signal line on the substrate at least partially overlaps with the orthographic projection of the second sub-signal line on the substrate, and the orthographic projection of the third sub-signal line on the substrate at least partially overlaps with the orthographic projection of the fourth sub-signal line on the substrate.

[0054] In an exemplary embodiment, the pixel driving circuit includes: first to seventh transistors and a first capacitor and a second capacitor, the first capacitor and the second capacitor respectively include: a first electrode plate and a second electrode plate, and the driving circuit layer includes a first semiconductor layer, a first conductive layer, a second conductive layer, a second semiconductor layer, a third conductive layer, a fourth conductive layer, and a fifth conductive layer sequentially provided on a substrate;

[0055] The first semiconductor layer includes at least: an active layer of a second transistor, an active layer of a third transistor, an active layer of a sixth transistor, and an active layer of a seventh transistor located in at least one sub-pixel;

[0056] The first conductive layer at least includes: a light-emitting signal line, a second scanning signal line, a third scanning signal line, and a first plate of a first capacitor located in at least one sub-pixel, a first plate of a second capacitor, a gate electrode of a second transistor, a gate electrode of a third transistor, a control electrode of a sixth transistor, and a gate electrode of a seventh transistor.

[0057] The second conductive layer at least includes: a first sub-signal line of the first scanning signal line, a third sub-signal line of the fourth scanning signal line, and a second plate of a first capacitor and a second plate of a second capacitor located in at least one sub-pixel;

[0058] The second semiconductor layer includes at least an active layer of a first transistor, an active layer of a fourth transistor, and an active layer of a fifth transistor located in at least one sub-pixel.

[0059] The third conductive layer at least includes: a second sub-signal line of the first scanning signal line, a fourth sub-signal line of the fourth scanning signal line, a power connection line, a first initial signal line, a second initial signal line and a third initial signal line;

[0060] The fourth conductive layer at least includes: an initial connection line, a first connection electrode located at at least one sub-pixel, and first electrodes and second electrodes of the first to seventh transistors;

[0061] The fifth conductive layer at least includes: a first power line and a data signal line.

[0062] In an exemplary embodiment, the driving circuit layer further includes: a light shielding layer disposed between the substrate and the first semiconductor layer;

[0063] The light shielding layer comprises at least: a light shielding structure located in at least one sub-pixel, wherein the light shielding structures of adjacent sub-pixels are connected to each other;

[0064] An orthographic projection of the light-shielding structure on the substrate at least partially overlaps with an orthographic projection of the gate electrode of the sixth transistor on the substrate.

[0065] In an exemplary embodiment, the light shielding structure includes: a first light shielding portion, a second light shielding portion, a third light shielding portion, and a fourth light shielding portion;

[0066] The orthographic projection of the first light-shielding portion on the substrate at least partially overlaps with the orthographic projection of the active layer of the sixth transistor on the substrate, the orthographic projection of the second light-shielding portion on the substrate at least partially overlaps with the orthographic projection of the active layer of the seventh transistor on the substrate, the orthographic projection of the third light-shielding portion on the substrate at least partially overlaps with the orthographic projection of the active layer of the third transistor on the substrate, and the orthographic projection of the fourth light-shielding portion on the substrate at least partially overlaps with the orthographic projection of the active layer of the second transistor on the substrate.

[0067] In an exemplary embodiment, the light shielding structure includes: a light shielding portion, a first light shielding connection portion, a second light shielding connection portion, a third light shielding connection portion, and a fourth light shielding connection portion;

[0068] The orthographic projection of the light-shielding portion on the substrate at least partially overlaps with the orthographic projection of the active layer of the sixth transistor on the substrate, and the orthographic projection of any one of the first light-shielding connection portion, the second light-shielding connection portion, the third light-shielding connection portion and the fourth light-shielding connection portion on the substrate does not overlap with the orthographic projection of any one of the active layer of the second transistor, the active layer of the third transistor and the active layer of the seventh transistor on the substrate.

[0069] In an exemplary embodiment, the light emitting signal line connected to the sub-pixel is located on a side where the first plate of the second capacitor of the sub-pixel is away from the first plate of the first capacitor of the sub-pixel, the second scanning signal line connected to the sub-pixel is located on a side where the first plate of the first capacitor of the sub-pixel is away from the first plate of the second capacitor of the sub-pixel, and the third scanning signal line connected to the sub-pixel is located on a side where the second scanning signal line connected to the sub-pixel is away from the first plate of the first capacitor of the sub-pixel.

[0070] In an exemplary embodiment, the second plate of the first capacitor and the second plate of the second capacitor are an integral structure connected to each other and provided with a first via hole and a second via hole, the first via hole exposing the first plate of the first capacitor and the second via hole exposing the second plate of the second capacitor;

[0071] The third sub-signal line of the fourth scan signal line is located on a side of the first sub-signal line of the first scan signal line away from the integrated structure of the second electrode plate of the first capacitor and the second electrode plate of the second capacitor;

[0072] The orthographic projection of the first sub-signal line of the first scanning signal line connected to the sub-pixel on the substrate is located between the orthographic projection of the luminous signal line connected to the sub-pixel on the substrate and the orthographic projection of the first plate of the second capacitor of the sub-pixel on the substrate, and the orthographic projection of the third sub-signal line of the fourth scanning signal line connected to the sub-pixel on the substrate is located on the side of the orthographic projection of the luminous signal line connected to the sub-pixel on the substrate away from the orthographic projection of the first plate of the second capacitor of the sub-pixel on the substrate.

[0073] In an exemplary embodiment, the second sub-signal line of the first scan signal line connected to the sub-pixel is located on one side of the fourth sub-signal line of the fourth scan signal line connected to the sub-pixel, the power supply connection line connected to the sub-pixel is located on one side of the second sub-signal line of the first scan signal line connected to the sub-pixel away from the fourth sub-signal line of the fourth scan signal line connected to the sub-pixel, the first initialization signal line connected to the sub-pixel is located on one side of the power supply connection line connected to the sub-pixel away from the second sub-signal line of the first scan signal line connected to the sub-pixel, and the third initialization signal line connected to the sub-pixel is located on one side of the first initialization signal line connected to the sub-pixel away from the power supply connection line connected to the sub-pixel;

[0074] The orthographic projection of the fourth sub-signal line of the fourth scanning signal line connected to the sub-pixel on the substrate is located on a side of the orthographic projection of the light emitting signal line connected to the sub-pixel on the substrate away from the orthographic projection of the first electrode plate of the second capacitor of the sub-pixel on the substrate;

[0075] The orthographic projection of the second sub-signal line of the first scanning signal line connected to the sub-pixel on the substrate is located between the orthographic projection of the light emitting signal line connected to the sub-pixel on the substrate and the orthographic projection of the first electrode plate of the second capacitor of the sub-pixel on the substrate;

[0076] An orthographic projection of a power connection line connected to the sub-pixel on the substrate at least partially overlaps with an orthographic projection of an integrated structure of the second electrode plate of the first capacitor and the second electrode plate of the second capacitor of the sub-pixel on the substrate, and is located between an orthographic projection of a first sub-signal line of the first scanning signal line on the substrate and an orthographic projection of the second scanning signal line on the substrate;

[0077] An orthographic projection of a first initial signal line connected to the sub-pixel on the substrate at least partially overlaps with an orthographic projection of a second scanning signal line connected to the sub-pixel on the substrate, and is located between an orthographic projection of a first plate of a first capacitor of the sub-pixel on the substrate and an orthographic projection of a third scanning signal line connected to the sub-pixel on the substrate;

[0078] The orthographic projection of the third initial signal line connected to the sub-pixel on the substrate at least partially overlaps with the orthographic projection of the third scanning signal line connected to the sub-pixel on the substrate, and is located on a side of the orthographic projection of the second scanning signal line connected to the sub-pixel on the substrate away from the orthographic projection of the first plate of the first capacitor of the sub-pixel on the substrate.

[0079] In an exemplary embodiment, the power connection line includes: a signal main line, a first protrusion, a second protrusion, and a third protrusion, the signal main line extending along a first direction, the first protrusion being located on a side of the signal main line close to the second sub-signal line of the first scan signal line, the second protrusion and the third protrusion being located on a side of the signal main line away from the second sub-signal line of the first scan signal line, and the second protrusion and the third protrusion being arranged along the first direction;

[0080] The orthographic projections of the second protrusion and the third protrusion on the substrate at least partially overlap with the orthographic projections of the integrated structure of the second electrode plate of the first capacitor and the second electrode plate of the second capacitor on the substrate;

[0081] The orthographic projection of the first via hole on the substrate is located between the orthographic projection of the second protrusion on the substrate and the orthographic projection of the third protrusion on the substrate.

[0082] In an exemplary embodiment, the orthographic projection of the first connection electrode on the substrate at least partially overlaps with the orthographic projections of the signal main line, the second protrusion, and the third protrusion of the power connection line on the substrate, and does not overlap with the orthographic projection of the first protrusion of the power connection line on the substrate.

[0083] In an exemplary embodiment, an orthographic projection of the first power line on the substrate at least partially overlaps an orthographic projection of the second plate of the first capacitor and the integrated structure of the second plate of the second capacitor, the first connection electrode, the signal main portion of the power connection line, and the second protrusion on the substrate;

[0084] The orthographic projection of the first power supply line connected to the sub-pixel on the substrate is located on a side of the data signal line connected to the sub-pixel away from the initial connection line connected to the sub-pixel.

[0085] In a third aspect, the present disclosure further provides a display device, comprising: the above-mentioned display substrate.

[0086] In a fourth aspect, the present disclosure further provides a driving method for a pixel driving circuit, configured to drive the above-mentioned pixel driving circuit, the method comprising:

[0087] The node control subcircuit, under the control of the signals of the first scan signal line, the second scan signal line, the third scan signal line, and the fourth scan signal line, drives the signal of the first node through the signals of the first initial signal line, the data signal line, and the first power line, provides the signal of the second initial signal line to the second node, and provides the signal of the third initial signal line to the third node;

[0088] The light control subcircuit provides the signal of the first power line to the third node under the control of the signal of the light signal line. The driving subcircuit outputs the driving current to the second node under the control of the signals of the first node and the third node.

[0089] Still other aspects will become apparent upon reading and understanding the accompanying drawings and detailed description.

[0090] Summary of the Figures

[0091] The accompanying drawings are used to provide an understanding of the technical solution of the present disclosure and constitute a part of the specification. Together with the embodiments of the present disclosure, they are used to explain the technical solution of the present disclosure and do not constitute a limitation to the technical solution of the present disclosure.

[0092] FIG1 is a schematic structural diagram of a pixel driving circuit provided by an embodiment of the present disclosure;

[0093] FIG2 is a schematic diagram of the structure of a node control subcircuit;

[0094] FIG3 is an equivalent circuit diagram of a node control subcircuit;

[0095] FIG4 is an equivalent circuit diagram of the light emitting control subcircuit and the driving subcircuit;

[0096] FIG5 is an equivalent circuit diagram of a pixel driving circuit;

[0097] FIG6 is a timing diagram of an operation of a pixel driving circuit;

[0098] FIG7 is a first structural diagram of a display substrate provided in an embodiment of the present disclosure;

[0099] FIG8 is a second structural diagram of a display substrate provided in an embodiment of the present disclosure;

[0100] FIG9 is a schematic diagram showing a portion of the film layers of a substrate;

[0101] FIG10 is a second schematic diagram showing a portion of the film layer of the display substrate;

[0102] FIG11 is a schematic diagram of a light shielding layer pattern of the display substrate provided in FIG7 ;

[0103] FIG12 is a schematic diagram of a light shielding layer pattern of the display substrate provided in FIG8 ;

[0104] FIG13 is a schematic diagram of a first semiconductor layer pattern of a display substrate provided in FIG7 and FIG8;

[0105] FIG14 is a schematic diagram of the display substrate provided in FIG7 after a first semiconductor layer pattern is formed;

[0106] FIG15 is a schematic diagram of the display substrate provided in FIG8 after a first semiconductor layer pattern is formed;

[0107] FIG16 is a schematic diagram of a first conductive layer pattern of a display substrate provided in FIG7 and FIG8;

[0108] FIG17 is a schematic diagram of the display substrate provided in FIG7 after a first conductive layer pattern is formed;

[0109] FIG18 is a schematic diagram of the display substrate provided in FIG8 after a first conductive layer pattern is formed;

[0110] FIG19 is a schematic diagram of a second conductive layer pattern of the display substrate provided in FIG7 and FIG8;

[0111] FIG20 is a schematic diagram of the display substrate provided in FIG7 after a second conductive layer pattern is formed;

[0112] FIG21 is a schematic diagram of the display substrate provided in FIG8 after a second conductive layer pattern is formed;

[0113] FIG22 is a schematic diagram of a second semiconductor layer pattern of the display substrate provided in FIG7 and FIG8;

[0114] FIG23 is a schematic diagram of the display substrate provided in FIG7 after a second semiconductor layer pattern is formed;

[0115] FIG24 is a schematic diagram of the display substrate provided in FIG8 after a second semiconductor layer pattern is formed;

[0116] FIG25 is a schematic diagram of a third conductive layer pattern of the display substrate provided in FIG7 and FIG8;

[0117] FIG26 is a schematic diagram of the display substrate provided in FIG7 after a third conductive layer pattern is formed;

[0118] FIG27 is a schematic diagram of the display substrate provided in FIG8 after a third conductive layer pattern is formed;

[0119] FIG28 is a schematic diagram of the display substrate provided in FIG7 after a seventh insulating layer pattern is formed;

[0120] FIG29 is a schematic diagram of the display substrate provided in FIG8 after a seventh insulating layer pattern is formed;

[0121] FIG30 is a schematic diagram showing a fourth conductive layer pattern of the display substrate provided in FIG7 and FIG8;

[0122] FIG31 is a schematic diagram of the display substrate provided in FIG7 after a fourth conductive layer pattern is formed;

[0123] FIG32 is a schematic diagram of the display substrate provided in FIG8 after a fourth conductive layer pattern is formed;

[0124] FIG33 is a schematic diagram of the display substrate provided in FIG7 after an eighth insulating layer pattern is formed;

[0125] FIG34 is a schematic diagram of the display substrate provided in FIG8 after an eighth insulating layer pattern is formed;

[0126] FIG35 is a schematic diagram showing a fifth conductive layer pattern of the display substrate provided in FIG7 and FIG8;

[0127] FIG36 is a schematic diagram of the display substrate provided in FIG7 after a fifth conductive layer pattern is formed;

[0128] FIG37 is a schematic diagram showing the display substrate provided in FIG8 after a fifth conductive layer pattern is formed.

[0129] Details

[0130] In order to make the purpose, technical solutions and advantages of the present disclosure clearer, the embodiments of the present disclosure will be described in detail below with reference to the accompanying drawings. Note that the embodiments can be implemented in a variety of different forms. A person of ordinary skill in the art can easily understand the fact that the methods and contents can be transformed into various forms without departing from the purpose and scope of the present disclosure. Therefore, the present disclosure should not be interpreted as being limited to the contents described in the following embodiments. Unless there is a conflict, the embodiments in the present disclosure and the features in the embodiments can be arbitrarily combined with each other. In order to keep the following description of the embodiments of the present disclosure clear and concise, the present disclosure omits detailed descriptions of some known functions and known components. The drawings of the embodiments of the present disclosure only involve structures related to the embodiments of the present disclosure. Other structures can refer to the general design

[0131] The scales of the figures in this disclosure can be used as a reference for actual processes, but are not limited to such. For example, the width-to-length ratio of the channel, the thickness and spacing of the various film layers, and the width and spacing of the various signal lines can be adjusted according to actual needs. The number of pixels in the display substrate and the number of sub-pixels in each pixel are not limited to the numbers shown in the figures. The figures described in this disclosure are merely schematic structural diagrams, and one embodiment of this disclosure is not limited to the shapes or values ​​shown in the figures.

[0132] In this specification, ordinal numbers such as “first”, “second” and “third” are provided to avoid confusion among constituent elements, and are not intended to limit the number.

[0133] In this specification, for convenience, words and phrases indicating orientation or positional relationships, such as "middle," "upper," "lower," "front," "back," "vertical," "horizontal," "top," "bottom," "inside," and "outside," are used to illustrate the positional relationships of constituent elements with reference to the accompanying drawings. This is merely for the purpose of facilitating the description of this specification and simplifying the description, and does not indicate or imply that the device or element referred to must have a specific orientation, be constructed, or operate in a specific orientation. Therefore, they should not be construed as limiting the present disclosure. The positional relationships of constituent elements may be appropriately changed depending on the direction in which each constituent element is described. Therefore, the present disclosure is not limited to the words and phrases described in the specification and may be appropriately replaced according to the circumstances.

[0134] In this specification, unless otherwise specified or limited, the terms "mounted," "connected," and "connected" should be understood broadly. For example, they can refer to fixed, removable, or integral connections; mechanical or electrical connections; direct connections, indirect connections through intermediaries, or internal communication between two components. Those skilled in the art will understand the specific meanings of these terms in this disclosure.

[0135] In this specification, a transistor refers to a device consisting of at least three elements: a gate electrode, a drain electrode, and a source electrode. A transistor has a channel region between a drain electrode (drain electrode element, drain region, or drain electrode) and a source electrode (source electrode element, source region, or source electrode), and current can flow through the drain electrode, the channel region, and the source electrode. Note that in this specification, the channel region refers to the region through which current primarily flows.

[0136] In this specification, the first electrode can be a drain electrode and the second electrode can be a source electrode, or vice versa. The functions of "source electrode" and "drain electrode" may be interchanged when using transistors with opposite polarity or when the direction of current changes during circuit operation. Therefore, in this specification, "source electrode" and "drain electrode" may be interchanged.

[0137] In this specification, "electrically connected" includes components connected together via an element having some electrical function. There are no particular limitations on the "element having some electrical function" as long as it enables the transfer of electrical signals between the connected components. Examples of "element having some electrical function" include not only electrodes and wiring, but also switching elements such as transistors, resistors, inductors, capacitors, and other components with various functions.

[0138] In this specification, "parallel" refers to a state where the angle formed by two straight lines is greater than -10° and less than 10°, and thus also includes a state where the angle is greater than -5° and less than 5°. Furthermore, "perpendicular" refers to a state where the angle formed by two straight lines is greater than 80° and less than 100°, and thus also includes a state where the angle is greater than 85° and less than 95°.

[0139] In this specification, the terms "film" and "layer" may be interchanged. For example, "conductive layer" may be replaced with "conductive film." Similarly, "insulating film" may be replaced with "insulating layer."

[0140] In this specification, the term "same-layer arrangement" refers to a structure formed by patterning two (or more) structures using the same patterning process. The materials of these structures can be the same or different. For example, the precursor materials for forming the multiple structures arranged in the same layer can be the same, and the materials of the final structures can be the same or different.

[0141] The triangles, rectangles, trapezoids, pentagons or hexagons in this specification are not in the strict sense, but may be approximate triangles, rectangles, trapezoids, pentagons or hexagons, etc. There may be some small deformations caused by tolerances, and there may be chamfers, arc edges and deformations.

[0142] The term "about" in the present disclosure refers to a numerical value that is not strictly defined and allows for process and measurement errors.

[0143] Low-temperature polysilicon (LTPS) technology is used in display substrates. LTPS technology boasts advantages such as high resolution, high response speed, high brightness, and a high aperture ratio. Although popular in the market, LTPS technology also has drawbacks, such as high production costs and high power consumption. This is why low-temperature polycrystalline oxide (LTPO) technology has emerged as a viable solution. Compared to LTPS technology, LTPO technology offers lower leakage current and faster pixel response. The addition of an oxide layer to the display substrate reduces the energy required to excite the pixels, thereby reducing power consumption during screen display. However, compared to display products using LTPO technology, the manufacturing process is more complex and costly. With the emergence of high-mobility oxide materials, oxide-driven OLED devices have become possible. This has made display products using oxide technology possible. Compared to LTPO technology, oxide technology offers a simpler process, lower cost, and lower leakage current, making it a new mainstream trend. However, in oxide-based display products, the pixel driver circuit has a shorter charging time, which cannot meet the requirements of high-resolution display substrates, affecting the display quality of the display products.

[0144] Figure 1 is a schematic diagram of the structure of a pixel driver circuit according to an embodiment of the present disclosure, Figure 2 is a schematic diagram of the structure of a node control subcircuit, and Figure 3 is an equivalent circuit diagram of the node control subcircuit. As shown in Figures 1 to 3, the pixel driver circuit according to an embodiment of the present disclosure is configured to drive a light-emitting device to emit light. The pixel driver circuit includes: a node control subcircuit, a light-emitting control subcircuit, and a driver subcircuit.

[0145] In an exemplary embodiment, as shown in FIG1 , the node control sub-circuit may be electrically connected to the first node N1, the second node N2, the third node N3, the first scan signal line Gate1, the second scan signal line Gate2, the third scan signal line Gate3, the fourth scan signal line Gate4, the first initial signal line INIT1, the second initial signal line INIT2, the third initial signal line INIT3, the data signal line Data, and the first power line VDD, respectively, and may be configured to drive the signal of the first node N1 through the first initial signal line INIT1, the data signal line Data, and the signal of the third node N3 under the control of the signals of the first scan signal line Gate1, the second scan signal line Gate2, the third scan signal line Gate3, and the fourth scan signal line Gate4, provide the signal of the second initial signal line INIT2 to the second node N2, provide the signal of the third initial signal line INIT3 to the third node N3, and provide the signal of the third node N3 or the data signal line Data to the fourth node N4.

[0146] In an exemplary embodiment, as shown in Figures 1 to 3, the node control subcircuit includes: an energy storage subcircuit, which is electrically connected to the first node N1, the fourth node N4 and the first power line VDD, respectively, and is configured to store the voltage difference between the signals of the first node N1 and the fourth node N4 and the voltage difference between the signal of the fourth node N4 and the first power line VDD, so as to drive the signal of the first node N1 through the signal of the first power line and the signal of the fourth node N4.

[0147] In an exemplary embodiment, as shown in FIG3 , the energy storage subcircuit may include: a first capacitor C1 and a second capacitor C2, each of which includes: a first plate and a second plate. The first plate C11 of the first capacitor C1 is electrically connected to the first power line VDD, and the second plate C12 of the first capacitor C1 is electrically connected to the fourth node N4; the first plate C21 of the second capacitor C2 is electrically connected to the first node N1, and the second plate C22 of the second capacitor C2 is electrically connected to the fourth node N4.

[0148] In an exemplary embodiment, as shown in FIG1 , the light emitting control sub-circuit may be electrically connected to the first power line VDD, the light emitting signal line EM, and the third node N3, respectively, and may be configured to provide the signal of the first power line VDD to the third node N3 under the control of the signal of the light emitting signal line EM.

[0149] In an exemplary embodiment, as shown in FIG1 , the driving sub-circuit is electrically connected to the first node N1 , the second node N2 , and the third node N3 , respectively, and is configured to output a driving current to the second node N2 under the control of signals of the first node N1 and the third node N3 .

[0150] In an exemplary embodiment, as shown in FIG. 1 , the light emitting device is electrically connected to the second node N2 and the second power line VSS, respectively.

[0151] In an exemplary embodiment, the first power line VDD may continuously provide a high voltage power signal, and the second power line VSS may continuously provide a low voltage power signal.

[0152] In an exemplary embodiment, the voltage value of the signal of the first power line VDD may be approximately 2.5V to 3V, and exemplarily, the voltage value of the signal of the first power line VDD may be approximately 2.8V.

[0153] In an exemplary embodiment, the voltage value of the signal of the second power line VSS may be approximately -3 volts (V) to -3.5 volts (V), and illustratively, the voltage value of the signal of the second power line VSS may be approximately -3.2 volts (V).

[0154] In an exemplary embodiment, the voltage value of the signal of the second power line VSS may be approximately -3 volts (V) to -3.5 volts (V), and illustratively, the voltage value of the signal of the second power line VSS may be approximately -3.2 volts (V).

[0155] In an exemplary embodiment, the light-emitting device may be an organic light-emitting diode (OLED), including a stacked first electrode (anode), an organic light-emitting layer, and a second electrode (cathode). Exemplarily, the anode of the organic light-emitting diode is electrically connected to the second node N2, and the cathode of the organic light-emitting diode is electrically connected to the second power line VSS.

[0156] In an exemplary embodiment, the organic light-emitting layer may include a stacked hole injection layer (HIL), a hole transport layer (HTL), an electron blocking layer (EBL), an emitting layer (EML), a hole blocking layer (HBL), an electron transport layer (ETL), and an electron injection layer (EIL). In an exemplary embodiment, the hole injection layers of all sub-pixels may be a common layer connected together, the electron injection layers of all sub-pixels may be a common layer connected together, the hole transport layers of all sub-pixels may be a common layer connected together, the electron transport layers of all sub-pixels may be a common layer connected together, and the hole blocking layers of all sub-pixels may be a common layer connected together. The light-emitting layers of adjacent sub-pixels may have a small overlap or may be isolated, and the electron blocking layers of adjacent sub-pixels may have a small overlap or may be isolated.

[0157] The pixel driving circuit provided by the embodiment of the present disclosure is configured to drive a light-emitting device, and the pixel driving circuit includes: a node control subcircuit, a light-emitting control subcircuit and a driving subcircuit; the node control subcircuit is electrically connected to the first node, the second node, the third node, the first scan signal line, the second scan signal line, the third scan signal line, the fourth scan signal line, the first initial signal line, the second initial signal line, the third initial signal line, the data signal line and the first power line, respectively, and is configured to drive the signal of the first node through the first initial signal line, the data signal line and the signal of the third node under the control of the signal of the first scan signal line, the second scan signal line, the third scan signal line and the fourth scan signal line, provide the signal of the second initial signal line to the second node, and provide the signal of the third initial signal line to the third node; The node control subcircuit is electrically connected to the first power line, the light-emitting signal line and the third node, and is configured to provide the signal of the first power line to the third node under the control of the signal of the light-emitting signal line; the driving subcircuit is electrically connected to the first node, the second node and the third node, and is configured to output a driving current to the second node under the control of the signals of the first node and the third node; the light-emitting device is electrically connected to the second node and the second power line, respectively. The node control subcircuit includes: an energy storage subcircuit, the energy storage subcircuit includes: a first capacitor and a second capacitor, the first capacitor and the second capacitor include: a first plate and a second plate; the first plate of the first capacitor is electrically connected to the first power line, and the second plate of the first capacitor is electrically connected to the fourth node; the first plate of the second capacitor is electrically connected to the first node, and the second plate of the second capacitor is electrically connected to the fourth node. The present disclosure can compensate the pixel driving circuit through the signal of the second initial signal line by setting the node control subcircuit, the light-emitting control subcircuit and the driving subcircuit, thereby increasing the compensation time of the pixel driving circuit, extending the charging time of the pixel driving circuit, and improving the reliability of the pixel driving circuit.

[0158] In an exemplary embodiment, as shown in FIG. 2 , the node control subcircuit may further include a reset subcircuit, a compensation subcircuit, and a write subcircuit.

[0159] As shown in FIG2 , the reset sub-circuit is electrically connected to the first node N1, the second node N2, the third node N3, the first scan signal line Gate1, the second scan signal line Gate2, the third scan signal line Gate3, the first initial signal line INIT1, the second initial signal line INIT2, and the third initial signal line INIT3, respectively, and is configured to provide the signal of the first initial signal line INIT1 to the first node N1 under the control of the signal of the first scan signal line Gate1, and to provide the signal of the second initial signal line INIT2 to the second node N2 under the control of the signal of the second scan signal line Gate2, and to provide the signal of the second initial signal line INIT3 to the second node N2 under the control of the signal of the third scan signal line Gate3. The compensation sub-circuit is electrically connected to the third node N3, the fourth node N4 and the first scanning signal line Gate1, and is configured to, under the control of the signal of the first scanning signal line Gate1, provide the signal of the third node N3 to the fourth node N4 to compensate for the signal of the fourth node N4; the write sub-circuit is electrically connected to the fourth node N4, the fourth scanning signal line Gate4 and the data signal line Data, and is configured to, under the control of the signal of the fourth scanning signal line Gate4, provide the signal of the data signal line Data to the fourth node N4.

[0160] In an exemplary embodiment, as shown in FIG3 , the reset subcircuit may include a first transistor T1 , a second transistor T2 , and a third transistor T3 , the compensation subcircuit may include a fourth transistor T4 , and the write transistor may include a fifth transistor T5 . Among them, the gate electrode of the first transistor T1 is electrically connected to the first scan signal line Gate1, the first electrode of the first transistor T1 is electrically connected to the first initial signal line INIT1, and the second electrode of the first transistor T1 is electrically connected to the first node N1; the gate electrode of the second transistor T2 is electrically connected to the second scan signal line Gate2, the first electrode of the second transistor T2 is electrically connected to the second initial signal line INIT2, and the second electrode of the second transistor T2 is electrically connected to the second node N2; the gate electrode of the third transistor T3 is electrically connected to the third scan signal line Gate3, the first electrode of the third transistor T3 is electrically connected to the third initial signal line INIT3, and the second electrode of the second transistor T2 is electrically connected to the third node N3; the gate electrode of the fourth transistor T4 is electrically connected to the first scan signal line Gate1, the first electrode of the fourth transistor T4 is electrically connected to the fourth node N4, and the second electrode of the fourth transistor T4 is electrically connected to the third node N3; the gate electrode of the fifth transistor T5 is electrically connected to the fourth scan signal line Gate4, the first electrode of the fifth transistor T5 is electrically connected to the data signal line Data, and the second electrode of the fifth transistor T5 is electrically connected to the fourth node N4.

[0161] Figure 4 is an equivalent circuit diagram of the light-emission control subcircuit and the driver subcircuit. As shown in Figure 4 , the driver subcircuit may include a sixth transistor T6, and the light-emission control subcircuit may include a seventh transistor T7. The gate electrode of the sixth transistor T6 is electrically connected to the first node N1, the first electrode of the sixth transistor T6 is electrically connected to the third node N3, and the second electrode of the sixth transistor T6 is electrically connected to the second node N2. The gate electrode of the seventh transistor T7 is electrically connected to the light-emission signal line EM, the first electrode of the seventh transistor T7 is electrically connected to the first power line VDD, and the second electrode of the seventh transistor T7 is electrically connected to the third node N3.

[0162] Figure 5 is an equivalent circuit diagram of a pixel driving circuit. As shown in Figure 5, in an exemplary embodiment, the node control subcircuit includes: first transistors T1 to T5 and first and second capacitors C1 and C2; the driving subcircuit includes: sixth transistor T6; the light emission control subcircuit includes: seventh transistor T7; the first and second capacitors C1 and C2 include: first and second plates. Among them, the gate electrode of the first transistor T1 is electrically connected to the first scanning signal line Gate1, the first electrode of the first transistor T1 is electrically connected to the first initial signal line INIT1, and the second electrode of the first transistor T1 is electrically connected to the first node N1; the gate electrode of the second transistor T2 is electrically connected to the second scanning signal line Gate2, the first electrode of the second transistor T2 is electrically connected to the second initial signal line INIT2, and the second electrode of the second transistor T2 is electrically connected to the second node N2; the gate electrode of the third transistor T3 is electrically connected to the third scanning signal line Gate3, the first electrode of the third transistor T3 is electrically connected to the third initial signal line INIT3, and the second electrode of the second transistor T2 is electrically connected to the third node N3; the gate electrode of the fourth transistor T4 is electrically connected to the first scanning signal line Gate1, the first electrode of the fourth transistor T4 is electrically connected to the fourth node N4, and the second electrode of the fourth transistor T4 is electrically connected to the third node N3; The gate electrode of the fifth transistor T5 is electrically connected to the fourth scan signal line Gate4, the first electrode of the fifth transistor T5 is electrically connected to the data signal line Data, and the second electrode of the fifth transistor T5 is electrically connected to the fourth node N4; the gate electrode of the sixth transistor T6 is electrically connected to the first node N1, the first electrode of the sixth transistor T6 is electrically connected to the third node N3, and the second electrode of the sixth transistor T6 is electrically connected to the second node N2; the gate electrode of the seventh transistor T7 is electrically connected to the light emitting signal line EM, the first electrode of the seventh transistor T7 is electrically connected to the first power line VDD, and the second electrode of the seventh transistor T7 is electrically connected to the third node N3; the first plate C11 of the first capacitor C1 is electrically connected to the first power line VDD, and the second plate C12 of the first capacitor C1 is electrically connected to the fourth node N4; the first plate C21 of the second capacitor C2 is electrically connected to the first node N1, and the second plate C22 of the second capacitor C2 is electrically connected to the fourth node N4.

[0163] In an exemplary embodiment, the first transistor T1 may be referred to as a first node reset transistor. When the signal of the first scan signal line Gate1 is an active level signal, the signal of the first initial signal line INIT1 is written into the first node N1.

[0164] In an exemplary embodiment, the second transistor T2 may be referred to as a second node reset transistor. When the signal of the first scanning signal line Gate2 is an active level signal, the signal of the second initial signal line INIT2 is written into the second node N2 (also the anode of the light emitting device L).

[0165] In an exemplary embodiment, the third transistor T3 may be referred to as a third node reset transistor. When the signal of the third scan signal line Gate3 is an active level signal, the signal of the third initial signal line INIT3 is written into the third node N3.

[0166] In an exemplary embodiment, the fourth transistor T4 may be referred to as a compensation transistor. When the signal of the first scan signal line Gate1 is an active level signal, the signal of the third node N3 is written into the fourth node N4 to compensate for the signal of the fourth node N4.

[0167] In an exemplary embodiment, the fifth transistor T5 may be referred to as a write transistor. When the signal of the fourth scan signal line Gate is an active level signal, the signal of the data signal line Data is written into the second node N2.

[0168] In an exemplary embodiment, the sixth transistor T6 may be referred to as a driving transistor, and determines a driving current flowing between the first power line VDD and the second power line VSS according to a potential difference between the gate electrode and the first electrode of the sixth transistor T6.

[0169] In an exemplary embodiment, the seventh transistor T7 may be referred to as a light emitting transistor. When the signal of the light emitting signal line EM is an active level signal, the seventh transistor T7 forms a driving current path between the first power line VDD and the second power line VSS to enable the light emitting device to emit light.

[0170] In an exemplary embodiment, a length of a channel region of an active layer of the sixth transistor is greater than a length of a channel region of an active layer of any one of the first to fifth transistors and the seventh transistor, a width of a channel region of an active layer of the sixth transistor is greater than a width of a channel region of an active layer of any one of the first to fifth transistors and the seventh transistor, and a width-to-length ratio of a channel region of an active layer of the sixth transistor is less than a width-to-length ratio of a channel region of an active layer of any one of the first to fifth transistors and the seventh transistor.

[0171] An exemplary structure of the node control subcircuit, the driving subcircuit, and the light emitting control subcircuit is shown in Figure 5. Those skilled in the art will readily appreciate that the implementation of the node control subcircuit, the driving subcircuit, and the light emitting control subcircuit is not limited thereto.

[0172] Transistors can be divided into N-type transistors and P-type transistors according to their characteristics. When the transistor is a P-type transistor, the turn-on voltage is a low-level voltage (e.g., 0V, -5V, -10V, or other suitable voltages), and the turn-off voltage is a high-level voltage (e.g., 5V, 10V, or other suitable voltages). When the transistor is an N-type transistor, the turn-on voltage is a high-level voltage (e.g., 5V, 10V, or other suitable voltages), and the turn-off voltage is a low-level voltage (e.g., 0V, -5V, -10V, or other suitable voltages).

[0173] In an exemplary embodiment, the first transistor T1 to the seventh transistor T7 may be a P-type transistor or an N-type transistor. Using the same type of transistors in the pixel driving circuit can simplify the process flow, reduce the manufacturing difficulty of the display panel, and improve the product yield. In some possible implementations, the first transistor T1 to the seventh transistor T7 may include P-type transistors and N-type transistors.

[0174] In an exemplary embodiment, the first transistor T1 to the seventh transistor T7 may be low-temperature polysilicon thin-film transistors, or oxide thin-film transistors, or both. The active layer of the low-temperature polysilicon thin-film transistor is made of low-temperature polysilicon (LTPS), and the active layer of the oxide thin-film transistor is made of oxide semiconductor (Oxide). Low-temperature polysilicon thin-film transistors have advantages such as high mobility and fast charging, while oxide thin-film transistors have advantages such as low leakage current. Integrating low-temperature polysilicon thin-film transistors and oxide thin-film transistors on a display substrate to form a low-temperature polycrystalline oxide (LTPO) display substrate can leverage the advantages of both, enabling low-frequency driving, reducing power consumption, and improving display quality.

[0175] In example embodiments, the first transistor T1 , the fourth transistor T4 , and the fifth transistor T5 may be oxide transistors.

[0176] In an exemplary embodiment, the first transistor T1 , the fourth transistor T4 , and the fifth transistor T5 may be N-type transistors, and the second transistor T2 , the third transistor T3 , the sixth transistor T6 , and the seventh transistor T7 may be P-type transistors.

[0177] In example embodiments, the width-to-length ratio of the channel regions of the active layers of the first to fifth transistors T1 to T5 may be 2.5 / 3.

[0178] In an exemplary embodiment, the width-to-length ratio of the channel region of the active layer of the sixth transistor T6 (driving transistor) may be 3.5 / 20.

[0179] In example embodiments, a width-to-length ratio of a channel region of an active layer of the seventh transistor T7 may be 2.0 / 2.5.

[0180] In an exemplary embodiment, the signal of the first scan signal line Gate1 and the signal of the second scan signal line Gate2 may be inverted signals of each other.

[0181] In an exemplary embodiment, when the signal of the third scan signal line Gate3 is an active level signal, the signals of the first scan signal line Gate1 and the second scan signal line Gate2 are active level signals, and the signals of the fourth scan signal line Gate4 and the emission signal line EM are inactive level signals.

[0182] In an exemplary embodiment, when the signal of the fourth scan signal line Gate4 is an active level signal, the signals of the first scan signal line Gate1 , the second scan signal line Gate2 , the third scan signal line Gate3 and the emission signal line EM are inactive level signals.

[0183] In an exemplary embodiment, when the signal of the emission signal line EM is an active level signal, the signals of the first scan signal line Gate1 , the second scan signal line Gate2 , the third scan signal line Gate3 , and the fourth scan signal line Gate4 are inactive level signals.

[0184] In an exemplary embodiment, a duration in which a signal of any one of the first scan signal line Gate1 and the second scan signal line Gate2 is an active level signal is greater than a duration in which a signal of any one of the third scan signal line Gate3 and the fourth scan signal line Gate4 is an active level signal.

[0185] In an exemplary embodiment, the signal of the first initial signal line INIT1 and the signal of the second initial signal line INIT2 may be the same signal, and a voltage value of the signal of the first initial signal line INIT1 is smaller than a voltage value of the signal of the third initial signal line INIT3 .

[0186] In an exemplary embodiment, the first initial signal line INIT1 and the second initial signal line INIT2 may be the same signal line, or may be different signal lines transmitting the same signal, which is not limited in the present disclosure.

[0187] In an exemplary embodiment, the voltage value of the signal of the first initial signal line INIT1 may be approximately -2.8V to -3.2V, and illustratively, the voltage value of the signal of the first initial signal line INIT1 may be approximately -3V.

[0188] In an exemplary embodiment, the voltage value of the signal of the third initial signal line INIT3 may be approximately 5 volts (V) to 7 volts (V), and illustratively, the voltage value of the signal of the third initial signal line INIT3 may be approximately 6 volts (V).

[0189] In an exemplary embodiment, the voltage value of the signal on the second initial signal line INIT2 may be greater than the voltage value of the signal on the second power line VSS. For example, the voltage value of the signal on the second initial signal line INIT2 may be slightly greater than the voltage value of the signal on the second power line VSS. The voltage value of the signal on the second initial signal line INIT2 being greater than the voltage value of the signal on the second power line VSS can ensure that the light-emitting device does not emit light when the second node N2 (which is also the anode of the light-emitting device) is reset, thereby improving the display effect.

[0190] Figure 6 is a timing diagram of the operation of a pixel driving circuit. The following illustrates an exemplary embodiment of the present disclosure using the operation of the pixel driving circuit illustrated in Figure 5. The pixel driving circuit in Figure 5 includes seven transistors (first transistor T1 to seventh transistor T7) and two capacitors (first capacitor C1 and second capacitor C2). The first transistor T1, the fourth transistor T4, and the fifth transistor T5 are N-type transistors, while the second transistor T2, the third transistor T3, the sixth transistor T6, and the seventh transistor T7 are P-type transistors.

[0191] In an exemplary embodiment, the operation process of the pixel driving circuit may include:

[0192] The first phase P1 is called the initialization phase. The signals on the first scan signal line Gate1 and the light-emitting signal line EM are high-level signals, while the signals on the second scan signal line Gate2, the third scan signal line Gate3, and the fourth scan signal line Gate4 are low-level signals. The signal on the first scan signal line Gate1 is high-level, the first transistor T1 and the fourth transistor T4 are turned on, and the first initialization signal on the first initialization signal line INIT1 is written to the first node N1 via the turned-on first transistor T1. This initializes (resets) the first node N1 and clears the pre-stored voltage within it, completing initialization. The signal on the second scan signal line Gate2 is low-level, the second transistor T2 is turned on, and the second initialization signal on the second initialization signal line INIT2 is written to the second node N2 (also the anode of the light-emitting device L) via the turned-on second transistor T2. This initializes (resets) the second node N2 (also the anode of the light-emitting device L) and clears the pre-stored voltage within it, completing initialization. The signal on the third scan signal line Gate3 is low, the third transistor T3 is turned on, and the third initial signal on the third initial signal line INIT3 is written to the third node N3 and the fourth node N4 via the turned-on third transistor T3 and fourth transistor T4. This initializes (resets) the third node N3 and the fourth node N4, clearing the pre-stored voltage within them and completing initialization. At this point, the difference in voltage between the first node N1 and the third node N3 is less than the threshold voltage of the sixth transistor T6, and the sixth transistor T6 is turned on. The signal on the fourth scan signal line Gate is low, the fifth transistor T5 is turned off, the signal on the light-emitting signal line EM is high, and the seventh transistor T7 is turned off. In this stage, because the voltage of the second initial signal on the second initial signal line INIT2 is slightly less than the voltage of the second power line VSS, the light-emitting device L does not emit light.

[0193] In the second phase P2, known as the threshold compensation phase, the signals on the first scan signal line Gate1, the third scan signal line Gate3, and the emission signal line EM are high-level signals, while the signals on the second scan signal line Gate2 and the fourth scan signal line Gate4 are low-level signals. The signal on the first scan signal line Gate1 is high-level, the first transistor T1 and the fourth transistor T4 remain on, and the first initial signal on the first initial signal line INIT1 is written to the first node N1 via the turned-on first transistor T1. This continues initialization (resetting) of the first node N1, clearing the pre-stored voltage within it and completing initialization. The signal on the second scanning signal line Gate2 is a low-level signal, the second transistor T2 is turned on, and the second initial signal on the second initial signal line INIT2 is written to the second node N2 (also the anode of the light-emitting device L) through the turned-on second transistor T2, initializing (resetting) the second node N2 (also the anode of the light-emitting device L), clearing the pre-stored voltage therein, and completing initialization. The second initial signal on the second initial signal line INIT2 charges the fourth node N4 through the turned-on second transistor T2, the second node N2, the sixth transistor T6, the third node N3, and the turned-on fourth transistor T4 until the voltage value of the signal on the fourth node N4 satisfies V4 = Vinit1 - Vth, where Vinit1 is the voltage value of the first initial signal. The signal on the third scanning signal line Gate3 is a high-level signal, the third transistor T3 is turned off, the signal on the fourth scanning signal line Gate is a low-level signal, the fifth transistor T5 is turned off, the signal on the light-emitting signal line EM is a high-level signal, and the seventh transistor T7 is turned off. In this stage, since the voltage value of the second initial signal of the second initial signal line INIT2 is slightly lower than the voltage value of the signal of the second power line VSS, the light emitting device L does not emit light.

[0194] The third phase P3 is called the data writing phase. The signals on the second scan signal line Gate2, the third scan signal line Gate3, the fourth scan signal line Gate4, and the light-emitting signal line EM are high-level signals, while the signal on the first scan signal line Gate1 is low-level. The data signal line Data outputs a data signal. The signal on the fourth scan signal line Gate4 is high-level, and the fifth transistor T5 is turned on. The data signal on the data signal line Data is written to the fourth node N4 through the turned-on fifth transistor T5. At this point, the voltage V4 of the signal on the fourth node changes, satisfying V4 = Vdata, where Vdata is the voltage of the data signal. Under the action of the second capacitor C2, the voltage V1 of the signal on the first node N1 changes, satisfying V1 = Vdata + Vth. The signal on the first scan signal line Gate1 is low-level, and the first and fourth transistors T1 and T4 are turned off. The signal on the second scan signal line Gate2 is high-level, and the second transistor T2 is turned off. The signal on the third scan signal line Gate3 is high-level, and the third transistor T3 is turned off. The signal on the light-emitting signal line EM is high-level, and the seventh transistor T7 is turned off. In this stage, the light emitting device L does not emit light.

[0195] In the fourth phase P4, also known as the light-emitting phase, the signals on the second scan signal line Gate2 and the third scan signal line Gate3 are high-level signals, while the signals on the first scan signal line Gate1, the fourth scan signal line Gate4, and the light-emitting signal line EM are low-level signals. The signal on the light-emitting signal line EM is low-level, and the seventh transistor T7 is turned on. The power signal output from the first power line VDD provides a driving voltage to the second node N2 (also the first electrode of the light-emitting device L) through the turned-on seventh transistor T7, the third node N3, and the turned-on sixth transistor T6, driving the light-emitting device L to emit light. The signal on the first scan signal line Gate1 is low-level, and the first and fourth transistors T1 and T4 are turned off. The signal on the second scan signal line Gate2 is high-level, and the second transistor T2 is turned off. The signal on the third scan signal line Gate3 is high-level, and the third transistor T3 is turned off. The signal on the fourth scan signal line Gate4 is low-level, and the fifth transistor T5 is turned off.

[0196] During the driving process of the pixel driving circuit, the driving current flowing through the sixth transistor T6 (driving transistor) is determined by the voltage difference between its gate electrode and the first electrode. Since the voltage of the first node N1 is Vdata + Vth, the voltage value of the signal of the third node N3 is V3 = Vdd, where Vdd is the voltage value of the signal of the first power line, the driving current of the sixth transistor T6 is: I = K * (Vgs - Vth) 2 =K*(Vdata+Vth-Vdd-Vth) 2=K*(Vdata-Vdd) 2

[0197] Wherein, I is the driving current flowing through the sixth transistor T6, that is, the driving current driving the light emitting device L, K is a constant, Vgs is the voltage difference between the gate electrode and the first electrode of the sixth transistor T6, and Vth is the threshold voltage of the sixth transistor T6.

[0198] It can be seen from the derivation results of the above current formula that in the light-emitting stage, the driving current of the sixth transistor T6 is no longer affected by the threshold voltage of the sixth transistor T6, thereby eliminating the influence of the threshold voltage of the sixth transistor T6 on the driving current, ensuring uniform display brightness of the display product and improving the display effect of the entire display product.

[0199] In the second stage, i.e., the threshold compensation stage, the signal of the fourth node N4 is compensated by the signal of the second initial signal line INIT2, which extends the compensation time of the pixel driving circuit, increases the charging time of the pixel driving circuit, and improves the reliability of the pixel driving circuit.

[0200] An embodiment of the present disclosure further provides a display substrate comprising: a base and a plurality of sub-pixels arranged on the base, at least one sub-pixel comprising: a pixel driving circuit and a light-emitting device driven by the pixel driving circuit.

[0201] The pixel driving circuit is the pixel driving circuit provided by any of the aforementioned embodiments, and its implementation principle and implementation effect are similar, which will not be described in detail here.

[0202] Figure 7 is a schematic diagram of the structure of the display substrate provided in an embodiment of the present disclosure, Figure 8 is a schematic diagram of the structure of the display substrate provided in an embodiment of the present disclosure, Figure 9 is a schematic diagram of a portion of the film layer of the display substrate, and Figure 10 is a schematic diagram of a portion of the film layer of the display substrate. As shown in Figures 7 to 10, the display substrate may include: a substrate, and a driving circuit layer and a light-emitting structure layer sequentially arranged on the substrate, the driving circuit layer including: a plurality of pixel driving circuits, a plurality of light-emitting signal lines EM, a plurality of first initial signal lines INIT1, a plurality of second initial signal lines INIT2, a plurality of third initial signal lines, a plurality of first scan signal lines Gate1, a plurality of second scan signal lines Gate2, a plurality of third scan signal lines Gate3, a plurality of fourth scan signal lines Gate4, a plurality of first power lines VDD, and a plurality of data signal lines Data, and the light-emitting structure layer including: a light-emitting device.

[0203] In an exemplary embodiment, as shown in Figures 7 to 10, any signal line of the emission signal line EM, the first initial signal line INIT1, the second initial signal line INIT2, the third initial signal line, the first scan signal line Gate1, the second scan signal line Gate2, the third scan signal line Gate3, and the fourth scan signal line Gate4 at least partially extends along the first direction D1, and any signal line of the first power line VDD and the data signal line Data at least partially extends along the second direction D2, and the first direction D1 and the second direction D2 intersect.

[0204] In an exemplary embodiment, the display substrate may further include an encapsulation structure layer disposed on a side of the light emitting structure layer away from the substrate. The display substrate may include other film layers, such as a touch structure layer, etc., which are not limited in this disclosure.

[0205] In an exemplary embodiment, on a plane parallel to the display substrate, the display substrate may include: a plurality of sub-pixels, at least one sub-pixel may include: a pixel driving circuit and a light-emitting device, the pixel driving circuit being configured to output a corresponding current to the connected light-emitting device so that the light-emitting device emits light of corresponding brightness.

[0206] In an exemplary embodiment, the plurality of sub-pixels may include a plurality of pixel rows and a plurality of pixel columns. The plurality of sub-pixels arranged in sequence along the horizontal direction may be referred to as pixel rows, and the plurality of sub-pixels arranged in sequence along the vertical direction may be referred to as pixel columns. The plurality of pixel rows and the plurality of pixel columns constitute an array-arranged pixel array.

[0207] In an exemplary embodiment, a plurality of sub-pixels constitute one pixel unit, and the pixel unit may include a first sub-pixel, a second sub-pixel, and a third sub-pixel, or a first sub-pixel, a second sub-pixel, a third sub-pixel, and a fourth sub-pixel.

[0208] In an exemplary embodiment, when the pixel unit includes a first sub-pixel, a second sub-pixel, and a third sub-pixel, the first sub-pixel can be a red sub-pixel (R) that emits red light, the second sub-pixel can be a blue sub-pixel (B) that emits blue light, and the third sub-pixel P3 can be a green sub-pixel (G) that emits green light. The shapes of the three sub-pixels can be triangles, rectangles, diamonds, pentagons, or hexagons, etc., which are not limited in this disclosure. In the direction of the pixel rows, the first sub-pixel, the second sub-pixel, and the third sub-pixel can be arranged in sequence in an aligned manner, and in the direction of the pixel columns, the first sub-pixel, the second sub-pixel, and the third sub-pixel can be arranged in sequence in a staggered manner to form a herringbone layout of the sub-pixels. For example, the first sub-pixel in the odd row can be located between the second and third sub-pixels adjacent to each other in the even row, or the first sub-pixel in the even row can be located between the second and third sub-pixels adjacent to each other in the odd row. For another example, the second subpixel in an odd row may be located between the adjacent first and third subpixels in an even row, or the second subpixel in an even row may be located between the adjacent first and third subpixels in an odd row. For another example, the third subpixel in an odd row may be located between the adjacent first and second subpixels in an even row, or the third subpixel in an even row may be located between the adjacent first and second subpixels in an odd row.

[0209] In an exemplary embodiment, when the pixel unit includes a first sub-pixel, a second sub-pixel, a third sub-pixel, and a fourth sub-pixel, the first sub-pixel may be a red sub-pixel (R) that emits red light, the second sub-pixel may be a blue sub-pixel (B) that emits blue light, and the third sub-pixel and the fourth sub-pixel may be green sub-pixels (G) that emit green light. The shapes of the three sub-pixels may be triangular, rectangular, diamond, pentagonal, or hexagonal, etc., which is not limited in the present disclosure. In an exemplary embodiment, the four sub-pixels may be arranged in a horizontal parallel, vertical parallel, or square manner, which is not limited in the present disclosure. The four sub-pixels may be arranged in a square manner to form a GGRB pixel arrangement. In another exemplary embodiment, the four sub-pixels may be arranged in a diamond manner to form an RGGB pixel arrangement.

[0210] In an exemplary embodiment, the encapsulation structure layer may include a stacked first encapsulation layer, a second encapsulation layer, and a third encapsulation layer. The first encapsulation layer and the third encapsulation layer may be made of inorganic materials, the second encapsulation layer may be made of organic materials, and the second encapsulation layer is arranged between the first encapsulation layer and the third encapsulation layer to ensure that external water vapor cannot enter the light-emitting structure layer.

[0211] In an exemplary embodiment, the substrate can be a rigid substrate or a flexible substrate. The rigid substrate can be, but is not limited to, one or more of glass and conductive foil; the flexible substrate can be, but is not limited to, one or more of polyethylene terephthalate, polyethylene terephthalate, polyetheretherketone, polystyrene, polycarbonate, polyarylate, polyarylate, polyimide, polyvinyl chloride, polyethylene, and textile fibers. In an exemplary embodiment, the light-emitting structure layer includes an anode layer, a pixel definition layer, an organic structure layer, and a cathode layer sequentially stacked on the substrate. The anode layer includes an anode, the organic structure layer includes an organic light-emitting layer, and the cathode layer includes a cathode.

[0212] In exemplary embodiments, as shown in Figures 7 to 10 , the driver circuit layer further includes: a plurality of power connection lines VCL extending at least partially along a first direction; and at least one power connection line VCL connected to the pixel driver circuit and at least one first power line VDD, respectively. In the present disclosure, the plurality of power connection lines VCL extending along the first direction and the plurality of first power lines extending along the second direction form a mesh structure, ensuring that each pixel driver circuit receives a consistent power signal, thereby improving display uniformity across the display substrate.

[0213] In an exemplary embodiment, the driving circuit layer may further include a first connecting electrode. The first connecting electrode is respectively connected to the pixel driving circuit, the power connection line VCL, and the first power line VDD; the orthographic projection of the first connecting electrode on the substrate at least partially overlaps with the orthographic projections of the power connection line VCL and the first power line VDD on the substrate.

[0214] In an exemplary embodiment, as shown in FIG. 7 and FIG. 8 , the first initial signal line INIT1 and the second initial signal line INIT2 are the same signal line.

[0215] In an exemplary embodiment, as shown in Figures 7 and 8, the driving circuit layer may further include: a plurality of initial connection lines ICL extending at least partially along the second direction D2; and at least one initial connection line ICL connected to the pixel driving circuit and at least one first initial signal line INIT1, respectively. In the present disclosure, the plurality of first initial signal lines INIT1 extending along the first direction and the plurality of initial connection lines ICL extending along the second direction form a mesh structure, which can reduce the impact of differences in initial signals of the first initial signal lines connected to different pixel driving circuits due to differences in resistance of the first initial signal lines on low grayscales, thereby improving display uniformity of the display substrate.

[0216] In an exemplary embodiment, as shown in FIG. 7 and FIG. 8 , the orthographic projection of the initial connection line ICL on the substrate may be located between the orthographic projections of the data signal lines Data connected to two adjacent columns of sub-pixels connected to the initial connection line ICL on the substrate.

[0217] In an exemplary embodiment, the first scan signal line Gate1 includes a first sub-signal line and a second sub-signal line electrically connected to each other. For example, the first sub-signal line and the second sub-signal line may be disposed in different layers and may be electrically connected at the periphery of the display area, and an orthographic projection of the first sub-signal line on the substrate at least partially overlaps with an orthographic projection of the second sub-signal line on the substrate.

[0218] In an exemplary embodiment, the fourth scan signal line Gate4 includes: a third sub-signal line and a fourth sub-signal line that are arranged in different layers and are interconnected. Exemplarily, the third sub-signal line and the fourth sub-signal line can be arranged in different layers and can be electrically connected at the periphery of the display area, and the orthographic projection of the third sub-signal line on the substrate at least partially overlaps with the orthographic projection of the fourth sub-signal line on the substrate.

[0219] In an exemplary embodiment, the pixel driving circuit includes: first to seventh transistors and a first capacitor and a second capacitor, the first capacitor and the second capacitor respectively include: a first electrode plate and a second electrode plate, and the driving circuit layer includes a first semiconductor layer, a first conductive layer, a second conductive layer, a second semiconductor layer, a third conductive layer, a fourth conductive layer, and a fifth conductive layer sequentially provided on a substrate;

[0220] The first semiconductor layer includes at least: an active layer of a second transistor, an active layer of a third transistor, an active layer of a sixth transistor, and an active layer of a seventh transistor located in at least one sub-pixel;

[0221] The first conductive layer at least includes: a light emitting signal line EM, a second scanning signal line Gate2, a third scanning signal line Gate3, and a first plate of a first capacitor located in at least one sub-pixel, a first plate of a second capacitor, a gate electrode of a second transistor, a gate electrode of a third transistor, a control electrode of a sixth transistor, and a gate electrode of a seventh transistor;

[0222] The second conductive layer includes at least: a first sub-signal line of the first scanning signal line Gate1, a third sub-signal line of the fourth scanning signal line Gate4, and a second plate of a first capacitor and a second plate of a second capacitor located in at least one sub-pixel;

[0223] The second semiconductor layer includes at least an active layer of a first transistor, an active layer of a fourth transistor, and an active layer of a fifth transistor located in at least one sub-pixel.

[0224] The third conductive layer at least includes: a second sub-signal line of the first scan signal line Gate1, a fourth sub-signal line of the fourth scan signal line Gate4, a power connection line VCL, a first initial signal line INIT1, a second initial signal line INIT2 and a third initial signal line;

[0225] The fourth conductive layer at least includes: an initial connection line ICL, a first connection electrode located at at least one sub-pixel, and first electrodes and second electrodes of the first to seventh transistors;

[0226] The fifth conductive layer at least includes: a first power line VDD and a data signal line Data.

[0227] The signal line for power signal transmission in the present disclosure includes a power connection line located on the third conductive layer and a first power line located on the fifth conductive layer, the signal line for data signal transmission includes a data signal line on the fifth conductive layer, the second plate of the first capacitor and the second plate of the second capacitor are located on the second conductive layer, and the signal line for power signal transmission includes a power connection line located on the third conductive layer, which can shield the parasitic capacitance between the second plate of the first capacitor located on the second conductive layer and the second plate of the second capacitor and the data signal line on the fifth conductive layer (which is also the parasitic capacitance between the signal of the gate electrode of the sixth transistor and the data signal), thereby avoiding crosstalk between signals and improving the reliability of the display substrate.

[0228] In an exemplary embodiment, Figure 11 is a schematic diagram of the light-shielding layer pattern of the display substrate provided in Figure 7, and Figure 12 is a schematic diagram of the light-shielding layer pattern of the display substrate provided in Figure 8. As shown in Figures 11 and 12, the driving circuit layer may further include: a light-shielding layer disposed between the substrate and the first semiconductor layer; the light-shielding layer includes at least: a light-shielding structure located in at least one sub-pixel, with the light-shielding structures of adjacent sub-pixels interconnected.

[0229] In an exemplary embodiment, the orthographic projection of the light-shielding structure on the substrate may at least partially overlap with the orthographic projection of the gate electrode of the sixth transistor on the substrate. Exemplarily, the orthographic projection of the light-shielding structure on the substrate may cover the orthographic projection of the gate electrode of the sixth transistor on the substrate. The orthographic projection of the light-shielding structure on the substrate covering the orthographic projection of the gate electrode of the sixth transistor (also a drive transistor) on the substrate may increase the service life of the drive transistor and improve the reliability of the display substrate.

[0230] In an exemplary embodiment, as shown in Figure 11, the light-shielding structure may include: a first light-shielding portion 11, a second light-shielding portion 12, a third light-shielding portion 13 and a fourth light-shielding portion 14; wherein, the orthographic projection of the first light-shielding portion 11 on the substrate at least partially overlaps with the orthographic projection of the active layer of the sixth transistor on the substrate, the orthographic projection of the second light-shielding portion 12 on the substrate at least partially overlaps with the orthographic projection of the active layer of the seventh transistor on the substrate, the orthographic projection of the third light-shielding portion 13 on the substrate at least partially overlaps with the orthographic projection of the active layer of the third transistor on the substrate, and the orthographic projection of the fourth light-shielding portion 14 on the substrate at least partially overlaps with the orthographic projection of the active layer of the second transistor on the substrate.

[0231] In an exemplary embodiment, as shown in Figure 12, the light-shielding structure may include: a light-shielding portion 20, a first light-shielding connection portion 21, a second light-shielding connection portion 22, a third light-shielding connection portion 23 and a fourth light-shielding connection portion 24; wherein, the orthographic projection of the light-shielding portion 20 on the substrate at least partially overlaps with the orthographic projection of the active layer of the sixth transistor on the substrate, and the orthographic projection of any one of the first light-shielding connection portion 21, the second light-shielding connection portion 22, the third light-shielding connection portion 23 and the fourth light-shielding connection portion 24 on the substrate does not overlap with the orthographic projection of any one of the active layer of the second transistor, the active layer of the third transistor and the active layer of the seventh transistor on the substrate.

[0232] In an exemplary embodiment, the light-emitting signal line EM connected to the sub-pixel is located on a side where the first plate of the second capacitor of the sub-pixel is away from the first plate of the first capacitor of the sub-pixel, the second scanning signal line Gate2 connected to the sub-pixel is located on a side where the first plate of the first capacitor of the sub-pixel is away from the first plate of the second capacitor of the sub-pixel, and the third scanning signal line Gate3 connected to the sub-pixel is located on a side where the second scanning signal line Gate2 connected to the sub-pixel is away from the first plate of the first capacitor of the sub-pixel.

[0233] In an exemplary embodiment, as shown in FIG9 , the second plate C12 of the first capacitor and the second plate C22 of the second capacitor are an integral structure connected to each other and are provided with a first via V1 and a second via V2 , wherein the first via exposes the first plate of the first capacitor and the second via exposes the second plate of the second capacitor.

[0234] 9 , the third sub-signal line of the fourth scan signal line Gate4 is located on a side of the first sub-signal line of the first scan signal line Gate1 away from the integrated structure of the second plate C12 of the first capacitor and the second plate C22 of the second capacitor.

[0235] In an exemplary embodiment, as shown in Figures 7 and 8, the orthographic projection of the first sub-signal line of the first scanning signal line Gate1 connected to the sub-pixel on the substrate is located between the orthographic projection of the light-emitting signal line EM connected to the sub-pixel on the substrate and the orthographic projection of the first plate of the second capacitor of the sub-pixel on the substrate, and the orthographic projection of the third sub-signal line of the fourth scanning signal line Gate4 connected to the sub-pixel on the substrate is located on a side of the orthographic projection of the light-emitting signal line EM connected to the sub-pixel on the substrate away from the orthographic projection of the first plate of the second capacitor of the sub-pixel on the substrate.

[0236] In an exemplary embodiment, as shown in Figures 7 and 8, the second sub-signal line of the first scan signal line Gate1 connected to the sub-pixel is located on a side of the fourth sub-signal line of the fourth scan signal line Gate4 connected to the sub-pixel, the power connection line VCL connected to the sub-pixel is located on a side of the second sub-signal line of the first scan signal line Gate1 connected to the sub-pixel away from the fourth sub-signal line of the fourth scan signal line Gate4 connected to the sub-pixel, the first initial signal line INIT1 connected to the sub-pixel is located on a side of the power connection line VCL connected to the sub-pixel away from the second sub-signal line of the first scan signal line Gate1 connected to the sub-pixel, and the third initial signal line connected to the sub-pixel is located on a side of the first initial signal line INIT1 connected to the sub-pixel away from the power connection line VCL connected to the sub-pixel.

[0237] In an exemplary embodiment, as shown in Figures 7 and 8, the orthographic projection of the fourth sub-signal line of the fourth scanning signal line Gate4 connected to the sub-pixel on the substrate is located on a side of the orthographic projection of the light-emitting signal line EM connected to the sub-pixel on the substrate away from the orthographic projection of the first plate of the second capacitor of the sub-pixel on the substrate.

[0238] In an exemplary embodiment, as shown in Figures 7 and 8, the orthographic projection of the second sub-signal line of the first scanning signal line Gate1 connected to the sub-pixel on the substrate is located between the orthographic projection of the light-emitting signal line EM connected to the sub-pixel on the substrate and the orthographic projection of the first plate of the second capacitor of the sub-pixel on the substrate.

[0239] In an exemplary embodiment, as shown in Figures 7 and 8, the orthographic projection of the power connection line VCL connected to the sub-pixel on the substrate at least partially overlaps with the orthographic projection of the integrated structure of the second plate of the first capacitor and the second plate of the second capacitor of the sub-pixel on the substrate, and is located between the orthographic projection of the first sub-signal line of the first scan signal line Gate1 on the substrate and the orthographic projection of the second scan signal line Gate2 on the substrate.

[0240] In an exemplary embodiment, as shown in Figures 7 and 8, the orthographic projection of the first initial signal line INIT1 connected to the sub-pixel on the substrate at least partially overlaps with the orthographic projection of the second scanning signal line Gate2 connected to the sub-pixel on the substrate, and is located between the orthographic projection of the first plate of the first capacitor of the sub-pixel on the substrate and the orthographic projection of the third scanning signal line Gate3 connected to the sub-pixel on the substrate.

[0241] In an exemplary embodiment, as shown in Figures 7 and 8, the orthographic projection of the third initial signal line INIT3 connected to the sub-pixel on the substrate at least partially overlaps with the orthographic projection of the third scanning signal line Gate3 connected to the sub-pixel on the substrate, and is located on a side of the orthographic projection of the second scanning signal line Gate2 connected to the sub-pixel on the substrate away from the orthographic projection of the first plate of the first capacitor of the sub-pixel on the substrate.

[0242] In an exemplary embodiment, the power connection line VCL includes a main signal line, a first protrusion, a second protrusion, and a third protrusion. The main signal line extends along a first direction. The first protrusion is located on a side of the main signal line that is closer to the second sub-signal line of the first scan signal line Gate1. The second and third protrusions are located on a side of the main signal line that is farther from the second sub-signal line of the first scan signal line Gate1. The second and third protrusions are arranged along the first direction. The orthographic projections of the second and third protrusions on the substrate at least partially overlap with the orthographic projections of the integrated structure of the second plate of the first capacitor and the second plate of the second capacitor on the substrate.

[0243] In an exemplary embodiment, an orthographic projection of the first via hole on the substrate is located between an orthographic projection of the second protrusion on the substrate and an orthographic projection of the third protrusion on the substrate.

[0244] In an exemplary embodiment, as shown in Figures 7, 8 and 10, the orthographic projection of the first connection electrode VL1 on the substrate at least partially overlaps with the orthographic projections of the signal main line, the second protrusion and the third protrusion of the power connection line VCL on the substrate, and does not overlap with the orthographic projection of the first protrusion of the power connection line VCL on the substrate.

[0245] In an exemplary embodiment, as shown in Figures 7 and 8, the orthographic projection of the first power line VDD on the substrate at least partially overlaps with the orthographic projection of the second plate of the first capacitor and the integrated structure of the second plate of the second capacitor, the first connection electrode, the signal main body portion of the power connection line VCL, and the second protrusion on the substrate.

[0246] In an exemplary embodiment, as shown in FIG. 7 and FIG. 8 , the orthographic projection of the sub-pixel connected first power line VDD on the substrate is located on a side of the sub-pixel connected data signal line Data away from the sub-pixel connected initial connection line ICL.

[0247] The following is an illustrative explanation using the preparation process of a display substrate. The "patterning process" mentioned in the present disclosure includes processes such as coating photoresist, mask exposure, development, etching, and stripping photoresist for metal materials, inorganic materials, or transparent conductive materials, and includes processes such as coating organic materials, mask exposure, and development for organic materials. Deposition can be performed by any one or more of sputtering, evaporation, and chemical vapor deposition; coating can be performed by any one or more of spraying, spin coating, and inkjet printing; and etching can be performed by any one or more of dry etching and wet etching, which are not limited in the present disclosure. "Thin film" refers to a thin film made by deposition, coating, or other processes on a substrate using a certain material. If the "thin film" does not require a patterning process during the entire production process, the "thin film" can also be called a "layer." If the "thin film" requires a patterning process during the entire production process, it is called a "thin film" before the patterning process and a "layer" after the patterning process. The "layer" after the patterning process contains at least one "pattern." As used in this disclosure, "A and B are provided in the same layer" means that A and B are formed simultaneously through the same patterning process, and the "thickness" of the film layer refers to the dimension of the film layer in a direction perpendicular to the display substrate. In exemplary embodiments of this disclosure, "the orthographic projection of B is within the range of the orthographic projection of A" or "the orthographic projection of A contains the orthographic projection of B" means that the boundary of the orthographic projection of B falls within the boundary of the orthographic projection of A, or that the boundary of the orthographic projection of A overlaps the boundary of the orthographic projection of B.

[0248] The following describes the manufacturing process of the display substrate provided in FIG7 and FIG8 using a two-row and four-column pixel driving circuit. The manufacturing process of the display substrate provided by an exemplary embodiment may include:

[0249] (1) forming a light-shielding layer pattern on a substrate, including: sequentially depositing a first insulating film and a light-shielding film on the substrate, patterning the light-shielding film through a patterning process, and forming a first insulating layer covering the substrate and a light-shielding layer pattern located on the first insulating layer, as shown in FIG11 and FIG12.

[0250] In an exemplary embodiment, as shown in FIG. 11 and FIG. 12 , the light shielding layer may include at least a light shielding structure located in at least one sub-pixel.

[0251] In an exemplary embodiment, as shown in Figures 11 and 12, all the light shielding structures are interconnected as an integrated structure. The light shielding structures of adjacent sub-pixels in the same row are symmetrically arranged with respect to a virtual line extending along the second direction D2, and the light shielding structures of all sub-pixels in the same column are identical.

[0252] In an exemplary embodiment, as shown in FIG11 , the light shielding structure in the display substrate provided in FIG7 includes a first light shielding portion 11, a second light shielding portion 12, a third light shielding portion 13, and a fourth light shielding portion 14. The first light shielding portion 11, the second light shielding portion 12, the third light shielding portion 13, and the fourth light shielding portion 14 are interconnected and integrated.

[0253] In an exemplary embodiment, as shown in FIG11 , the second light-shielding portion 12 and the third light-shielding portion 13 are arranged along the second direction D2, and the third light-shielding portion 13 and the fourth light-shielding portion 14 are arranged along the first direction D1. In the second direction D2, the second light-shielding portion 12 of a sub-pixel can be located on the side of the first light-shielding portion 11 closer to the previous row of sub-pixels, and the third light-shielding portion 13 and the fourth light-shielding portion 14 of the sub-pixel can be located on the side of the first light-shielding portion 11 closer to the next row of sub-pixels. In the first direction D1, the fourth light-shielding portion 14 of a sub-pixel can be located on the side of the third light-shielding portion 13 closer to the next column of sub-pixels or on the side of the third light-shielding portion 13 closer to the previous column of sub-pixels.

[0254] 11 , the first light shielding portion 11 may include a light shielding main body portion 11A and a light shielding connecting portion 11B. The light shielding main body portion 11A and the light shielding connecting portion 11B are connected to each other as an integral structure.

[0255] In an exemplary embodiment, as shown in FIG11 , the light-shielding main portion 11A and the light-shielding connecting portion 11B are arranged along a first direction, with the light-shielding main portion 11A of a sub-pixel being located on the side of the light-shielding connecting portion 11B closer to the next column of sub-pixels or on the side of the light-shielding connecting portion 11B closer to the previous column of sub-pixels. When the fourth light-shielding portion 14 is located on the side of the third light-shielding portion 13 closer to the next column of sub-pixels, the light-shielding main portion 11A is located on the side of the light-shielding connecting portion 11B closer to the next column of sub-pixels. When the fourth light-shielding portion 14 is located on the side of the third light-shielding portion 13 closer to the previous column of sub-pixels, the light-shielding main portion 11A is located on the side of the light-shielding connecting portion 11B closer to the previous column of sub-pixels.

[0256] 11 , the light shielding main body portion 11A may be rectangular, and the corners of the rectangle may be chamfered. The light shielding connection portion 11B may be stripe-shaped extending along the first direction D1.

[0257] In an exemplary embodiment, as shown in FIG. 11 , the second light shielding portion 12 , the third light shielding portion 13 , and the fourth light shielding portion 14 may be in the shape of stripes extending along the second direction D2 .

[0258] In an exemplary embodiment, as shown in FIG11 , the second light-shielding portion of a sub-pixel is connected to the third light-shielding portion of a sub-pixel located in the previous row in the same column, and the third light-shielding portion of the sub-pixel is connected to the second light-shielding portion of a sub-pixel located in the next row in the same column. The light-shielding connecting portion of the first light-shielding portion of the sub-pixel is connected to the light-shielding connecting portion of the first light-shielding portion of one adjacent sub-pixel located in the same row, and the fourth light-shielding portion of the sub-pixel is connected to the fourth light-shielding portion of another adjacent sub-pixel located in the same row.

[0259] In an exemplary embodiment, as shown in FIG12 , the light shielding structure of the display substrate provided in FIG8 may include a light shielding portion 20, a first light shielding connection portion 21, a second light shielding connection portion 22, a third light shielding connection portion 23, and a fourth light shielding connection portion 24. The light shielding portion 20, the first light shielding connection portion 21, the second light shielding connection portion 22, the third light shielding connection portion 23, and the fourth light shielding connection portion 24 are an integrated structure connected to each other.

[0260] In an exemplary embodiment, as shown in FIG12 , the first light-shielding connection portion 21 and the second light-shielding connection portion 22 are arranged along the second direction D2. In the second direction D2, the first light-shielding connection portion 21 of a subpixel can be located on the side of the light-shielding portion 20 closer to the previous row of subpixels, and the second light-shielding connection portion 22 of the subpixel can be located on the side of the light-shielding portion 20 closer to the next row of subpixels. In the first direction D1, the third light-shielding connection portion 23 and the fourth light-shielding connection portion 24 of the subpixel are located on different sides of the light-shielding portion 20. When the third light-shielding connection portion 23 of a subpixel can be located on the side of the light-shielding portion 20 closer to the previous column of subpixels, the fourth light-shielding connection portion 24 of the subpixel can be located on the side of the light-shielding portion 20 closer to the next column of subpixels. When the third light-shielding connection portion 23 of a subpixel can be located on the side of the light-shielding portion 20 closer to the next column of subpixels, the fourth light-shielding connection portion 24 of the subpixel can be located on the side of the light-shielding portion 20 closer to the previous column of subpixels.

[0261] In an exemplary embodiment, as shown in FIG. 12 , the light shielding portion 20 may be rectangular in shape, and corners of the rectangle may be chamfered.

[0262] 12 , the second light-shielding connection portion 22 of the first light-shielding connection portion 21 may be in the shape of a strip extending along the second direction D2 , and the third light-shielding connection portion 23 and the fourth light-shielding connection portion 24 may be in the shape of a strip extending along the first direction D1 .

[0263] In an exemplary embodiment, as shown in FIG12 , the first light-shielding connection portion of a sub-pixel is connected to the second light-shielding connection portion of a sub-pixel located in the previous row in the same column, the second light-shielding connection portion of the sub-pixel is connected to the first light-shielding connection portion of a sub-pixel located in the next row in the same column, the third light-shielding connection portion of the sub-pixel is connected to the third light-shielding connection portion of one adjacent sub-pixel located in the same row, and the fourth light-shielding connection portion of the sub-pixel is connected to the fourth light-shielding connection portion of another adjacent sub-pixel located in the same row.

[0264] (2) Forming a first semiconductor layer pattern. In an exemplary embodiment, forming the first semiconductor layer pattern may include: sequentially depositing a second insulating film and a first semiconductor film on a substrate, patterning the first semiconductor film through a patterning process to form a second insulating layer covering the light-shielding layer and a first semiconductor layer pattern located on the second insulating layer, as shown in Figures 13 to 15 , where Figure 13 is a schematic diagram of the first semiconductor layer pattern of the display substrate provided in Figures 7 and 8 , Figure 14 is a schematic diagram of the display substrate provided in Figure 7 after the first semiconductor layer pattern is formed, and Figure 15 is a schematic diagram of the display substrate provided in Figure 8 after the first semiconductor layer pattern is formed.

[0265] In an exemplary embodiment, as shown in Figures 13 to 15, the first semiconductor layer pattern may include at least: an active layer T21 of a second transistor located in at least one sub-pixel, an active layer T31 of a third transistor, an active layer T61 of a sixth transistor, and an active layer T71 of a seventh transistor.

[0266] In an exemplary embodiment, as shown in FIG14 , in the display substrate provided in FIG7 , the orthographic projection of the first light-shielding portion on the substrate at least partially overlaps with the orthographic projection of the active layer T61 of the sixth transistor on the substrate. The orthographic projection of the second light-shielding portion on the substrate at least partially overlaps with the orthographic projection of the active layer T71 of the seventh transistor on the substrate. The orthographic projection of the third light-shielding portion on the substrate at least partially overlaps with the orthographic projection of the active layer T31 of the third transistor on the substrate. The orthographic projection of the fourth light-shielding portion on the substrate at least partially overlaps with the orthographic projection of the active layer T21 of the second transistor on the substrate.

[0267] In an exemplary embodiment, as shown in FIG15 , in the display substrate provided in FIG8 , an orthographic projection of the light-shielding portion on the substrate at least partially overlaps with an orthographic projection of the active layer T61 of the sixth transistor on the substrate. The orthographic projections of the first light-shielding connection portion, the second light-shielding connection portion, the third light-shielding connection portion, and the fourth light-shielding connection portion on the substrate do not overlap with an orthographic projection of any of the active layer T21 of the second transistor, the active layer T31 of the third transistor, and the active layer T71 of the seventh transistor on the substrate.

[0268] In an exemplary embodiment, in an exemplary embodiment, as shown in Figures 13 to 15, any one of the active layer T21 of the second transistor, the active layer T31 of the third transistor, the active layer T61 of the sixth transistor, and the active layer T71 of the seventh transistor of adjacent sub-pixels located in the same row is symmetrically arranged with respect to a virtual straight line extending along the second direction D2, and any one of the active layer T21 of the second transistor, the active layer T31 of the third transistor, the active layer T61 of the sixth transistor, and the active layer T71 of the seventh transistor of all sub-pixels located in the same column is the same.

[0269] 13 to 15 , for the same sub-pixel, the active layer T21 of the second transistor, the active layer T61 of the sixth transistor, and the active layer T71 of the seventh transistor may be connected to each other as an integral structure, while the active layer T31 of the third transistor may be provided separately.

[0270] In an exemplary embodiment, as shown in Figures 13 to 15, the active layer T31 of the third transistor of the subpixel is interconnected with the active layer T31 of the third transistor of one of the adjacent subpixels located in the same row, the active layer T71 of the seventh transistor of the subpixel is interconnected with the active layer T71 of the seventh transistor of one of the adjacent subpixels located in the same row, and the active layer T21 of the second transistor of the subpixel is interconnected with the active layer T21 of the second transistor of another adjacent subpixel located in the same row.

[0271] In an exemplary embodiment, as shown in Figures 13 to 15, the active layer T31 of the third transistor and the active layer T71 of the seventh transistor are arranged along the second direction D2. In the first direction D1, the active layer T21 of the second transistor and the active layer T71 of the seventh transistor may be located on the same side of the active layer T61 of the sixth transistor of the subpixel, and the active layer T61 of the sixth transistor may be located on the other side of the active layer T61 of the sixth transistor of the subpixel. In the second direction D2, the active layer T71 of the seventh transistor may be located on a side of the active layer T61 of the sixth transistor of the subpixel that is closer to the subpixels in the previous row, and the active layer T21 of the second transistor and the active layer T31 of the third transistor may be located on a side of the active layer T61 of the sixth transistor of the subpixel that is closer to the subpixels in the next row.

[0272] 13 to 15 , the active layers T21, T31, and T71 of the second, third, and seventh transistors may be shaped like an I. The active layer T61 of the sixth transistor may be shaped like an Ω.

[0273] In exemplary embodiments, as shown in Figures 13 to 15, the active layer of the transistor may include a first region, a second region, and a channel region located between the first and second regions. In exemplary embodiments, for a subpixel, the second region T21-2 of the active layer T21 of the second transistor may serve as the second region T61-2 of the active layer T61 of the sixth transistor, and the first region T61-1 of the active layer T61 of the sixth transistor may serve as the second region T71-2 of the active layer T71 of the seventh transistor. The first region T31-1 and the second region T31-2 of the active layer T31 of the third transistor and the first region T71-1 of the active layer T71 of the seventh transistor may be provided separately. The first region T71-1 of the active layer T71 of the seventh transistor of the sub-pixel is the same region as the first region T71-1 of the active layer T71 of the seventh transistor of one of the adjacent sub-pixels located in the same row, and the first region T21-1 of the active layer T21 of the second transistor of the sub-pixel is the same region as the first region T21-1 of the active layer T21 of the second transistor of another adjacent sub-pixel located in the same row.

[0274] (3) Forming a first conductive layer pattern. In an exemplary embodiment, forming the first conductive layer pattern may include: depositing a third insulating film and a first conductive film in sequence on the substrate on which the aforementioned pattern is formed, patterning the first conductive film through a patterning process to form a third insulating layer covering the first semiconductor layer pattern and a first conductive layer pattern located on the third insulating layer, as shown in Figures 16 to 18, Figure 16 is a schematic diagram of the first conductive layer pattern of the display substrate provided in Figures 7 and 8, Figure 17 is a schematic diagram of the display substrate provided in Figure 7 after the first conductive layer pattern is formed, and Figure 18 is a schematic diagram of the display substrate provided in Figure 8 after the first conductive layer pattern is formed. In an exemplary embodiment, the first conductive layer may be referred to as a first gate metal (Gate1) layer.

[0275] In an exemplary embodiment, as shown in Figures 16 to 18, the first conductive layer pattern may include at least: a first plate C11 of a first capacitor located in at least one sub-pixel, a first plate C21 of a second capacitor, a gate electrode T22 of a second transistor, a gate electrode T32 of a third transistor, a control electrode T62 of a sixth transistor, and a gate electrode T72 of a seventh transistor, and a light emitting signal line EM, a second scanning signal line Gate2, and a third scanning signal line Gate3 extending at least partially along the first direction D1.

[0276] In an exemplary embodiment, as shown in Figures 16 to 18, any one of the first plates of the first capacitor and the first plates of the second capacitor of adjacent sub-pixels located in the same row is symmetrically arranged with respect to a virtual straight line extending along the second direction D2, and any one of the first plates of the first capacitor and the first plates of the second capacitor of all sub-pixels located in the same column is the same.

[0277] In an exemplary embodiment, as shown in Figures 16 to 18, the first plate C11 of the first capacitor and the first plate C21 of the second capacitor of the sub-pixel are arranged along the second direction D2, and the first plate C21 of the second capacitor of the sub-pixel can be located on a side of the first plate C11 of the first capacitor close to the sub-pixels in the previous row.

[0278] In an exemplary embodiment, as shown in Figures 16 to 18, the shape of the first plate C11 of the first capacitor can be rectangular, and the corners of the rectangle can be chamfered, and the orthographic projection of the first plate C11 of the first capacitor on the substrate at least partially overlaps with the orthographic projection of the active layer of the sixth transistor on the substrate.

[0279] In an exemplary embodiment, as shown in Figures 16 to 18 , the first plate C21 of the second capacitor can be rectangular, with chamfered corners. The orthographic projection of the first plate C21 of the second capacitor on the substrate at least partially overlaps the orthographic projection of the active layer of the sixth transistor on the substrate. In an exemplary embodiment, the first plate C21 of the second capacitor can also serve as the control electrode T62 of the sixth transistor.

[0280] In an exemplary embodiment, the area of ​​the first plate C21 of the second capacitor may be greater than the area of ​​the first plate C11 of the first capacitor.

[0281] In an exemplary embodiment, as shown in Figures 16 to 18 , the second scan signal line Gate2 may be linearly shaped extending along the first direction D1. The second scan signal line Gate2 connected to the subpixel may be located on a side of the subpixel's first capacitor's first plate C11 that is away from the subpixel's second capacitor's first plate C21 (which also serves as the gate electrode T62 of the sixth transistor). The region where the second scan signal line Gate2 overlaps the active layer of the second transistor serves as the gate electrode T22 of the second transistor.

[0282] In an exemplary embodiment, as shown in Figures 16 to 18 , the third scan signal line Gate3 may be linearly shaped, extending along a first direction D1. The third scan signal line Gate3 connected to the subpixel may be located on a side of the second scan signal line Gate2 connected to the subpixel that is farther from the first plate C11 of the first capacitor of the subpixel. The region where the third scan signal line Gate3 overlaps with the active layer of the third transistor serves as the gate electrode T32 of the third transistor.

[0283] In an exemplary embodiment, as shown in Figures 16 to 18 , the emission signal line EM may be linear, extending along a first direction D1. The emission signal line EM connected to the subpixel may be located on a side of the first plate C21 of the subpixel's second capacitor (also the gate electrode T62 of the sixth transistor) away from the first plate C11 of the subpixel's first capacitor. The area where the emission signal line EM overlaps the active layer of the seventh transistor serves as the gate electrode T72 of the seventh transistor.

[0284] In an exemplary embodiment, the second scanning signal line Gate2, the third scanning signal line Gate3 and the light-emitting signal line EM can be designed with equal width, or can be designed with unequal width, can be straight lines, or can be broken lines, which not only facilitates the layout of the pixel structure, but also reduces the parasitic capacitance between the signal lines. The present disclosure does not limit this.

[0285] In an exemplary embodiment, after forming the first conductive layer pattern, the first conductive layer can be used as a shield to perform conductorization on the first semiconductor layer. The first semiconductor layer in the area shielded by the first conductive layer forms the channel region of the second transistor, the third transistor, the sixth transistor, and the seventh transistor T7, and the first semiconductor layer in the area not shielded by the first conductive layer is conductorized, that is, the first region and the second region of any one of the active layers of the first transistor, the second transistor, the sixth transistor, and the seventh transistor are both conductorized.

[0286] In an exemplary embodiment, the gate electrode T22 of the second transistor is arranged across the active layer of the second transistor, the gate electrode T32 of the third transistor is arranged across the active layer of the third transistor, the gate electrode T62 of the sixth transistor is arranged across the active layer of the sixth transistor, and the gate electrode T72 of the seventh transistor is arranged across the active layer of the seventh transistor. That is, the extension direction of the gate electrode of at least one transistor is perpendicular to the extension direction of the active layer.

[0287] (4) forming a second conductive layer pattern, including: sequentially depositing a fourth insulating film and a second conductive film on the substrate on which the aforementioned pattern is formed, patterning the fourth insulating film and the second conductive film through a patterning process to form a fourth insulating layer and a second conductive layer pattern located on the fourth insulating layer, as shown in Figures 19 to 21, Figure 19 is a schematic diagram of the second conductive layer pattern of the display substrate provided in Figures 7 and 8, Figure 20 is a schematic diagram of the display substrate provided in Figure 7 after the second conductive layer pattern is formed, and Figure 21 is a schematic diagram of the display substrate provided in Figure 8 after the second conductive layer pattern is formed. In an exemplary embodiment, the second conductive layer may be referred to as a second gate metal (GATE2) layer.

[0288] In an exemplary embodiment, as shown in Figures 19 to 21, the second conductive layer may include at least: a second plate C12 of a first capacitor and a second plate C22 of a second capacitor located in at least one sub-pixel, and a first sub-signal line Gate1A of a first scan signal line and a third sub-signal line Gate4A of a fourth scan signal line extending at least partially along the first direction D1.

[0289] In an exemplary embodiment, any one of the second plates C12 of the first capacitor and the second plates C22 of the second capacitor of adjacent sub-pixels located in the same row is symmetrically arranged with respect to a virtual straight line extending along the second direction D2, and any one of the second plates C12 of the first capacitor and the second plates C22 of the second capacitor of all sub-pixels located in the same column is the same.

[0290] In an exemplary embodiment, as shown in Figures 19 to 21, the second plate C12 of the first capacitor and the second plate C22 of the second capacitor can be interconnected as an integral structure. The outline of the second plate C12 of the first capacitor (also the second plate C22 of the second capacitor) can be rectangular, and the corners of the rectangle can be chamfered. The orthographic projection of the second plate C12 of the first capacitor (also the second plate C22 of the second capacitor) on the substrate at least partially overlaps with the orthographic projections of the first plate of the first capacitor and the first plate of the second capacitor on the substrate.

[0291] In an exemplary embodiment, as shown in Figures 19 to 21, the second plate C12 of the first capacitor (the second plate C22 of the second capacitor) is provided with a first via V1 and a second via V2. The first via V1 and the second via V2 can be rectangular in shape and are located in the middle of the second plate C12 of the first capacitor (the second plate C22 of the second capacitor). The first via V1 exposes the fourth insulating layer covering the first plate of the first capacitor, and the orthographic projection of the first plate of the first capacitor on the substrate includes the orthographic projection of the first via on the substrate. In an exemplary embodiment, the first via V1 exposes the first plate of the first capacitor, allowing the subsequently formed first connecting electrode to be connected to the first plate of the first capacitor. The second via V2 exposes the fourth insulating layer covering the first plate of the second capacitor, and the orthographic projection of the first plate of the second capacitor on the substrate includes the orthographic projection of the second via on the substrate. In an exemplary embodiment, the second via V2 exposes the first plate of the second capacitor, allowing the subsequently formed second electrode of the first transistor to be connected to the first plate of the second capacitor.

[0292] In an exemplary embodiment, as shown in Figures 19 to 21, the shape of the first sub-signal line Gate1A of the first scan signal line can be a line shape extending at least partially along the first direction D1, and the first sub-signal line Gate1A of the first scan signal line connected to the sub-pixel can be located on the side of the second plate C12 of the first capacitor of the sub-pixel (the second plate C22 of the second capacitor) close to the previous sub-pixel, and the area overlapping with the active layer of the first transistor of the subsequently formed sub-pixel serves as the first gate electrode T12A of the first transistor, and the area overlapping with the active layer of the fourth transistor of the subsequently formed sub-pixel serves as the first gate electrode T42A of the fourth transistor.

[0293] In an exemplary embodiment, as shown in Figures 19 to 21, the positive projection of the first sub-signal line Gate1A of the first scanning signal line connected to the sub-pixel on the substrate can be located between the positive projection of the light-emitting signal line connected to the sub-pixel on the substrate and the positive projection of the first plate of the second capacitor of the sub-pixel on the substrate.

[0294] In an exemplary embodiment, as shown in Figures 19 to 21, the shape of the third sub-signal line Gate4A of the fourth scan signal line can be a line shape extending at least partially along the first direction D1, and the third sub-signal line Gate4A of the fourth scan signal line connected to the sub-pixel can be located on a side of the first sub-signal line Gate1A of the first scan signal line connected to the sub-pixel away from the second plate C12 of the first capacitor of the sub-pixel (the second plate C22 of the second capacitor), and the area overlapping with the active layer of the fifth transistor of the sub-pixel formed subsequently serves as the first gate electrode T52A of the fifth transistor.

[0295] In an exemplary embodiment, as shown in Figures 19 to 21, the positive projection of the third sub-signal line Gate4A of the fourth scanning signal line connected to the sub-pixel on the substrate can be located on a side of the positive projection of the light-emitting signal line connected to the sub-pixel on the substrate away from the positive projection of the first plate of the second capacitor of the sub-pixel on the substrate.

[0296] In an exemplary embodiment, the first sub-signal line Gate1A of the first scanning signal line and the third sub-signal line Gate4A of the fourth scanning signal line can be designed with equal width, or can be designed with unequal width, can be a straight line, or can be a broken line, which not only facilitates the layout of the pixel structure, but also reduces the parasitic capacitance between the signal lines. The present disclosure does not limit this.

[0297] (5) forming a second semiconductor layer pattern, comprising: on a substrate on which the aforementioned pattern is formed, sequentially depositing a fifth insulating film and a second semiconductor film on the substrate, patterning the fifth insulating film and the second semiconductor film through a patterning process to form a fifth insulating layer and a second semiconductor layer pattern located on the fifth insulating layer, as shown in FIG22 to FIG24 , FIG22 is a schematic diagram of the second semiconductor layer pattern of the display substrate provided in FIG7 and FIG8 , FIG23 is a schematic diagram of the display substrate provided in FIG7 after the second semiconductor layer pattern is formed, and FIG24 is a schematic diagram of the display substrate provided in FIG8 after the second semiconductor layer pattern is formed.

[0298] In exemplary embodiments, as shown in FIG. 22 to FIG. 24 , the second semiconductor layer may include at least an active layer T11 of a first transistor, an active layer T41 of a fourth transistor, and an active layer T51 of a fifth transistor located in at least one subpixel.

[0299] In an exemplary embodiment, the active layer T41 of the fourth transistor and the active layer T51 of the fifth transistor are connected to each other as an integral structure, and the active layer T11 of the first transistor is provided separately.

[0300] In an exemplary embodiment, as shown in Figures 22 to 24, any one of the active layers T11 of the first transistor, the active layer T41 of the fourth transistor, and the active layer T51 of the fifth transistor of adjacent sub-pixels located in the same row is symmetrically arranged with respect to a virtual straight line extending along the second direction D2, and any one of the active layers T11 of the first transistor, the active layer T41 of the fourth transistor, and the active layer T51 of the fifth transistor of all sub-pixels located in the same column is the same.

[0301] In an exemplary embodiment, as shown in Figures 22 to 24, in the first direction D1, the active layer T11 of the first transistor of the subpixel may be located on a side of the active layer T41 of the fourth transistor that is closer to the subpixels in the previous row or the subpixels in the next row. In the second direction D2, the active layer T51 of the fifth transistor of the subpixel may be located on a side of the active layer T41 of the fourth transistor of the subpixel that is closer to the subpixels in the previous row.

[0302] 22 to 24 , the active layers T11 and T51 of the first and fifth transistors may have an I shape, and the active layer T41 of the fourth transistor may have a horizontally inverted L shape.

[0303] In an exemplary embodiment, as shown in Figures 22 to 24, the orthographic projection of the active layer T11 of the first transistor of the sub-pixel on the substrate at least partially overlaps with the orthographic projection of the first sub-signal line Gate1A of the first scanning signal line connected to the sub-pixel, the light-emitting signal line connected to the sub-pixel, and the second plate of the first capacitor of the sub-pixel (also the second plate of the second capacitor) on the substrate.

[0304] In an exemplary embodiment, as shown in Figures 22 to 24, the positive projection of the active layer T11 of the first transistor of the sub-pixel on the substrate at least partially overlaps with the positive projection of the first sub-signal line Gate1A of the first scanning signal line connected to the sub-pixel and the light emitting signal line connected to the sub-pixel on the substrate.

[0305] In an exemplary embodiment, an orthographic projection of the active layer T51 of the fifth transistor of the sub-pixel on the substrate overlaps an orthographic projection of the third sub-signal line Gate4A of the fourth scan signal line connected to the sub-pixel on the substrate.

[0306] In an exemplary embodiment, the active layer of each transistor located in the second conductive layer may include a first region, a second region, and a channel region located between the first region and the second region. In an exemplary embodiment, the first region T41-1 of the active layer of the fourth transistor may also serve as the second region T51-2 of the active layer of the fifth transistor. The first region T11-1 and the second region T11-2 of the active layer T11 of the first transistor, the second region T41-2 of the active layer of the fourth transistor, and the first region T51-1 of the active layer of the fifth transistor may be separately provided.

[0307] In an exemplary embodiment, the active layer T11 of the first transistor is disposed across the first gate electrode of the first transistor, the active layer T41 of the fourth transistor is disposed across the first gate electrode of the fourth transistor, and the active layer T51 of the fifth transistor is disposed across the first gate electrode of the fifth transistor.

[0308] (6) Forming a third conductive layer, including: depositing a sixth insulating film and a third conductive film in sequence on the substrate having the aforementioned pattern formed thereon, patterning the sixth insulating film and the third conductive film through a patterning process to form a sixth insulating layer pattern and a third conductive layer pattern located on the sixth insulating layer, as shown in Figures 25 to 27, Figure 25 is a schematic diagram of the third conductive layer pattern of the display substrate provided in Figures 7 and 8, Figure 26 is a schematic diagram of the display substrate provided in Figure 7 after the third conductive layer pattern is formed, and Figure 27 is a schematic diagram of the display substrate provided in Figure 8 after the third conductive layer pattern is formed. In an exemplary embodiment, the third conductive layer may be referred to as a third gate metal (GATE3) layer.

[0309] In an exemplary embodiment, as shown in Figures 25 to 27, the third conductive layer may include at least: a second sub-signal line Gate1B of the first scan signal line extending at least partially along the first direction D1, a fourth sub-signal line Gate4B of the fourth scan signal line, a power connection line VCL, a first initial signal line INIT1, a second initial signal line INIT2 and a third initial signal line INIT3.

[0310] In exemplary embodiments, as shown in Figures 25 to 27, the second sub-signal line Gate1B of the first scan signal line can be linearly shaped, extending along a first direction D1. The orthographic projection of the second sub-signal line Gate1B of the first scan signal line on the substrate at least partially overlaps with the orthographic projection of the first sub-signal line of the first scan signal line on the substrate, and the line is electrically connected to the first sub-signal line of the first scan signal line. The area where the second sub-signal line Gate1B of the first scan signal line connected to the subpixel overlaps with the active layer of the second transistor of the subpixel serves as the second gate electrode T22B of the second transistor, and the area where the second sub-signal line Gate1B of the first scan signal line connected to the subpixel overlaps with the active layer of the fourth transistor of the subpixel serves as the second gate electrode T42B of the fourth transistor. The first gate electrode and the second gate electrode of the first transistor constitute the gate electrode of the first transistor. The first gate electrode and the second gate electrode of the fourth transistor constitute the gate electrode of the fourth transistor.

[0311] In an exemplary embodiment, as shown in Figures 25 to 27, the positive projection of the second sub-signal line Gate1B of the first scanning signal line connected to the sub-pixel on the substrate can be located between the positive projection of the light-emitting signal line connected to the sub-pixel on the substrate and the positive projection of the first plate of the second capacitor of the sub-pixel on the substrate.

[0312] In exemplary embodiments, as shown in Figures 25 to 27, the fourth sub-signal line Gate4B of the fourth scan signal line can be linearly shaped, extending along the first direction D1. The orthographic projection of the fourth sub-signal line Gate4B of the fourth scan signal line on the substrate at least partially overlaps with the orthographic projection of the third sub-signal line of the fourth scan signal line on the substrate, and is electrically connected to the third sub-signal line of the fourth scan signal line. The region where the fourth sub-signal line Gate4B of the fourth scan signal line connected to the subpixel overlaps with the active layer of the fifth transistor of the subpixel serves as the second gate electrode T52B of the fifth transistor. The first gate electrode and the second gate electrode of the fifth transistor constitute the gate electrode of the fifth transistor.

[0313] In an exemplary embodiment, as shown in Figures 25 to 27, the positive projection of the fourth sub-signal line Gate4B of the fourth scanning signal line connected to the sub-pixel on the substrate can be located on a side of the positive projection of the light-emitting signal line connected to the sub-pixel on the substrate away from the positive projection of the first plate of the second capacitor of the sub-pixel on the substrate.

[0314] In an exemplary embodiment, as shown in Figures 25 to 27 , the power connection line VCL may be linear, with a main portion extending along the first direction D1. The power connection line VCL connected to the subpixel may be located on a side of the second sub-signal line Gate1B of the first scan signal line connected to the subpixel, away from the fourth sub-signal line Gate4B of the fourth scan signal line connected to the subpixel. The orthographic projection of the power connection line VCL on the substrate at least partially overlaps the orthographic projection of the second plate of the first capacitor (also the second plate of the second capacitor) on the substrate.

[0315] In an exemplary embodiment, as shown in Figures 25 to 27, the positive projection of the power connection line VCL connected to the sub-pixel on the substrate can be located between the positive projection of the first sub-signal line of the first scan signal line connected to the sub-pixel on the substrate and the projection of the second scan signal line connected to the sub-pixel on the substrate.

[0316] In an exemplary embodiment, as shown in Figures 25 to 27, the power connection line VCL may include a main signal line 30, a first protrusion 31, a second protrusion 32, and a third protrusion 33. The main signal line 30, the first protrusion 31, the second protrusion 32, and the third protrusion 33 may be an interconnected, integral structure. The first protrusion 31 may be located on a side of the main signal line 30 that is closer to the second sub-signal line Gate1B of the first scan signal line, and the second protrusion 32 and the third protrusion 33 may be located on a side of the main signal line 30 that is farther from the second sub-signal line Gate1B of the first scan signal line. The second protrusion 32 and the third protrusion 33 are arranged along the first direction D1.

[0317] 25 to 27 , the signal main line 30 may be in the shape of a line extending in the first direction D1. The first, second, and third protrusions 31, 32, and 33 may be in the shape of a rectangle.

[0318] In an exemplary embodiment, as shown in FIG. 25 to FIG. 27 , the orthographic projections of the second protrusion 32 and the third protrusion 33 on the substrate at least partially overlap with the orthographic projections of the second plate of the first capacitor (also the second plate of the second capacitor) on the substrate.

[0319] In an exemplary embodiment, as shown in Figures 25 to 27, the first initial signal line INIT1 and the second initial signal line INIT2 are the same signal line, and may be in the form of a line with a main portion extending along the first direction D1. The first initial signal line INIT1 (also the second initial signal line INIT2) connected to the subpixel is located on a side of the power connection line VCL connected to the subpixel, away from the second sub-signal line Gate1B of the first scan signal line. The orthographic projection of the first initial signal line INIT1 (also the second initial signal line INIT2) on the substrate at least partially overlaps with the orthographic projection of the second scan signal line on the substrate.

[0320] In an exemplary embodiment, as shown in Figures 25 to 27, the positive projection of the first initial signal line INIT1 (also the second initial signal line INIT2) connected to the sub-pixel on the substrate is located between the positive projection of the first plate of the first capacitor of the sub-pixel on the substrate and the positive projection of the third scanning signal line connected to the sub-pixel on the substrate.

[0321] In an exemplary embodiment, as shown in Figures 25 to 27, the third initial signal line INIT3 may be in the form of a line with a main portion extending along the first direction D1. The third initial signal line INIT3 is located on a side of the first initial signal line INIT1 (and also the second initial signal line INIT2) away from the power connection line VCL. The orthographic projection of the third initial signal line INIT3 connected to the subpixel on the substrate at least partially overlaps with the orthographic projection of the third scan signal line connected to the subpixel on the substrate.

[0322] In an exemplary embodiment, as shown in Figures 25 to 27, the positive projection of the third initial signal line INIT3 connected to the sub-pixel on the substrate is located on a side of the positive projection of the second scanning signal line connected to the sub-pixel on the substrate away from the positive projection of the first plate of the first capacitor connected to the sub-pixel on the substrate.

[0323] In an exemplary embodiment, the second sub-signal line Gate1B of the first scanning signal line, the fourth sub-signal line Gate4B of the fourth scanning signal line, the power connection line VCL, the first initial signal line INIT1, the second initial signal line INIT2 and the third initial signal line INIT3 can be designed with equal width, or can be designed with unequal width, can be straight lines, or can be broken lines, which not only facilitates the layout of the pixel structure but also reduces the parasitic capacitance between the signal lines. The present disclosure is not limited here.

[0324] In an exemplary embodiment, after forming the third conductive layer pattern, the third conductive layer can be used as a shield to perform conductorization on the second semiconductor layer. The second semiconductor layer in the area shielded by the third conductive layer forms the channel region of the active layer of the first transistor, the fourth transistor, and the fifth transistor, and the second semiconductor layer in the area not shielded by the third conductive layer is conductorized, that is, the first area and the second area of ​​the active layer of the first transistor, the fourth transistor, and the fifth transistor are both conductorized.

[0325] (7) Forming a seventh insulating layer pattern. In an exemplary embodiment, forming the seventh insulating layer pattern may include: depositing a seventh insulating film on the substrate on which the aforementioned pattern is formed, patterning the seventh insulating film using a patterning process to form a seventh insulating layer covering the third conductive layer, wherein a plurality of vias are provided on the seventh insulating layer, as shown in FIG28 and FIG29 . FIG28 is a schematic diagram of the display substrate provided in FIG7 after the seventh insulating layer pattern is formed, and FIG29 is a schematic diagram of the display substrate provided in FIG8 after the seventh insulating layer pattern is formed.

[0326] In an exemplary embodiment, as shown in FIG. 28 and FIG. 29 , the plurality of via holes of the seventh insulating layer may include at least a third via hole V3 to a nineteenth via hole V19 located in at least one sub-pixel.

[0327] In an exemplary embodiment, the third via of the sub-pixel is the same via as the third via of one of the adjacent sub-pixels located in the same row, the fifth via of the sub-pixel is the same via as the fifth via of another adjacent sub-pixel located in the same row, and the seventh via of the sub-pixel is the same via as the seventh via of another adjacent sub-pixel located in the same row.

[0328] In an exemplary embodiment, as shown in Figures 28 and 29, the orthographic projection of the third via V3 on the substrate is located within the range of the orthographic projection of the first area of ​​the active layer of the second transistor on the substrate, the third insulating layer, the fourth insulating layer, the fifth insulating layer and the sixth insulating layer in the third via V3 are etched away to expose the surface of the first area of ​​the active layer of the second transistor, and the third via V3 is configured to connect the first electrode of the subsequently formed second transistor (which is also the initial connection line ICL) to the first area of ​​the active layer of the second transistor through the via.

[0329] In an exemplary embodiment, as shown in Figures 28 and 29, the orthographic projection of the fourth via V4 on the substrate is located within the range of the orthographic projection of the second area of ​​the active layer of the second transistor (also the second area of ​​the active layer of the sixth transistor) on the substrate, the third insulating layer, the fourth insulating layer, the fifth insulating layer and the sixth insulating layer in the fourth via V4 are etched away to expose the surface of the second area of ​​the active layer of the second transistor (also the second area of ​​the active layer of the sixth transistor), and the fourth via V4 is configured to connect the second electrode of the subsequently formed second transistor (also the second electrode of the sixth transistor) to the second area of ​​the active layer of the second transistor (also the second area of ​​the active layer of the sixth transistor) through the via.

[0330] In an exemplary embodiment, as shown in Figures 28 and 29, the orthographic projection of the fifth via V5 on the substrate is located within the range of the orthographic projection of the first area of ​​the active layer of the third transistor on the substrate, the third insulating layer, the fourth insulating layer, the fifth insulating layer and the sixth insulating layer in the fifth via V5 are etched away to expose the surface of the first area of ​​the active layer of the third transistor, and the fifth via V5 is configured to connect the first electrode of the subsequently formed third transistor to the first area of ​​the active layer of the third transistor through the via.

[0331] In an exemplary embodiment, as shown in Figures 28 and 29, the orthographic projection of the sixth via V6 on the substrate is located within the range of the orthographic projection of the second region of the active layer of the third transistor on the substrate, the third insulating layer, the fourth insulating layer, the fifth insulating layer and the sixth insulating layer within the sixth via V6 are etched away to expose the surface of the second region of the active layer of the third transistor, and the sixth via V6 is configured to connect the second electrode of the subsequently formed third transistor (which is also the second electrode of the fourth transistor, the first electrode of the sixth transistor and the second electrode of the seventh transistor) to the second region of the active layer of the third transistor through the via.

[0332] In an exemplary embodiment, as shown in Figures 28 and 29, the orthographic projection of the seventh via V7 on the substrate is located within the range of the orthographic projection of the first area of ​​the active layer of the seventh transistor on the substrate, the third insulating layer, the fourth insulating layer, the fifth insulating layer and the sixth insulating layer in the seventh via V7 are etched away to expose the surface of the first area of ​​the active layer of the seventh transistor, and the seventh via V7 is configured to connect the first electrode of the subsequently formed seventh transistor to the first area of ​​the active layer of the seventh transistor through the via.

[0333] In an exemplary embodiment, as shown in Figures 28 and 29, the orthographic projection of the eighth via V8 on the substrate is located within the range of the orthographic projection of the second area of ​​the active layer of the seventh transistor (also the first area of ​​the sixth transistor) on the substrate, the third insulating layer, the fourth insulating layer, the fifth insulating layer and the sixth insulating layer in the eighth via V8 are etched away to expose the surface of the second area of ​​the active layer of the seventh transistor (also the first area of ​​the sixth transistor), and the eighth via V8 is configured to connect the second electrode of the subsequently formed third transistor (also the second electrode of the fourth transistor, the first electrode of the sixth transistor and the second electrode of the seventh transistor) to the second area of ​​the active layer of the seventh transistor (also the first area of ​​the sixth transistor) through the via.

[0334] In an exemplary embodiment, as shown in Figures 28 and 29, the orthographic projection of the ninth via V9 on the substrate is located within the range of the orthographic projection of the first via on the substrate, the fifth insulating layer and the sixth insulating layer in the ninth via V9 are etched away to expose the surface of the first plate of the first capacitor, and the ninth via V9 is configured to connect a subsequently formed first connecting electrode to the first plate of the first capacitor through the via.

[0335] In an exemplary embodiment, as shown in Figures 28 and 29, the orthographic projection of the tenth via V10 on the substrate is located within the range of the orthographic projection of the second via on the substrate, the fifth insulating layer and the sixth insulating layer in the tenth via V10 are etched away, exposing the surface of the first plate of the second capacitor (which is also the gate electrode of the sixth transistor), and the tenth via V10 is configured to connect the second electrode of the subsequently formed first transistor to the first plate of the second capacitor (which is also the gate electrode of the sixth transistor) through the via.

[0336] In an exemplary embodiment, as shown in Figures 28 and 29, the orthographic projection of the eleventh via V11 on the substrate is located within the range of the orthographic projection of the second plate of the first capacitor (also the second plate of the second capacitor) on the substrate, the fifth insulating layer and the sixth insulating layer in the eleventh via V11 are etched away, and the eleventh via V11 exposes the surface of the second plate of the first capacitor (also the second plate of the second capacitor), and the eleventh via V11 is configured to connect the first electrode of the subsequently formed fourth transistor (also the second electrode of the fifth transistor) to the second plate of the first capacitor (also the second plate of the second capacitor) through the via.

[0337] In an exemplary embodiment, as shown in Figures 28 and 29, the orthographic projection of the twelfth via V12 on the substrate is located within the range of the orthographic projection of the first region of the active layer of the first transistor on the substrate, the sixth insulating layer in the twelfth via V12 is etched away to expose the surface of the first region of the active layer of the first transistor, and the twelfth via V12 is configured to connect the first electrode of the subsequently formed first transistor to the first region of the active layer of the first transistor through the via.

[0338] In an exemplary embodiment, as shown in Figures 28 and 29, the orthographic projection of the thirteenth via V13 on the substrate is located within the range of the orthographic projection of the second region of the active layer of the first transistor on the substrate, the sixth insulating layer in the thirteenth via V13 is etched away to expose the surface of the second region of the active layer of the first transistor, and the thirteenth via V13 is configured to connect the second electrode of the subsequently formed first transistor to the second region of the active layer of the first transistor through the via.

[0339] In an exemplary embodiment, as shown in Figures 28 and 29, the orthographic projection of the fourteenth via V14 on the substrate is located within the range of the orthographic projection of the first area of ​​the active layer of the fourth transistor (also the second area of ​​the active layer of the fifth transistor) on the substrate, the sixth insulating layer in the fourteenth via V14 is etched away to expose the surface of the first area of ​​the active layer of the fourth transistor (also the second area of ​​the active layer of the fifth transistor), and the fourteenth via V14 is configured to connect the first electrode of the subsequently formed fourth transistor (also the second electrode of the fifth transistor) to the first area of ​​the active layer of the fourth transistor (also the second area of ​​the active layer of the fifth transistor) through the via.

[0340] In an exemplary embodiment, as shown in Figures 28 and 29, the orthographic projection of the fifteenth via V15 on the substrate is located within the range of the orthographic projection of the second region of the active layer of the fourth transistor on the substrate, the sixth insulating layer in the fifteenth via V15 is etched away, exposing the surface of the second region of the active layer of the fourth transistor, and the fifteenth via V15 is configured to connect the second electrode of the subsequently formed third transistor (which is also the second electrode of the fourth transistor, the first electrode of the sixth transistor, and the second electrode of the seventh transistor) to the second region of the active layer of the fourth transistor through the via.

[0341] In an exemplary embodiment, as shown in Figures 28 and 29, the orthographic projection of the sixteenth via V16 on the substrate is located within the range of the orthographic projection of the first area of ​​the active layer of the fifth transistor on the substrate, the sixth insulating layer in the sixteenth via V16 is etched away, the fifteenth via V15 exposes the surface of the first area of ​​the active layer of the fifth transistor, and the sixteenth via V16 is configured to connect the first electrode of the subsequently formed fifth transistor to the first area of ​​the active layer of the fifth transistor through the via.

[0342] In an exemplary embodiment, as shown in Figures 28 and 29, the orthographic projection of the seventeenth via hole V17 on the substrate is located within the range of the orthographic projection of the power connection line on the substrate, exposing the surface of the power connection line, and the seventeenth via hole V17 is configured to connect the subsequently formed first connection electrode to the power connection line through the via hole.

[0343] In an exemplary embodiment, as shown in Figures 28 and 29, the orthographic projection of the eighteenth via V18 on the substrate is located within the range of the orthographic projection of the first initial signal line (also the second initial signal line) on the substrate, exposing the surface of the first initial signal line (also the second initial signal line), and the eighteenth via V18 is configured to connect the first electrode of the subsequently formed second transistor (also the initial connection line ICL) to the first initial signal line (also the second initial signal line) through the via.

[0344] In an exemplary embodiment, as shown in Figures 28 and 29, the orthographic projection of the nineteenth via V19 on the substrate is located within the range of the orthographic projection of the third initial signal line on the substrate, exposing the surface of the third initial signal line, and the nineteenth via V19 is configured to connect the first electrode of the subsequently formed third transistor to the third initial signal line through the via.

[0345] In an exemplary embodiment, a virtual straight line extending in the second direction D2 may pass through the third via hole V3 and the eighteenth via hole V18 .

[0346] In an exemplary embodiment, a virtual straight line extending in the second direction D2 may pass through the fifth via hole V5 and the nineteenth via hole V19 .

[0347] In an exemplary embodiment, a virtual straight line extending in the second direction D2 may pass through the eighth via hole V8 and the fifteenth via hole V15 .

[0348] (9) Forming a fourth conductive layer pattern. In an exemplary embodiment, forming the fourth conductive layer pattern may include: depositing a fourth conductive film on the substrate on which the aforementioned pattern is formed, patterning the fourth conductive film using a patterning process, and forming a fourth conductive layer pattern disposed on the seventh insulating layer, as shown in Figures 30 to 32. As shown in Figures 30 to 32, Figure 30 is a schematic diagram of the fourth conductive layer pattern of the display substrate provided in Figures 7 and 8, Figure 31 is a schematic diagram of the display substrate provided in Figure 7 after the fourth conductive layer pattern is formed, and Figure 32 is a schematic diagram of the display substrate provided in Figure 8 after the fourth conductive layer pattern is formed. In an exemplary embodiment, the fourth conductive layer may be referred to as a first source / drain metal (SD1) layer.

[0349] In an exemplary embodiment, as shown in Figures 30 to 32, the fourth conductive layer pattern may include at least: an initial connection line ICL extending at least partially along the second direction D2, and a first electrode T13 and a second electrode T14 of a first transistor, a first electrode T23 and a second electrode T24 of a second transistor, a first electrode T33 and a second electrode T34 of a third transistor, a first electrode T43 and a second electrode T44 of a fourth transistor, a first electrode T53 and a second electrode T54 of a fifth transistor, a first electrode T63 and a second electrode T64 of a sixth transistor, a first electrode T73 and a second electrode T74 of a seventh transistor, and a first connection electrode VL1 located at at least one sub-pixel.

[0350] In an exemplary embodiment, as shown in Figures 30 to 32, any one of the first electrode T13 and the second electrode T14 of the first transistor, the first electrode T23 and the second electrode T24 of the second transistor, the first electrode T33 and the second electrode T34 of the third transistor, the first electrode T43 and the second electrode T44 of the fourth transistor, the first electrode T53 and the second electrode T54 of the fifth transistor, the first electrode T63 and the second electrode T64 of the sixth transistor, the first electrode T73 and the second electrode T74 of the seventh transistor, and the first connection electrode VL1 of adjacent sub-pixels located in the same row are arranged symmetrically with respect to a virtual straight line extending along the second direction D2.

[0351] In an exemplary embodiment, as shown in Figures 30 to 32, the initial connection line ICL is located between two adjacent columns of sub-pixels whose active layers of the second transistors are connected to each other, and is electrically connected to the two adjacent columns of sub-pixels. The initial connection line ICL coincides with the symmetry axes of the two adjacent columns of sub-pixels.

[0352] In an exemplary embodiment, as shown in Figures 30 to 32, the initial connection line ICL may be shaped like a line extending along the second direction D2. The overlapping region of the initial connection line ICL and the first region of the active layer of the second transistor may also serve as the first electrode T23 of the second transistor. The initial connection line ICL (also the first electrode T23 of the second transistor) is connected to the first region of the active layer of the second transistor through a third via hole, and is connected to the first initial signal line (also the second initial signal line) through an eighteenth via hole.

[0353] In an exemplary embodiment, as shown in Figures 30 to 32, in the first direction D1, the first electrode T13 and the second electrode T14 of the first transistor, the first electrode T23 and the second electrode T24 of the second transistor, the first electrode T33 and the second electrode T34 of the third transistor, the first electrode T43 and the second electrode T44 of the fourth transistor, the first electrode T53 and the second electrode T54 of the fifth transistor, the first electrode T63 and the second electrode T64 of the sixth transistor, the first electrode T73 and the second electrode T74 of the seventh transistor, and the first connection electrode VL1 of at least one subpixel may be located on the same side of the initial connection line ICL.

[0354] In an exemplary embodiment, as shown in Figures 30 to 32, the first electrode T13 of the first transistor and the initial connection line ICL are connected to each other as an integral structure. The first electrode T13 of the first transistor may be in the shape of a line extending along the first direction D1. The first electrode T13 of the first transistor is connected to the first region of the active layer of the first transistor through a twelfth via V12.

[0355] In an exemplary embodiment, as shown in Figures 30 to 32, the second electrode T14 of the first transistor is provided separately. The second electrode T14 of the first transistor can be in a block shape. The second electrode T14 of the first transistor is connected to the second region of the active layer of the first transistor through a thirteenth via hole, and is connected to the first plate of the second capacitor (which is also the gate electrode of the sixth transistor) through a tenth via hole.

[0356] In an exemplary embodiment, as shown in Figures 30 to 32, the second electrode T24 of the second transistor and the second electrode T64 of the sixth transistor may be an integrated structure connected to each other. The second electrode T24 of the second transistor (also the second electrode T64 of the sixth transistor) may be shaped like a dumbbell. The second electrode T24 of the second transistor (also the second electrode T64 of the sixth transistor) may be connected to the second region of the active layer of the second transistor (also the second region of the active layer of the sixth transistor) through a fourth via.

[0357] In an exemplary embodiment, as shown in Figures 30 to 32, the first electrode T33 of the third transistor is provided separately. The first electrode T33 of the third transistor can be in a block shape. The first electrode T33 of the third transistor is connected to the first region of the active layer of the third transistor through a fifth via hole and is connected to the third initial signal line through a nineteenth via hole.

[0358] In an exemplary embodiment, as shown in Figures 30 to 32, the second electrode T34 of the third transistor, the second electrode T44 of the fourth transistor, the first electrode T63 of the sixth transistor, and the second electrode T74 of the seventh transistor may be an interconnected integral structure. The second electrode T34 of the third transistor (also the second electrode T44 of the fourth transistor, the first electrode T63 of the sixth transistor, and the second electrode T74 of the seventh transistor) may be shaped like a dumbbell extending along the second direction D2. The second electrode T34 of the third transistor (also the second electrode T44 of the fourth transistor, the first electrode T63 of the sixth transistor, and the second electrode T74 of the seventh transistor) is connected to the second region of the active layer of the third transistor via a sixth via, connected to the second region of the active layer of the seventh transistor (also the first region of the sixth transistor) via an eighth via, and connected to the second region of the active layer of the fourth transistor via a fifteenth via.

[0359] In an exemplary embodiment, as shown in Figures 30 to 32, the first electrode T43 of the fourth transistor and the second electrode T54 of the fifth transistor may be interconnected and integrally formed. The first electrode T43 of the fourth transistor (also the second electrode T54 of the fifth transistor) may be shaped like a dumbbell with a main portion extending along the second direction D2. The first electrode T43 of the fourth transistor (also the second electrode T54 of the fifth transistor) is connected to the second plate of the first capacitor (also the second plate of the second capacitor) via an eleventh via, and to the first region of the active layer of the fourth transistor (also the second region of the active layer of the fifth transistor) via a fourteenth via.

[0360] In an exemplary embodiment, as shown in Figures 30 to 32, the first electrode T53 of the fifth transistor is provided separately. The first electrode T53 of the fifth transistor may be in the shape of a strip extending along the first direction D1. The first electrode T53 of the fifth transistor is connected to the first region of the active layer of the fifth transistor through a sixteenth via hole.

[0361] In an exemplary embodiment, as shown in Figures 30 to 32, the first electrode T73 of the seventh transistor is separately provided. The first electrode T73 of the seventh transistor may be shaped like a gourd. The first electrode T73 of the seventh transistor is connected to the first region of the active layer of the seventh transistor through a seventh via.

[0362] 30 to 32 , the first connection electrode VL1 may be rectangular in shape. The first connection electrode VL1 is connected to the power connection line through the seventeenth via hole and to the first plate of the first capacitor through the ninth via hole.

[0363] In an exemplary embodiment, as shown in FIG. 30 to FIG. 32 , an orthographic projection of the first connection electrode on the substrate at least partially overlaps with orthographic projections of the second and third protruding portions of the power connection line on the substrate.

[0364] (10) Forming a first flat layer pattern. In an exemplary embodiment, forming the first flat layer pattern may include: depositing an eighth insulating film on the substrate on which the aforementioned pattern is formed, patterning the eighth insulating film using a patterning process to form an eighth insulating layer covering the fourth conductive layer, coating a first flat film on the eighth insulating layer, and patterning the first flat film using a patterning process to form a first flat layer pattern covering the aforementioned pattern, wherein the first flat layer is provided with a plurality of via patterns, as shown in FIG33 and FIG34 . FIG33 is a schematic diagram of the display substrate provided in FIG7 after the eighth insulating layer pattern is formed, and FIG34 is a schematic diagram of the display substrate provided in FIG8 after the eighth insulating layer pattern is formed.

[0365] In an exemplary embodiment, as shown in FIG. 33 and FIG. 34 , the plurality of via holes of the first planar layer may include at least twentieth to twenty-third via holes V20 to V23 .

[0366] In an exemplary embodiment, as shown in Figures 33 and 34, the orthographic projection of the twentieth via V20 on the substrate is located within the range of the orthographic projection of the second electrode of the second transistor (also the second electrode of the sixth transistor) on the substrate, the eighth insulating layer in the twentieth via V20 is etched away to expose the surface of the second electrode of the second transistor (also the second electrode of the sixth transistor), and the twentieth via V20 is configured to connect a subsequently formed second connecting electrode to the second electrode of the second transistor (also the second electrode of the sixth transistor) through the via.

[0367] In an exemplary embodiment, as shown in Figures 33 and 34, the orthographic projection of the twenty-first via V21 on the substrate is located within the range of the orthographic projection of the first electrode of the fifth transistor on the substrate, the eighth insulating layer in the twenty-first via V21 is etched away to expose the surface of the first electrode of the fifth transistor, and the twenty-first via V21 is configured to connect a subsequently formed data signal line to the first electrode of the fifth transistor through the via.

[0368] In an exemplary embodiment, as shown in Figures 33 and 34, the orthographic projection of the twenty-second via V22 on the substrate is located within the range of the orthographic projection of the first electrode of the seventh transistor on the substrate, the eighth insulating layer in the twenty-second via V22 is etched away to expose the surface of the first electrode of the seventh transistor, and the twenty-second via V22 is configured to connect a subsequently formed first power line to the first electrode of the seventh transistor through the via.

[0369] In an exemplary embodiment, as shown in Figures 33 and 34, the orthographic projection of the twenty-third via hole V23 on the substrate is located within the range of the orthographic projection of the first connecting electrode on the substrate, the eighth insulating layer in the twenty-third via hole V23 is etched away to expose the surface of the first connecting electrode, and the twenty-third via hole V23 is configured to connect a subsequently formed first power line to the first connecting electrode through the via hole.

[0370] (11) forming a fifth conductive layer pattern, including: depositing a fifth conductive film on the substrate having the aforementioned pattern formed thereon, and patterning the fifth conductive film through a patterning process to form a fifth conductive layer pattern, as shown in FIG35 to FIG37 , FIG35 is a schematic diagram of the fifth conductive layer pattern of the display substrate provided in FIG7 and FIG8 , FIG36 is a schematic diagram of the display substrate provided in FIG7 after the fifth conductive layer pattern is formed, and FIG37 is a schematic diagram of the display substrate provided in FIG8 after the fifth conductive layer pattern is formed. In an exemplary embodiment, the fifth conductive layer may be referred to as a second source / drain metal (SD2) layer.

[0371] In an exemplary embodiment, as shown in FIGS. 35 to 37 , the fifth conductive layer may include at least a second connection electrode VL2 located in at least one sub-pixel, and a data signal line Data and a first power line VDD extending at least partially along the second direction D2. A plurality of data signal lines Data are arranged along the first direction D1, and a plurality of first power lines VDD are arranged along the first direction D1.

[0372] 35 to 37 , adjacent sub-pixels are connected to data signal lines Data and first power lines VDD symmetrically with respect to a virtual straight line extending along the second direction D2.

[0373] In an exemplary embodiment, as shown in FIG. 35 to FIG. 37 , the data signal line Data and the first power line VDD to which the sub-pixel is connected are located on different sides of the second connection electrode of the sub-pixel.

[0374] 35 to 37 , the first power line VDD is connected to one of the adjacent power lines and is spaced apart from the other adjacent power line. Two data signal lines Data are disposed between the two spaced apart first power lines.

[0375] In an exemplary embodiment, as shown in Figures 35 to 37, the orthographic projection of the initial connection line ICL on the substrate is located between the orthographic projections of the data signal lines connected to two adjacent columns of sub-pixels connected to the initial connection line ICL on the substrate, and the orthographic projection of the first power line connected to the sub-pixels on the substrate is located on the side of the data signal line connected to the sub-pixels away from the initial connection line ICL connected to the sub-pixels.

[0376] 35 to 37 , the data signal line Data may be in the shape of a line with a main portion extending along the second direction D2 . The sub-pixel-connected data signal line Data is connected to the first electrode of the fifth transistor of the sub-pixel through the twenty-first via hole.

[0377] In an exemplary embodiment, as shown in Figures 35 to 37, the first power line VDD may be in the shape of a line with a main portion extending along the second direction D2. The first power line VDD connected to the sub-pixel is connected to the first electrode of the seventh transistor through the twenty-second via hole and to the first connection electrode through the twenty-third via hole.

[0378] In an exemplary embodiment, as shown in Figures 35 to 37, the orthographic projection of the first power line VDD on the substrate at least partially overlaps with the orthographic projections of the second plate of the first capacitor (also the second plate of the second capacitor) and the signal main body and the second protrusion of the power connection line on the substrate.

[0379] In an exemplary embodiment, as shown in Figures 35 to 37, the shape of the second connection electrode VL2 may be a line or a gourd shape at least partially along the second direction D2. The second connection electrode VL2 is connected to the second electrode of the second transistor (also the second electrode of the sixth transistor) through a twenty-third via hole and is configured to be connected to the anode of a subsequently formed light-emitting device. The shape of the connection electrode connected to the anode of different light-emitting devices may vary.

[0380] In an exemplary embodiment, the width of the first power line VDD may be greater than the width of the data signal line Data.

[0381] (12) forming a second flat layer pattern, comprising: coating a second flat film on the substrate having the aforementioned pattern formed thereon, and patterning the second flat film through a patterning process to form a second flat layer pattern covering the aforementioned pattern.

[0382] At this point, the drive circuit layer is prepared on the substrate. In a plane parallel to the display substrate, the drive circuit layer may include multiple pixel drive circuits, and the pixel drive circuits are connected to the first scan signal line, the second scan signal line, the third scan signal line, the fourth scan signal line, the light-emitting signal line, the first initial signal line, the second initial signal line, the third initial signal line, the data signal line, and the first power line. The drive circuit layer can be arranged on the substrate. The drive circuit layer may include a first insulating layer, a light-shielding layer, a second insulating layer, a first semiconductor layer, a third insulating layer, a first conductive layer, a fourth insulating layer, a second conductive layer, a fifth insulating layer, a second semiconductor layer, a sixth insulating layer, a third conductive layer, a seventh insulating layer, a fourth conductive layer, an eighth insulating layer, a first planar layer, a fifth conductive layer, and a second planar layer, which are sequentially arranged on the substrate.

[0383] In example embodiments, the first semiconductor layer may be an amorphous silicon layer or a polycrystalline silicon layer.

[0384] In one exemplary embodiment, the second semiconductor layer may be a metal oxide layer. The metal oxide layer may be an oxide containing indium and tin, an oxide containing tungsten and indium, an oxide containing tungsten, indium, and zinc, an oxide containing titanium and indium, an oxide containing titanium, indium, and tin, an oxide containing indium and zinc, an oxide containing silicon, indium, and tin, or an oxide containing indium or gallium and zinc. The metal oxide layer may be a single layer, a double layer, or a multilayer.

[0385] In an exemplary embodiment, the first conductive layer, the second conductive layer, the third conductive layer, the fourth conductive layer and the fifth conductive layer can be made of metal materials, such as any one or more of silver (Ag), copper (Cu), aluminum (Al) and molybdenum (Mo), or alloy materials of the above metals, such as aluminum neodymium alloy (AlNd) or molybdenum niobium alloy (MoNb), and can be a single-layer structure or a multi-layer composite structure, such as Mo / Cu / Mo, etc.

[0386] In an exemplary embodiment, the first insulating layer, the second insulating layer, the third insulating layer, the fourth insulating layer, the fifth insulating layer, the sixth insulating layer, the seventh insulating layer and the eighth insulating layer can be made of any one or more of silicon oxide (SiOx), silicon nitride (SiNx) and silicon oxynitride (SiON), and can be a single layer, a multilayer or a composite layer.

[0387] In an exemplary embodiment, the first planarization layer and the second planarization layer may be made of an organic material such as resin.

[0388] In an exemplary embodiment, after the driving circuit layer is prepared, a light emitting structure layer is prepared on the driving circuit layer. The preparation process of the light emitting structure layer may include the following operations.

[0389] An anode conductive film is deposited on the substrate on which the aforementioned pattern is formed, and the anode conductive film is patterned using a patterning process to form an anode conductive layer pattern arranged on the second flat layer. A pixel definition film is deposited on the substrate on which the aforementioned pattern is formed, and the pixel definition film is patterned using a patterning process to form a pixel definition layer pattern exposing the anode conductive layer pattern. An organic light-emitting material is coated on the substrate on which the pixel definition layer pattern is formed, and the organic light-emitting material is patterned using a patterning process to form an organic structure layer pattern. A cathode conductive film is deposited on the substrate on which the organic material layer pattern is formed, and the cathode conductive film is patterned using a patterning process to form a cathode conductive layer.

[0390] At this point, the light-emitting structure layer is prepared on the substrate.

[0391] In an exemplary embodiment, the subsequent preparation process may include: forming a packaging structure layer on the cathode conductive layer, the packaging structure layer may include a stacked first packaging layer, a second packaging layer and a third packaging layer, the first packaging layer and the third packaging layer may be made of inorganic materials, the second packaging layer may be made of organic materials, and the second packaging layer is arranged between the first packaging layer and the third packaging layer to ensure that external water vapor cannot enter the light-emitting structure layer.

[0392] In an exemplary embodiment, the anode conductive layer includes at least a plurality of anode patterns. The plurality of anode patterns may include an anode of a first light-emitting device, an anode of a second light-emitting device, an anode of a third light-emitting device, and an anode of a fourth light-emitting device, wherein the anode of the first light-emitting device is located in a red sub-pixel emitting red light, the anode of the second light-emitting device may be located in a blue sub-pixel emitting blue light, the anode of the third light-emitting device may be located in a first green sub-pixel emitting green light, and the anode of the fourth light-emitting device may be located in a second green sub-pixel emitting green light.

[0393] In an exemplary embodiment, the anode of the first light emitting device and the anode of the second light emitting device may be alternately arranged along the first direction D1, and the anode of the third light emitting device and the anode of the fourth light emitting device may be alternately arranged along the first direction D1. Alternatively, the anode of the first light emitting device and the anode of the second light emitting device may be alternately arranged along the second direction D2, and the anode of the third light emitting device and the anode of the fourth light emitting device may be alternately arranged along the second direction D2.

[0394] In an exemplary embodiment, the shapes and areas of the anode electrodes of the four sub-pixels in one pixel unit may be the same, or may be different.

[0395] In an exemplary embodiment, the anode conductive layer has a single-layer structure, such as indium tin oxide (ITO) or indium zinc oxide (IZO), or may have a multi-layer composite structure, such as ITO / Ag / ITO.

[0396] In an exemplary embodiment, the organic structure layer may include at least an organic light emitting layer of a light emitting device.

[0397] In an exemplary embodiment, the cathode conductive layer may include at least cathodes of a plurality of light emitting devices.

[0398] In an exemplary embodiment, the cathode layer may be made of a metal material, such as any one or more of silver (Ag), copper (Cu), aluminum (Al), and molybdenum (Mo), or a conductive alloy material thereof, such as aluminum-neodymium alloy (AlNd) or molybdenum-niobium alloy (MoNb), and may have a single-layer structure or a multi-layer composite structure, such as Mo / Cu / Mo. For example, the fourth conductive layer may be a three-layer stacked structure formed of titanium, aluminum, and titanium.

[0399] The display substrate adopted in the embodiment of the present disclosure can be applied to display products with any resolution.

[0400] The embodiment of the present disclosure further provides a driving method of a pixel driving circuit. The pixel driving circuit is set to drive. The driving method of the pixel driving circuit provided by the embodiment of the present disclosure may include the following steps:

[0401] Step 100: Under the control of the signals of the first scanning signal line, the second scanning signal line, the third scanning signal line and the fourth scanning signal line, the node control subcircuit drives the signal of the first node through the signals of the first initial signal line, the data signal line and the first power line, provides the signal of the second initial signal line to the second node, and provides the signal of the third initial signal line to the third node.

[0402] Step 200: The light-emitting control subcircuit provides the signal of the first power line to the third node under the control of the signal of the light-emitting signal line, and the driving subcircuit outputs the driving current to the second node under the control of the signals of the first node and the third node.

[0403] An embodiment of the present disclosure further provides a display device, including: a display substrate.

[0404] The display substrate is the display substrate provided by any of the aforementioned embodiments, and the implementation principle and effect are similar, which will not be repeated here.

[0405] In an exemplary embodiment, the display device can be: a liquid crystal panel, electronic paper, an OLED panel, an active-matrix organic light emitting diode (AMOLED) panel, a mobile phone, a tablet computer, a television, a monitor, a laptop computer, a digital photo frame, a navigator, or any other product or component with a display function.

[0406] The drawings in this disclosure only relate to the structures involved in the embodiments of this disclosure, and other structures may refer to general designs.

[0407] For the sake of clarity, the thickness and size of layers or microstructures are exaggerated in the drawings used to describe the embodiments of the present disclosure. It will be understood that when an element such as a layer, film, region, or substrate is referred to as being "on" or "under" another element, the element can be "directly on" or "under" the other element, or intervening elements may be present.

[0408] Although the embodiments disclosed in this disclosure are as described above, the contents described are merely embodiments adopted to facilitate understanding of the disclosure and are not intended to limit the disclosure. Any person skilled in the art to which the disclosure belongs may make any modifications and changes in the form and details of the implementation without departing from the spirit and scope of the disclosure. However, the scope of patent protection of the disclosure shall still be based on the scope defined by the attached claims.

Claims

1. A pixel driving circuit, configured to drive a light emitting device, the pixel driving circuit comprising: A node control subcircuit, a light emission control subcircuit and a driving subcircuit; The node control subcircuit is electrically connected to the first node, the second node, the third node, the first scan signal line, the second scan signal line, the third scan signal line, the fourth scan signal line, the first initial signal line, the second initial signal line, the third initial signal line, the data signal line and the first power line, respectively, and is configured to drive the signal of the first node through the signal of the first initial signal line, the data signal line and the first power line under the control of the signal of the first scan signal line, the second scan signal line, the third scan signal line and the fourth scan signal line, provide the signal of the second initial signal line to the second node, and provide the signal of the third initial signal line to the third node; The light emitting control subcircuit is electrically connected to the first power line, the light emitting signal line and the third node respectively, and is configured to provide the signal of the first power line to the third node under the control of the signal of the light emitting signal line; The driving subcircuit is electrically connected to the first node, the second node and the third node respectively, and is configured to output a driving current to the second node under the control of the signals of the first node and the third node; The light emitting device is electrically connected to the second node and the second power line respectively; The node control subcircuit includes: an energy storage subcircuit, the energy storage subcircuit includes: a first capacitor and a second capacitor, the first capacitor and the second capacitor include: a first plate and a second plate; The first plate of the first capacitor is electrically connected to the first power line, and the second plate of the first capacitor is electrically connected to the fourth node; The first plate of the second capacitor is electrically connected to the first node, and the second plate of the second capacitor is electrically connected to the fourth node.

2. The pixel driving circuit according to claim 1, wherein: The node control subcircuit also includes: a reset subcircuit, a compensation subcircuit and a write subcircuit; The reset subcircuit is electrically connected to the first node, the second node, the third node, the first scan signal line, the second scan signal line, the third scan signal line, the first initial signal line, the second initial signal line and the third initial signal line, respectively, and is configured to provide the signal of the first initial signal line to the first node under the control of the signal of the first scan signal line, provide the signal of the second initial signal line to the second node under the control of the signal of the second scan signal line, and provide the signal of the third initial signal line to the third node under the control of the signal of the third scan signal line; The compensation subcircuit is electrically connected to the third node, the fourth node and the first scanning signal line respectively, and is configured to provide the signal of the third node to the fourth node under the control of the signal of the first scanning signal line, so as to compensate the signal of the fourth node; The writing sub-circuit is electrically connected to the fourth node, the fourth scanning signal line and the data signal line respectively, and is configured to provide the signal of the data signal line to the fourth node under the control of the signal of the fourth scanning signal line.

3. The pixel driving circuit according to claim 2, wherein: The reset subcircuit comprises: a first transistor, a second transistor and a third transistor; A gate electrode of the first transistor is electrically connected to the first scan signal line, a first electrode of the first transistor is electrically connected to the first initial signal line, and a second electrode of the first transistor is electrically connected to the first node; A gate electrode of the second transistor is electrically connected to the second scan signal line, a first electrode of the second transistor is electrically connected to the second initial signal line, and a second electrode of the second transistor is electrically connected to the second node; A gate electrode of the third transistor is electrically connected to the third scan signal line, a first electrode of the third transistor is electrically connected to the third initial signal line, and a second electrode of the second transistor is electrically connected to the third node.

4. The pixel driving circuit according to claim 2, wherein: The compensation sub-circuit includes: a fourth transistor, and the writing transistor includes: a fifth transistor; A gate electrode of the fourth transistor is electrically connected to the first scan signal line, a first electrode of the fourth transistor is electrically connected to the fourth node, and a second electrode of the fourth transistor is electrically connected to the third node; A gate electrode of the fifth transistor is electrically connected to the fourth scan signal line, a first electrode of the fifth transistor is electrically connected to the data signal line, and a second electrode of the fifth transistor is electrically connected to the fourth node.

5. The pixel driving circuit according to claim 1, wherein: The node control subcircuit further includes: a first transistor to a fifth transistor, the driving subcircuit includes: a sixth transistor, and the light emitting control subcircuit includes: a seventh transistor; A gate electrode of the first transistor is electrically connected to the first scan signal line, a first electrode of the first transistor is electrically connected to the first initial signal line, and a second electrode of the first transistor is electrically connected to the first node; A gate electrode of the second transistor is electrically connected to the second scan signal line, a first electrode of the second transistor is electrically connected to the second initial signal line, and a second electrode of the second transistor is electrically connected to the second node; A gate electrode of the third transistor is electrically connected to the third scan signal line, a first electrode of the third transistor is electrically connected to the third initial signal line, and a second electrode of the second transistor is electrically connected to the third node; A gate electrode of the fourth transistor is electrically connected to the first scan signal line, a first electrode of the fourth transistor is electrically connected to the fourth node, and a second electrode of the fourth transistor is electrically connected to the third node; A gate electrode of the fifth transistor is electrically connected to the fourth scan signal line, a first electrode of the fifth transistor is electrically connected to the data signal line, and a second electrode of the fifth transistor is electrically connected to the fourth node; A gate electrode of the sixth transistor is electrically connected to the first node, a first electrode of the sixth transistor is electrically connected to the third node, and a second electrode of the sixth transistor is electrically connected to the second node; A gate electrode of the seventh transistor is electrically connected to the light emitting signal line, a first electrode of the seventh transistor is electrically connected to the first power supply line, and a second electrode of the seventh transistor is electrically connected to the third node.

6. The pixel driving circuit according to claim 5, wherein: The first transistor, the fourth transistor and the fifth transistor are oxide transistors and are N-type transistors, and the second transistor, the third transistor, the sixth transistor and the seventh transistor are P-type transistors; The length of the channel region of the active layer of the sixth transistor is greater than the length of the channel region of the active layer of any one of the first to fifth transistors and the seventh transistor, the width of the channel region of the active layer of the sixth transistor is greater than the width of the channel region of the active layer of any one of the first to fifth transistors and the seventh transistor, and the width-to-length ratio of the channel region of the active layer of the sixth transistor is less than the width-to-length ratio of the channel region of the active layer of any one of the first to fifth transistors and the seventh transistor.

7. The pixel driving circuit according to claim 1 or 6, wherein: The signal of the first scanning signal line and the signal of the second scanning signal line are mutually inverted signals; When the signal of the third scanning signal line is a valid level signal, the signals of the first scanning signal line and the second scanning signal line are valid level signals, and the signals of the fourth scanning signal line and the light emitting signal line are invalid level signals; When the signal of the fourth scanning signal line is a valid level signal, the signals of the first scanning signal line, the second scanning signal line, the third scanning signal line and the light emitting signal line are invalid level signals; When the signal of the light emitting signal line is a valid level signal, the signals of the first scanning signal line, the second scanning signal line, the third scanning signal line and the fourth scanning signal line are invalid level signals; The signal of any one of the first scanning signal line and the second scanning signal line is a valid level signal. The duration of the signal is greater than the duration of the signal of any one of the third scanning signal line and the fourth scanning signal line being a valid level signal.

8. The pixel driving circuit according to claim 7, wherein: The signal of the first initial signal line and the signal of the second initial signal line are the same signal, and the voltage value of the signal of the first initial signal line is smaller than the voltage value of the signal of the third initial signal line; A voltage value of a signal on the second initial signal line is greater than a voltage value of a signal on the second power line.

9. A display substrate, comprising: A substrate and a plurality of sub-pixels arranged on the substrate, at least one sub-pixel comprising: a pixel driving circuit as claimed in any one of claims 1 to 8 and a light-emitting device driven by the pixel driving circuit.

10. The display substrate according to claim 9, further comprising: A driving circuit layer and a light emitting structure layer are sequentially stacked on the substrate, wherein the driving circuit layer includes: a plurality of pixel driving circuits, a plurality of light emitting signal lines, a plurality of first initial signal lines, a plurality of second initial signal lines, a plurality of third initial signal lines, a plurality of first scanning signal lines, a plurality of second scanning signal lines, a plurality of third scanning signal lines, a plurality of fourth scanning signal lines, a plurality of first power supply lines and a plurality of data signal lines, and the light emitting structure layer includes: a light emitting device; Any one of the light-emitting signal line, the first initial signal line, the second initial signal line, the third initial signal line, the first scanning signal line, the second scanning signal line, the third scanning signal line and the fourth scanning signal line extends at least partially along the first direction, and any one of the first power line and the data signal line extends at least partially along the second direction, and the first direction and the second direction intersect.

11. The display substrate according to claim 10, wherein: The driving circuit layer further includes: a plurality of power connection lines extending at least partially along the first direction; At least one power connection line is respectively connected to the pixel driving circuit and the at least one first power line.

12. The display substrate according to claim 11, wherein: The driving circuit layer further includes: a first connecting electrode; The first connecting electrodes are respectively connected to the pixel driving circuit, the power connection line and the first power line; The orthographic projection of the first connecting electrode on the substrate at least partially overlaps with the orthographic projections of the power connection line and the first power line on the substrate.

13. The display substrate according to claim 12, wherein: The first initial signal line and the second initial signal line are the same signal line, and the driving circuit layer further comprises: a plurality of initial connection lines extending at least partially along the second direction; At least one initial connection line, connected to the pixel driving circuit and at least one first initial signal line respectively; The orthographic projection of the initial connection line on the substrate is located between the orthographic projections of the data signal lines connected to two adjacent columns of sub-pixels connected by the initial connection line on the substrate.

14. The display substrate according to claim 13, wherein: The first scanning signal line includes: a first sub-signal line and a second sub-signal line electrically connected to each other, and the fourth scanning signal line includes: a third sub-signal line and a fourth sub-signal line electrically connected to each other; The orthographic projection of the first sub-signal line on the substrate at least partially overlaps with the orthographic projection of the second sub-signal line on the substrate, and the orthographic projection of the third sub-signal line on the substrate at least partially overlaps with the orthographic projection of the fourth sub-signal line on the substrate.

15. The display substrate according to claim 14, wherein: The pixel driving circuit comprises: first to seventh transistors and a first capacitor and a second capacitor, the first capacitor and the second capacitor respectively comprise: a first electrode plate and a second electrode plate, and the driving circuit layer comprises a first semiconductor layer, a first conductive layer, a second conductive layer, a second semiconductor layer, a third conductive layer, a fourth conductive layer and a fifth conductive layer sequentially arranged on a substrate; The first semiconductor layer includes at least: an active layer of a second transistor, an active layer of a third transistor, an active layer of a sixth transistor, and an active layer of a seventh transistor located in at least one sub-pixel; The first conductive layer at least includes: a light emitting signal line, a second scanning signal line, a third scanning signal line, and a first plate of a first capacitor located in at least one sub-pixel, a first plate of a second capacitor, a gate electrode of a second transistor, a gate electrode of a third transistor, a control electrode of a sixth transistor, and a gate electrode of a seventh transistor The second conductive layer at least includes: a first sub-signal line of the first scanning signal line, a third sub-signal line of the fourth scanning signal line, and a second plate of a first capacitor and a second plate of a second capacitor located in at least one sub-pixel; The second semiconductor layer includes at least: an active layer of a first transistor, an active layer of a fourth transistor, and an active layer of a fifth transistor located in at least one sub-pixel; The third conductive layer at least includes: a second sub-signal line of the first scanning signal line, a fourth sub-signal line of the fourth scanning signal line, a power connection line, a first initial signal line, a second initial signal line and a third initial signal line; The fourth conductive layer at least includes: an initial connection line, a first connection electrode located at at least one sub-pixel, and first and second electrodes of the first to seventh transistors; The fifth conductive layer at least includes: a first power line and a data signal line.

16. The display substrate according to claim 15, wherein: The driving circuit layer further includes: a light shielding layer disposed between the substrate and the first semiconductor layer; The light shielding layer at least includes: a light shielding structure located in at least one sub-pixel, and the light shielding structures of adjacent sub-pixels are connected to each other; The orthographic projection of the light shielding structure on the substrate at least partially overlaps with the orthographic projection of the gate electrode of the sixth transistor on the substrate.

17. The display substrate according to claim 16, wherein: The light shielding structure comprises: a first light shielding portion, a second light shielding portion, a third light shielding portion and a fourth light shielding portion; The orthographic projection of the first light-shielding portion on the substrate at least partially overlaps with the orthographic projection of the active layer of the sixth transistor on the substrate, the orthographic projection of the second light-shielding portion on the substrate at least partially overlaps with the orthographic projection of the active layer of the seventh transistor on the substrate, the orthographic projection of the third light-shielding portion on the substrate at least partially overlaps with the orthographic projection of the active layer of the third transistor on the substrate, and the orthographic projection of the fourth light-shielding portion on the substrate at least partially overlaps with the orthographic projection of the active layer of the second transistor on the substrate.

18. The display substrate according to claim 16, wherein: The light shielding structure comprises: a light shielding portion, a first light shielding connecting portion, a second light shielding connecting portion, a third light shielding connecting portion and a fourth light shielding connecting portion; The orthographic projection of the light-shielding portion on the substrate at least partially overlaps with the orthographic projection of the active layer of the sixth transistor on the substrate, and the orthographic projection of any one of the first light-shielding connection portion, the second light-shielding connection portion, the third light-shielding connection portion and the fourth light-shielding connection portion on the substrate does not overlap with the orthographic projection of any one of the active layer of the second transistor, the active layer of the third transistor and the active layer of the seventh transistor on the substrate.

19. The display substrate according to claim 17 or 18, wherein: The light emitting signal line connected to the sub-pixel is located on the side where the first plate of the second capacitor of the sub-pixel is away from the first plate of the first capacitor of the sub-pixel, the second scanning signal line connected to the sub-pixel is located on the side where the first plate of the first capacitor of the sub-pixel is away from the first plate of the second capacitor of the sub-pixel, and the third scanning signal line connected to the sub-pixel is located on the side where the second scanning signal line connected to the sub-pixel is away from the first plate of the first capacitor of the sub-pixel.

20. The display substrate according to claim 19, wherein: The second electrode plate of the first capacitor and the second electrode plate of the second capacitor are an integrated structure connected to each other, and are provided with a first via hole and a second via hole, the first via hole exposes the first electrode plate of the first capacitor, and the second via hole exposes the second electrode plate of the second capacitor; The third sub-signal line of the fourth scanning signal line is located at a side of the first sub-signal line of the first scanning signal line away from the integrated structure of the second electrode plate of the first capacitor and the second electrode plate of the second capacitor; The orthographic projection of the first sub-signal line of the first scanning signal line connected to the sub-pixel on the substrate is located between the orthographic projection of the light-emitting signal line connected to the sub-pixel on the substrate and the orthographic projection of the first plate of the second capacitor of the sub-pixel on the substrate, and the orthographic projection of the third sub-signal line of the fourth scanning signal line connected to the sub-pixel on the substrate is located on the side of the orthographic projection of the light-emitting signal line connected to the sub-pixel on the substrate away from the orthographic projection of the first plate of the second capacitor of the sub-pixel on the substrate.

21. The display substrate according to claim 20, wherein: The second sub-signal line of the first scanning signal line connected to the sub-pixel is located on one side of the fourth sub-signal line of the fourth scanning signal line connected to the sub-pixel, the power supply connection line connected to the sub-pixel is located on one side of the second sub-signal line of the first scanning signal line connected to the sub-pixel away from the fourth sub-signal line of the fourth scanning signal line connected to the sub-pixel, the first initial signal line connected to the sub-pixel is located on one side of the power supply connection line connected to the sub-pixel away from the second sub-signal line of the first scanning signal line connected to the sub-pixel, and the third initial signal line connected to the sub-pixel is located on one side of the first initial signal line connected to the sub-pixel away from the power supply connection line connected to the sub-pixel; The positive projection of the fourth sub-signal line of the fourth scanning signal line connected to the sub-pixel on the substrate is located on a side where the positive projection of the light emitting signal line connected to the sub-pixel on the substrate is away from the positive projection of the first electrode plate of the second capacitor of the sub-pixel on the substrate; The positive projection of the second sub-signal line of the first scanning signal line connected to the sub-pixel on the substrate is located between the positive projection of the light-emitting signal line connected to the sub-pixel on the substrate and the positive projection of the first electrode plate of the second capacitor of the sub-pixel on the substrate; The orthographic projection of the power connection line connected to the sub-pixel on the substrate at least partially overlaps with the orthographic projection of the integrated structure of the second electrode plate of the first capacitor of the sub-pixel and the second electrode plate of the second capacitor on the substrate, and is located between the orthographic projection of the first sub-signal line of the first scanning signal line on the substrate and the orthographic projection of the second scanning signal line on the substrate; The positive projection of the first initial signal line connected to the sub-pixel on the substrate at least partially overlaps with the positive projection of the second scanning signal line connected to the sub-pixel on the substrate, and is located between the positive projection of the first plate of the first capacitor of the sub-pixel on the substrate and the positive projection of the third scanning signal line connected to the sub-pixel on the substrate; The positive projection of the third initial signal line connected to the sub-pixel on the substrate at least partially overlaps with the positive projection of the third scanning signal line connected to the sub-pixel on the substrate, and is located on the side of the positive projection of the second scanning signal line connected to the sub-pixel on the substrate away from the positive projection of the first plate of the first capacitor of the sub-pixel on the substrate.

22. The display substrate according to claim 21, wherein: The power connection line includes: a signal main line, a first protrusion, a second protrusion and a third protrusion, the signal main line extends along a first direction, the first protrusion is located on a side of the signal main line close to the second sub-signal line of the first scanning signal line, the second protrusion and the third protrusion are located on a side of the signal main line away from the second sub-signal line of the first scanning signal line, and the second protrusion and the third protrusion are arranged along the first direction; The orthographic projections of the second protrusion and the third protrusion on the substrate at least partially overlap with the orthographic projections of the integrated structure of the second electrode plate of the first capacitor and the second electrode plate of the second capacitor on the substrate; The orthographic projection of the first via hole on the substrate is located between the orthographic projection of the second protrusion on the substrate and the orthographic projection of the third protrusion on the substrate.

23. The display substrate according to claim 22, wherein: The orthographic projection of the first connection electrode on the substrate at least partially overlaps with the orthographic projections of the signal main line, the second protrusion and the third protrusion of the power connection line on the substrate, and does not overlap with the orthographic projection of the first protrusion of the power connection line on the substrate.

24. The display substrate according to claim 22 or 23, wherein: The orthographic projection of the first power line on the substrate at least partially overlaps with the orthographic projection of the second electrode plate of the first capacitor and the integrated structure of the second electrode plate of the second capacitor, the first connecting electrode, the signal main body portion of the power connecting line, and the second protruding portion on the substrate; The orthographic projection of the first power supply line connected to the sub-pixel on the substrate is located on a side of the data signal line connected to the sub-pixel away from the initial connection line connected to the sub-pixel.

25. A display device comprising: A display substrate as claimed in any one of claims 9 to 24.

26. A driving method of a pixel driving circuit, configured to drive the pixel driving circuit according to any one of claims 1 to 8, the method comprising: The node control subcircuit drives the signal of the first node through the signal of the first initial signal line, the data signal line and the first power line under the control of the signal of the first scanning signal line, the second scanning signal line, the third scanning signal line and the fourth scanning signal line, provides the signal of the second initial signal line to the second node, and provides the signal of the third initial signal line to the third node; The light-emitting control subcircuit provides the signal of the first power line to the third node under the control of the signal of the light-emitting signal line, and the driving subcircuit outputs the driving current to the second node under the control of the signals of the first node and the third node.

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