Bias temperature instability (bti) measurement system

Abstract

A bias temperature instability (BTI) measurement system is disclosed. One example includes a method for performing a BTI test procedure (106) of a DUT (110). The method includes coupling a contact pad of a DUT circuit (112) to a test device (102). The DUT circuit (112) includes a differential input stage and a gain stage. The differential input stage includes a differential pair of transistors fabricated to match the DUT (110). The method also includes providing a BTI stress from the test apparatus (102) to one of the differential pairs of transistor devices to simulate BTI aging of a respective one of the differential pairs of transistors. The method also includes providing a differential input voltage from the test device (102) to the differential input stage. The method further includes measuring, via the test apparatus (102), an output voltage at an output of the gain stage in response to the differential input voltage to determine a threshold voltage change between the differential pair of transistor devices.

Description

Technical Field

[0001] This manual relates to the testing of electronic circuits, and more specifically to BTI measurement systems. Background Technology

[0002] Semiconductor devices (e.g., integrated circuits (ICs)) may experience parameter shifts throughout their operational lifespan. Manufacturers of such devices often want to predict these parameter shifts as a measure of device reliability, allowing for the specification of device parameter limits to detect potential failures due to deviations from these limits. For high-precision devices, such as high-precision operational amplifiers (OP-AMPs), parameter shifts may involve offset voltage shifts and can be extremely low values ​​(e.g., in the microvolt range). Particularly for transistor devices, one way to predict parameter shifts is to perform bias temperature instability (BTI) testing. BTI testing can be performed on semiconductor devices manufactured in batches on semiconductor wafers. During the testing phase, the manufactured ICs may undergo various operational tests, such as BTI testing, using test equipment. Summary of the Invention

[0003] One example includes a method for performing a bias temperature instability (BTI) test procedure on a device under test (DUT). The method includes coupling contact pads of the DUT circuitry to a test apparatus. The DUT circuitry includes a differential input stage and a gain stage. The differential input stage includes differential pairs fabricated to match transistor devices of the DUT. The method further includes providing BTI stress from the test apparatus to one of the differential pairs of the transistor devices to simulate BTI aging of a corresponding one of the differential pairs of the transistor devices. The method also includes providing a differential input voltage from the test apparatus to the differential input stage. The method further includes measuring an output voltage at the output of the gain stage via the test apparatus in response to the differential input voltage to determine a threshold voltage change between the differential pairs of the transistor devices.

[0004] Another example includes a circuit. The circuit includes a current source stage having a first input, a second input, a first output, and a second output. The first input of the current source stage is adapted to receive a bias voltage, and the second input of the current source stage is adapted to receive a bias control voltage. The circuit also includes a differential input stage comprising a first input transistor device and a second input transistor device. The first input transistor device may have a control input, an input, an output, and a terminal. The second input transistor device may have a control input, an input, an output, and a terminal. The control input of the first input transistor device is adapted to receive a first control input voltage, and the control input of the second input transistor device is adapted to receive a second control input voltage. The input of each of the first and second input transistor devices is coupled to a first output of the current source stage, and the terminal of the first input transistor device is coupled to a terminal of the second input transistor device. The circuit also includes a current mirror stage having a first input, a second input, and an output. The first input of the current mirror stage is coupled to the output of the first input transistor device, and the second input of the current mirror stage is coupled to the output of the second input transistor device. The circuit also includes a gain stage having a first input, a second input, and an output. The first input of the gain stage can be coupled to the output of the second input transistor device, the second input of the gain stage can be coupled to the second output of the current source stage, and the output of the gain stage can be coupled to the output of the current mirror stage. The circuit further includes a first contact pad coupled to the control input of the first input transistor device, a second contact pad coupled to the control input of the second input transistor device, a third contact pad coupled to the second input of each of the first and second input transistor devices, a fourth contact pad coupled to the output of the first input transistor device, a fifth contact pad coupled to the output of the second input transistor device, a sixth contact pad coupled to the terminals of the first and second input transistor devices, and a seventh contact pad coupled to the second input of the gain stage.

[0005] Another example includes a test system for performing a BTI test process on multiple DUTs. The system includes a semiconductor wafer. The semiconductor wafer includes multiple circuit dies. Each of the circuit dies includes at least one DUT. The semiconductor wafer also includes at least one DUT circuit, each comprising a differential input stage and a gain stage. The differential input stage includes differential pairs fabricated to match transistor devices to the DUT. The system further includes test equipment, with contact pads of the DUT circuit arranged to couple to the test equipment. The test equipment can be configured to provide BTI stress to one of the differential pairs of transistor devices to simulate BTI aging of a corresponding one of the differential pairs of transistor devices, provide a differential input voltage to the differential pairs of transistor devices, and measure an output voltage at the output of the gain stage in response to the differential input voltage to determine a threshold voltage change between the differential pairs of transistor devices.

[0006] Another example includes a semiconductor wafer. The wafer includes a plurality of circuit dies. Each of the circuit dies includes at least one DUT (Device Under Test). The wafer also includes a plurality of DUT circuits. Each of the DUT circuits includes a current source stage configured to provide a first current and a second current. Each of the DUT circuits also includes a differential input stage, the differential input stage including differential pairs of transistor devices, each configured to conduct a portion of the first current in response to receiving a corresponding differential input voltage. Each of the differential pairs of transistor devices can be fabricated to match the at least one DUT in each of the circuit dies. Each of the DUT circuits also includes a current mirror stage coupled to the differential input stage. The current mirror stage includes a bias terminal through which the portion of the first current is provided. Each of the DUT circuits also includes a gain stage coupled to the bias terminal and configured to provide an output voltage based on the second current in response to the differential input voltage. Each of the DUT circuits further includes a contact pad configured to provide BTI stress to one of the differential pairs of the transistor device to perform BTI testing of at least one DUT for each of the circuit dies via a corresponding one of the DUT circuits. Attached Figure Description

[0007] Figure 1 This is an example block diagram of a circuit testing system.

[0008] Figure 2 This is an example diagram of a semiconductor wafer.

[0009] Figure 3 This is an example block diagram of a device under test (DUT) circuit.

[0010] Figure 4 This is an example diagram of a DUT circuit.

[0011] Figure 5 This is an example of a voltage curve.

[0012] Figure 6 This is an instance of a method used to test the DUT. Detailed Implementation

[0013] This specification relates to the testing of electronic circuits, and more specifically to bias temperature instability (BTI) measurement systems. Circuit test systems can perform testing of one or more devices-under-test (DUTs) during the testing phase of semiconductor circuit device fabrication, for example, at the semiconductor wafer level. Test equipment can be electrically coupled to contact pads of the DUT circuitry fabricated on the wafer. As described in more detail herein, test equipment can provide BTI testing of transistor devices of the DUT circuitry, said transistor devices being fabricated to match the DUT. As described herein, the term "fabrication match" describes a relationship between two semiconductor devices (e.g., transistor devices) that are fabricated approximately identically or to scale, such that manufacturing process tolerances and temperature effects can affect the two semiconductor devices in approximately the same manner. Therefore, test equipment can perform BTI testing of transistor devices of the DUT circuitry to simulate the effects of aging on the DUT on the semiconductor wafer.

[0014] The DUT circuit may include a differential input stage comprising a pair of differential transistors, each of the transistor devices in the pair being fabricated matched to each other and fabricated matched to the DUT on a semiconductor wafer. The DUT circuit may also include a gain stage configured to provide an output voltage in response to a differential input voltage provided to the differential input stage and thus to the differential pair of transistor devices. For BTI testing, a test apparatus may be electrically coupled to the contact pads of the DUT circuit to measure the output voltage in response to the provision of a differential input voltage. For example, the test apparatus may provide a continuously variable amplitude of one input voltage relative to a fixed amplitude of another differential input voltage and measure the resulting continuously changing output voltage. Therefore, the test apparatus can obtain a baseline measurement of the output voltage.

[0015] After obtaining a baseline measurement of the output voltage, the test equipment can apply BTI stress to one of the transistor devices in a differential transistor pair. As described herein, the term "BTI stress" refers to a manner that simulates aging of the transistor device. BTI stress can be applied in various ways to simulate aging, such as by applying a predefined voltage to the control input (e.g., the gate) of the transistor device at a predefined temperature, while grounding all other terminals of the transistor device (e.g., including substrate body connections). For example, this BTI stress can cause the breakdown of silicon-hydrogen bonds at the polysilicon gate due to the accumulation of electron tunneling from the substrate of the transistor device, thereby introducing defects into the transistor device. For instance, BTI stress on the transistor device can cause a threshold voltage V... T The increase and saturation current I DSAT The reduction in this value can provide characteristic information as the shift of the prediction parameters of the DUT on the wafer.

[0016] To complete a BTI test, the test equipment can again measure the output voltage in response to the application of a differential input voltage. For example, after obtaining a continuously variable output voltage during a baseline measurement, the test equipment can measure the output voltage at a specific amplitude of the differential input voltage. Therefore, after applying BTI stress, the test equipment can measure the output voltage at the same specific amplitude of the differential input voltage to determine the difference in threshold voltages between the differential transistor pairs caused by the BTI stress.

[0017] For example, test equipment can measure the gain of the DUT circuitry based on the slope of a continuously variable output voltage (e.g., during baseline determination). Therefore, the test equipment can divide the output voltage difference by the gain of the DUT circuitry to determine the change in the threshold voltage of a BTI-stressed transistor device. Due to the gain of the DUT circuitry, the change in threshold voltage can be measured in the microvolt range, while conventional parameter shifting modeling techniques can only achieve millivolt-level accuracy. Therefore, the change in the threshold voltage of a BTI-stressed transistor device corresponds to a predicted parameter shift of the DUT on the wafer.

[0018] Figure 1 This is an example block diagram of a circuit test system 100. The circuit test system 100 can be implemented to provide bias temperature instability (BTI) testing of one or more devices under test (DUTs), as described herein. The circuit test system 100 includes a test apparatus 102 that can correspond to any of a variety of circuit test equipment (e.g., an automated test apparatus (ATE)). The test apparatus 102 is configured to perform various tests on the semiconductor wafer 104 after the semiconductor wafer 104 has been manufactured. Figure 1In this example, test equipment 102 is configured to perform BTI test procedure 106 and other test procedures 108. Other test procedures 108 may include any of a variety of standard tests on the manufactured semiconductor device, such as parameter testing and current testing.

[0019] exist Figure 1 In this example, semiconductor wafer 104 includes multiple device under test (DUT) 110s and at least one DUT circuit 112. As described herein, test apparatus 102 is configured to perform a BTI test procedure 106 on the DUT circuit 112 to provide parameter shift data of the DUT 110s based on the results of the BTI test procedure 106 on the DUT circuit 112. Test apparatus 102 includes: a processor 114 containing instructions on how to perform the BTI test procedure 106 and other test procedures 108; and a memory 116 for recording the results of the BTI test procedure 106 and other test procedures 108. Therefore, parameter shift data of the DUT 110s can be stored in and accessed from the memory 116.

[0020] Each of the DUT circuits 112 may include a differential input stage, which includes a differential transistor pair. Each of the transistor devices in the differential transistor pair may be fabricated to match each other and to match a DUT 110 on semiconductor wafer 104. Each of the DUT circuits 112 may also include a gain stage configured to provide an output voltage in response to a differential input voltage provided to the differential input stage and thus to the differential pair of transistor devices. For BTI testing, test equipment may be electrically coupled to contact pads of the DUT circuits 112 to measure the output voltage in response to the provision of a differential input voltage. For example, the DUT circuits 112 may include contact pads at each node to facilitate BTI stress in one of the transistor devices of the differential input stage to facilitate the BTI testing process 106.

[0021] As described in more detail herein, a BTI test procedure 106 for a given DUT circuit 112 may include measurements of the output voltage before and after the BTI stress provided during the BTI test procedure 106. For example, the test apparatus 102 may obtain a continuously variable output voltage during baseline measurements, from which the test apparatus 102 may determine the gain of the corresponding DUT circuit 112 and may measure the output voltage at a specific amplitude of the differential input voltage. Thus, after the BTI stress is provided, the test apparatus may measure the output voltage at the same specific amplitude of the differential input voltage to determine the difference in threshold voltage between the differential transistor pairs caused by the BTI stress. Due to the high gain of the DUT circuit 112 measured by the test apparatus 102, the change in threshold voltage can be measured in the microvolt range, whereas conventional parameter shifting modeling techniques can only achieve millivolt-level accuracy. Therefore, based on the fabrication matching of the transistor device based on the DUT circuit 112 with the DUT 110 on the semiconductor wafer 104, the change in threshold voltage of the BTI-stressed transistor device may correspond to a predicted parameter shift in each of the DUTs 110 on the semiconductor wafer 104.

[0022] Figure 2 This is an example diagram of a semiconductor wafer 200. The semiconductor wafer 200 may correspond to... Figure 1 The example is semiconductor wafer 104. Therefore, in the following... Figure 2 In the examples, refer to Figure 1 Examples.

[0023] exist Figure 2 In this example, semiconductor wafer 200 is shown as a disk, but semiconductor wafer 200 can have any of a variety of shapes. Semiconductor wafer 200 includes a plurality of circuit dies 202 distributed across its top surface. Each of the circuit dies 202 may contain at least one DUT (Device Underlying Device), for example... Figure 1 The example is DUT 110. Semiconductor wafer 200 also includes multiple DUT circuits 204 similarly distributed across the top surface of semiconductor wafer 200, for example... Figure 1 The DUT circuit 112 in the example. In Figure 2 In the examples, the DUT circuitry 204 can be distributed around the surface of the semiconductor wafer 200, for example, uniformly distributed in an array and / or approximately equidistant from each other. Furthermore, the examples demonstrate the number and distribution of the circuit dies 202 and DUT circuitry 204, allowing the dies 202 and DUT circuitry 204 to be arranged in any of a variety of ways, and the number can be significantly greater than [a certain number]. Figure 2 The number shown in the examples.

[0024] As described above, DUT circuit 204 may include differential pairs of transistor devices fabricated to match the DUTs of each of the circuit dies 202 on semiconductor wafer 200. Therefore, the differential pairs of transistor devices may be fabricated approximately identically or proportionally to the DUTs of each of the circuit dies 202, such that manufacturing tolerances and temperature effects may affect the two semiconductor devices in approximately the same manner. For example, the transistor devices of DUT circuit 204 may be fabricated to most closely match the DUT on the nearest side of the circuit die 202 in DUT circuit 204 to provide the closest possible manufacturing process match.

[0025] As described herein, test equipment 102 can be configured to perform individual BTI test procedures 106 on each of the DUT circuits 204. To accurately model the parameter shifts of the DUT in the circuit die 202, test equipment 102 can provide different parameters of the BTI stress provided in each of the individual BTI test procedures 106. Therefore, the parameter shifts of the DUT in the circuit die 202 can be modeled for different operating conditions and in different environments.

[0026] For example, test equipment 102 can apply BTI stress to one of the transistor devices in a differential transistor pair by providing a predefined voltage to the control input (e.g., the gate) of the transistor device at a predefined temperature, while grounding all other terminals of the transistor device (e.g., including substrate body connections). The combination of predefined voltage and predefined temperature can be different for each BTI test procedure 106. For example, DUT circuits 204 can each be fabricated for the specific purpose of providing a single BTI test procedure 106.

[0027] Assuming that the BTI stress of one of the transistor devices in each of the DUT circuits 204 effectively causes the transistor device to be permanently operationally adjusted (e.g., as in lifetime simulation), the DUT circuit 204 can be discarded after the BTI test process 106 (e.g., after the single-stage testing of the circuit die 202). However, by including a number of DUT circuits 204 that can adapt to each combination of predefined voltages and predefined temperatures for each BTI stress of the transistor devices in one of the DUT circuits 204, the BTI test process 106 can jointly model the parametric shifts of the DUT in the circuit die 202 under any of a variety of operating conditions and environments. As another example, the semiconductor wafer 200 may include a number of DUT circuits 204 that can facilitate multiple instances of each combination of voltages and temperatures for the BTI stress in the BTI test process 106 for each of the corresponding multiple sets of DUT circuits 204. Therefore, multiple instances of each combination of voltage and temperature can be applied to the DUT on the corresponding circuit die 202 on the proximal side of each of the multiple sets of DUT circuits 204 to accommodate the manufacturing process matching of the proximal DUT with respect to the DUT circuit 204.

[0028] Figure 3 This is an example block diagram of DUT circuit 300. DUT circuit 300 may correspond to one of DUT circuits 112 or one of DUT circuits 204. Therefore, in Figure 3 Refer to the following description of the instance. Figure 1 and 2 Examples.

[0029] The DUT circuit 300 can be configured as an operational amplifier (OP-AMP) comprising a current source stage 302, a differential input stage 304, a current mirror stage 306, and a gain stage 308. The current source stage 302 is configured to respond to a source voltage V. DD and bias voltage V INT The differential input stage 304 provides at least one current. The differential input stage 304 includes a pair of differential transistors 310 (“transistor pairs”), each of which is configured to conduct a portion of one of the currents supplied from the current source stage 302 in response to a differential input voltage, which is represented as a first input voltage V. IN_P Second input voltage V IN_N As described above, the differential transistor pair 310 is manufactured matched (e.g., approximately identical) to each other and manufactured matched to the DUT of the circuit die 202.

[0030] The current mirror stage 306 is configured to conduct a portion of a current supplied from the differential input stage 304 under approximately equal bias inputs at the respective control terminals (e.g., gates) of the current mirror transistor. The gain stage 308 is configured to provide an output voltage V based on a current supplied from the current source stage 302 (e.g., a current different from the current supplied through the differential input stage 304). OUT Gain stage 308 may include transistor devices that set the gain of DUT circuit 300 (e.g., based on gate size characteristics) and are controlled by differential input stage 304. Therefore, the output voltage V... OUT It can have a first input voltage V IN_P With the second input voltage V IN_N The magnitude difference between the amplitudes. In this way, based on the gain of the DUT circuit 300 and based on the arrangement of the differential transistor pairs 310, the threshold voltage difference between the differential transistor pairs 310 caused by the BTI stress of one of the transistor devices of the differential transistor pairs 310 can be measured with extremely high accuracy (e.g., in the microvolt range).

[0031] Figure 4 This is an example diagram of DUT circuit 400. DUT circuit 400 in... Figure 4 In the example shown, it is an OP-AMP. DUT circuit 400 contains multiple transistor devices (hereinafter referred to as "transistors") shown as PMOS transistors. However, other arrangements or types of transistors may actually be implemented. DUT circuit 400 may correspond to one of DUT circuits 112, one of DUT circuits 204, and / or DUT circuit 300. Therefore, in the following... Figure 4 Reference in the description of the instance Figures 1 to 3 Examples.

[0032] The DUT circuit 400 includes a current source stage 402, which includes a first source transistor P1 and a second source transistor P2. Based on the source voltage V... DD and bias voltage V INT A first source transistor P1 is configured to conduct a first current I1, and a second source transistor P2 is configured to conduct a second current I2. For example, source transistors P1 and P2 may be manufactured matched (e.g., approximately identical) relative to each other, such that the first current I1 and the second current I2 have equal magnitudes.

[0033] The DUT circuit also includes a differential input stage 404, which includes a first input transistor P3 and a second input transistor P4. As described above, input transistors P3 and P4 can be manufactured to match each other (e.g., approximately identical) and to match the DUT to the circuit die 202. The first input transistor P3 is powered by an input voltage V. IN_PThe transistor P4 is controlled and has a source coupled to the first source transistor P1, and the second transistor P4 is controlled by the input voltage V. IN_N The transistor controls and also has a source coupled to the first source transistor P1. Therefore, each of the input transistors P3 and P4 is configured to conduct a portion of the first current, respectively shown as I. 1_1 and I 1_2 .

[0034] The DUT circuit 400 also includes a current mirror stage 406, which includes a first mirror transistor P5 and a second mirror transistor P6. For example, mirror transistors P5 and P6 may be manufactured matched (e.g., approximately identical) relative to each other. Figure 4 In this example, the first mirror transistor P5 is gate-source coupled to act as a conductor for the first portion of the current I. 1_1 The transistor is a diode-connected transistor. The second mirror transistor P6 has a gate coupled to the gate-source coupling of the first mirror transistor P5, and a drain coupled to the drain of the first mirror transistor P5. Therefore, the second mirror transistor P6 mirrors the first mirror transistor P5 by having the same control bias to conduct a second portion of the current I. 1_2 Additionally, the DUT circuit 400 includes a bias terminal 408 disposed between the source of the second mirror transistor P6 and the drain (e.g., output) of the second input transistor P4.

[0035] The DUT circuit 400 further includes a gain stage 410, which includes a gain transistor P7 and a resistor R1 and a capacitor C1 arranged in series between the gate and source of the gain transistor P7. The gate of the gain transistor P7 is coupled to a bias terminal 408, the drain of the gain transistor P7 is coupled to the drains of mirror transistors P5 and P6, and the source of the gain transistor P7 is coupled to an output terminal 412, which is also coupled to the drain of a second source transistor P2. Therefore, the gain transistor P7 is configured to operate based on a second current I2 provided from the second source transistor P2 and in response to a second partial current I. 1_2 The bias voltage V at the bias terminal 408 B The output voltage V is provided from the output terminal 412. OUT For example, the gain transistor P7 may have a size (e.g., gate size) that, along with the source voltage V, is... DD and / or bias voltage V INT The amplitude can be used to set the gain of the DUT circuit 400. Bias voltage V B It can have a first input voltage V IN_P With the second input voltage V IN_N The magnitude of the difference in amplitude between them. Therefore, the output voltage V OUT It can have gain and bias voltage V based on DUT circuit. BThe amplitude.

[0036] exist Figure 4 In one example, the DUT circuit 400 further includes multiple contact pads 414 at each terminal between the transistor device and the input / output. Specifically, the DUT circuit 400 includes pads 414 for providing source voltage V. DD The first contact pad 414 at the input terminal and the bias voltage V INT The second contact pad 414 is located at the input terminal. The DUT circuit 400 includes a first input voltage V. IN_P The third contact pad 414 at the input terminal and the second input voltage V IN_N The DUT circuit 400 includes a fourth contact pad 414 at the input terminal. The DUT circuit 400 includes a fifth contact pad 414 at the terminal between the source of input transistors P3 and P4 and the drain of the first source transistor P1. The DUT circuit 400 includes a sixth contact pad 414 at the terminal between the body connection of input transistors P3 and P4. The DUT circuit 400 includes a seventh contact pad 414 at the terminal between the source of the first input transistor P3 and the first mirror transistor P5, and an eighth contact pad 414 at the terminal coupled to the drain of mirror transistors P5 and P6 and the gain transistor P7. The DUT circuit 400 includes a ninth contact pad 414 at the bias terminal 408 and a tenth contact pad 414 at the output terminal 412.

[0037] For the BTI testing process, the test device 102 can be coupled to each of the contact pads 414 and can initially provide a differential voltage V. IN_P and V IN_N And measure the output voltage V OUT For example, the test device 102 can be relative to a first input voltage V. IN_P Second input voltage V IN_N Another fixed amplitude in the middle provides the first input voltage V. IN_P Second input voltage V IN_N One of them has a continuously variable amplitude (e.g., sweeping from a low amplitude to a high amplitude), and the resulting continuously changing output voltage V can be measured. OUT Therefore, the test device 102 can obtain the output voltage V in this way. OUT Baseline measurements.

[0038] Figure 5 This is an example of a voltage curve graph 500. Voltage curve graph 500 plots the variable input voltage V on the X-axis. IN With the variable output voltage V on the Y-axis OUT The relationship between input voltage V and input voltage V. IN This can correspond to an input voltage V that sweeps from a low amplitude to a high amplitude with continuously variable amplitude.IN_P and V IN_N The one mentioned above. Graph 500 shows the output voltage V. OUT The baseline curve is a solid line (502). Output voltage V OUT The variable amplitude can be recorded by the test device 102 and stored in the memory 116. The test device 102 can determine the output voltage V. OUT The region of maximum amplitude change, and therefore the output voltage V can be based on the approximately linear region of maximum amplitude change. OUT The slope is used to determine the gain of the DUT circuit 400. Alternatively, the gain can be modeled / estimated before the DUT circuit 400 is manufactured.

[0039] The test device 102 can then select the input voltage V. IN The amplitude, which is within the range of the input voltage V IN The lower amplitude of the amplitude range, which corresponds to the output voltage V. OUT The maximum change in amplitude. At the output voltage V OUT The selected amplitude point is shown at 504 in the baseline curve 502. Therefore, the selected amplitude point 504 corresponds to the output voltage V before the application of BTI stress. OUT The initial measurement. Figure 5 In the example, the amplitude point 504 is selected at an input voltage V of approximately 2.480V. IN At that point, and the output voltage V OUT The initial measurement value was approximately 4.25V.

[0040] Return to view Figure 4 An example is given by the input voltage V. IN The output voltage V is obtained at the selected amplitude. OUT Following baseline measurements, the test equipment applies BTI stress to one of the input transistors P3 and P4 (e.g., where the input voltage V...). IN (One of the amplitude-sweeped input transistors P3 and P4). To provide BTI stress, the test equipment 102 can provide a predefined amplitude of the input voltage to the gate of the respective one of the input transistors P3 and P4 at a predefined temperature for a predefined duration.

[0041] In one example, the relevant transistor device is described below as a first transistor device P3. Test equipment 102 may be electrically connected to each of ten contact pads 414. To provide BTI stress, test equipment 102 may provide a zero voltage amplitude (e.g., ground connection) to each of the nine contact pads 414 not coupled to the gate of the first transistor device P3. Test equipment 102 may then apply a first input voltage V at a predefined temperature for a predefined duration. IN_PA predefined amplitude is provided to the gate of the first transistor device P3. After the predefined duration is completed, the BTI stress is immediately completed to simulate the aging of the first input transistor P3 to determine the estimated parameter shift of the DUT in the circuit die 202.

[0042] The predefined duration can be any duration considered sufficient for a suitable simulation of aging the corresponding transistor device, and can be determined based on standards, estimates, and / or experimentally. First input voltage V IN_P The predefined amplitude can be one of several static amplitudes that can be used to fully model the parametric shift lifetime performance of the DUT of circuit die 202. For example, the predefined static amplitude can be 7V, 8V, and 9V. The predefined temperature can be one of several temperatures that can be used to fully model the parametric shift lifetime performance of the DUT of circuit die 202. For example, the predefined temperature can be 125°C and 175°C.

[0043] When applying BTI stress to the first input transistor P3, the test apparatus 102 can provide a combination of predefined amplitude and predefined temperature. In the provided example, the BTI stress of the first transistor P3 can be any one of 7V at 125°C, 7V at 175°C, 8V at 125°C, 8V at 175°C, 9V at 125°C, and 9V at 175°C. To fully model the parametric shift lifetime performance of the DUT of the circuit die 202, the test apparatus 102 can provide one of the above combinations of predefined amplitude and predefined temperature to the first transistor device P3 of the DUT circuit 400, and can provide each of the other combinations of predefined amplitude and predefined temperature to the corresponding other one of the first transistor device to the semiconductor wafer 204 in a separate corresponding BTI test process 106 of the DUT circuit 204. Therefore, the total combination of predefined amplitudes and predefined temperatures in the individual BTI test process 106 yields sufficient data for accurate and complete modeling of the parametrically shifted lifetime effect of the DUT of the circuit die 202.

[0044] After applying BTI stress to the first transistor device P3, the test equipment can measure the output voltage V again. OUT See again Figure 5 For example, graph 500 shows the output voltage V. OUT The BTI stress curve is represented by the dashed line 506. The BTI stress output voltage V... OUT The variable amplitude can be recorded by test device 102 and stored in memory 116, but this may not be necessary for the purpose of BTI test process 106. Test device 102 can then select the output voltage V. OUT The selected input voltage V in the baseline measurement of amplitudeIN (For example, V in the above examples) IN_P The same amplitude as the output voltage V. OUT The selected amplitude point is shown at 508 in the BTI stress curve 506. Selected amplitude point 508 represents the same input voltage V as selected amplitude point 504 in the baseline measurement. IN The amplitude is represented as an input voltage V of approximately 2.480V. IN Amplitude. However, because BTI stress alters the threshold voltage V of the corresponding transistor device (e.g., the first input transistor P3). T Therefore, the same measurement point in the BTI stress curve 506 leads to the measured output voltage V. OUT The smaller amplitude. Figure 5 In the example, a selected amplitude point 508 of approximately 2.480V results in an output voltage V of approximately 2.5V. OUT BTI stress measurement. Figure 5 The example will be the output voltage V in the initial measurement. OUT The difference between the amplitude and the BTI stress measurement is shown as ΔV. OUT (For example, approximately 1.75V).

[0045] Therefore, the test device 102 can calculate the change ΔV in the threshold voltage of the first input transistor P3. T Therefore, the threshold voltage difference between input transistors P3 and P4 is calculated. The change in threshold voltage ΔV T The following can be calculated:

[0046] ΔV T = ΔV OUT / G Equation 1

[0047] Where: G is the gain of the DUT circuit 400 (e.g., the output voltage V in the region based on the maximum magnitude change). OUT (Calculated from the slope).

[0048] Therefore, Equation 1 can be based on determining the output voltage V. OUT The high gain of the time-of-flight DUT circuit 400 provides the calculated threshold voltage change ΔV with extremely high accuracy (e.g., in the microvolt range). T Therefore, the calculated change in threshold voltage ΔV T The determination yields significantly higher accuracy than conventional BTI testing procedures, which can only be modeled in the millivolt range. This is achieved by calculating the change ΔV of the threshold voltage for each combination of predefined voltage and predefined temperature for the corresponding individual BTI testing procedure 106. T Therefore, the test equipment 102 can fully and accurately model the parametric shift lifetime effect of the DUT on the semiconductor wafer 200.

[0049] In view of the aforementioned structural and functional features, reference will be made to Figure 6 To better understand the methods in the various aspects described herein. Figure 6 The methods are not limited to the order in which they are described, because in this specification, some aspects may appear in a different order than those shown and described herein and / or in parallel with other aspects shown and described herein. Furthermore, not all of the described features may be required to implement the methods in one aspect of the current instance.

[0050] Figure 6 This is an example of method 600 for performing a BTI test process (e.g., BTI test process 106) for multiple DUTs (e.g., DUT 110). At 602, contact pads (e.g., contact pad 312) of the DUT circuitry (e.g., DUT circuitry 112) are coupled to a test device (e.g., test device 102). The DUT circuitry may include differential input stages (e.g., differential input stage 304) and gain stages (e.g., gain stage 308). The differential input stages may include differential pairs (e.g., differential transistor pair 310) fabricated to match transistor devices to the DUT. At 604, BTI stress is provided from the test device to one of the differential pairs of transistor devices to simulate BTI aging of the corresponding one of the differential pairs of transistor devices. At 606, a differential input voltage (e.g., input voltage V) is applied... IN_P and V IN_N The voltage is supplied from the test equipment to the differential input stage. At 608, in response to the differential input voltage, the output voltage (e.g., output voltage V) is measured via the test equipment at the output of the gain stage (e.g., output terminal 412). OUT To determine the threshold voltage change between differential pairs of a transistor device (e.g., the threshold voltage change ΔV). T ).

[0051] As used herein, the terms “terminal,” “node,” “interconnect,” “pin,” and “lead” are used interchangeably. Unless specifically stated otherwise, these terms are generally used to refer to interconnections or ends between device elements, circuit elements, integrated circuits, devices, or other electronic or semiconductor components.

[0052] The use of the phrase "grounding" in the foregoing description includes chassis grounding, ground wire grounding, floating grounding, virtual grounding, digital grounding, general grounding, and / or any other form of grounding connection applicable to or suited to the teachings herein. In this specification, unless otherwise stated, "about," "approximately," or "generally" preceding a parameter means within + / - 10% of said parameter, or, if the parameter is zero, within a reasonable range of values ​​approximately zero.

[0053] In this description, the term "coupling" may encompass a connection, communication, or signaling path that enables the functional relationship to be consistent with this specification. For example, if device A generates a signal to control device B to perform an action, then: (a) in a first instance, device A is coupled to device B via a direct connection; or (b) in a second instance, if intermediate component C does not alter the functional relationship between device A and device B, then device A is coupled to device B via intermediate component C such that device B is controlled by the control signal generated by device A.

[0054] In this specification, a device "configured to" perform a task or function may be configured (e.g., programmed and / or hardwired) to perform the function during manufacturing by the manufacturer, and / or may be configured (or reconfigured) by the user after manufacturing to perform the function and / or other additional or alternative functions. Configuration may be achieved through firmware and / or software programming of the device, through the construction and / or layout of the device's hardware components and interconnects, or a combination thereof. Furthermore, circuits or devices described herein as containing specific components may actually be configured to couple to those components to form the described circuit system or device. For example, a structure described herein as containing one or more semiconductor elements (e.g., transistors), one or more passive elements (e.g., resistors, capacitors, and / or inductors), and / or one or more sources (e.g., voltage sources and / or current sources) may actually contain only semiconductor elements within a single physical device (e.g., semiconductor dies and / or integrated circuit (IC) packages), and may be configured to couple to at least some of the passive elements and / or sources to form the described structure during or after manufacturing, for example, by an end user and / or a third party.

[0055] The phrase "based on" means "at least partially based on". Therefore, if X is based on Y, then X can be a function of Y and any number of other factors.

[0056] Within the scope of the claims, modifications to the described embodiments are possible, and other embodiments are also possible.

Claims

1. A method for performing a bias temperature instability (BTI) test process on a plurality of devices under test (DUTs), the method comprising: coupling contact pads of a DUT circuit to a test apparatus, the DUT circuit including a differential input stage and a gain stage, the differential input stage including a differential pair of transistor devices that are matched to the DUT; providing a BTI stress from the test apparatus to one of the differential pair of transistor devices to simulate a BTI aging of the respective one of the differential pair of transistor devices; providing a differential input voltage from the test apparatus to the differential input stage; and in response to the differential input voltage, measuring an output voltage at an output of the gain stage via the test apparatus to determine a threshold voltage change between the differential pair of transistor devices.

2. The method of claim 1, wherein measuring the output voltage comprises: measuring the output voltage at a first time prior to providing the BTI stress to the respective one of the differential pair of transistor devices; measuring the output voltage at a second time after providing the BTI stress to the respective one of the differential pair of transistor devices; and determining the threshold voltage change based on a difference in magnitude of the output voltage between the first time and the second time.

3. The method of claim 2, wherein measuring the output voltage further comprises dividing the difference in magnitude of the output voltage between the first time and the second time by a gain of the gain stage to determine the threshold voltage change between the differential pair of transistor devices.

4. The method of claim 3, further comprising determining the gain of the gain stage based on a slope of the output voltage across a range of magnitudes of the differential input voltage.

5. The method of claim 1, wherein providing the differential input voltage comprises: providing a first input voltage to a first one of the differential pair of transistor devices at a fixed magnitude; and providing a second input voltage to a second one of the differential pair of transistor devices, the second input voltage being continuously variable from a first magnitude to a second magnitude, wherein measuring the threshold voltage change comprises continuously measuring the output voltage at the gain stage in response to the fixed magnitude of the first input voltage concurrently with the continuously variable magnitude of the second input voltage.

6. The method of claim 5, wherein measuring the output voltage comprises selecting: a magnitude of the second input voltage along the continuously variable magnitude that corresponds to an output measurement magnitude; a first magnitude of the output voltage measured in response to the output measurement magnitude of the second input voltage at a first time prior to providing the BTI stress to the respective one of the differential pair of transistor devices; and a second magnitude of the output voltage measured in response to the output measurement magnitude of the second input voltage at a second time after providing the BTI stress to the respective one of the differential pair of transistor devices. ​ ​ ​ 7. The method of claim 6, wherein measuring the output voltage comprises measuring a slope of the output voltage across the continuously variable magnitude of the second input voltage to determine a gain of the gain stage.

8. The method of claim 7, wherein measuring the output voltage further comprises dividing a difference in the magnitude of the output voltage between the first time and the second time by the gain of the gain stage to determine the threshold voltage shift between the differential pair of transistor devices.

9. The method of claim 1, wherein providing the BTI stress comprises: providing a predefined voltage to a control input terminal of the respective one of the differential pair of transistor devices at a predefined temperature for a predefined duration; and providing a ground connection to each remaining terminal of the respective one of the differential pair of transistor devices at the predefined temperature for the predefined duration.

10. The method of claim 9, wherein the DUT circuit is one of a plurality of DUT circuits, wherein providing the BTI stress comprises each of a different combination of one of a plurality of predefined voltages to the control input terminal of the respective one of the differential pair of transistor devices and one of a plurality of predefined temperatures for the predefined duration for each of the plurality of DUT circuits.

11. A semiconductor device, comprising: a current source stage having a first input, a second input, and a first output and a second output, the first input of the current source stage adapted to receive a bias voltage, and the second input of the current source stage adapted to receive a bias control voltage; a differential input stage comprising a first input transistor device and a second input transistor device, the first input transistor device having a control input, an input, an output, and a terminal, the second input transistor device having a control input, an input, an output, and a terminal, the control input of the first input transistor device adapted to receive a first control input voltage, the control input of the second input transistor device adapted to receive a second control input voltage, the input of each of the first input transistor device and the second input transistor device coupled to the first output of the current source stage, and the terminal of the first input transistor device coupled to the terminal of the second input transistor device; a current mirror stage having a first input, a second input, and an output, the first input of the current mirror stage coupled to the output of the first input transistor device, and the second input of the current mirror stage coupled to the output of the second input transistor device; a gain stage having a first input, a second input, and an output, the first input of the gain stage coupled to the output of the second input transistor device, the second input of the gain stage coupled to the second output of the current source stage, and the output of the gain stage coupled to the output of the current mirror stage; a first contact pad coupled to the control input of the first input transistor device; ​ a second contact pad coupled to the control input of the second input transistor device; a third contact pad coupled to the second input of each of the first input transistor device and the second input transistor device; a fourth contact pad coupled to the output of the first input transistor device; a fifth contact pad coupled to the output of the second input transistor device; a sixth contact pad coupled to the terminals of the first input transistor device and the second input transistor device; and a seventh contact pad coupled to the second input of the gain stage.

12. The semiconductor device of claim 11, further comprising: an eighth contact pad coupled to the first input of the current source stage; a ninth contact pad coupled to the second input of the current source stage; and a tenth contact pad coupled to the output of the current mirror stage.

13. The semiconductor device of claim 11, wherein the current source stage comprises: a first source transistor device having a control input, an input, and an output, the control input of the first source transistor device adapted to receive the bias control voltage, the input of the first source transistor device adapted to receive the bias voltage, the output of the first source transistor device coupled to the input of the first input transistor device; and a second source transistor device having a control input, an input, and an output, the control input of the second source transistor device adapted to receive the bias control voltage, the input of the second source transistor device adapted to receive the bias voltage, the output of the second source transistor device coupled to the input of the second input transistor device.

14. The semiconductor device of claim 11, wherein the current mirror stage comprises: a first mirror transistor device having a control input, an input, and an output, the control input and the input of the first mirror transistor device coupled to the output of the first input transistor device, the output of the first mirror transistor device coupled to the output of the gain stage; and a second mirror transistor device having a control input, an input, and an output, the control input of the second mirror transistor device coupled to the output of the first input transistor device, the input of the second mirror transistor device coupled to the output of the second input transistor device, the output of the second mirror transistor device coupled to the output of the gain stage.

15. The semiconductor device of claim 11, wherein the gain stage comprises a gain transistor device having a control input, an input, and an output, the control input of the gain transistor device coupled to the output of the second input transistor device, the input of the gain transistor device coupled to the second output of the current source stage, and the output of the gain transistor device coupled to the output of the current mirror stage. ​ ​ ​ ​ 16. The semiconductor device of claim 11, wherein the semiconductor device is an operational amplifier (OP-AMP).

17. A test system for performing a bias temperature instability (BTI) test process for a plurality of devices under test (DUTs), the system comprising: a semiconductor wafer comprising: a plurality of circuit dies, each of the circuit dies comprising at least one DUT; and at least one DUT circuit each comprising a differential input stage and a gain stage, the differential input stage comprising a differential pair of transistor devices that are fabricated to match the DUT; and a test apparatus, contact pads of each of the at least one DUT circuit are arranged to be coupled to the test apparatus, the test apparatus is configured to provide a BTI stress to one of the differential pair of transistor devices to simulate a BTI aging of the respective one of the differential pair of transistor devices, provide a differential input voltage to the differential pair of transistor devices, and measure an output voltage at an output of the gain stage in response to the differential input voltage to determine a threshold voltage change between the differential pair of transistor devices.

18. The system of claim 17, wherein the at least one DUT circuit further comprises: a current source stage configured to provide a first current and a second current, wherein the differential pair of transistor devices are each configured to conduct a portion of the first current in response to receiving a respective the differential input voltage; and a current mirror stage coupled to the differential input stage, the current mirror stage comprising a bias terminal through which the portion of the first current is provided, wherein the gain stage is coupled to the bias terminal and configured to provide the output voltage in response to the differential input voltage.

19. The system of claim 17, wherein the test apparatus is configured to: measure the output voltage at a first time prior to providing the BTI stress to the respective one of the differential pair of transistor devices; measure the output voltage at a second time after providing the BTI stress to the respective one of the differential pair of transistor devices; and determine the threshold voltage change based on a difference in magnitude of the output voltage between the first time and the second time.

20. The system of claim 19, wherein the test apparatus is further configured to: provide a first input voltage to a first one of the differential pair of transistor devices at a fixed magnitude; provide a second input voltage to a second one of the differential pair of transistor devices, the second input voltage is continuously variable from a first magnitude to a second magnitude; and measure a threshold voltage of the second one of the differential pair of transistor devices by continuously measuring the output voltage at the gain stage in response to the fixed magnitude of the first input voltage concurrently with the continuously variable magnitude of the second input voltage.

21. The system of claim 19, wherein the test apparatus is configured to: determining a gain of the gain stage by measuring a slope of the output voltage across the continuously variable amplitude of the second input voltage; and dividing a difference in the amplitude of the output voltage between the first time and the second time by the gain to determine the threshold voltage change between the differential pair of transistor devices.

22. A semiconductor wafer comprising: a plurality of circuit dies, each of the circuit dies comprising at least one device under test (DUT); a plurality of DUT circuits, each of the DUT circuits comprising: a current source stage configured to provide a first current and a second current; a differential input stage comprising a differential pair of transistor devices each configured to conduct a portion of the first current in response to receiving a respective differential input voltage, each of the differential pair of transistor devices being fabricated to match the at least one DUT of each of the circuit dies; a current mirror stage coupled to the differential input stage, the current mirror stage comprising a bias terminal through which the portion of the first current is provided; a gain stage coupled to the bias terminal and configured to provide an output voltage based on the second current in response to the differential input voltage; and a contact pad configured to provide a bias temperature instability (BTI) stress to one of the differential pair of transistor devices to perform a BTI test of the at least one DUT of each of the circuit dies via a respective one of the DUT circuits.

23. The wafer of claim 22, wherein the current source stage comprises: a first source transistor device configured to conduct the first current in response to a bias control voltage; and a second source transistor device configured to conduct the second current in response to the bias control voltage.

24. The wafer of claim 22, wherein the current mirror stage comprises: a first mirror transistor device coupled to a first one of the differential pair of transistor devices, the first mirror transistor device being diode-connected to conduct a first portion of the first current; and a second mirror transistor device coupled to a second one of the differential pair of transistor devices, the second mirror transistor device having a control input terminal coupled to a control input terminal of the first mirror transistor device to conduct a second portion of the first current, wherein the bias terminal is disposed between the second one of the differential pair of transistor devices and the second mirror transistor device.

25. The wafer of claim 22, wherein the gain stage comprises a gain transistor device configured to conduct the second current in response to a control voltage provided at the bias terminal. ​ ​

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