Circuit device and electronic equipment

Abstract

A circuit device and an electronic apparatus. The circuit device includes: a voltage division circuit that divides a voltage to be measured and outputs the divided voltage to a voltage division node; a comparison circuit that compares the voltage of the voltage division node with a reference voltage; and a control circuit. The voltage division circuit includes first to n-th resistors provided in series between a voltage node to be measured and a voltage division node, and first to n-th transistors in which an i-th transistor and an i-th resistor are connected in parallel. The control circuit sets the j-th transistor to one of ON and OFF, sets the first to (j-1)-th transistors to the other of ON and OFF, and outputs measurement data by determining the ON or OFF of the j-th transistor on the basis of the comparison result of the comparison circuit.

Description

Technical Field

[0001] This invention relates to circuit devices and electronic devices, etc. Background Technology

[0002] Patent Document 1 discloses a measuring circuit for measuring battery voltage. The measuring circuit includes a counter, a resistor circuit that divides the battery voltage according to a voltage division ratio set based on the counter's count value, and a comparator that compares the output voltage of the resistor circuit with a reference voltage. The resistor circuit includes seven resistors connected in series between the battery voltage node and the output node of the resistor circuit, and seven transistors, each connected in parallel with each resistor. The seven transistors are turned on or off according to the counter's count value, thereby changing the voltage division ratio of the resistor circuit. The battery voltage is then measured based on the comparison result of the comparator comparing the output voltage of the resistor circuit with the reference voltage.

[0003] Patent Document 1: Japanese Patent Application Publication No. 2019-175755

[0004] When switching the transistors on and off, the source or drain voltage of the transistors varies due to charge injection and other factors. Because this voltage variation propagates to the input of the comparator, the voltage may not be measured accurately. Summary of the Invention

[0005] One aspect of this disclosure relates to a circuit arrangement comprising: a voltage divider circuit disposed between a voltage node to be measured and a ground node, for dividing the voltage of the voltage node to be measured, i.e., the voltage to be measured, and outputting the voltage to the voltage divider node; a comparison circuit for comparing the voltage of the voltage divider node with a reference voltage; and a control circuit, wherein the voltage divider circuit comprises: a first resistor to an nth resistor, which are connected in series between the voltage node to be measured and the voltage divider node, wherein n is an integer greater than or equal to 3; a first transistor to an nth transistor, wherein the i-th transistor is connected to the first resistor to the nth transistor. The i-th resistor in the n-th resistor is connected in parallel and is controlled to be turned on or off according to control data from the control circuit, where i is an integer greater than or equal to 1 and less than or equal to n. The control circuit sets the j-th transistor to be either on or off, and sets the 1st to (j-1)th transistors to be either on or off. The on or off state of the j-th transistor is determined according to the comparison result of the comparison circuit, thereby determining the control data, where j is an integer greater than or equal to 2 and less than or equal to n. The control circuit outputs the measurement data of the voltage of the measured object according to the determined control data.

[0006] In addition, another aspect of this disclosure relates to an electronic device that includes the circuitry and battery described above, wherein the voltage to be measured is the battery voltage. Attached Figure Description

[0007] Figure 1 This is the first structural example of a circuit device.

[0008] Figure 2 This is an example of the structure of a circuit that generates control data in a control circuit.

[0009] Figure 3 These are waveform examples illustrating the operation of the control circuit.

[0010] Figure 4 This is a diagram illustrating the second structural example of a circuit device.

[0011] Figure 5 This is the third structural example of a circuit device.

[0012] Figure 6 It is the truth table for normal mode and test mode.

[0013] Figure 7 This is a detailed structural example of the first and second trimmer resistors.

[0014] Figure 8 These are examples of the structure of electronic devices and systems.

[0015] Label Explanation

[0016] 10: Battery; 100: Circuit device; 110: Voltage divider circuit; 111: First resistor circuit; 112: Second resistor circuit; 115: P-type MOS transistor; 140: Register; 150: Control circuit; 160: Comparator circuit; 170: Power receiving circuit; 180: Charging circuit; 190: Discharging circuit; 200: Electronic device; 210: Battery; 220: Processing device; 300: Power supply device; 310: Power supply circuit; 320: Control circuit; 400: System; N1: First node; NDIV: Voltage divider node ; NGND: Grounding node; NVIN: Measured object voltage node; RA1~RA8: 1st resistor~8th resistor; RT1: 1st trimmer resistor; RT2: 2nd trimmer resistor; SAR[7:0]: Measurement data; TA1~TA8: 1st transistor~8th transistor; TB11~TA81: 1st charge absorption transistor; TB12~TA82: 2nd charge absorption transistor; VDIV: Voltage of voltage divider node; VIN: Measured object voltage; VREF: Reference voltage; XBIT[7:0]: Control data. Detailed Implementation

[0017] The preferred embodiments of this disclosure are described in detail below. Furthermore, the embodiments described below are not intended to unduly limit the scope of the claims, and not all structures described in these embodiments are necessarily essential components. Additionally, the connections in these embodiments include electrical connections. An electrical connection is a connection capable of transmitting electrical signals, voltage, or current, and includes connections capable of transmitting information based on electrical signals. Electrical connections can also be connections via passive or active components, etc.

[0018] 1. Example of the first structure

[0019] Figure 1 This is a first structural example of the circuit device 100. The circuit device 100 measures the voltage value of the target voltage VIN and outputs measurement data SAR[7:0] as the result. Furthermore, the number of bits in the measurement data SAR[7:0] is assumed to be 8, but the number of bits can be arbitrary. The circuit device 100 includes a voltage divider circuit 110, a control circuit 150, and a comparator circuit 160. The circuit device 100 is, for example, an integrated circuit device on a semiconductor substrate in which multiple circuit elements are integrated.

[0020] Voltage divider circuit 110 is disposed between the voltage node NVIN to be measured and the ground node NGND. That is, one end of voltage divider circuit 110 is connected to the voltage node NVIN to be measured, and the other end is connected to the ground node NGND. The voltage node NVIN to be measured is the node to which the voltage VIN to be measured is input. The ground node NGND is the node to which the ground voltage GND is input. Voltage divider circuit 110 divides the voltage VIN to be measured and outputs it to voltage divider node NDIV. Voltage divider circuit 110 includes first resistor RA1 to eighth resistor RA8, first transistor TA1 to eighth transistor TA8, first resistor circuit 111, and second resistor circuit 112. Alternatively, voltage divider circuit 110 may also include P-type MOS transistor 115.

[0021] The source of the P-type MOS transistor 115 is connected to the voltage node NVIN of the target voltage, and the drain is connected to the node NA. An enable signal XEN is input from the control circuit 150 to the gate of the P-type MOS transistor 115.

[0022] Resistors RA1 through RA8 are connected in series between node NA and node N1. Figure 1The diagram shows an example of resistors connected in series from the high potential side in the order of 8th resistor RA8, ..., 2nd resistor RA2, and 1st resistor RA1, but the connection order is not limited to this. Furthermore, the number of resistors connected in series is set to 8 here, but the number of resistors can also be n. n is an integer greater than or equal to 3. The resistance values ​​of resistors 1st resistor RA1 to 8th resistor RA8 are weighted in binary, with the resistance value of 8th resistor RA8 being the largest. That is, when j is an integer greater than or equal to 2 and less than or equal to 8, the resistance value of RAj is twice the resistance value of RAj-1.

[0023] Transistors TA1 to TA8 are P-type MOS transistors. Let i be an integer greater than 1 and less than 8. The i-th transistor TAi is connected in parallel with the i-th resistor RAi. That is, the source of the i-th transistor TAi is connected to one end of the i-th resistor RAi, and the drain is connected to the other end of the i-th resistor RAi. The bit signal XBIT[i-1] of the control data XBIT[7:0] is input from the control circuit 150 to the gate of the i-th transistor TAi. The control data XBIT[7:0] is the data that controls the voltage division ratio of the voltage divider circuit 110.

[0024] The first resistor circuit 111 is disposed between the first node N1 and the voltage divider node NDIV. That is, one end of the first resistor circuit 111 is connected to the first node N1, and the other end is connected to the voltage divider node NDIV. As an example, the resistance value of the first resistor circuit 111 is greater than the sum of the resistance values ​​of the first resistor RA1 to the eighth resistor RA8. However, it is not limited to this; the resistance value of the first resistor circuit 111 may also be less than the sum of the resistance values ​​of the first resistor RA1 to the eighth resistor RA8, or it may be switchable according to the measurement range as described later.

[0025] The second resistor circuit 112 is disposed between the voltage divider node NDIV and the ground node NGND. That is, one end of the second resistor circuit 112 is connected to the voltage divider node NDIV, and the other end is connected to the ground node NGND.

[0026] Comparator circuit 160 is a comparator that compares the voltage VDIV at the voltage divider node NDIV with a reference voltage VREF. The reference voltage VREF is a constant voltage and can be input to comparator circuit 160 from a voltage generation circuit (not shown) included in circuit device 100, or from an external input to circuit device 100. Figure 1 The diagram illustrates an example where a reference voltage VREF is input to the positive input terminal of the comparator and a voltage VDIV is input to the negative input terminal. The comparator circuit 160 outputs an output signal XHDL as the comparison result. The output signal XHDL is low when VDIV ≥ VREF and high when VDIV < VREF.

[0027] The control circuit 150 enables or disables the voltage divider circuit 110 via the enable signal XEN. When the enable signal XEN is low, the P-type MOS transistor 115 is turned on, and the voltage divider circuit 110 is enabled. When the enable signal XEN is high, the P-type MOS transistor 115 is turned off, and the voltage divider circuit 110 is disabled. Hereinafter, the voltage divider circuit 110 is assumed to be enabled.

[0028] The control circuit 150 changes the control data XBIT[7:0] to various values, thereby changing the voltage division ratio of the voltage divider circuit 110. For each value of the control data XBIT[7:0], the control circuit 150 determines the measurement data SAR[7:0] based on the logic level of the output signal XHDL of the comparison circuit 160, and outputs the measurement data SAR[7:0].

[0029] Specifically, the voltage VDIV of the voltage divider node NDIV is given by the following formula (1). RA represents the resistance value of the variable resistor circuit when the first resistor RA1 to the eighth resistor RA8 and the first transistor TA1 to the eighth transistor TA8 are considered as a variable resistor circuit. R111 is the resistance value of the first resistor circuit 111, and R112 is the resistance value of the second resistor circuit 112.

[0030] VDIV=VIN×{R112 / (RA+R111+R112)}···(1)

[0031] Control circuit 150 changes the resistance value and VDIV by changing the control data XBIT[7:0]. Based on this, the logic level of the output signal XHDL of comparator circuit 160 is determined. Control circuit 150 determines the control data XBIT[7:0] when the voltage VDIV at voltage divider node NDIV is equal to the reference voltage VREF, and outputs its logically inverted data BIT[7:0] as the measurement data SAR[7:0] for the measured voltage VIN. The logically inverted data BIT[7:0] is data obtained by logically inverting each bit of the control data XBIT[7:0].

[0032] As described above, by not providing any other resistors between the voltage node NVIN and the first resistors RA1 to RA8, the on-resistance of the first transistors TA1 to TA8 is reduced compared to the case where other resistors are provided. This allows for a reduction in the gate size of the first transistors TA1 to TA8. By reducing the gate size, charge injection is reduced, decreasing the likelihood of misjudgment by the comparator circuit 160, thus improving the accuracy of voltage measurement. Furthermore, as described above, the resistance value of the first resistor circuit 111 is, for example, greater than the total resistance value of the first resistors RA1 to RA8. Therefore, voltage fluctuations caused by charge injection from the first transistors TA1 to TA8 are less likely to reach the voltage divider node NDIV, reducing the likelihood of misjudgment by the comparator circuit 160, and thus improving the accuracy of voltage measurement.

[0033] One example of the method by which the control circuit 150 determines the measurement data SAR[7:0] is a binary search. This method is described below. However, the method by which the control circuit 150 determines the measurement data SAR[7:0] is not limited to binary search, and various algorithms can be used.

[0034] Figure 2 This is an example of the structure of a circuit in control circuit 150 that generates data BIT[7:0], which is the logic inversion data of control data XBIT[7:0]. Control circuit 150 includes trigger circuits FF1 to FF8, trigger circuit FFE, latch circuits LT1 to LT8, inverter circuit INV, and logic OR circuits OR1 to OR8.

[0035] Figure 3 This is an explanation Figure 2 A waveform example of the operation of the control circuit 150 is shown. Here, an example is shown where the measured data SAR[7:0] is 01100100. The data is represented in binary. The waveform of the output signal XHDL of the comparator circuit 160 is assigned a 0 or 1 corresponding to the logic level of the signal HDL. The signal HDL is the logic inversion of the output signal XHDL.

[0036] During measurement, the control circuit 150 inputs a clock signal CLK from an oscillation circuit (not shown) to the clock terminals of trigger circuits FF1-FF8 and FFE. Trigger circuits FF1-FF8 and FFE latch the input signal on the rising edge of the clock signal CLK. One cycle of the clock signal is defined as the period from the rising edge of CLK to the next rising edge, and these cycles are sequentially named the 1st cycle, the 2nd cycle, ..., the 9th cycle.

[0037] The trigger circuits are connected in series in the order of FF8, FF7, ..., FF1, FFE, which constitute a shift register. When the control circuit 150 starts the measurement, it inputs a high pulse of signal SC to the data terminal of the trigger circuit FF8 at the beginning of the shift register. Signal SC changes from low level to high level before the initial rising edge of the clock signal CLK, and changes from high level to low level at the initial falling edge of the clock signal CLK. By shifting the signal SC in sequence, the output signal Q[7] of the trigger circuit FF8 becomes high level in the first cycle of the clock signal CLK, the output signal Q[6] of the trigger circuit FF7 becomes high level in the second cycle of the clock signal CLK, ..., and the output signal Q[0] of the trigger circuit FF1 becomes high level in the eighth cycle of the clock signal CLK.

[0038] Through the operation of this shift register, in the first cycle of the clock signal CLK, the output signal BIT[7] of the OR8 logic circuit becomes high ("1"); in the second cycle of the clock signal CLK, the output signal BIT[6] of the OR7 logic circuit becomes high; ..., in the eighth cycle of the clock signal CLK, the output signal BIT[0] of the OR1 logic circuit becomes high. Thus, by using the output signal XHDL of the comparison circuit 160 when BIT[7], BIT[6], ..., BIT[0] become high in sequence, the bits of the measurement data SAR[7:0] are determined sequentially from the upper bit, thereby performing a binary search.

[0039] Specifically, the inverter circuit INV outputs the logic inverted signal HDL of the output signal XHDL of the comparator circuit 160. The data terminals of latch circuits LT1 to LT8 are input with signal HDL. The clock terminal of latch circuit LT8 is input with the logic inverted signal Q[7] of the trigger circuit FF8. Latch circuit LT8 latches signal HDL at the falling edge of Q[7]. Similarly, latch circuit LT7 latches signal HDL at the falling edge of Q[6], ..., latch circuit LT1 latches signal HDL at the falling edge of Q[0]. Taking the first and second cycles as examples, the output signal BIT[7] is high in the first cycle and low at the beginning of the second cycle. Therefore, latch circuit LT8 latches signal HDL at the beginning of the second cycle. The latched signal HDL is the logic inverted signal of the output signal XHDL of the comparator circuit 160 corresponding to the high-level output signal BIT[7]. Figure 3In the example, the level is low (“0”). The output signal M[7] of the latch circuit LT8 is low, therefore, at the beginning of the second cycle, the output signal BIT[7] of the logic OR circuit OR8 is determined to be low (“0”). Subsequently, at the beginning of the third to the ninth cycle, the logic levels of the output signals BIT[6] to BIT[0] of the logic OR circuits OR7 to OR1 are determined sequentially. The control circuit 150 outputs the determined data BIT[7:0] as the measurement data SAR[7:0].

[0040] The final trigger circuit FFE of the shift register outputs a high-level end signal EOC in the 9th cycle. When the end signal EOC becomes high, the control circuit 150 outputs the data BIT[7:0] determined as described above as the measurement data SAR[7:0].

[0041] In binary search, compared to the counter method such as in Patent Document 1, fewer transistors are switched on and off, thus reducing voltage fluctuations caused by charge injection. In the counter method of Patent Document 1, for example, when the data BIT[7:0] changes from 01111111 to 10000000, the on / off state of 8 transistors is switched simultaneously. On the other hand, according to this embodiment, as... Figure 3 As shown, the maximum number of transistors that can simultaneously switch between on and off is two. For example, in the second and third cycles, when the data BIT[7:0] switches from 10000000 to 01000000, only two transistors switch between on and off simultaneously. Furthermore, when two transistors switch simultaneously, they are adjacent to each other. In this case, if one transistor switches from on to off and the other switches from off to on, a portion of the charge injection can be canceled out. For example, the source-side charge injection of one transistor cancels out the drain-side charge injection of the other transistor. This reduces the impact of charge injection.

[0042] In this embodiment, the circuit device 100 includes a voltage divider circuit 110, a comparator circuit 160, and a control circuit 150. The voltage divider circuit 110 is disposed between the target voltage node NVIN and the ground node NGND, and divides the target voltage VIN, which is the voltage of the target voltage node NVIN, and outputs it to the voltage divider node NDIV. The comparator circuit 160 compares the voltage VDIV of the voltage divider node NDIV with the reference voltage VREF. The voltage divider circuit 110 includes first resistors RA1 to nth resistors RAN and first transistors TA1 to nth transistors TAN. n is an integer of 3 or more. The first resistors RA1 to nth resistors RAN are connected in series between the target voltage node NVIN and the voltage divider node NDIV. The i-th transistor TAi of the first transistors TA1 to nth transistors TAN is connected in parallel with the i-th resistor RAi of the first resistors RA1 to nth resistors RAN. i is an integer of 1 or more and n less. Transistors TA1 through TAN are controlled to be turned on or off according to control data XBIT[n-1:0] from control circuit 150. Control circuit 150 sets transistor TAj to either be on or off, and sets transistors TA1 through (j-1)th transistors TAj-1 to either be on or off. J is an integer greater than or equal to 2 and less than or equal to n. Control circuit 150 determines the on or off state of transistor TAj based on the comparison result of comparator circuit 160, and determines control data XBIT[7:0]. Based on the determined control data XBIT[7:0], control circuit 150 outputs measurement data SAR[7:0] of the measured voltage VIN.

[0043] According to this embodiment, transistors TA1 through TAN are turned on one by one, and the bits of the measurement data SAR[7:0] corresponding to the turned-on transistors are determined based on the comparison result of the comparison circuit 160 at this time. This reduces the number of transistors that are simultaneously switched on and off during voltage measurement, thus reducing voltage fluctuations caused by charge injection from the transistors. Consequently, the accuracy of voltage measurement can be improved.

[0044] In addition, Figure 1 In the example, n = 8. Figure 2 and Figure 3 In the example, the data BIT[7:0] is determined as the logical inversion data of the control data XBIT[7:0], and the measurement data SAR[7:0] of the measured object voltage VIN is output based on this data BIT[7:0]. This is equivalent to determining the control data XBIT[7:0], and the measurement data SAR[7:0] of the measured object voltage VIN is output based on this control data XBIT[7:0]. In Figure 2 and Figure 3In the example described, the control circuit 150 sets the j-th transistor TAj to be on and sets the first transistor TA1 to the (j-1)-th transistor TAj-1 to be off, and determines whether the j-th transistor TAj is on or off based on the comparison result of the comparator circuit 160. However, it is also possible for the control circuit 150 to set the j-th transistor TAj to be off and set the first transistor TA1 to the (j-1)-th transistor TAj-1 to be on, and determine whether the j-th transistor TAj is on or off based on the comparison result of the comparator circuit 160.

[0045] In this embodiment, the control circuit 150 may also set the nth transistor TAn to either on or off, and set the first transistor TA1 to the (n-1)th transistor TAn-1 to the other side of on or off, determining whether the nth transistor TAn is on or off based on the comparison result of the comparator circuit 160. Similarly, the control circuit 150 may set the (n-1)th transistor TAn-1 to either on or off, and set the first transistor TA1 to the (n-2)th transistor TAn-2 to the other side of on or off, determining whether the (n-1)th transistor TAn-1 is on or off based on the comparison result of the comparator circuit 160. Likewise, the control circuit 150 may also set the first transistor TA1 to either on or off, determining whether the first transistor TA1 is on or off based on the comparison result of the comparator circuit 160.

[0046] Thus, as in Figure 2 and Figure 3 As explained in the document, the maximum number of transistors that can be switched on and off simultaneously is 2. Therefore, compared with the counter method in Patent Document 1, the number of transistors that can be switched on and off simultaneously during voltage measurement can be reduced, and voltage fluctuations caused by charge injection from the transistors can be reduced.

[0047] In addition, in this embodiment, among the first resistor RA1 to the nth resistor RAN, the resistance value of the first resistor RA1 is the smallest, and the resistance value of the nth resistor RAN is the largest. The resistance values ​​are weighted by binary.

[0048] According to this embodiment, the resistance value of the variable resistor circuit composed of the first resistor RA1 to the nth resistor Ran and the first transistor TA1 to the nth transistor TAn is linear with respect to the data BIT[7:0]. Moreover, as described above, while the first transistor TA1 to the nth transistor TAn are turned on sequentially, the measurement data SAR[7:0] is determined bit by bit from the top bit according to the comparison result of the comparison circuit 160. That is, the measurement data SAR[7:0] is determined by a so-called binary search.

[0049] Alternatively, in this embodiment, the voltage divider circuit 110 may also include a first resistor circuit 111 disposed between the first node N1 and the voltage divider node NDIV. The first resistor RA1 to the nth resistor RAN may also be connected in series between the first node N1 and the voltage node NVIN of the object being measured.

[0050] In addition, in this embodiment, the resistance value of the first resistor circuit 111 may also be greater than the total resistance value of the first resistor RA1 to the nth resistor RAN.

[0051] According to this embodiment, voltage fluctuations caused by charge injection from the first transistor TA1 to the nth transistor TAN are attenuated by the first resistor circuit 111 and propagate to the voltage divider node NDIV. Therefore, the comparison in the comparator circuit 160 is less affected by voltage fluctuations, and the accuracy of voltage measurement is improved.

[0052] Alternatively, in this embodiment, the voltage divider circuit 110 may also include a second resistor circuit 112 disposed between the voltage divider node NDIV and the ground node NGND.

[0053] According to this embodiment, the voltage divider circuit 110 can divide the voltage VIN of the object to be measured and the ground voltage GND through the first resistor RA1 to the nth resistor RAN, the first resistor circuit 111 and the second resistor circuit 112.

[0054] In addition, in this embodiment, the circuit device 100 may also intermittently measure the voltage VIN of the object to be measured. "Intermittently measuring" means that calculating the measurement data SAR[7:0] once or multiple times is taken as one measurement action, and the voltage VIN of the object to be measured is not measured between each measurement action, that is, there is a period in which the measurement data SAR[7:0] is not calculated.

[0055] According to this embodiment, since the measured power consumption is intermittent, the power consumption of the circuit device 100 can be reduced. Furthermore, compared to a counter method as described in Patent Document 1, the measurement time can be shortened through binary search, thus reducing the circuit's operating time and further reducing power consumption.

[0056] 2. Example of the second structure

[0057] Figure 4 This is a diagram illustrating a second structural example of the circuit device 100. Furthermore, regarding... Figure 4 The structure other than that shown in the diagram and description is the same as that in the first structural example. In the second structural example, the voltage divider circuit 110 further includes a first charge absorption transistor TBi1 and a second charge absorption transistor TBi2. i is an integer greater than or equal to 1 and less than or equal to 8.

[0058] The first charge-absorbing transistor TBi1 and the second charge-absorbing transistor TBi2 are P-type MOS transistors. The source and drain of the first charge-absorbing transistor TBi1 are connected to the source of the i-th transistor TAi. The source and drain of the second charge-absorbing transistor TBi2 are connected to the drain of the i-th transistor TAi. The logic inversion signal BIT[i-1] of the signal XBIT[i-1] input to the gate of the first charge-absorbing transistor TBi1 and the second charge-absorbing transistor TBi2 is applied to the gate of the i-th transistor TAi. The gate area of ​​the first charge-absorbing transistor TBi1 and the second charge-absorbing transistor TBi2 is half the gate area of ​​the i-th transistor TAi.

[0059] Taking i=1 as an example. When the signal XBIT[0] changes from low to high or from high to low, charge is generated at the source and drain of the first transistor TA1 due to charge injection. However, since the logic level of the signal BIT[0] changes in the opposite logic to that of the signal XBIT[0], the first charge absorption transistor TB11 absorbs the charge at the source, and the second charge absorption transistor TB12 absorbs the charge at the drain. Therefore, the voltage fluctuation of the voltage divider node NDIV caused by charge injection is reduced. Since the gate area of ​​each charge absorption transistor is half the gate area of ​​the first transistor TA1, the amount of charge generated due to charge injection is the same as the amount of charge absorbed by the two charge absorption transistors. Thus, the voltage fluctuation of the voltage divider node NDIV caused by charge injection is effectively reduced. The same applies to the cases of i=2 to i=8.

[0060] In this embodiment, the voltage divider circuit 110 includes a first charge absorption transistor TBi1 and a second charge absorption transistor TBi2. The first charge absorption transistor TBi1 is connected to the source of the i-th transistor TAi, and its gate is input with the inverted signal BIT[i-1] of the i-th bit XBIT[i-1] of the control data XBIT[7:0]. The second charge absorption transistor TBi2 is connected to the drain of the i-th transistor TAi, and its gate is input with the inverted signal BIT[i-1] of the i-th bit XBIT[i-1].

[0061] As described above, each charge-absorbing transistor absorbs the charge at the source and drain of the i-th transistor TAi caused by charge injection. Therefore, the voltage fluctuation at the voltage divider node NDIV caused by charge injection is reduced.

[0062] In addition, in this embodiment, the gate area of ​​the first charge absorption transistor TBi1 and the second charge absorption transistor TBi2 may also be half the gate area of ​​the i-th transistor TAi.

[0063] As described above, the amount of charge generated by charge injection is the same as the amount of charge absorbed by the two charge absorption transistors. Therefore, the voltage fluctuation at the voltage divider node NDIV caused by charge injection is effectively reduced.

[0064] 3. Example of the third structure

[0065] Figure 5 This is a third structural example of circuit device 100. Furthermore, structures other than those described below are the same as those in the first or second structural examples. In the third structural example, the voltage divider circuit 110 includes a P-type MOS transistor 115, a variable resistor circuit RA, a first resistor circuit 111, and a second resistor circuit 112. The variable resistor circuit RA refers to the variable resistor circuit composed of the first resistor RA1 to the eighth resistor RA8 and the first transistor TA1 to the eighth transistor TA8. The control circuit 150 includes a register 140.

[0066] The first resistor circuit 111 includes a resistor RB, a switch SWB, a resistor RC, and a first fine-tuning resistor RT1. Resistor RB and switch SWB are connected in parallel between the first node N1 and node NB. Resistor RC is connected between node NB and node NC. The first fine-tuning resistor RT1 is connected between node NC and voltage divider node NDIV.

[0067] The second resistor circuit 112 includes a second trimming resistor RT2 and a resistor RC. The second trimming resistor RT2 is connected between the voltage divider node NDIV and node ND. The resistor RC is connected between node NC and ground node NGND.

[0068] The control circuit 150 controls the switch SWB to be on or off by outputting a switch control signal XS to the switch SWB, thus setting the measurement range of the voltage VIN of the object being measured. The measurement range refers to the range between the voltage value of the object being measured corresponding to the minimum value of the measurement data SAR[7:0] and the voltage value of the object being measured corresponding to the maximum value of the measurement data SAR[7:0]. The measurement range when the switch SWB is on is lower than the measurement range when the switch SWB is off. That is, the upper limit of the measurement range when the switch SWB is on is lower than the upper limit of the measurement range when the switch SWB is off, and the lower limit of the measurement range when the switch SWB is on is lower than the lower limit of the measurement range when the switch SWB is off.

[0069] The first trimmer resistor RT1 and the second trimmer resistor RT2 are variable resistors that adjust the voltage measurement deviation caused by the deviation of the reference voltage VREF. For example, the reference voltage VREF is generated based on the bandgap voltage, and the reference voltage VREF is deviated due to individual deviations in the bandgap voltage. In this case, for the same measurement target voltage VIN, the resistance ratio of the first trimmer resistor RT1 and the second trimmer resistor RT2 is adjusted to obtain the same measurement data SAR[7:0]. Specifically, register 140 stores the trimmer data TRIM[7:0]. The control circuit 150 outputs the trimmer data TRIM[7:0] as resistance ratio control data SW[7:0] to the first trimmer resistor RT1 and the second trimmer resistor RT2. Thus, the resistance ratio of the first trimmer resistor RT1 and the second trimmer resistor RT2 is set. The trimmer data TRIM[7:0] is measured in advance, such as during the manufacture of the circuit device 100. For example, circuit device 100 includes a non-volatile memory (not shown) pre-stored with fine-tuning data TRIM[7:0], and control circuit 150 loads the fine-tuning data TRIM[7:0] from the non-volatile memory into register 140. Alternatively, an electronic device including circuit device 100 may also include a non-volatile memory (not shown) pre-stored with fine-tuning data TRIM[7:0] and a processing device. Furthermore, the fine-tuning data TRIM[7:0] can also be written from the non-volatile memory to register 140 by the processing device.

[0070] The method for determining the fine-tuning data TRIM[7:0] is explained. Figure 6 This is the truth table for normal mode and test mode. When the mode signal TMODE is 0, it is normal mode. Normal mode is the mode in which the circuit device 100 performs normal operations such as voltage measurement. When the mode signal TMODE is 1, it is test mode. Test mode is the mode that determines the fine-tuning data TRIM[7:0]. The mode signal TMODE is set from an external device, for example. TMODE=0 can be the default setting, or it can be set from a register of the electronic device containing the circuit device 100. TMODE=1 is set from a check device that checks the circuit device 100, for example.

[0071] When TMODE=1, i.e., test mode, control circuit 150 outputs 00000000 as data BIT[7:0], i.e., outputs 11111111 as control data XBIT[7:0]. As a result, transistors TA1 through TA8 are all turned off, and the resistance value of the variable resistor circuit RA reaches its maximum. Furthermore, control circuit 150 changes the resistance ratio control data SW[7:0], thereby changing the resistance ratio between the first trimmer resistor RT1 and the second trimmer resistor RT2. For example, control circuit 150 changes the resistance ratio sequentially from its minimum to its maximum value, and the resistance ratio control data SW[7:0] when the output signal XHDL of the output comparator circuit 160 is inverted is used as measurement data SAR[7:0]. This measurement data SAR[7:0] becomes the trimmer data TRIM[7:0] in normal mode. For example, an external inspection device obtains the measurement data SAR[7:0] from the circuit device 100 in test mode and writes it as trimmer data TRIM[7:0] into a non-volatile memory (not shown).

[0072] When TMODE=0, i.e., in normal mode, the fine-tuning data TRIM[7:0] written to non-volatile memory or the like is loaded into register 140. The control circuit 150 outputs the fine-tuning data TRIM[7:0] from register 140 as resistance ratio control data SW[7:0]. Thus, the resistance ratio of the first fine-tuning resistor RT1 and the second fine-tuning resistor RT2 is controlled using the fine-tuning data TRIM[7:0] determined in test mode. In addition, the control circuit 150 determines the data BIT[7:0] corresponding to the voltage VIN to be measured using the method described in the first structural example, and outputs the data BIT[7:0] as measurement data SAR[7:0].

[0073] Figure 7 This is a detailed structural example of the first trimmer resistor RT1 and the second trimmer resistor RT2. The first trimmer resistor RT1 consists of resistors RP1 to RP8 and switches SP1 to SP8. Resistors RP1 to RP8 are connected in series between node NC and voltage divider node NDIV. Switch SPk is connected in parallel with resistor RPk. k is an integer greater than 1 and less than 8. The resistance values ​​of resistors RP1 to RP8 are binary-weighted. The second trimmer resistor RT2 consists of resistors RN1 to RN8 and switches SN1 to SN8. Resistors RN1 to RN8 are connected in series between voltage divider node NDIV and node ND. Switch SNk is connected in parallel with resistor RNk. The resistance values ​​of resistors RN1 to RN8 are binary-weighted. The resistance value of resistor RNk is the same as the resistance value of resistor RPk.

[0074] The control circuit 150 inputs a bit signal SW[k-1] of the resistance ratio control data SW[7:0] to the switch SPk of the first fine-tuning resistor RT1. Switch SPk is turned on when SW[k-1] is high and turned off when SW[k-1] is low. The logic inversion signal XSW[k-1] of the bit signal SW[k-1] is input to the switch SNk of the second fine-tuning resistor RT2. Switch SNk is turned on when XSW[k-1] is high and turned off when XSW[k-1] is low. When one of the switches SPk of the first fine-tuning resistor RT1 and SNk of the second fine-tuning resistor RT2 is turned on, the other is turned off, and the resistance values ​​of resistors RPk and RNk are the same. Therefore, the sum of the resistance values ​​of the first fine-tuning resistor RT1 and the second fine-tuning resistor RT2 remains unchanged (RP1+RP2+…+RP8), and the resistance ratio of the first fine-tuning resistor RT1 and the second fine-tuning resistor RT2 changes.

[0075] In this embodiment, the voltage divider circuit 110 includes a first fine-tuning resistor RT1 disposed between the first node N1 and the voltage divider node NDIV, and a second fine-tuning resistor RT2 disposed between the voltage divider node NDIV and the ground node NGND. The first resistor RT1 to the nth resistor RAN are connected in series between the target voltage node NVIN and the first node N1. The deviation of the reference voltage VREF is adjusted using the resistance ratio of the first fine-tuning resistor RT1 and the second fine-tuning resistor RT2.

[0076] According to this embodiment, the deviation of the voltage measurement result caused by the deviation of the reference voltage VREF is adjusted. For example, even if the reference voltage VREF is deviated due to the individual deviation of the circuit device 100, the same measurement data SAR[7:0] can be obtained for the same measurement target voltage VIN in each individual.

[0077] In addition, in this embodiment, the total resistance value of the first fine-tuning resistor RT1 and the second fine-tuning resistor RT2 can also be constant and independent of the resistance ratio.

[0078] When the total resistance of the voltage divider circuit 110 changes due to the deviation of the reference voltage VREF, the measurement range of the target voltage VIN may change. According to this embodiment, the total resistance of the first trimmer resistor RT1 and the second trimmer resistor RT2 remains constant; therefore, even if the deviation of the reference voltage VREF is adjusted, the total resistance of the voltage divider circuit 110 remains unchanged. Thus, even if the deviation of the reference voltage VREF is adjusted, the measurement range of the target voltage VIN does not change.

[0079] 4. Electronic devices and systems

[0080] Figure 8This is a structural example of an electronic device 200 and a system 400, which include a circuit device 100. The system 400 includes a power supply device 300 and an electronic device 200. Hereinafter, an example of the power supply device 300 supplying power to the electronic device 200 via contactless power transmission will be described, but power supply can also be contact-based.

[0081] The power supply device 300 includes a power supply coil L1, a power supply circuit 310, and a control circuit 320. The power supply circuit 310 supplies power to the electronic device 200 by driving the power supply coil L1. The control circuit 320 controls the power supply of the power supply circuit 310.

[0082] Electronic device 200 includes circuitry 100, battery 210, and processing device 220. Battery 210 is, for example, a secondary battery, such as a lithium-ion secondary battery, nickel-metal hydride battery, or nickel-cadmium battery. Alternatively, battery 100 can also be implemented using a supercapacitor or the like. Processing device 220 is a device that controls electronic device 200, such as a processor like a CPU or microcomputer.

[0083] The circuit device 100 includes a receiving coil L2, a receiving circuit 170, a charging circuit 180, a voltage divider circuit 110, a control circuit 150, a comparator circuit 160, and a discharging circuit 190. The voltage divider circuit 110, control circuit 150, and comparator circuit 160 are described in the first to third structural examples; here, the battery voltage of the battery 210 is the target voltage VIN. The receiving circuit 170 receives power from the transmitting coil L1 via the receiving coil L2. That is, the receiving circuit 170 rectifies the AC voltage generated in the receiving coil L2 by the transmitted power into a DC voltage. The charging circuit 180 charges the battery 210 using the power received by the receiving circuit 170. The discharging circuit 190 supplies power to the processing device 220 using the power from the battery 210. For example, the discharging circuit 190 is a DC-DC converter that converts the battery voltage into the power supply voltage of the processing device 220.

[0084] Electronic device 200 is, for example, a hearing aid or an audio-visual headset, or a wearable device. The headset is, for example, referred to as a wireless headset. Furthermore, electronic device 200 can include various devices such as head-mounted displays, smartphones, mobile phones, and other portable communication terminals, watches, biometric measuring devices, shavers, electric toothbrushes, list computers, handheld terminals, or in-vehicle systems for automobiles.

[0085] Furthermore, while this embodiment has been described in detail above, those skilled in the art will readily understand that various modifications can be made without substantially departing from the new aspects and effects of this disclosure. Therefore, all such modifications are included within the scope of this disclosure. For example, a term described at least once with a different term that is more general or synonymous can be replaced with that different term anywhere in the specification or drawings. Additionally, all combinations of this embodiment and its modifications are also included within the scope of this disclosure. Furthermore, the structure and operation of systems, electronic devices, power transmission devices, circuit devices, voltage divider circuits, control circuits, and comparison circuits are not limited to the structures and operations described in this embodiment, and various modifications can be implemented.

Claims

1. A circuit device characterized by comprising: a voltage-dividing circuit provided between a measurement target voltage node and a ground node, dividing a voltage of the measurement target voltage node, that is, a measurement target voltage, and outputting to a voltage-dividing node; a comparison circuit comparing a voltage of the voltage-dividing node with a reference voltage; and a control circuit, the voltage-dividing circuit comprising: first to nth resistors provided in series between the measurement target voltage node and the voltage-dividing node, where n is an integer of 3 or more; first to nth transistors, where an ith transistor is connected in parallel to an ith resistor among the first to nth resistors, and is controlled to be turned on or turned off according to control data from the control circuit, where i is an integer of 1 or more and n or less, the control circuit setting a jth transistor to one of turned on and turned off, and setting the first to j-1th transistors to the other of turned on and turned off, deciding turned on or turned off of the jth transistor according to a comparison result of the comparison circuit, thereby deciding the control data, where j is an integer of 2 or more and n or less, the control circuit outputting measurement data of the measurement target voltage according to the decided control data.

2. The circuit device according to claim 1, characterized in that the control circuit sets the nth transistor to one of turned on and turned off, and sets the first to n-1th transistors to the other of turned on and turned off, decides turned on or turned off of the nth transistor according to a comparison result of the comparison circuit, sets the n-1th transistor to one of turned on and turned off, and sets the first to n-2th transistors to the other of turned on and turned off, decides turned on or turned off of the n-1th transistor according to a comparison result of the comparison circuit, and performs the processing in the above manner until n = 1, that is, sets the first transistor to one of turned on and turned off, and decides turned on or turned off of the first transistor according to a comparison result of the comparison circuit.

3. The circuit device according to claim 1, characterized in that in the first to nth resistors, a resistance value of the first resistor is the smallest, a resistance value of the nth resistor is the largest, and the resistance values are binary weighted.

4. The circuit device according to claim 1, characterized in that the voltage-dividing circuit comprises a first resistor circuit provided between a first node and the voltage-dividing node, the first to nth resistors are connected in series between the first node and the measurement target voltage node.

5. The circuit device according to claim 4, characterized in that a resistance value of the first resistor circuit is larger than a total resistance value of the first to nth resistors.

6. The circuit device according to claim 4, characterized in that the voltage-dividing circuit comprises a second resistor circuit provided between the voltage-dividing node and the ground node.

7. The circuit device according to claim 1, characterized in that the voltage-dividing circuit comprises: ​ ​ a first charge absorption transistor connected to a source of the i-th transistor, a gate of the first charge absorption transistor being inputted with an inverted signal of the i-th bit of the control data; and a second charge absorption transistor connected to a drain of the i-th transistor, a gate of the second charge absorption transistor being inputted with the i-th bit.

8. The circuit device according to claim 7, wherein gate areas of the first and second charge absorption transistors are half of a gate area of the i-th transistor.

9. The circuit device according to claim 1, wherein the voltage dividing circuit includes: a first trimming resistor provided between a first node and the voltage dividing node; and a second trimming resistor provided between the voltage dividing node and the ground node, the first through n-th resistors are connected in series between the measurement target voltage node and the first node, the circuit device performs the offset adjustment of the reference voltage in accordance with a resistance ratio of the first and second trimming resistors.

10. The circuit device according to claim 9, wherein a total resistance value of the first and second trimming resistors is constant regardless of the resistance ratio.

11. The circuit device according to claim 1, wherein the circuit device intermittently performs the measurement of the measurement target voltage.

12. An electronic device, comprising: the electronic device includes: the circuit device according to any one of claims 1 to 11; and a battery, the measurement target voltage is a battery voltage of the battery.

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