Methods, apparatus, and articles of manufacture for mitigating interference in Doppler distance representations

Abstract

The invention relates to a method, an apparatus, and an article of manufacture for mitigating interference in Doppler distance representations. An example apparatus includes interface circuitry (212) for receiving digital samples representing a chirp frame. The apparatus includes programmable circuitry (214) programmable by instructions to: determine, for a range Fourier transform (FT) representation of the chirp frame, a reconstructed chirp in the chirp frame that includes chirps of corrupted samples; determining a first Doppler range representation of the chirp frame based on the range FT representation, the range FT representation including the reconstructed chirp; and determining a second Doppler distance representation as an element-by-element minimum between the first Doppler distance representation and a third Doppler distance representation of the chirp frame, the third Doppler distance representation based on the digital samples including reconstructed samples that replace the corrupted samples of the chirp. Other examples are described.

Description

[0001] Cross Reference to Related Applications

[0002] This patent application claims the benefit of and priority to Indian Provisional Patent Application No. 202441067446, filed September 6, 2024, which is hereby incorporated by reference in its entirety. TECHNICAL FIELD

[0003] This description generally relates to Doppler division multiple access radar, and more particularly, to methods, apparatuses, and articles for mitigating interference in Doppler range profiles. BACKGROUND

[0004] Doppler division multiple access (DDMA) is a method that divides the Doppler dimension or Doppler domain into multiple sub-zones and assigns transmitters to one sub-zone. This can be performed by generating a chirp sequence such that there is a linear increase (or decrease) in the beginning phase of each chirp. Different transmitters can have different rates of phase increase or decrease. Multiple transmitters are enabled for each chirp. When received and processed according to a two-dimensional fast Fourier transform (FFT), the DDMA signals from different transmitters will each occupy a different frequency band in the Doppler domain. In this way, DDMA facilitates simultaneous use of multiple transmitters within a single chirp, while preventing multiple transmitters from interfering with each other in the Doppler domain, also providing the ability to separate data from each transmitter. SUMMARY

[0005] For methods, apparatuses, and articles for mitigating interference in Doppler range profiles, one example apparatus includes interface circuitry to receive digital samples representing a chirp frame. The apparatus includes programmable circuitry to: determine, for a range Fourier transform (FT) representation of the chirp frame, a reconstructed chirp of a chirp in the chirp frame that includes a corrupt sample; determine, based on the range FT representation, a first Doppler range representation of the chirp frame, the range FT representation including the reconstructed chirp; and determine a second Doppler range representation as an element-wise minimum between the first Doppler range representation of the chirp frame and a third Doppler range representation, the third Doppler range representation based on the digital samples including reconstructed samples that replace the corrupt sample of the chirp. The programmable circuitry can be one or more programmable circuits that are programmable by instructions. Other examples are described.

[0006] For methods, apparatus, and articles of manufacture for mitigating interference in Doppler range representations, one example non-transitory computer-readable medium includes instructions for causing programmable circuitry to determine, for a range Fourier transform (FT) representation of a chirp frame, a reconstructed chirp of a chirp in the chirp frame that includes a corrupt sample, the chirp frame received from an environment by a radar integrated circuit and represented by digital samples. The non-transitory computer-readable medium includes instructions for causing programmable circuitry to determine, based on the range FT representation, a first Doppler range representation of the chirp frame, the range FT representation including the reconstructed chirp. The non-transitory computer-readable medium includes instructions for causing programmable circuitry to determine a second Doppler range representation as an element-wise minimum between the first Doppler range representation of the chirp frame and a third Doppler range representation, the third Doppler range representation based on the digital samples including reconstructed samples that replace the corrupt sample of the chirp. The programmable circuitry can be one or more programmable circuits programmable by the instructions. Other examples are described.

[0007] For methods, apparatus, and articles of manufacture for mitigating interference in Doppler range representations, one example method includes receiving, with interface circuitry, digital samples representing a chirp frame. The method includes replacing, with zero-value chirps, in the digital samples, chirps in the chirp frame that include corrupt samples, by executing instructions with programmable circuitry. The method includes determining, with the programmable circuitry, based on the digital samples, a range Fourier transform (FT) representation of the chirp frame, the digital samples including the zero-value chirps, the range FT representation having a first dimension and a second dimension. The method includes determining, for respective indices across the second dimension of the range FT representation, Doppler FT representations, by executing instructions with the programmable circuitry. The method includes, for respective Doppler FT representations: setting, with the programmable circuitry, to zero, values that do not satisfy a threshold for peaks in the respective Doppler FT representation; and determining, with the programmable circuitry, an inverse range FT representation to generate reconstructed chirps. The method includes replacing, with the programmable circuitry, in the range FT representation, the chirps that include the corrupt samples with the reconstructed chirps. The method includes determining, with the programmable circuitry, based on the range FT representation, a Doppler range representation of the chirp frame, the range FT representation including the reconstructed chirps. The programmable circuitry can be one or more programmable circuits programmable by the instructions. Other examples are described. BRIEF DESCRIPTION OF DRAWINGS

[0008] Figure 1 A block diagram of an example radar system including example radar circuitry.

[0009] Figure 2 may be implemented Figure 1A block diagram of any example of a radar transceiver integrated circuit (IC) in a radar circuit.

[0010] Figure 3A A timing diagram of instance frames for instance chirping.

[0011] Figure 3B A diagram of the instance processing flow for generating an instance Doppler distance representation of the received frame after reflection chirping.

[0012] Figure 4A This is a timing diagram of interference that can occur in radar applications.

[0013] Figure 4B For corresponding Figure 4A A graphical illustration of digital samples of the timing diagram.

[0014] Figure 5 A diagram of the instance processing flow for generating the first instance Doppler distance representation of the received frame after reflection chirping to mitigate interference along the distance dimension.

[0015] Figure 6 A diagram of the instance processing flow for generating a second instance Doppler distance representation of the received frame with reflected chirp to mitigate interference along the Doppler dimension.

[0016] Figure 7 A diagram of the instance processing flow for generating a third instance Doppler distance representation of the received frame after reflection chirping to mitigate interference along the range and Doppler dimensions.

[0017] Figure 8 A diagram showing the instance processing flow for reconstructing damaged ADC samples along the distance and Doppler dimensions.

[0018] Figure 9 To represent a flowchart of instance machine-readable instructions or instance operations, you can use Figure 2 The instance programmable circuit system implementation of the radar transceiver IC performs at least one of the following operations: implements instance machine-readable instructions or instance operations, instantiates instance machine-readable instructions or instance operations, or executes instance machine-readable instructions or instance operations to determine the Doppler range representation thereby mitigating interference along the range dimension and the Doppler dimension.

[0019] Figure 10 To represent a flowchart of instance machine-readable instructions or instance operations, you can use Figure 2An instance programmable circuit system implementation of a radar transceiver IC performs at least one of the following operations: executes an instance machine-readable instruction or instance operation, instantiates an instance machine-readable instruction or instance operation, or executes an instance machine-readable instruction or instance operation to determine a reconstructed chirp containing a corrupted sample of reflected chirp.

[0020] Figure 11 To represent a flowchart of instance machine-readable instructions or instance operations, you can use Figure 2 The instance programmable circuit system implementation of the radar transceiver IC performs at least one of the following operations: implements instance machine-readable instructions or instance operations, instantiates instance machine-readable instructions or instance operations, or executes instance machine-readable instructions or instance operations to determine the Doppler range representation thereby mitigating interference along the range dimension and the Doppler dimension.

[0021] Figure 12 For containing machine-readable instructions or executions that are constructed to implement, instantiate, or execute instances. Figure 9 , 10 and 11 instance operations to implement Figure 2 A block diagram of an example processing platform for a programmable circuit system of a radar transceiver IC.

[0022] Figure 13 for Figure 12 A block diagram of an example implementation of a programmable circuit system.

[0023] Figure 14 for Figure 12 A block diagram of another implementation scheme for a programmable circuit system.

[0024] Figure 15 This is a block diagram of an example software / firmware / instruction distribution platform (e.g., one or more servers), which is used to distribute software, instructions, or firmware (e.g., corresponding to...) Figure 9 , 10 The machine-readable instructions (and 11) are distributed to client devices associated with end users or consumers (e.g., for licensing, selling, or using), retailers (e.g., for selling, reselling, licensing, or sublicensing), or original equipment manufacturers (OEMs) (e.g., for inclusion in products to be distributed to, for example, retailers or other end users (e.g., direct purchase customers).

[0025] The diagrams are not necessarily to scale. Generally, one or more diagrams and the same reference numerals in this description refer to the same or similar features or parts (in terms of at least one of their function or structure). Although the diagrams show areas with clearly defined lines and boundaries, some or all of these lines and boundaries may be idealized. In reality, boundaries or lines may be unobservable, mixed, or irregular. Detailed Implementation

[0026] Figure 1 For example radar circuit 102 A 102 B 102 C 102 D 102 E 102 F 102 G 102 H A block diagram of an example radar system 100. In Figure 1 In this example, the radar system 100 also includes an instance processor circuit 104. Figure 1 In the example, radar circuit 102 A 102 B 102 C 102 D 102 E 102 F 102 G 102 H One or more of these components can be referred to as the radar front-end, and the processor circuit 104 can be referred to as the radar back-end. In some instances, radar circuit 102... A 102 B 102 C 102 D 102 E 102 F 102 G 102 H One or more of the components and processor circuitry 104 are implemented separately and may be adapted to be coupled together. Alternatively, radar circuitry 102... A 102 B 102 C 102 D 102 E 102 F 102 G 102 H One or more of these are implemented, for example, in a single-chip package or on a system-on-a-chip (SoC) (e.g., a single IC) as processor circuitry 104. In radar circuitry 102... A 102 B 102 C 102 D 102 E 102 F 102 G 102 H In an example where one or more of these are implemented as processor circuitry 104 on the SoC, radar circuitry 102...A 102 B 102 C 102 D 102 E 102 F 102 G 102 H One or more of them can correspond to the sub-circuits of the IC that form the SoC.

[0027] exist Figure 1 In the illustrated example, processor circuit 104 is coupled to radar circuit 102. A 102 B 102 C 102 D 102 E 102 F 102 G 102 H Each of these (e.g., via an interface) facilitates any suitable communication technology (e.g., serial interface, parallel interface, etc.) and is configured to perform at least one of the following operations: from radar circuit 102 A 102 B 102 C 102 D 102 E 102 F 102 G 102 H Each of the components receives data or transmits data to each of the radar circuits. In some instances, processor circuit 104 and radar circuit 102... A 102 B 102 C 102 D 102 E 102 F 102 G 102 H The interface between each of them can be a high-speed serial interface, such as a low-voltage differential signaling (LVDS) interface. Alternatively, the processor circuit 104 and the radar circuit 102... A 102 B 102 C 102 D 102 E 102 F 102 G 102 H The interface between each of them can be a low-speed interface, such as the Serial Peripheral Interface (SPI).

[0028] exist Figure 1In the illustrated example, radar circuit 102 A 102 B 102 C 102 D 102 E 102 F 102 G 102 H One or more of them can implement DDMA, as described herein. For example, radar circuit 102 A 102 B 102 C 102 D 102 E 102 F 102 G 102 H One or more of these can generate and emit chirp sequences into the environment, sometimes referred to as chirp frames, such that there is a linear increase (or decrease) in the initial phase of each chirp. Figure 1 In the example, radar circuit 102 A 102 B 102 C 102 D 102 E 102 F 102 G 102 H One or more of them include functions for generating one or more chirped signals as described herein. Additionally, radar circuit 102 A 102 B 102 C 102 D 102 E 102 F 102 G 102 H Each of these also includes the capability to generate one or more digital intermediate frequency (IF) signals (sometimes called dechirped signals, beat signals, or raw radar signals) from the reflected chirp.

[0029] exist Figure 1 In the illustrated example, radar circuit 102 A 102 B 102 C 102 D 102 E 102 F 102 G 102 HEach of these includes at least a portion for performing signal processing on the received radar signal (e.g., reflected chirp, digital IF signal, etc.), and a function for providing the result of the signal processing to the processor circuit 104. In some examples, radar circuit 102 A 102 B 102 C 102 D 102 E 102 F 102 G 102 H Each of these includes functionality for performing a range Fourier transform (FT) for each received frame (e.g., each sequence of chirps in the frames). Alternatively or concurrently, radar circuit 102... A 102 B 102 C 102 D 102 E 102 F 102 G 102 H Each of these contains functions for performing a Doppler FT for each received frame (e.g., after performing a range FT, and based on its result). In some of the examples provided herein, one or both of the range FT and the Doppler FT may be a range fast Fourier transform (FFT) and / or a Doppler FFT.

[0030] exist Figure 1 In the illustrated example, the processor circuit 104 includes the following functions: processing data from the radar circuit 102. A 102 B 102 C 102 D 102 E 102 F 102 G 102 H The processor circuitry 104 receives data from one or more sources to determine, for example, one or more of the distance, velocity, or angle of any object detected by the radar system 100. Alternatively or concurrently, the processor circuitry 104 includes functions for performing post-processing of information about the detected object, such as tracking the object or determining the rate and direction of motion. In some instances, the processor circuitry 104 performs at least one of velocity disambiguation or collision detection.

[0031] exist Figure 1 In the illustrated example, processor circuit 104 includes components for processing data from radar circuit 102. A 102 B 102 C 102D 102 E 102 F 102 G 102 H One or more processors or a combination of processors receive data from one or more of them. Figure 1 In this example, processor circuit 104 also provides data to radar circuit 102. A 102 B 102 C 102 D 102 E 102 F 102 G 102 H One or more of the following. For example, processor circuit 104 may include one or more of the following: digital signal processor (DSP), microcontroller, SoC combining both DSP and microcontroller, field programmable gate array (FPGA), or any combination thereof.

[0032] exist Figure 1 In the illustrated examples, radar system 100 can be implemented in various applications to measure distance, speed, acceleration, and angle, such as advanced driver assistance systems (ADAS) and motor vehicles. In some instances, radar system 100 can be implemented in other vehicles (e.g., aircraft or ships), industrial use cases, imaging radar, robotics, automation (e.g., industrial automation, building automation, etc.), security and surveillance (e.g., building security), people counting, or medical devices for blood pressure monitoring, mood monitoring, and sleep monitoring. Figure 1 In this example, radar system 100 is implemented in an automotive application. For instance, radar circuit 102... A 102 B 102 C 102 D 102 E 102 F 102 G 102 H Positioned around the vehicle to provide assistance to the driver. Figure 1 This demonstrates an example use case with eight radar circuits, while some vehicles may only have corner radar circuits. A 102 C 102 F 102 H Or forward radar circuit 102 E .

[0033] Figure 2 For implementation Figure 1 Radar circuit 102A 102 B 102 C 102 D 102 E 102 F 102 G 102 H A block diagram of an example radar transceiver integrated circuit (IC) 200, representing any of the above. Figure 2 In the example, radar transceiver IC 200, i.e., radar integrated circuit, includes example chirp synthesizer circuit 202 and example transmitters 2041 to 204. N Example transmitting antennas 2061 to 206 N Example receiving antennas 2081 to 208 M Instance receivers 2101 to 210 M Instance interface circuit system 212 and instance processor circuit 214. Additionally, in Figure 2 In the example, transmitters 2041 to 204 N Each includes instance phase shifters 2161 to 216. N and example power amplifiers (PAs) 2181 to 218 N .

[0034] exist Figure 2 In the illustrated example, receivers 2101 to 210 M Each example includes low-noise amplifiers (LNAs) 2201 to 220. M Example mixers 2221 to 222 M and example analog-to-digital converters (ADCs) 2241 to 224 M .exist Figure 2 In one example, the radar transceiver IC 200 includes transmitters 2041 to 2044. N Transmitting antennas 2061 to 206 N Receiving antennas 2081 to 208 M and receivers 2101 to 210 M Four of each of them (e.g., N equals M equals four). In some instances, the radar transceiver IC 200 contains different numbers of transmitters 2041 to 204. N Transmitting antennas 2061 to 206 N Receiving antennas 2081 to 208 M Or receiver 2101 to 210 M Any one of them.

[0035] In some instances, the radar transceiver IC 200 and the processor circuitry 214 are implemented separately and may be adapted to be coupled together. Alternatively, the radar transceiver IC 200 may be implemented as processor circuitry 214, for example, in a single-chip package or on a SoC (e.g., a single IC). In the instance where the radar transceiver IC 200 is implemented as processor circuitry 214 on the SoC, the radar transceiver IC 200 may correspond to a sub-circuit of the IC forming the SoC.

[0036] exist Figure 2 In the illustrated example, the chirped synthesizer circuit 202 is implemented by at least one of an analog or digital circuit system. Figure 2 In this example, the chirped synthesizer circuit 202 is coupled to transmitters 2041 to 2044. N For example, the chirped synthesizer circuit 202 is coupled to transmitters 2041 to 2044. N Phase shifters 2161 to 216 N Additionally, in Figure 2 In this example, the chirped synthesizer circuit 202 is coupled to receivers 2101 to 210. M For example, the chirped synthesizer circuit 202 is coupled to receivers 2101 to 210. M Mixers 2221 to 222 M In some instances, the chirped synthesizer circuit 202 is coupled to the processor circuit 214.

[0037] exist Figure 2 In the illustrated example, phase shifters 2161 to 216 N Each of these is implemented by at least one of an analog or digital circuit system. Figure 2 In the examples, phase shifters 2161 to 216 N Each of these is coupled to the chirped synthesizer circuit 202. Additionally, in Figure 2 In the examples, phase shifters 2161 to 216 N Coupled to PA 2181 to 218 N (For example, the corresponding phase shifter is coupled to the corresponding PA). In Figure 2 In the examples, PA 2181 to 218 N Each of these is implemented by at least one of an analog or digital circuit system. Additionally, in Figure 2 In the examples, PA 2181 to 218 N Coupled to phase shifters 2161 to 216 N and transmitting antennas 2061 to 206 N .

[0038] In modern applications, radar circuits (e.g., Figure 2The radar transceiver IC 200 contains multiple transmitters and multiple receivers. DDMA provides a method for dividing the Doppler domain spectrum into multiple sub-segments and assigning each of the multiple transmitters to a corresponding sub-segment. For example, DDMA is widely used in automotive frequency modulated continuous wave (FMCW) radar applications. In DDMA, multiple transmitters simultaneously transmit chirped frames, where the chirp across frames by each transmitter applies a linear phase transition (Φ). For the k-th indexed transmitter, Where N TX Let be the number of transmitters, and k be the number of transmitters that will emit a phase transition Φ. k The index value of the transmitter of the signal within the range [1:N]. Therefore, N TX The phase transition of the transmitter is proportional to the transmitter index and increases linearly. DDMA generation is divided into N. TX The Doppler domain spectrum of each frequency band, wherein each target detected by the radar circuitry generates N... TX There are N peaks or representations, and each peak (e.g., an image) corresponds to N. TX One of the transmitters.

[0039] exist Figure 2 In the illustrated example, radar transceiver IC 200 implements DDMA. For instance, chirp synthesizer circuit 202 includes functionality for receiving chirp parameter values ​​(e.g., from processor circuit 214) of a chirp sequence in a radar frame. In some instances, the chirp parameters are defined by the radar system architecture and may include, for example, functions for indicating transmitters 2041 to 2044. N Which transmitter enable parameters are enabled, the start value of the chirp frequency, the chirp frequency slope, the ADC sampling time, the ramp-up end time, and the transmitter start time, etc.? Figure 2 In some instances, the chirped synthesizer circuit 202 also includes functionality for generating signals (e.g., chirps, chirped frames, etc.) for transmission based on chirp parameter values ​​(e.g., received from processor circuit 214). In some instances, the chirped synthesizer circuit 202 includes a phase-locked loop (PLL) oscillator with a voltage-controlled oscillator (VCO). In additional or alternative instances, the chirped synthesizer circuit 202 includes a local oscillator (LO).

[0040] exist Figure 2 In the illustrated example, phase shifters 2161 to 216 NEach of the components receives an output signal (e.g., a chirp, a chirped frame, etc.) provided by the chirped synthesizer circuit 202 and modulates the output signal provided by the chirped synthesizer circuit 202 to generate a chirped frame with a linear phase transition across the chirp. For example, for the first instance index transmitter 2041, the first instance index phase shifter 2161 applies a first phase transition Φ1 between consecutive chirps of the frame. Therefore, the first index phase shifter 2161 generates a chirped frame in which the phase transitions between consecutive chirps of the frame are equal (e.g., ΔΦ for TX1). C1-C2 =ΔΦ C2-C3 =ΔΦ C3-C4 …=ΔΦ C(N-1)-CN Additionally, for example, for the Nth instance index emitter 204 N The Nth instance index phase shifter 216 N Apply the Nth phase transition Φ between consecutive chirps of the frame. N Therefore, the Nth index phase shifter 216 N Generate chirped frames where the phase transitions between consecutive chirps of a frame are equal (e.g., for TX). N , ΔΦ C1-C2 =ΔΦ C2-C3 =ΔΦ C3-C4 …=ΔΦ C(N-1)-CN ).

[0041] Figure 3A For example, chirp 3061 to 306 N Timing diagram 302 for instance frame 304. In Figure 3A In this example, timing diagram 302 depicts frequency versus time. For example... Figure 3A As explained in the text, chirp is a signal in which the frequency of the signal changes linearly over time. Figure 3A In some instances, frame 304 refers to a series (e.g., N) of chirps that are equally spaced in time. Therefore, in some instances, frame 304 is referred to as an FMCW frame. Figure 3A In this example, frame 304 contains a linear increase (or decrease) in the phase of each chirp of frame 304. Therefore, the phase transitions between consecutive chirs of frame 304 are equal (e.g., ΔΦ). C1-C2 =ΔΦ C2-C3 =ΔΦ C3-C4 …=ΔΦ C(N-1)-CN (When chirping 3061 to 306) N When frame 304 is emitted into the environment and reflected from an object, the received frame can be processed according to a two-dimensional FFT and represented as a Doppler distance representation.

[0042] Return to Figure 2 transmitters 2041 to 204 N Simultaneously, chirped frames are transmitted, with transmitters 2041 to 204...N Each chirp across frames in the model applies a phase transition (Φ), as described above. Figure 2 In the examples, LNA 2201 to 220 M Each of these is implemented by at least one of an analog or digital circuit system. Figure 2 In the examples, LNA 2201 to 220 M Coupled to mixers 2221 to 222 M and receiving antennas 2081 to 208 M Additionally, mixers 2221 to 222 M Each of these is implemented by at least one of an analog or digital circuit system. Figure 2 In the examples, mixers 2221 to 222 M Coupled to chirped synthesizer circuits 202, LNA2201 to 220 M and ADC 2241 to 224 M .

[0043] exist Figure 2 In the examples described, ADC 2241 to 224 M Each of these is implemented by at least one of an analog or digital circuit system. Figure 2 In the examples, ADC 2241 to 224 M Coupled to mixers 2221 to 222 M Interface circuit system 212. Furthermore, interface circuit system 212 is implemented by at least one of analog or digital circuit systems. For example, interface circuit system 212 is implemented according to communication technologies such as serial interfaces (e.g., SPI, LVDS interfaces, etc.), parallel interfaces, etc., and is configured to facilitate communication according to the communication technology. Figure 2 In this example, the interface circuit system 212 is coupled to ADCs 2241 to 224. M And processor circuit 214.

[0044] exist Figure 2 In the illustrated example, processor circuitry 214 is coupled to interface circuitry system 212. In some examples, processor circuitry 214 is coupled to chirped synthesizer circuitry 202. Figure 2 In this example, the processor circuit 214 is implemented by at least one of an analog or digital circuit system. For example, the processor circuit 214 may be implemented by a DSP, a microcontroller, an FFT engine, a combined DSP and microcontroller processor, an FPGA, or an application-specific integrated circuit (ASIC).

[0045] exist Figure 2In the illustrated example, processor circuit 214 can be instantiated (e.g., created, generated, materialized, implemented, etc.) by a programmable circuit system (e.g., at least one programmable circuit), such as a central processing unit (CPU) executing a first instruction, an FPGA, a programmable logic device (PLD), a general-purpose array logic (GAL) device, a programmable array logic (PAL) device, a complex programmable logic device (CPLD), a simple programmable logic device (SPLD), a microcontroller unit (MCU), a programmable system-on-a-chip (PSoC), etc. Alternatively or concurrently, Figure 2 The processor circuitry 214 can be instantiated (e.g., created, generated, materialized, implemented, etc.) by (i) an ASIC or (ii) an FPGA that is constructed or configured to perform operations corresponding to the first instruction in response to the execution of the second instruction. Therefore, some or all of the processor circuitry 214 can be instantiated at the same or different times. Some or all of the processor circuitry 214 can be instantiated, for example, in one or more threads that are executed simultaneously or serially on hardware. Furthermore, in some instances, some or all of the processor circuitry 214 can be implemented by a microprocessor circuitry system that executes instructions or an FPGA circuitry system that performs operations to implement one or more virtual machines or containers.

[0046] exist Figure 2 In the illustrated example, receiving antennas 2081 to 208 M Each of these receives signals reflected from the environment within the field of view of the radar transceiver IC 200. For example, receiving antennas 2081 to 208... M Each of them receives a reflected chirped frame from the environment. Because the chirped frame is reflected from the environment, there is a time delay or phase shift between the transmitted chirped frame and the reflected chirped frame. Figure 2 In the examples, LNA 2201 to 220 M Each of the components amplifies the received frame after reflection and chirping, and forwards the amplified received frame to mixers 2221 to 222. M .exist Figure 2 In the examples, mixers 2221 to 222 M Each of these components mixes the amplified received frame with a chirped frame provided by the chirped synthesizer circuit 202 to produce a chirped IF received frame. Additionally, ADCs 2241 to 224... M Each of them samples the chirped IF received frame to generate a digital sample of the analog signal.

[0047] exist Figure 2 In the illustrated example, the interface circuit system 212 ranges from ADC 2241 to 224. MIt receives digital samples and forwards them to processor circuit 214 for processing. Figure 2 In one example, the radar transceiver IC 200 has R MAX Specification, where R MAX This refers to the maximum range of targets that the radar transceiver IC 200 can detect. The radar transceiver IC 200 implements IF filtering to filter out targets with a value greater than τ. MAX The delayed reflected signal, where τ MAX Equals two Rs MAX Divide by the speed of light IF filtering ensures that the signal has reduced or minimal bandwidth while allowing detection of signals from the target of interest, and thus helps minimize the ADC sampling rate. IF filtering also helps minimize interference from other radars.

[0048] In some instances, the radar transceiver IC 200 includes ADCs 2241 to 224. M The digital front-end (DFE) circuitry between the interface circuitry 212 and the receiver 210. For example, the DFE circuitry extends from receiver 2101 to 210. M The system receives the IF signal and performs decimation filtering or other processing operations on the digital IF signal, such as reducing the data transmission rate of the digital IF signal. Alternatively, the DFE circuitry performs other operations on the digital IF signal, such as those performed by receivers 2101 to 210. M DC offset removal or compensation (e.g., digital compensation) for non-ideals in the receiver (e.g., inter-receiver gain imbalance non-ideal, inter-receiver phase imbalance non-ideal, etc.).

[0049] exist Figure 2 In the illustrated example, processor circuitry 214 receives digital samples representing reflected chirped frames from interface circuitry 212. Figure 2 In some instances, processor circuitry 214 is configured to perform at least a portion of signal processing on the digital IF signal generated from the received radar frame. In other instances, processor circuitry 214 is configured to transmit the result of the signal processing. For example, processor circuitry 214 transmits the result of the signal processing to a processing unit (e.g., processor circuitry 104).

[0050] exist Figure 2 In the illustrated example, processor circuitry 214 includes functionality for performing a range FFT on each received frame after the reflected chirp. For instance, the location of the signal power peak in the range dimension across the range FFT directly corresponds to the distance of the target from radar transceiver IC 200. Figure 3BIn some instances, processor circuitry 214 also includes functionality for performing a Doppler FFT on the result of a distance FFT. In some instances, processor circuitry 214 receives control information (e.g., chirp timing, power levels, triggering of monitoring functions, etc.) via an SPI bus. For example, based on the control information, processor circuitry 214 provides data parameters or control signals to chirp synthesizer circuitry 202.

[0051] Figure 3B This is a diagram of an instance processing flow 308 for generating an instance Doppler distance representation 310 of a chirped received frame. For example, the processing flow 308 for generating the Doppler distance representation 310 (sometimes referred to as a Doppler distance heatmap) includes processor circuitry 214 processing digital samples representing the chirped received frame to generate an instance matrix 312 of the distance FFT. Figure 3B In this example, the rows of matrix 312 correspond to the distance FFT of the corresponding chirped segment in the received frame after reflection chirping, and the columns of matrix 312 correspond to the distance dimension of the distance FFT. In this way, targets captured in the received frame after reflection chirping are separated by distance.

[0052] exist Figure 3B In the illustrated example, processor circuitry 214 generates a Doppler range representation 310 by processing the range FFT representation of the chirped received frame (e.g., matrix 312) across the range dimension (e.g., columns of matrix 312). For example, processor circuitry 214 performs an FFT (e.g., Doppler FFT) across the range dimension of the range FFT representation. In this way, targets captured in the chirped received frame are separated by velocity. Therefore, the Doppler range representation 310 of the chirped received frame resolves the target in both the range dimension and the Doppler (e.g., velocity) dimension.

[0053] exist Figure 4AIn the illustrated example, the Doppler range representation 310 is a three-dimensional plot depicting distance in meters (m) and velocity in meters per second (m / s), where the signal in the two-dimensional range-velocity field has associated values ​​providing a third dimension. Signal peaks in the Doppler range representation 310 correspond to targets in the field of view of the radar transceiver IC 200. For example, the Doppler range representation 310 includes a first instance representation 314 of a first object in the field of view of the radar transceiver IC 200 and a second instance representation 316 of a second object in the field of view of the radar transceiver IC 200. For simplicity, the Doppler range representation 310 corresponds to an embodiment of the radar transceiver IC 200 with a single transmitter (e.g., a first index transmitter 2041) without DDMA modulation. For example, the Doppler range representation 310 depicts the first representation 314 of the first object and the second representation 316 of the second object. In the case of DDMA modulation, the Doppler distance representation 310 will contain N instances of a first object and a second object with Doppler offsets, the Doppler offsets corresponding to the distances at transmitters 2041 to 204... N The phase shift applied.

[0054] Figure 4A Timing diagram 402 illustrates interference that can occur in radar applications. Timing diagram 402 represents interference during the detection of example chirp 404. Figure 4A In this example, timing diagram 402 depicts frequency versus time. For example... Figure 4A As explained, chirp 404 is a signal in which the frequency of the signal changes linearly with time. Figure 4A In the instance, the instance delay window 406 around chirp 404 (e.g., by τ) MAX (Indicates) that the signal and chirp 404 are in-band. For example, delay window 406 corresponds to a frequency difference of tens of megahertz (MHz) relative to the frequency of chirp 404 at a given time.

[0055] Based on down-conversion and low-pass filtering (e.g., performed by radar transceiver IC 200), only the portion of the signal within delay window 406 and chirp 404 is in-band. Therefore, only the portion of the chirp that overlaps with delay window 406 and chirp 404 is in-band. Figure 4B In the instance, interference occurs whenever instance cross chirp 408 intersects chirp 404 in the band (e.g., intersecting with delay window 406). Figure 4A For corresponding Figure 4B A graphical illustration of the digital samples in timing diagram 402 is provided in 410. Figure 2In the example, the instance digital sample 412 corresponding to the portion of chirp 404 that overlaps with cross-chirp 408 is corrupted. If the signal power of cross-chirp 408 is greater than the signal power of chirp 404 (e.g., several decibels (dB) greater than the signal power of chirp 404), the degree of corruption of digital sample 412 increases.

[0056] In radar applications (e.g., automotive applications), interference from other radars can severely impair performance. With increasing radar penetration and automation levels, the extent to which interference between radars damages performance will increase. To facilitate the coexistence of multiple radars, radar interference must be mitigated. Numerous studies have been conducted to explore interference mitigation techniques. These include the IMIKO project by the Cooperation in Radar for Autonomous Electric Cars, the MOSARIM project in the European Union (Providing Greater Safety for All Through Radar Interference Mitigation), and radar interference research conducted by the National Highway Traffic Safety Administration (NHTSA) in the United States.

[0057] Generally, techniques for mitigating interference involve detection and reconstruction. Detection involves detecting digit samples corrupted by interference. Many detection techniques are possible. One instance detection technique involves calculating the average magnitude of digit samples in the chirp and identifying samples with magnitudes greater than a threshold above the average magnitude as corrupted samples. Reconstruction involves reconstructing the corrupted digit samples. Reconstruction can reduce artifacts caused by interference in Doppler distance representations (e.g., heatmaps). One reconstruction technique involves setting the chirped corrupted digit samples to zero, performing a distance FFT on the digit samples containing zero-value samples, and identifying peaks in the distance FFT. The distance FFT is a complex matrix. Therefore, peaks within the distance FFT correspond to the maximum absolute value of the distance FFT.

[0058] Based on the peak value, the reconstruction technique includes setting values ​​in the distance FFT that are outside a threshold of the peak value to zero, and performing an inverse distance FFT to generate reconstructed digital samples. For example, the reconstruction technique includes setting values ​​in the distance FFT that are greater than or below a threshold of the peak value to zero. After generating the reconstructed digital samples, the reconstruction technique includes replacing corrupted digital samples with the reconstructed digital samples. The reconstruction technique described above can be used for all chirps in a chirped frame to generate a chirped frame containing reconstructed samples. After reconstructing all chirped samples for a frame, the signal processor can perform a distance FFT on the chirped frame containing the reconstructed samples and perform a Doppler FFT on the distance FFT to generate a Doppler distance representation.

[0059] The reconstruction techniques described above mitigate interference caused by interfering chirps with a slope significantly different from the chirp being monitored (also known as scanning interference sources). However, different types of interference sources are possible. For example, the reconstruction techniques described above do not mitigate interference caused by interfering chirps with a slope similar to the chirp being monitored (also known as parallel interference sources). In the example described herein, processor circuitry 214 reduces interference artifacts in the Doppler range representation caused by both scanning and parallel interference sources. For example, processor circuitry 214 reconstructs the chirp along both the range and Doppler dimensions to generate a hybrid Doppler range representation that improves the overall performance of radar transceiver IC 200.

[0060] Return to Figure 5 In the illustrated example, processor circuit 214 generates two Doppler distance representations of the received chirped frame and calculates the element-wise minimum between the two Doppler distance representations to generate a composite Doppler distance representation of the received chirped frame, which mitigates interference along both the distance and Doppler dimensions. For example, processor circuit 214 generates a first Doppler distance representation of the chirped frame that mitigates interference along the distance dimension, and generates a second Doppler distance representation of the chirped frame that mitigates interference along the Doppler dimension. Figure 5 A diagram of instance processing flow 500 for generating a first instance Doppler distance representation 502 of the received frame after reflection chirping to mitigate interference along the distance dimension.

[0061] exist Figure 5 In the illustrated example, the first instance process 504 includes processor circuitry 214 reconstructing corrupted digital samples based on a distance FFT, where values ​​outside a threshold of peak values ​​are set to zero. For example, the first process 504 includes processor circuitry 214 setting the chirped instance corrupted ADC sample 506 in the instance matrix 508 of chirped ADC samples to zero. For example, corrupted ADC sample 506 is an ADC sample in matrix 508 that has been identified as affected by interference (e.g., by a detection technique). Figure 5 In the example, the rows of matrix 508 correspond to the corresponding chirps in the received frame after reflection chirping, and the columns of matrix 508 correspond to ADC samples in time.

[0062] exist Figure 5 In the illustrated example, the first process 504 includes processor circuitry 214 performing a distance FFT on matrix 508 (with zero-value ADC samples) to identify peaks in the distance FFT representation of matrix 508. Figure 5In this example, the distance FFT representation of matrix 508 is a complex matrix. Therefore, the first process 504 includes processor circuitry 214 converting the distance FFT representation of matrix 508 (e.g., by taking its absolute value) into a positive real matrix for the purpose of identifying peaks. Figure 5 In one instance, the first process 504 further includes processor circuitry 214 setting the value of the distance FFT representation of matrix 508 that does not meet the threshold (e.g., a threshold greater than or below the peak, a threshold greater than or above the peak, etc.) to zero.

[0063] For example, the first process 504 includes processor circuitry 214 setting values ​​in the distance FFT representation of matrix 508 that are greater than or below a threshold (e.g., do not meet) to zero. Figure 5 In this example, the threshold is 3dB. The first process 504 also includes processor circuitry 214 performing an inverse distance FFT on the distance FFT representation (with zeroed values) of matrix 508 to generate an instance of a corrupted ADC sample 506, followed by a reconstructed ADC sample 510. Figure 5 In one instance, the first process 504 includes processor circuitry 214 replacing the damaged ADC sample 506 in matrix 508 with a reconstructed ADC sample 510.

[0064] exist Figure 5 In the illustrated example, the second instance procedure 512 includes processor circuitry 214 performing a distance FFT on matrix 508 (with reconstructed ADC samples 510). Figure 5 In this example, the second process 512 includes performing a Doppler FFT on the distance FFT representation of matrix 508 (with reconstructed ADC samples 510) to generate a first Doppler distance representation 502. The first Doppler distance representation 502 is a three-dimensional plot depicting distance in meters versus velocity in m / s, where signals in the two-dimensional distance-velocity field have associated magnitudes providing a third dimension. Generally, the first Doppler distance representation 502 is a complex matrix. Therefore, the processor circuitry 214 can determine the absolute value of the first Doppler distance representation 502 to convert it into magnitudes before performing subsequent processing.

[0065] exist Figure 2In the illustrated example, the first Doppler range representation 502 includes a first instance representation 514 of a first object in the field of view of the radar transceiver IC 200 and a second instance representation 516 of a second object in the field of view of the radar transceiver IC 200. For simplicity, the Doppler range representation 502 corresponds to an embodiment of the radar transceiver IC 200 having a single transmitter (e.g., a first index transmitter 2041) without DDMA modulation. For example, the Doppler range representation 502 depicts a first representation 514 of the first object and a second representation 516 of the second object. In the case of DDMA modulation, the Doppler range representation 502 would include N instances of the first and second objects with Doppler offsets corresponding to transmitters 2041 to 2042. N The phase shift applied.

[0066] Additionally, processing flow 500 corresponds to the operation executed by processor circuitry 214 to generate a first Doppler range representation 502 for the reflected chirped frames received at a single receiver (e.g., the first index receiver 2101). Specifically, processor circuitry 214 targets receivers 2101 to 210 of the radar transceiver IC 200. M Processing flow 500 is performed on each of the received reflected chirped frames, where M Doppler distances represent M instances containing the first and second objects. In such an instance, processor circuitry 214 pairs receivers 2101 to 210. M The first Doppler distance representation of each of the elements is summed to generate a composite first Doppler distance representation.

[0067] Return to Figure 6 In the illustrated example, processor circuitry 214 generates a second Doppler distance representation of the chirped frame, which mitigates interference along the Doppler dimension. For example, Figure 6 A diagram of instance processing flow 600 for generating a second instance Doppler distance representation 602 of the received frame after reflection chirping to mitigate interference along the Doppler dimension. Figure 6 In one instance, the first instance process 604 includes processor circuitry 214 setting the chirp of matrix 508 containing the corrupted ADC sample 506 to an instance zero-value chirp 606. For example, processor circuitry 214 sets the values ​​of the rows of matrix 508 containing the corrupted ADC sample 506 to zero to generate zero-value chirp 606.

[0068] exist Figure 6In the illustrated example, the first process 604 includes processor circuitry 214 performing a distance FFT on matrix 508 (with zero-value chirps 606) to generate an instance distance FFT representation 608 of matrix 508. For example, processor circuitry 214 performs a distance FFT on the non-zero chirps (e.g., non-zero rows) of matrix 508 to generate the distance FFT representation 608. Figure 6 In one instance, the second instance process 610 includes processor circuitry 214 performing a Doppler FFT on each column of the distance FFT representation 608 and identifying peaks in the Doppler FFT representation of each column of the distance FFT representation 608. For example, the distance FFT representation 608 and the Doppler FFT representation of each column thereof are complex matrices. Therefore, the second process 610 includes processor circuitry 214 converting at least one of the distance FFT representation 608 or the Doppler FFT representation of each column (e.g., by taking the absolute value) into at least one positive real matrix for the purpose of identifying peaks.

[0069] exist Figure 6 In the illustrated example, the second process 610 includes processor circuitry 214 that, for each column of the FFT representation 608, sets the values ​​of the Doppler FFT representations of each column of the FFT representation 608 that do not meet a peak threshold (e.g., a threshold greater than or below the peak, a threshold greater than or above the peak, etc.) to zero. For example, the second process 610 includes processor circuitry 214 that, for each column of the FFT representation 608, sets the values ​​of the Doppler FFT representations of each column of the FFT representation 608 that are greater than or below (e.g., do not meet) a peak threshold to zero. Figure 6 In one instance, the threshold is 3dB. The second process 610 further includes processor circuitry 214 performing an inverse Doppler FFT on each column of the Doppler FFT representation of the distance FFT representation 608 to generate a reconstructed chirp 612 of matrix 508 containing instances of chirps from corrupted ADC samples 506. Figure 6 In one instance, the second process 610 includes processor circuitry 214 replacing the zero-value chirp 606 of the distance FFT representation 608 of matrix 508 with a reconstructed chirp 612.

[0070] exist Figure 6In the illustrated example, the third instance process 614 includes processor circuitry 214 performing a Doppler FFT on the distance FFT representation 608 (with reconstructed chirp 612) to generate a second Doppler distance representation 602. The second Doppler distance representation 602 is a three-dimensional graph depicting distance in meters versus velocity in m / s, where the signals in the two-dimensional distance-velocity field have associated magnitudes providing a third dimension. Generally, the second Doppler distance representation 602 is a complex matrix. Therefore, processor circuitry 214 can determine the absolute value of the second Doppler distance representation 602 to convert it into magnitudes before performing subsequent processing.

[0071] exist Figure 2 In the illustrated example, the second Doppler range representation 602 includes a first instance representation 616 of a first object in the field of view of the radar transceiver IC 200 and a second instance representation 618 of a second object in the field of view of the radar transceiver IC 200. For simplicity, the Doppler range representation 602 corresponds to an embodiment of the radar transceiver IC 200 having a single transmitter (e.g., a first index transmitter 2041) without DDMA modulation. For example, the Doppler range representation 602 depicts a first representation 616 of the first object and a second representation 618 of the second object. In the case of DDMA modulation, the Doppler range representation 602 would include N instances of the first and second objects with Doppler offsets corresponding to transmitters 2041 to 2042. N The phase shift applied.

[0072] Additionally, processing flow 600 corresponds to the operation executed by processor circuitry 214 to generate a second Doppler range representation 602 for the reflected chirped frames received at a single receiver (e.g., the first index receiver 2101). Specifically, processor circuitry 214 targets receivers 2101 to 210 of the radar transceiver IC 200. M Processing flow 600 is performed on each of the received reflected chirped frames, where M Doppler distances represent M instances containing the first and second objects. In such an instance, processor circuitry 214 pairs receivers 2101 to 210. M The second Doppler distance representation of each of the elements is summed to generate a composite second Doppler distance representation.

[0073] Return to Figure 7 In the illustrated example, processor circuitry 214 generates a third Doppler distance representation as the element-wise minimum between a first Doppler distance representation (e.g., first Doppler distance representation 502) that mitigates interference along the range dimension of the chirped frame and a second Doppler distance representation (e.g., second Doppler distance representation 602) that mitigates interference along the range dimension of the chirped frame. For example,Figure 7 A diagram of instance processing flow 700 for generating a third instance Doppler range representation 702 of the received frame after reflection chirping to mitigate interference along the range and Doppler dimensions. Figure 7 In one instance, the processor circuit 214 generates a third Doppler distance representation 702 by calculating the element-wise minimum between the first instance Doppler distance representation 704 and the second instance Doppler distance representation 706.

[0074] exist Figure 5 In the examples described, according to Figure 5 The processing flow 500 generates the first Doppler distance representation 704. For example, the first Doppler distance representation 704 corresponds to... Figure 7 The first Doppler distance is represented as 502. Figure 6 In the example, according to Figure 6 The processing flow 600 generates a second Doppler distance representation 706. For example, the second Doppler distance representation 706 corresponds to... Figure 7 The second Doppler distance is represented as 602. For example... Figure 2 As explained in the document, the first Doppler distance representation 704 contains a first instance interference artifact 708 across the distance library, and the second Doppler distance representation 706 contains a second instance interference artifact 710 across the Doppler library.

[0075] By calculating the third Doppler distance representation 702 as the element-wise minimum between the first Doppler distance representation 704 and the second Doppler distance representation 706, the processor circuit 214 reduces the first interference artifact 708 and the second interference artifact 710. For example, the element-wise minimum between the first Doppler distance representation 704 and the second Doppler distance representation 706 does not preserve the first interference artifact 708 or the second interference artifact 710. Therefore, based on the third Doppler distance representation 702, the processor circuit 214 can better detect the first instance representation 712 of the first object, the second instance representation 714 of the second object, and the third instance representation 716 of the third object. Thus, the third Doppler distance representation 702 generated by the processor circuit 214 is a better approximation of the instance-ideal Doppler distance representation 718 of the received frame after reflection chirping compared to the first Doppler distance representation 704 or the second Doppler distance representation 706.

[0076] As described above, Doppler range representation 502 and Doppler range representation 602 correspond to an embodiment of a radar transceiver IC 200 with a single transmitter (e.g., the first index transmitter 2041) without DDMA modulation. In the case of DDMA modulation, Doppler range representation 502 and Doppler range representation 602 would contain N instances of a first object, a second object, and a third object with Doppler offsets corresponding to transmitters 2041 to 2044. N The applied phase shift. Additionally, processor circuit 214 actually performs processing steps 500 and 600 for the reflected chirped frames received at radar transceiver IC 200. In fact, processor circuit 214 processes receivers 2101 to 210... M The first Doppler distance representations of each of the elements in the array are summed in step 502 to generate a composite first Doppler distance representation. Additionally, processor circuitry 214 actually pairs receivers 2101 to 210. M The second Doppler distance representation 602 of each element is summed to generate a composite second Doppler distance representation. In fact, when processing flow 700 is executed, processor circuit 214 generates a third Doppler distance representation 702 as the element-wise minimum between the composite first Doppler distance representation and the composite second Doppler distance representation.

[0077] Return to Figure 2 As illustrated in the examples, by generating the first Doppler range representation 502 and the second Doppler range representation 602 as described above, the processor circuit 214 improves the dynamic range of the range library of the Doppler range representation and the dynamic range of the Doppler library. For example, by generating the first Doppler range representation 502 as described above, the processor circuit 214 improves the dynamic range of the individual range library of the first Doppler range representation 502. Furthermore, by generating the second Doppler range representation 602 as described above, the processor circuit 214 improves the dynamic range of the individual Doppler library of the second Doppler range representation 602. Therefore, by generating the third Doppler range representation 702 as described above (e.g., performing reconstruction along the range dimension and the Doppler dimension), the processor circuit 214 improves the overall performance of the radar transceiver IC 200.

[0078] exist Figure 8 In the illustrated example, processor circuitry 214 additionally or alternatively performs the process of reconstructing the corrupted ADC sample along the distance dimension and along the Doppler dimension. For example, Figure 8 A diagram of instance processing flow 800 for reconstructing corrupted ADC samples along the distance and Doppler dimensions. Figure 8In this example, the instance matrix 802 of the chirped ADC samples contains instance zero-value samples 804 corresponding to damaged ADC samples. For example, a damaged ADC sample is an ADC sample in matrix 802 that has been identified as being affected by interference (e.g., by a detection technique).

[0079] exist Figure 8 In the illustrated example, the rows of matrix 802 correspond to the corresponding chirps in the received frame after reflection chirping, and the columns of matrix 802 correspond temporally to ADC samples. Figure 8 In one instance, the first instance process 806 includes processor circuitry 214 performing a two-dimensional FFT on matrix 802. For example, processor circuitry 214 performs a distance FFT along the rows of matrix 802 and a Doppler FFT along the columns represented by the distance FFT of matrix 802.

[0080] exist Figure 8 In the illustrated example, the two-dimensional FFT representation of matrix 802 is a complex matrix. Therefore, processor circuitry 214 converts the two-dimensional FFT representation of matrix 802 into a real positive matrix to generate the instance Doppler distance representation 808. For example, processor circuitry 214 temporarily converts the two-dimensional FFT representation of matrix 802 into a real positive matrix in order to determine the peak value of the Doppler distance representation 808 as described below. For example, processor circuitry 214 converts the two-dimensional FFT representation of matrix 802 into a real positive matrix by taking the absolute value of the two-dimensional FFT representation of matrix 802. In some instances, processor circuitry 214 converts the two-dimensional FFT representation of matrix 802 into a real positive matrix by taking the logarithm of the absolute value of the two-dimensional FFT representation of matrix 802.

[0081] exist Figure 8 In the illustrated example, based on the first process 806, the processor circuit 214 generates the Doppler distance representation 808 of the matrix 802. Figure 8 In one example, the second instance process 810 includes processor circuitry 214 identifying instance peaks 812 (after conversion to a real positive matrix) in the Doppler distance representation 808. Additionally, the second process 810 includes processor circuitry 214 setting values ​​in the Doppler distance representation 808 that do not satisfy a threshold for peak 812 (e.g., a threshold greater than or below the peak, a threshold greater than or above the peak, etc.) to zero. For example, the second process 810 includes processor circuitry 214 setting values ​​in the Doppler distance representation 808 that are greater than or below (e.g., do not satisfy) a threshold for peak 812 to zero. Figure 8 In this example, the threshold is 6dB.

[0082] exist Figure 8In the illustrated example, based on the second process 810, the processor circuit 214 generates an instance zero-value Doppler distance representation 814. For example, the zero-value Doppler distance representation 814 includes instances of peak value 812, values ​​816 that satisfy a threshold, and instance zero values ​​818 corresponding to values ​​that do not satisfy the threshold in the Doppler distance representation 808. Figure 8 In the example, the third instance process 820 includes processor circuitry 214 performing an inverse two-dimensional FFT on the zero-value Doppler distance representation 814.

[0083] For example, processor circuitry 214 performs an inverse Doppler FFT along the columns of the zero-value Doppler distance representation 814 and an inverse distance FFT along the rows of the zero-value Doppler distance representation 814 to generate an instance matrix 822 of reconstructed chirped ADC samples. Figure 8 In this example, matrix 822 contains reconstructed ADC samples 824 corresponding to the zero-value samples 804 of matrix 802. Figure 9 In this instance, the fourth instance process 826 includes processor circuitry 214 replacing the zero-value sample 804 in matrix 802 with the reconstructed ADC sample 824. In this way, the damaged ADC sample in matrix 802 is replaced with the reconstructed ADC sample 824.

[0084] exist Figure 2 In the illustrated example, processor circuitry 214 can perform a two-dimensional FFT on the matrix output from processing flow 800. For example, processor circuitry 214 performs a distance FFT on matrix 802 (having reconstructed ADC samples 824), and performs a Doppler FFT on the distance FFT representation of matrix 802 to generate a Doppler distance representation of the reflected chirped frames. Figure 9 As explained in the document, the processing flow 800 reconstructs the damaged ADC sample along the distance dimension and the Doppler dimension.

[0085] Figure 9 To represent a flowchart of instance machine-readable instructions or instance operation 900, you can use Figure 9 The instance programmable circuit system implementation of the radar transceiver IC 210 performs at least one of the following operations: executes instance machine-readable instructions or instance operations, instantiates instance machine-readable instructions or instance operations, or executes instance machine-readable instructions or instance operations to determine the Doppler range representation thereby mitigating interference along the range dimension and the Doppler dimension. Figure 9 At least one of the instance machine-readable instructions or instance operations 900 begins at block 902, where transmitters 2041 to 204... N At least one of them will emit the chirped frame into the environment. For example, the first index transmitter 2041 will emit the chirped frame into the environment. In some instances, any number of transmitters 2041 to 204...N The chirped frame is emitted into the environment.

[0086] exist Figure 9 In the illustrated example, at box 904, receivers 2101 to 210 M At least one of them receives a reflected chirped frame from the environment. For example, the first index receiver 2101 receives a reflected chirped frame from the environment. In some instances, any number of receivers 2101 to 210 M Receive reflected chirped frames from the environment. Figure 9 In one example, at block 906, interface circuitry 212 receives digital samples representing reflected chirped frames. For instance, interface circuitry 212 receives digital samples from a first index receiver 2101. In some instances, interface circuitry 212 receives digital samples from any number of receivers 2101 to 210. M Receive digital samples.

[0087] exist Figure 5 In the illustrated example, at block 908, based on digital samples, processor circuitry 214 determines reconstructed samples of corrupted samples in a chirped frame. For example, for chirped frames, processor circuitry 214 sets corrupted samples to zero, determines a chirped distance FFT representation, and sets values ​​in the distance FFT representation that do not satisfy a threshold (e.g., outside of) a peak in the distance FFT representation to zero. For example, the distance FFT representation is a chirped distance FFT representation. Figure 9 In this example, the distance FT representation is a complex matrix. Therefore, processor circuit 214 converts the distance FT representation (e.g., by taking its absolute value) into a positive real matrix before determining the peak value. Figure 9 In one example, processor circuitry 214 sets values ​​in the distance FT representation that have an absolute value greater than or less than (e.g., do not meet) a threshold to zero. Alternatively, for example, processor circuitry 214 determines the inverse distance FT representation of the chirped distance FT representation to generate reconstructed samples.

[0088] Using reconstructed samples, processor circuitry 214 replaces damaged samples in the reflected chirp with reconstructed samples. In some instances, at block 908, processor circuitry 214 determines the reconstructed sample for each damaged sample in the reflected chirp frame. For example, processor circuitry 214, based on... Figure 6 The processing flow 500 determines the reconstructed sample for each corrupted sample in the reflected chirped frame. Figure 10In this example, at block 910, processor circuitry 214 determines a first Doppler distance representation of a chirped frame based on digital samples, wherein the digital samples contain chirped data with reconstructed samples. For example, processor circuitry 214 determines a range FT representation of the chirped frame based on the digital samples. Additionally, processor circuitry 214 determines a Doppler FT representation of the range FT representation to determine the first Doppler distance representation. For example, the Doppler FT representation is a Doppler FFT representation of the range FT representation.

[0089] exist Figure 9 In the illustrated example, at block 912, for the distance FT representation of the reflected chirped frame, processor circuitry 214 determines the reconstructed chirp of the reflected chirped frame containing the corrupted sample, where the distance FT representation is based on the digital sample. In some instances, at block 912, processor circuitry 214 determines the reconstructed chirp of each reflected chirped frame containing the corrupted sample. For example, processor circuitry 214 based on... Figure 9 The processing flow 600 identifies the reconstructed chirp for each reflected chirp containing the damaged sample. Combined with... Figure 10 The description and specification provide at least one of the example machine-readable instructions or example operations used to implement block 912.

[0090] exist Figure 2 In the illustrated example, at block 914, processor circuitry 214 determines a second Doppler range representation of the chirped frame based on the range FT representation of the chirped frame. For instance, processor circuitry 214 performs a Doppler FT along the range dimension (also referred to as the range library) of the range FT representation of the chirped frame to determine the second Doppler range representation. Figure 10 In this example, the distance FT representation includes the reconstructed chirp. At block 916, processor circuitry 214 determines the third Doppler distance representation as the element-wise minimum between the first and second Doppler distance representations. Therefore, the third Doppler distance representation contains relatively fewer interference artifacts than either the first or second Doppler distance representation. Consequently, subsequent processing based on the third Doppler distance representation will produce more accurate results.

[0091] Figure 10 To represent a flowchart of instance machine-readable instructions or instance operation 912, the following can be used: Figure 10 The instance programmable circuit system implementation of the radar transceiver IC 200 performs at least one of the following operations: executes instance machine-readable instructions or instance operations, instantiates instance machine-readable instructions or instance operations, or executes instance machine-readable instructions or instance operations to determine a reconstructed chirp containing a corrupted sample of reflected chirp. Figure 10At least one of the instance machine-readable instructions or instance operations 912 begins at block 1002, where processor circuitry 214 replaces the reflected chirp containing the corrupted sample with a zero-value chirp in the digital sample. In other words, a zero-value chirp replaces the reflected chirp containing the corrupted sample in the digital sample. In some instances, at block 1002, processor circuitry 214 replaces each reflected chirp containing the corrupted sample with a zero-value chirp.

[0092] exist Figure 10 In the illustrated example, at block 1004, processor circuitry 214 determines a distance FT representation of the reflected chirped frame based on digital samples, wherein the digital samples contain zero-value chirps. As described herein, the distance FT representation has a first dimension (e.g., height indicating the number of rows) and a second dimension (e.g., width indicating the number of columns). Figure 10 In the example, at box 1006, processor circuitry 214 determines the Doppler FT representation for the corresponding index of the second dimension of the distance FT representation. For instance, processor circuitry 214 determines the Doppler FT representation for each column of the distance FT representation.

[0093] exist Figure 11 In the illustrated example, the distance FT representation and Doppler FT representation of each column are complex matrices. Therefore, processor circuit 214 converts at least one of the distance FT representation or Doppler FT representation of each column (e.g., by taking the absolute value) into at least one positive real matrix before determining the peak value. Figure 2 In the example, at box 1008, for the corresponding Doppler FT representation, processor circuit 214 sets the value of the threshold that does not satisfy the peak in the corresponding Doppler FT representation to zero. Figure 11 In some instances, for a given Doppler FT representation, processor circuitry 214 sets values ​​greater than or below (e.g., not satisfying) a threshold in the corresponding Doppler FT representation to zero. In some instances, at block 1008, processor circuitry 214 sets all values ​​that do not satisfy the threshold to zero.

[0094] exist Figure 11In the illustrated example, at block 1010, for the corresponding Doppler FT representation, processor circuitry 214 determines an inverse Doppler FT representation to generate a reconstructed chirp. At block 1012, processor circuitry 214 replaces the reflected chirp in the range FT representation of the reflected chirp frame with the reconstructed chirp. For example, processor circuitry 214 replaces the reflected chirp containing the corrupted sample with the reconstructed chirp. In other words, the reconstructed chirp replaces the reflected chirp of the corrupted sample containing the chirp in the range FT representation. In some instances, at block 1012, processor circuitry 214 replaces all reflected chirps containing the corrupted sample with the reconstructed chirp. After block 1012, at block 914, at least one of instance machine-readable instructions or instance operation 912 returns to at least one of instance machine-readable instructions or instance operation 1002.

[0095] Figure 11 To represent a flowchart of instance machine-readable instructions or instance operation 1100, the following can be used: Figure 11 The instance programmable circuit system implementation of the radar transceiver IC 200 performs at least one of the following operations: implements instance machine-readable instructions or instance operations, instantiates instance machine-readable instructions or instance operations, or executes instance machine-readable instructions or instance operations to determine the Doppler range representation thereby mitigating interference along the range dimension and the Doppler dimension. Figure 11 At least one of the instance machine-readable instructions or instance operations 1100 begins at block 1102, where transmitters 2041 to 204... N At least one of the transmitter circuitry (the transmitter system) transmits the chirped frame into the environment. For example, the first index transmitter 2041 transmits the chirped frame into the environment. In some instances, any number of transmitters 2041 to 204... N The chirped frame is emitted into the environment.

[0096] exist Figure 11 In the illustrated example, at box 1104, receivers 2101 to 210... M At least one of the receiver circuitry receives a reflected chirped frame from the environment. For example, in a first instance, receiver 2101 receives a reflected chirped frame from the environment. In some instances, any number of receivers 2101 to 210... M Receive reflected chirped frames from the environment. Figure 11 In one example, at block 1106, interface circuitry 212 receives digital samples representing reflected chirped frames. For instance, interface circuitry 212 receives digital samples from a first index receiver 2101. In some instances, interface circuitry 212 receives digital samples from any number of receivers 2101 to 210. M Receive digital samples. Figure 11In one instance, at box 1108, processor circuitry 214 sets the corrupted samples of the chirped frames in the digital sample to zero. In some instances, processor circuitry 214 sets all corrupted samples in the chirped frames in the digital sample to zero.

[0097] exist Figure 11 In the illustrated example, at box 1110, processor circuitry 214 determines the distance FT representation of the reflected chirped frame based on digital samples. Figure 11 In the example, at block 1112, processor circuitry 214 determines the Doppler FT representation of the distance FT representation to generate a first Doppler distance representation of the reflected chirped frame. At block 1114, processor circuitry 214 determines the peak value of the first Doppler distance representation. Figure 11 In this instance, the first Doppler distance representation is a complex matrix. Therefore, the processor circuit 214 converts the first Doppler distance representation (e.g., by taking its absolute value) into a positive real matrix before determining the peak value.

[0098] exist Figure 12 In the illustrated example, at block 1116, processor circuitry 214 sets the absolute value of the first Doppler distance, representing the threshold that does not meet the peak value, to zero. Figure 9 In one instance, processor circuitry 214 sets values ​​in the first Doppler distance representation that are greater than or less than (e.g., do not meet) a threshold in the first Doppler distance representation to zero. In some instances, processor circuitry 214 sets all values ​​in the first Doppler distance representation that do not meet the threshold to zero.

[0099] exist Figure 2 In the illustrated example, at block 1118, processor circuitry 214 calculates the inverse Doppler Fourier Transform (FT) of the first Doppler distance representation to generate a distance FT representation. At block 1120, processor circuitry 214 calculates the inverse distance FT of the distance FT representation to generate a reconstructed sample of the corrupted sample. In some instances, processor circuitry 214 calculates both the inverse Doppler FT and the inverse distance FT to generate a reconstructed sample of all corrupted samples from the chirped frame. At block 1122, processor circuitry 214 replaces the corrupted sample in the digital sample with the reconstructed sample. In other words, the reconstructed sample replaces the chirped corrupted sample in the digital sample. In some instances, processor circuitry 214 replaces all corrupted samples with the reconstructed sample.

[0100] exist Figure 9In the illustrated example, at block 1124, processor circuitry 214 determines a second Doppler distance representation of the chirped frame based on digital samples, wherein the digital samples contain chirped data with reconstructed samples. For example, processor circuitry 214 determines a range FT representation of the chirped frame based on the digital samples. Additionally, for example, processor circuitry 214 determines a Doppler FT representation of the range FT representation to generate a second Doppler distance representation of the chirped frame.

[0101] Figure 13 This is a block diagram of an instance programmable circuit system platform 1200, which is configured to perform one or a combination of the following operations: implement or instantiate. Figure 12 , 10 One or more of the instance machine-readable instructions or instance operations of 11, to implement Figure 12 The radar transceiver IC 200. The programmable circuit system platform 1200 can be, for example, a server, personal computer, workstation, self-learning machine (e.g., neural network), mobile device (e.g., mobile phone, smartphone, e.g., iPad). TM Tablet computers, personal digital assistants (PDAs), internet devices, DVD players, CD players, digital video recorders, Blu-ray players, game consoles, personal video recorders, set-top boxes, headphones (e.g., augmented reality (AR) headphones, virtual reality (VR) headphones, etc.) or other wearable devices, or any other type of computing or electronic device.

[0102] The illustrated programmable circuit system platform 1200 includes a programmable circuit system 1212. The illustrated programmable circuit system 1212 is hardware. For example, the programmable circuit system 1212 may be implemented by one or more integrated circuits, logic circuits, FPGAs, microprocessors, CPUs, GPUs, DSPs, or microcontrollers from any desired series or manufacturer. The programmable circuit system 1212 may be implemented by one or more semiconductor-based (e.g., silicon-based) devices. In this example, the programmable circuit system 1212 implements an example chirped synthesizer circuit 202 and an example processor circuit 214.

[0103] The programmable circuit system 1212 of the illustrated example includes local memory 1213 (e.g., cache, registers, etc.). The programmable circuit system 1212 of the illustrated example communicates with main memories 1214 and 1216 via bus 1218, the main memories including volatile memory 1214 and non-volatile memory 1216. The volatile memory 1214 may be one or more synchronous dynamic random access memories (SDRAM) or dynamic random access memories (DRAM). Dynamic Random Access Memory Or any other type of RAM device. Non-volatile memory 1216 may be implemented by flash memory or one or a combination of any other desired type of memory device. Access to the main memory 1214, 1216 of the illustrated example is controlled by memory controller 1217. In some instances, memory controller 1217 may be implemented by one or more integrated circuits, logic circuits, microcontrollers, or any other type of circuit system from any desired series or manufacturer to manage the data flow to and from main memory 1214, 1216.

[0104] The programmable circuit system platform 1200 of the illustrated example also includes an interface circuit system 1220. The interface circuit system 1220 can be implemented in hardware according to any type of interface standard, such as an Ethernet interface, a Universal Serial Bus (USB) interface, etc. Interfaces include Near Field Communication (NFC) interfaces, Peripheral Component Interconnect (PCI) interfaces, and Peripheral Component Interconnect High Speed ​​(PCIe) interfaces.

[0105] In the illustrated example, one or more input devices 1222 are connected to the interface circuitry 1220. The input devices 1222 allow a user (e.g., a human user, a machine user, etc.) to input one or a combination of data or commands into the programmable circuitry 1212. The input devices 1222 may be implemented as, for example, an audio sensor, microphone, camera (still or video), keyboard, buttons, mouse, touchscreen, trackpad, trackball, dotted device, or a combination of voice recognition systems.

[0106] One or more output devices 1224 are also connected to the interface circuitry 1220 of the illustrated example. The one or more output devices 1224 may be implemented, for example, by one or a combination of a display device (e.g., a light-emitting diode (LED), an organic light-emitting diode (OLED), a liquid crystal display (LCD), a cathode ray tube (CRT) display, an in-situ switching (IPS) display, a touchscreen, etc.), a haptic output device, a printer, or a speaker. Therefore, the interface circuitry 1220 of the illustrated example includes one or a combination of a graphics driver card, a graphics driver chip, or a graphics processor circuitry system such as a GPU.

[0107] The interface circuit system 1220 of the illustrated example also includes communication devices, such as a transmitter, receiver, transceiver, modem, residential gateway, wireless access point, or network interface, or a combination thereof, to facilitate the exchange of data with external machines (e.g., any kind of computing device) via network 1226. Communication can be conducted via, for example, Ethernet connections, digital subscriber line (DSL) connections, telephone line connections, coaxial cable systems, satellite systems, beyond-line-of-sight wireless systems, line-of-sight wireless systems, cellular telephone systems, optical connections, etc. In this example, the interface circuit system 1220 implements example transmitters 2041 to 204... N Example transmitting antennas 2061 to 206 N Example receiving antennas 2081 to 208 M Instance receivers 2101 to 210 M and example interface circuit system 212.

[0108] The programmable circuit system platform 1200 of the illustrated example also includes one or more mass storage disks or devices 1228 for storing one or more of firmware, software, or data. Examples of such mass storage disks or devices 1228 include one or more magnetic storage devices (e.g., floppy disks, drives, HDDs, etc.), optical storage devices (e.g., Blu-ray discs, CDs, DVDs, etc.), RAID systems, or solid-state storage disks or devices, such as flash memory devices and SSDs.

[0109] can be Figure 9 , 10 The machine-readable instructions 1232 implemented by the machine-readable instructions of 11 may be stored in one or a combination of mass storage device 1228, volatile memory 1214, non-volatile memory 1216 or at least one non-transitory computer-readable storage medium (e.g., a removable CD or DVD).

[0110] Figure 2 for Figure 2 A block diagram of an example implementation of the programmable circuit system 1212. In this example, Figure 9 The programmable circuit system 1212 is implemented by the microprocessor 1300. For example, the microprocessor 1300 may be a general-purpose microprocessor (e.g., a general-purpose microprocessor circuit system). The microprocessor 1300 implements... Figure 12 , 10 Some or all of the machine-readable instructions in the flowchart of 11, in order to effectively translate Figure 13 The circuit system is instantiated as a logic circuit to perform operations corresponding to those machine-readable instructions. In some such instances, Figure 14The circuit system is instantiated by the hardware circuitry of the microprocessor 1300 in conjunction with machine-readable instructions. For example, the microprocessor 1300 may be implemented by a multi-core hardware circuitry system such as a CPU, DSP, GPU, XPU, etc. Although it may contain any number of instance cores 1302 (e.g., one core), this instance of the microprocessor 1300 is a multi-core semiconductor device containing N cores. The cores 1302 of the microprocessor 1300 may operate independently or collaboratively to execute machine-readable instructions. For example, machine code corresponding to firmware, embedded software, or software programs may be executed by one of the cores 1302, or by multiple cores 1302 at the same or different times. In some instances, the machine code corresponding to firmware, embedded software, or software programs is split into threads and executed in parallel by two or more of the cores 1302. Software programs may correspond to... Figure 12 , 10 The flowcharts in 11 represent part or all of the machine-readable instructions or operations.

[0111] Core 1302 can communicate via a first instance bus 1304. In some instances, the first bus 1304 can be implemented as a communication bus to enable communication associated with one or more of the cores 1302. For example, the first bus 1304 can be implemented via at least one of an Interconnect Integrated Circuit (I2C) bus, a Serial Peripheral Interface (SPI) bus, a PCI bus, or a PCIe bus. Alternatively, the first bus 1304 can be implemented by any other type of computing or electrical bus. Core 1302 can obtain data, instructions, and signals from one or more external devices via instance interface circuitry 1306. Core 1302 can output data, instructions, and signals to one or more external devices via interface circuitry 1306. While the core 1302 of this instance includes instance local memory 1320 (e.g., a Level 1 (L1) cache, which can be partitioned into an L1 data cache and an L1 instruction cache), the microprocessor 1300 also includes instance shared memory 1310 (e.g., a Level 2 (L2) cache) that can be shared by the cores for high-speed access to data and instructions. Data and instructions can be transferred (e.g., shared) by writing to or reading from the shared memory 1310. The local memory 1320 and the shared memory 1310 of each of the cores 1302 may be multi-level cache memory and main memory (e.g., Figure 13 It is part of the storage device hierarchy of the main memory (1214, 1216). Higher-level memories in the hierarchy exhibit shorter access times and have smaller storage capacities compared to lower-level memories. Changes to the various levels of the cache hierarchy are managed by cache coherence strategies (e.g., coordination).

[0112] Each core 1302 may be referred to as a CPU, DSP, GPU, or any other type of hardware circuit system. Each core 1302 includes a control unit circuit system 1314, an arithmetic and logic (AL) circuit system 1316 (sometimes referred to as an ALU), multiple registers 1318, local memory 1320, and a second instance bus 1322. Other structures may exist. For example, each core 1302 may include a vector unit circuit system, a single instruction multiple data (SIMD) unit circuit system, a load / store unit (LSU) circuit system, a branch / jump unit circuit system, a floating-point unit (FPU) circuit system, etc. The control unit circuit system 1314 includes semiconductor-based circuitry configured to control (e.g., coordinate) the movement of data within the corresponding core 1302. The AL circuit system 1316 includes semiconductor-based circuitry configured to perform one or more mathematical or logical operations on the data within the corresponding core 1302. In some instances, the AL circuit system 1316 performs integer-based operations. In other instances, the AL circuit system 1316 also performs floating-point operations. In other instances, the AL circuit system 1316 may include a first AL circuit system that performs integer-based operations and a second AL circuit system that performs floating-point operations. In some instances, the AL circuit system 1316 may be referred to as an arithmetic logic unit (ALU).

[0113] Register 1318 is a semiconductor-based structure used to store data and instructions, such as the results of one or more operations performed by the AL circuit system 1316 corresponding to core 1302. For example, register 1318 may contain one or more vector registers, one or more SIMD registers, one or more general-purpose registers, one or more flag registers, one or more segment registers, one or more machine-specific registers, one or more instruction pointer registers, one or more control registers, one or more debug registers, one or more memory management registers, one or more machine check registers, etc. Register 1318 may be as follows: Figure 13 The arrangement shown is grouped. Alternatively, register 1318 can be organized in any other arrangement, format, or structure, for example, by distributing it throughout core 1302 to reduce access time. The second bus 1322 can be implemented by at least one of an I2C bus, an SPI bus, a PCI bus, or a PCIe bus.

[0114] Each core 1302 or more generally, the microprocessor 1300 may include additional or alternative structures to those shown and described above. For example, one or more clock circuits, one or more power supplies, one or more power gates, one or more cache home agents (CHAs), one or more convergence / common grid stoppers (CMS), one or more shifters (e.g., one or more barrel shifters) or other circuitry may be present. The microprocessor 1300 is a semiconductor device manufactured to include a number of transistors interconnected in one or more integrated circuits (ICs) contained in one or more packages to implement the structures described above.

[0115] Microprocessor 1300 may include or cooperate with one or more accelerators (e.g., acceleration circuitry, hardware accelerators, etc.). In some instances, accelerators are implemented by logic circuitry to perform certain tasks faster and more efficiently than a general-purpose processor can. Examples of accelerators include ASICs and FPGAs, such as those described herein. GPUs, DSPs, or other programmable devices may also serve as accelerators. Accelerators may be mounted on microprocessor 1300, in the same chip package as microprocessor 1300, or in one or more separate packages with microprocessor 1300.

[0116] Figure 9 for Figure 14 A block diagram of another embodiment of the programmable circuit system 1212 is shown. In this example, the programmable circuit system 1212 is implemented by an FPGA circuit system 1400. For example, the FPGA circuit system 1400 may be implemented by an FPGA. The FPGA circuit system 1400 can be used, for example, to execute machine-readable instructions that can be implemented by corresponding FPGAs. Figure 9 The instance microprocessor 1300 performs operations in other ways. However, once configured, the FPGA circuit system 1400 instantiates operations and functions corresponding to machine-readable instructions in hardware, and therefore can generally perform operations / functions faster than those that can be performed by a general-purpose microprocessor implementing the corresponding software.

[0117] More specifically, as described above Figure 9 The microprocessor 1300 (which is programmable and can be executed by...) Figure 9 , 10 Compared to some or all of the general-purpose devices represented in one or more flowcharts of 11 (but whose interconnection and logic circuitry system are fixed once manufactured), Figure 9 The FPGA circuit system 1400 of this example includes interconnect and logic circuit systems, which can be configured, constructed, programmed, and interconnected in different ways or in combination after manufacturing to instantiate, for example, corresponding to those made by... Figure 14 , 10The FPGA circuit system 1400 represents some or all of the machine-readable instructions in one or more flowcharts. Specifically, the FPGA circuit system 1400 can be considered as an array of logic gates, interconnects, and switches. Switches can be programmed to change the way logic gates are interconnected via interconnects, thereby effectively forming one or more dedicated logic circuits (unless and until the FPGA circuit system 1400 is reprogrammed). The configured logic circuits enable logic gates to cooperate in different ways to perform different operations on data received from the input circuit system. Those operations can correspond to... Figure 14 , 10 And 11, some or all of the instructions represented by one or more flowcharts (e.g., at least one in software or firmware). Therefore, the FPGA circuit system 1400 can be configured or constructed in at least one of the following ways to effectively connect the corresponding... Figure 14 , 10 Some or all of the machine-readable instructions in one or more flowcharts of 11 are instantiated into special-purpose logic circuits to perform the operations / functions corresponding to those software instructions in a special-purpose manner similar to that of an ASIC. Therefore, the FPGA circuit system 1400 can be coupled with a general-purpose microprocessor to perform operations / functions corresponding to those software instructions. Figure 14 , 10 The operation / function is performed faster than some or all of the machine-readable instructions in 11.

[0118] exist Figure 14 In some instances, the FPGA circuit system 1400 is configured or constructed in response to being programmed (or reprogrammed one or more times) based on a binary file. In some instances, the binary file may be compiled or generated based on instructions in, for example, Lucid's Hardware Description Language (HDL), the Very High Speed ​​Integrated Circuit (VHSIC) Hardware Description Language (VHDL), or Verilog. For example, a user (e.g., a human user, a machine user, etc.) may write code or programs corresponding to one or more operations / functions in the HDL; the code / program may be transformed into a low-level language as needed; and the code / program (e.g., code / program in a low-level language) may be (e.g., by a compiler, software application, etc.) converted into a binary file. In some instances, Figure 14 The FPGA circuit system 1400 can access or load at least one of the binary files, so that... Figure 14 The FPGA circuit system 1400 is configured or constructed to perform one or more operations / functions. For example, a binary file may be generated by... Figure 14The FPGA circuit system 1400 can access one or a combination of bit streams (e.g., one or more computer-readable bits, one or more machine-readable bits, etc.), data (e.g., computer-readable data, machine-readable data, etc.) or machine-readable instructions to perform operations on... Figure 14 At least one of the FPGA circuit system 1400 or one or more of its components is configured or constructed.

[0119] In some instances, the binary file undergoes at least one of compilation, generation, transformation, or otherwise output from a unified software platform used for programming FPGAs. For example, the unified software platform can transform first instructions (e.g., code or program) corresponding to one or more operations / functions in a high-level language (e.g., C, C++, Python, etc.) into second instructions corresponding to one or more operations / functions in HDL. In some such instances, the binary file undergoes at least one of compilation, generation, or otherwise output from the unified software platform based on the second instructions. In some instances, Figure 14 The FPGA circuit system 1400 can access or load at least one of the binary files, so that... Figure 13 The FPGA circuit system 1400 is configured or constructed to perform one or more operations / functions. For example, a binary file may be generated by... Figure 9 The FPGA circuit system 1400 can access one or a combination of bit streams (e.g., one or more computer-readable bits, one or more machine-readable bits, etc.), data (e.g., computer-readable data, machine-readable data, etc.) or machine-readable instructions to perform operations on... Figure 14 At least one of the FPGA circuit system 1400 or one or more of its components is configured or constructed.

[0120] Figure 14The FPGA circuit system 1400 includes an instance input / output (I / O) circuit system 1402 to perform at least one of the following operations: obtaining data from or outputting data to at least one of the instance configuration circuit system 1404 or the external hardware 1406. For example, the configuration circuit system 1404 may be implemented by an interface circuit system that provides a binary file, which may be implemented by one or more of bitstreams, data, or machine-readable instructions to configure the FPGA circuit system 1400 or one or more portions thereof. In some such instances, the configuration circuit system 1404 may obtain the binary file from a user, a machine (e.g., a hardware circuit system (e.g., a programmable or dedicated circuit system) that can implement artificial intelligence / machine learning (AI / ML) models to generate binary files), or any combination thereof. In some instances, the external hardware 1406 may be implemented by an external hardware circuit system. For example, the external hardware 1406 may be implemented by... Figure 13 The microprocessor 1300 is implemented.

[0121] The FPGA circuit system 1400 also includes an array of instance logic gate systems 1408, multiple instance configurable interconnects 1410, and instance memory circuit systems 1412. The logic gate systems 1408 and configurable interconnects 1410 are configurable to instantiate corresponding to... Figure 12 , 10 One or more operations / functions, or other desired operations, from at least some of the machine-readable instructions in 11. Figure 13 The logic gate system 1408 shown is manufactured in blocks or groups. Each block contains semiconductor-based electrical structures that can be configured into logic circuits. In some instances, the electrical structures contain logic gates (e.g., AND gates, OR gates, NOR gates, etc.) that provide basic building blocks for the logic circuits. Electrically controlled switches (e.g., transistors) are present in each of the logic gate system 1408 to enable the configuration of one or a combination of electrical structures or logic gates to form a circuit for performing the desired operation / function. The logic gate system 1408 may include other electrical structures such as lookup tables (LUTs), registers (e.g., flip-flops or latches), multiplexers, etc.

[0122] The configurable interconnect 1410 of the illustrated example may be a conductive path, trace, via, etc., that may contain electrically controlled switches (e.g., transistors), the state of which can be changed by programming (e.g., using an HDL instruction language) to activate or deactivate one or more connections between one or more of the logic gate circuit system 1408 to program the desired logic circuit.

[0123] The storage circuit system 1412 of the illustrated example is configured to store one or more results of one or more operations performed by corresponding logic gates. The storage circuit system 1412 may be implemented by registers, etc. In the illustrated example, the storage circuit system 1412 is distributed within the logic gate circuit system 1408 to facilitate access and improve execution speed.

[0124] Figure 12 The example FPGA circuit system 1400 also includes an example-specific operating circuit system 1414. In this example, the specific operating circuit system 1414 includes a specific circuit system 1416, which can be invoked to implement common functions, thus eliminating the need for field programming of those functions. Examples of such specific circuit systems 1416 include memory (e.g., DRAM) controller circuit systems, PCIe controller circuit systems, clock circuit systems, transceiver circuit systems, memory and multiplier-accumulator circuit systems. Other types of specific circuit systems may exist. In some examples, the FPGA circuit system 1400 may also include an example general-purpose programmable circuit system 1418, such as an example CPU 1420 or an example DSP 1422. Other general-purpose programmable circuit systems 1418, such as GPUs, XPUs, etc., may also exist, either additionally or alternatively.

[0125] although Figure 13 and 14 illustrate Figure 14 Two example implementations of the programmable circuit system 1212 are provided, but many other approaches are envisioned. For example, the FPGA circuit system may include an onboard CPU, such as... Figure 13 One or more of the instance CPU 1420. Therefore, Figure 9 The programmable circuit system 1212 can also be configured by at least combining Figure 14 Example microprocessor 1300 and Figure 9 This is implemented using an example FPGA circuit system 1400. In some such hybrid instances, Figure 9 One or more core 1302 can be implemented by Figure 2 , 10 The first part of one or more flowcharts representing machine-readable instructions in 11 is used to perform one or more first operations / functions. Figure 13 The FPGA circuit system 1400 can be configured or constructed to perform at least one of the following functions: Figure 14 , 10 The flowchart of section 11 represents one or more second operations / functions in the second part of machine-readable instructions, or at least one of which can be configured or constructed by the ASIC to perform operations corresponding to those performed by the second part of the machine-readable instructions. Figure 2 , 10The flowchart of 11 represents one or more third operations / functions in the third part of a machine-readable instruction.

[0126] therefore, Figure 13 Some or all of the circuitry in a system can be instantiated at the same or different times. For example, Figure 14 One or more identical or different parts of the microprocessor 1300 can be programmed to execute one or more machine-readable instructions at the same or different times. In some instances, Figure 2 At least one of the same or different parts of the FPGA circuit system 1400 may be configured or constructed to perform operations / functions corresponding to one or more parts of machine-readable instructions at the same or different times.

[0127] In some instances, Figure 13 Some or all of the circuitry in a system can be instantiated, for example, in one or more threads that are executed in parallel or serially. Figure 12 The microprocessor 1300 can execute machine-readable instructions in one or more threads, either in parallel or serially. In some instances, Figure 13 The FPGA circuit system 1400 can be configured or constructed to operate / function in parallel or serially. Furthermore, in some instances, Figure 14 Some or all of the circuit systems can be in Figure 12 It is implemented within one or more virtual machines or containers on the microprocessor 1300.

[0128] In some instances, Figure 13 The programmable circuit system 1212 can be located in one or more packages. For example, Figure 14 microprocessor 1300 or Figure 14 At least one of the FPGA circuitry systems 1400 may be housed in one or more packages. In some instances, the XPU may be derived from... Figure 14 The programmable circuit system 1212 is implemented, and the programmable circuit system may be located in one or more packages. For example, the XPU may be contained within a CPU in one package (e.g., Figure 15 microprocessor 1300, Figure 12 CPU1420, etc.), and DSP in another package (e.g., Figure 12 DSP 1422), GPU in another package, and FPGA in yet another package (e.g., Figure 9 FPGA circuit system 1400).

[0129] Figure 9 The flowchart in the middle describes the software (e.g., Figure 12The instance software distribution platform 1505 distributes instance machine-readable instructions (1232) to other hardware devices (e.g., one or more hardware devices owned or operated by a third party from the owner or operator of the software distribution platform). The instance software distribution platform 1505 may be implemented by any computer server, data facility, cloud service, etc., capable of storing software and transferring software to other computing devices. The third party may be a customer of an entity that owns or operates at least one of the software distribution platforms 1505. For example, the entity that owns or operates at least one of the software distribution platforms 1505 may be a software (e.g., Figure 2 The third party may be at least one of the developers, sellers, or licensors of the machine-readable instruction 1232. The third party may be a consumer, user, retailer, OEM, etc., who purchases or licenses one or a combination of the software for at least one of use, resale, or sublicense. In the illustrated example, the software distribution platform 1505 includes one or more servers and one or more storage devices. The storage devices store the machine-readable instruction 1232, which may correspond to... Figure 2 , 10 The instance machine-readable instructions 1232 are as described above. One or more servers of the instance software distribution platform 1505 communicate with the instance network 1510, which may correspond to any one or more of the Internet or any instance network described above. In some instances, one or more servers respond to a request to transfer software to a requesting party as part of a commercial transaction. Payment for at least one of the software delivery, sale, or licensing may be handled by one or more servers of at least one of the software distribution platforms or by a third-party payment entity. The servers enable one or more purchasers or licensors to download machine-readable instructions 1232 from the software distribution platform 1505. For example, this may correspond to... Figure 2 , 10 The software containing the machine-readable instructions of instance 11 can be downloaded to instance programmable circuit system platform 1200, which will execute machine-readable instructions 1232 to implement radar transceiver IC 200. In some instances, one or more servers of software distribution platform 1505 periodically distribute the software (e.g., Figure 2 The instance machine-readable instructions (1232) are used to provide, transmit, or cause at least one of these updates to ensure that improvements, patches, updates, etc., are distributed and applied to the software at the end-user device. Although referred to as software above, distributed “software” may alternatively be firmware.

[0130] Although Figure 2 Implementation instructions Figure 2 The radar transceiver IC 200 is an example of this approach, but... Figure 2One or more of the elements, processes, or apparatuses described herein may be combined, divided, rearranged, omitted, eliminated, or implemented in any other way. Furthermore, examples include chirped synthesizer circuit 202 and transmitters 2041 to 204. N Example transmitting antennas 2061 to 206 N Example receiving antennas 2081 to 208 M Instance receivers 2101 to 210 M Instance interface circuit system 212, instance processor circuit 214, or more generally Figure 9 The example radar transceiver IC 200 can be implemented solely in hardware or in combination with software and firmware. Therefore, for example, the example chirp synthesizer circuit 202, and example transmitters 2041 to 204... N Example transmitting antennas 2061 to 206 N Example receiving antennas 2081 to 208 M Instance receivers 2101 to 210 M The instance interface circuit system 212, the instance processor circuit 214, or more generally, any of the instance radar transceiver IC 200 can be implemented by a programmable circuit system in combination with one or more machine-readable instructions (e.g., firmware or software), a processor circuit system, one or more analog circuits, one or more digital circuits, one or more logic circuits, one or more programmable processors, one or more programmable microcontrollers, one or more graphics processing units (one or more GPUs), one or more digital signal processors (one or more DSPs), one or more ASICs, one or more programmable logic devices (one or more PLDs), or one or more field-programmable logic devices (one or more FPLDs) (e.g., FPGAs). Furthermore, Figure 2 The example radar transceiver IC 200 may include, in addition to Figure 2 Those other than or substitutes described in the text Figure 12 The elements, processes, or apparatus described herein may include one or more of the elements, processes, and apparatus described herein, or may include more than one of any or all of the elements, processes, and apparatus described herein.

[0131] Figure 13 , 10 The examples shown in 11 represent machine-readable instructions (which can be executed by a programmable circuit system to...) Figure 9 (at least one of the implementations or instantiations of the radar transceiver IC 200) or represents instance operation (which can be executed by a programmable circuit system to...) Figure 9 One or more flowcharts (for at least one of the implementations or instantiations of the radar transceiver IC 200). Machine-readable instructions may be provided for programmable circuit systems (e.g., in conjunction with the following). ​The programmable circuit system 1212 shown in the described example programmable circuit system platform 1200 implements one or more executable programs or one or more executable programs or one or more portions of one or more executable programs, and may be combined with the following ​ Or, as described in example 14, a programmable circuit system (e.g., an FPGA) performs one or more functions or parts thereof. In some instances, machine-readable instructions cause operations, tasks, etc., to be performed or executed in a real-world manner. As used herein, “automation” means without human intervention.

[0132] The program may be embodied in instructions (e.g., at least one of software or firmware) stored on one or more non-transitory computer-readable or machine-readable storage media, such as one or a combination of the following: cache memory, magnetic storage device or disk (e.g., floppy disk, hard disk drive (HDD) etc.), optical storage device or optical disk (e.g., Blu-ray disc, optical disc (CD), digital versatile disc (DVD) etc.), redundant array of independent disks (RAID), register, ROM, solid-state drive (SSD), SSD memory, non-volatile memory (e.g., electrically erasable programmable read-only memory (EEPROM), flash memory, etc.), volatile memory (e.g., any type of random access memory (RAM) etc.), or any other storage device or storage disk. The instructions of the non-transitory computer-readable or machine-readable media may be programmed or executed by a programmable circuit system located in one or more hardware devices, but the entire program or a portion thereof may alternatively be executed or instantiated or embodied in dedicated hardware by one or more hardware devices other than the programmable circuit system. Machine-readable instructions may be distributed across multiple hardware devices or implemented by two or more hardware devices (e.g., server and client hardware devices). For example, client hardware devices may be implemented by endpoint client hardware devices (e.g., hardware devices associated with at least one of a human user or a machine user) or intermediate client hardware device gateways (e.g., radio access networks (RANs)) that facilitate communication between the server and endpoint client hardware devices. Similarly, non-transitory computer-readable storage media may contain one or more media. Furthermore, although references... ​ , 10The example program is described using one or more flowcharts as illustrated in section 11, but many other methods for implementing the example radar transceiver IC 200 may be used instead. For example, the execution order of one or more flowchart blocks may be changed, or some of the described blocks may be changed, eliminated, or combined. Additionally or alternatively, any or all blocks of the flowchart may be implemented by one or more hardware circuits (e.g., processor circuitry, discrete analog circuitry, discrete digital circuitry, integrated analog circuitry, integrated digital circuitry, FPGA, ASIC, comparator, operational amplifier, logic circuitry, etc.) configured to perform the corresponding operation without implementing software or firmware. Programmable circuitry may be distributed across different network locations or local to one or more hardware devices (e.g., a single-core processor (e.g., a single-core CPU), a multi-core processor (e.g., a multi-core CPU, XPU, etc.)). As used herein, programmable circuitry includes any type of circuitry, such as one or a combination of a CPU or FPGA, that is programmable to perform the desired function. A programmable circuit system may comprise any combination of the following: one or more CPUs and one or more FPGAs located in the same package (e.g., the same integrated circuit (IC) package or in two or more separate housings); one or more CPUs or FPGAs in a single machine; one or more CPUs or FPGAs distributed across multiple servers in a server rack; or multiple processors distributed across one or more server racks. Alternatively or additionally, in any of the contexts described above, a programmable circuit system may comprise a programmable logic device (PLD), a general-purpose array logic (GAL) device, a programmable array logic (PAL) device, a complex programmable logic device (CPLD), a simple programmable logic device (SPLD), a microcontroller unit (MCU), a system-on-a-chip (PSoC), or any combination thereof.

[0133] Machine-readable instructions described herein may be stored in one or more of the following formats: compressed format, encrypted format, segmented format, compiled format, executable format, encapsulated format, etc. As described herein, machine-readable instructions may be stored as data (e.g., computer-readable data, machine-readable data, one or more bits (e.g., one or more computer-readable bits, one or more machine-readable bits, etc.), bit streams (e.g., computer-readable bit streams, machine-readable bit streams, etc.)) or data structures (e.g., one or more portions of instructions, code, representations of code, etc.) that can be used to create, manufacture, or produce machine-executable instructions. For example, machine-readable instructions may be segmented and stored on one or more storage devices, disks, or computing devices (e.g., servers) located at the same or different locations within a network or network set (e.g., in the cloud, edge devices, etc.). Machine-readable instructions may require one or more of the following to be installed, modified, adapted, updated, combined, supplemented, configured, decrypted, decompressed, decapsulated, distributed, redistributed, compiled, etc., to make them directly readable, interpretable, or executable by computing devices or other machines. For example, machine-readable instructions may be stored in multiple portions individually compressed, encrypted, or stored on separate computing devices, wherein the portions, when decrypted, decompressed, or combined, form a set of one or more computer-executable or machine-executable instructions that together form one or more functions or operations of a program such as those described herein.

[0134] In another instance, machine-readable instructions may be stored in a state that allows them to be read by a programmable circuit system, but additional libraries (e.g., dynamic link libraries (DLLs)), software development kits (SDKs), application programming interfaces (APIs), etc., are required to execute the machine-readable instructions on a particular computing device or another device. In yet another instance, the machine-readable instructions (e.g., storage settings, data inputs, recorded network addresses, etc.) may need to be configured before they can be executed wholly or partially. Therefore, machine-readable, computer-readable, or machine-readable media as used herein may contain one or a combination of instructions and one or more programs, regardless of the specific format or state of the machine-readable instructions or the one or more programs.

[0135] The machine-readable instructions described in this article can be represented by any past, present, or future instruction language, scripting language, programming language, etc. For example, machine-readable instructions can be represented using any of the following languages: C, C++, Java, C-Sharp, Perl, Python, JavaScript, Hypertext Markup Language (HTML), Structured Query Language (SQL), Swift, etc.

[0136] As mentioned above, ​ , 10The operations of 11 can be performed using executable instructions (e.g., at least one of computer-readable or machine-readable instructions) stored on one or more non-transitory computer-readable or machine-readable media. As used herein, the terms non-transitory computer-readable media, non-transitory computer-readable storage media, non-transitory machine-readable media, and non-transitory machine-readable storage media are expressly defined as including any type of computer-readable storage device or disk, excluding propagation signals and transmission media. Examples of such non-transitory computer-readable media, non-transitory computer-readable storage media, non-transitory machine-readable media, or non-transitory machine-readable storage media include one or more optical storage devices, magnetic storage devices, HDDs, flash memory, read-only memory (ROM), CDs, DVDs, caches, any type of RAM, registers, or any other storage device or disk, wherein information is stored for any duration (e.g., extended time period, permanent, transient, temporary buffer, cached information). As used herein, the terms "non-transitory computer-readable storage device" and "non-transitory machine-readable storage device" are defined as comprising any physical (mechanical, magnetic, electromechanical, or electrical) hardware designed to retain information for a period of time, excluding the propagation of signals and the transmission medium. Examples of non-transitory computer-readable storage devices or non-transitory machine-readable storage devices include one or a combination of the following: any type of random access memory, any type of read-only memory, solid-state memory, flash memory, optical disk, magnetic disk, disk drive, or redundant array of independent disks (RAID) system. As used herein, the term "device" refers to a physical structure, such as one or a combination of the following: mechanical, electromechanical, or electrical equipment, hardware, or circuitry that may or may not be configured to execute computer-readable instructions, machine-readable instructions, etc.

[0137] "Including" and "comprises" (and all their forms and tenses) are used herein as open-ended terms. Therefore, whenever a technical solution uses any form of "including" or "comprises" (e.g., includes, encompassing, including, having, etc.) as a preposition or within any kind of technical solution description, additional elements, terms, etc., may be present without exceeding the scope of the corresponding technical solution or description. As used herein, when the phrase "at least" is used as a transitional term, for example, in a preposition of a technical solution, it is open-ended in the same way as the terms "comprises" and "comprises" are open-ended. As used herein in the context of describing structures, components, items, objects, and things, the phrase "at least one of A and B" means an implementation comprising either: (1) at least one A, (2) at least one B, or (3) at least one A and at least one B. Similarly, as used herein in the context of describing structures, components, projects, objects, and things, the phrase “at least one of A or B” means an implementation that includes any of the following: (1) at least one A, (2) at least one B, or (3) at least one A and at least one B. As used herein in the context of describing the execution or implementation of processes, instructions, actions, activities, etc., the phrase “at least one of A or B” means an implementation that includes any of the following: (1) at least one A, (2) at least one B, or (3) at least one A and at least one B. Similarly, as used herein in the context of describing the execution or implementation of processes, instructions, actions, activities, etc., the phrase “at least one of A or B” means an implementation that includes any of the following: (1) at least one A, (2) at least one B, or (3) at least one A and at least one B.

[0138] As used herein, singular references (e.g., "a(a)", "an(an)", "first", "second", etc.) do not exclude plurals. As used herein, the term "a(a)" or "an(an)" refers to one or more of the objects mentioned. The terms "a(a)" (or "an(an)"), "one or more", and "at least one" are used interchangeably herein. Furthermore, although listed separately, multiple components, elements, or actions may be implemented by, for example, the same entity or object. Additionally, while individual features may be included in different instances or solutions, these features may be combined, and inclusion in different instances or solutions does not imply that the combination of features is infeasible or disadvantageous at least one of them.

[0139] As used herein, unless otherwise indicated, a connection reference (e.g., attachment, coupling, connection, and engagement) may include an intermediate part between elements referenced by the connection reference between those elements or by at least one of the elements in relative movement. Therefore, a connection reference does not necessarily imply that two elements are directly connected to each other or are in a fixed relationship.

[0140] Unless otherwise specifically stated, descriptive terms such as “first,” “second,” “third,” etc., are used herein without intending or otherwise indicating priority, physical order, arrangement, or any sorting in the list, but only as markers or arbitrary names to distinguish elements in order to facilitate understanding of the described instance. In some instances, the descriptive term “first” may be used to refer to an element in a detailed description, while the same element may be referred to in the technical solution by different descriptive terms such as “second” or “third.” In such instances, such descriptive terms are used only to clearly identify those elements within the context of the description (e.g., within the technical solution), in which elements may otherwise share the same name.

[0141] As used herein, the phrase “communication” includes variations thereof, encompassing one or a combination of direct communication or indirect communication through one or more intermediate components, and not requiring direct physical (e.g., wired) communication or constant communication, but also including selective communication at at least one of periodic intervals, predetermined intervals, non-periodic intervals, or one-off events.

[0142] As used herein, a “programmable circuit system” is defined as comprising at least one of the following: (i) one or more special-purpose circuits (e.g., special-purpose circuits (ASICs)) configured to perform one or more specific operations and comprising one or more semiconductor-based logic devices (e.g., electrical hardware implemented by one or more transistors), or (ii) one or more general-purpose semiconductor-based circuits programmable by instructions to perform one or more specific functions or operations and comprising one or more semiconductor-based logic devices (e.g., electrical hardware implemented by one or more transistors). Examples of programmable circuit systems include programmable microprocessors, such as: a central processing unit (CPU) that can execute a first instruction to perform one or more operations or functions; a field-programmable gate array (FPGA) that can be programmed with a second instruction to configure or construct at least one of the FPGAs, thereby instantiating one or more operations or functions corresponding to the first instruction; a graphics processing unit (GPU) that can execute a first instruction to perform one or more operations or functions; a digital signal processor (DSP) that can execute a first instruction to perform one or more operations or functions; an XPU; a network processing unit (NPU); one or more microcontrollers that can execute a first instruction to perform one or more operations or functions; or an integrated circuit, such as an application-specific integrated circuit (ASIC). For example, an XPU can be implemented by a heterogeneous computing system that includes various types of programmable circuit systems (e.g., one or more FPGAs, one or more CPUs, one or more GPUs, one or more NPUs, one or more DSPs, etc., and one or more of any combination thereof) and orchestration techniques (e.g., one or more application programming interfaces (one or more APIs)) that can assign one or more computing tasks to any one or more of the various types of programmable circuit systems that are suitable and can be used to perform one or more computing tasks.

[0143] As used herein, an integrated circuit / circuit system is defined as one or more semiconductor packages containing one or more circuit elements, such as transistors, capacitors, inductors, resistors, current paths, diodes, etc. For example, an integrated circuit can be implemented as one or more of an ASIC, FPGA, chip, microchip, programmable circuit system, semiconductor substrate coupling multiple circuit elements, system-on-a-chip (SoC), etc.

[0144] In this description, the term "coupling" may encompass a connection, communication, or signaling path that achieves a functional relationship consistent with this description. For example, if device A generates a signal to control device B to perform an action, then: (a) in a first instance, device A is coupled to device B via a direct connection; or (b) in a second instance, device A is coupled to device B via an intermediate component C, provided that the intermediate component C does not alter the functional relationship between device A and device B, such that device B is controlled by device A via a control signal generated by device A.

[0145] Unless otherwise stated, terms such as node and interconnect can be used to mean the interconnection or termination between device elements, circuit elements, integrated circuits, devices or other electronic or semiconductor components.

[0146] In this description and claims, the "circuit system" described may include one or more circuits. A circuit or device described herein as including certain components may be substantially adapted to be coupled to those components to form the described circuit system or device. For example, a structure described as including one or more semiconductor elements (e.g., transistors), one or more passive elements (e.g., one or a combination of resistors, capacitors, or inductors), or one or more sources (e.g., at least one of voltage sources or current sources) may substantially include only semiconductor elements within a single physical device (e.g., at least one of a semiconductor die or integrated circuit (IC) package) and may be adapted to be coupled at manufacturing time or after manufacturing time, for example by at least one of an end user or a third party, to at least some of the passive elements or sources to form the described structure.

[0147] The circuits described herein can be reconfigured to include the replaced components to provide functionality at least partially similar to that available before the component replacement. While some elements in the described examples are contained within the integrated circuit and others are external to the integrated circuit, in other example embodiments, additional or fewer features may be incorporated into the integrated circuit. Additionally, some or all of the features described as external to the integrated circuit may be contained within the integrated circuit, and some features described as internal to the integrated circuit may be incorporated externally. As used herein, the term "integrated circuit" means one or more circuits that are at least one of the following: (i) incorporated in / above a semiconductor substrate; (ii) incorporated in a single semiconductor package; (iii) incorporated in the same module; or (iv) incorporated in / on the same printed circuit board.

[0148] Any values ​​given in this document are approximate, recognizing the potential for variation in real-world applications. Values ​​stated may not be accurate due to at least one of manufacturing tolerances or other real-world defects. Unless otherwise stated, values ​​stated are intended to be + / - 10% of the stated value, or, if the value is zero, a reasonable range of values ​​near zero.

[0149] Within the scope of the claims, modifications are possible in the described examples, and other examples are also possible.

[0150] Based on the foregoing, it should be understood that example systems, apparatuses, articles, and methods for improving dynamic range in the presence of interference have been described. The described systems, apparatuses, articles, and methods improve the efficiency of using computing devices by reducing artifacts associated with interference reconstruction. Reducing artifacts associated with interference reconstruction directly leads to fewer trade-offs in higher-level functions (e.g., object tracking) and fewer false target detections. Therefore, the described systems, apparatuses, articles, and methods relate to one or more improvements in the operation of machines, such as computers or other electronic, electromechanical, or mechanical devices.

Claims

1. An apparatus comprising: interface circuitry to receive digital samples representing a chirp frame; and programmable circuitry to: determine, for a range Fourier transform (FT) representation of the chirp frame, a reconstructed chirp of a chirp in the chirp frame that contains a corrupt sample; determine, based on the range FT representation, a first Doppler range representation of the chirp frame, the range FT representation containing the reconstructed chirp; and determine a second Doppler range representation as an element-wise minimum between the first Doppler range representation of the chirp frame and a third Doppler range representation, the third Doppler range representation based on the digital samples containing reconstructed samples that replace the corrupt sample of the chirp.

2. The apparatus of claim 1 including receiver circuitry to receive the chirp frame from an environment.

3. The apparatus of claim 1, wherein the chirp frame is a first chirp frame reflected from an environment, and the apparatus includes transmitter circuitry to transmit a second chirp frame into the environment.

4. The apparatus of claim 1, wherein the programmable circuitry is to: determine, based on the digital samples, the reconstructed sample of the corrupt sample; and determine, based on the digital samples containing the chirp with the reconstructed sample, the third Doppler range representation.

5. The apparatus of claim 1, wherein the programmable circuitry is to: replace, in the digital samples, the chirp containing the corrupt sample with a zero- valued chirp; determine, based on the digital samples containing the zero-valued chirp, the range FT representation of the chirp frame, the range FT representation having a first dimension and a second dimension; determine, for respective indices across the second dimension of the range FT representation, Doppler FT representations; for respective Doppler FT representations: set to zero values that do not satisfy a threshold for a peak in the respective Doppler FT representation; and determine an inverse range FT representation to generate the reconstructed chirp; and replace, in the range FT representation, the chirp containing the corrupt sample with the reconstructed chirp.

6. The apparatus of claim 1, wherein the programmable circuitry is to: determine the range FT representation of the chirp frame, the range FT representation containing the reconstructed chirp; and determine Doppler FT representations of the range FT representation to determine the first Doppler range representation.

7. The apparatus of claim 1, wherein the second Doppler range representation determined as the element-wise minimum between the first Doppler range representation and the third Doppler range representation will mitigate a first interference in a range dimension and a second interference in a Doppler dimension.

8. A non-transitory computer-readable medium comprising instructions for causing programmable circuitry to: determine, for a range Fourier transform (FT) representation of a chirp frame, a reconstructed chirp of a chirp in the chirp frame that contains a corrupt sample, the chirp frame received by a radar integrated circuit from an environment and represented by digital samples; determining a first Doppler range representation of the chirp frame based on the range FT representation, the range FT representation including the reconstructed chirp; and determining a second Doppler range representation as an element-wise minimum between the first Doppler range representation of the chirp frame and a third Doppler range representation, the third Doppler range representation based on the digital samples, the digital samples including reconstructed samples that replace the damaged samples of the chirp.

9. The non-transitory computer-readable medium of claim 8, wherein the instructions cause the programmable circuitry to: determine the reconstructed samples of the damaged samples based on the digital samples; and determine the third Doppler range representation based on the digital samples, the digital samples including the chirp with the reconstructed samples.

10. The non-transitory computer-readable medium of claim 8, wherein the instructions cause the programmable circuitry to: replace the chirp including the damaged samples with a zero-valued chirp in the digital samples; determine the range FT representation of the chirp frame based on the digital samples, the digital samples including the zero-valued chirp, the range FT representation having a first dimension and a second dimension; determine, for respective indices across the second dimension of the range FT representation, Doppler FT representations; for respective Doppler FT representations: set values that do not satisfy a threshold for a peak in the respective Doppler FT representation to zero; and determine an inverse range FT representation to generate the reconstructed chirp; and replace the chirp including the damaged samples in the range FT representation with the reconstructed chirp.

11. The non-transitory computer-readable medium of claim 8, wherein the instructions cause the programmable circuitry to: determine the range FT representation of the chirp frame, the range FT representation including the reconstructed chirp; and determine Doppler FT representations of the range FT representation to determine the first Doppler range representation.

12. The non-transitory computer-readable medium of claim 8, wherein the second Doppler range representation determined as the element-wise minimum between the first Doppler range representation and the third Doppler range representation will mitigate a first interference in a range dimension and a second interference in a Doppler dimension.

13. The non-transitory computer-readable medium of claim 12, wherein mitigation of the first interference and the second interference will improve a dynamic range of the radar integrated circuit.

14. A method comprising: receiving, with interface circuitry, digital samples representing a chirp frame; replacing, with programmable circuitry executing instructions, a chirp in the chirp frame including a damaged sample with a zero-valued chirp in the digital samples; determining, with the programmable circuitry executing instructions, a range Fourier transform (FT) representation of the chirp frame based on the digital samples, the digital samples including the zero-valued chirp, the range FT representation having a first dimension and a second dimension; determining, for respective indices of the second dimension representing the range FT, a Doppler FT representation by executing instructions with the programmable circuitry; for respective Doppler FT representations: setting, by executing instructions with the programmable circuitry, values that do not satisfy a threshold of a peak in the respective Doppler FT representation to zero; and determining, by executing instructions with the programmable circuitry, an inverse range FT representation to generate a reconstructed chirp; replacing, by executing instructions with the programmable circuitry, the chirp in the range FT representation that includes the corrupted samples with the reconstructed chirp; and determining, by executing instructions with the programmable circuitry, a Doppler range representation of the chirp frame based on the range FT representation that includes the reconstructed chirp.

15. The method of claim 14, wherein the Doppler range representation is a first Doppler range representation, and the method includes determining a second Doppler range representation as an element-wise minimum between the first Doppler range representation and a third Doppler range representation of the chirp frame, the third Doppler range representation based on the digital samples that include reconstructed samples in place of the corrupted samples of the chirp.

16. The method of claim 15, including: determining the reconstructed samples of the corrupted samples based on the digital samples; and determining the third Doppler range representation based on the digital samples that include the chirp with the reconstructed samples.

17. The method of claim 15, wherein the second Doppler range representation determined as the element-wise minimum between the first Doppler range representation and the third Doppler range representation will mitigate a first interference in a range dimension and a second interference in a Doppler dimension.

18. The method of claim 14, including receiving the chirp frame from an environment with receiver circuitry.

19. The method of claim 14, wherein the chirp frame is a first chirp frame reflected from an environment, and the method includes transmitting a second chirp frame into the environment with transmitter circuitry.

20. The method of claim 14, wherein the Doppler FT representation is a first Doppler FT representation, and the method includes: determining the range FT representation of the chirp frame that includes the reconstructed chirp; and determining a second Doppler FT representation of the range FT representation to determine the Doppler range representation.

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