Simulation model and rack signal synchronous correction method and device, equipment and medium

Abstract

The method is mainly applied to the technical field of vehicle engineering. The invention discloses a signal synchronization correction method, device and equipment for a simulation model and a rack and a medium, and the method comprises the steps: collecting an instruction signal transmitted by the simulation model and a feedback signal returned by the rack based on a synchronization mark, the synchronization mark is the same identification code carried by the signal frame corresponding to the instruction signal and the signal frame corresponding to the feedback signal; determining a delay time between the command signal and the feedback signal; when the delay time is greater than a preset delay threshold value, generating a signal compensation amount according to the delay time; and based on the signal compensation amount, performing advanced compensation on a time axis on an instruction signal sent by the simulation model so as to enable the simulation model to send a corrected instruction signal. According to the invention, the test requirements of high precision and strong self-adaption can be met, and the test efficiency and reliability are remarkably improved.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of vehicle engineering, in particular to a simulation model and test bench signal synchronization correction method, device, equipment and medium. BACKGROUND

[0002] In modern industrial automation, automotive electronics, aerospace and many other fields, the joint test of simulation model and test bench is a key link in the product development and verification process. Hardware-in-the-loop (HIL) test platform is a widely used test means in these fields. Its main function is to connect the tested controller with the simulation model, simulate various working conditions and signal inputs in the actual operating environment, test and evaluate the performance, function and stability of the controller, and ensure the reliability and safety of the product in actual application.

[0003] However, in the existing general HIL test platform, a series of problems need to be solved. First of all, most HIL test platforms are not based on real-time operating system (RTOS), and their software environment and hardware resources are relatively limited, which makes it difficult to meet the requirements of complex real-time signal processing and accurate time delay compensation. Under non-high-end hardware configuration, such as common HIL platforms based on ordinary commercial computers or low-end embedded systems, the computing power, data transmission rate and storage capacity are all constrained to a certain extent, which brings great challenges to signal synchronization correction. SUMMARY

[0004] The present application provides a simulation model and test bench signal synchronization correction method, device, equipment and medium, which can meet the testing requirements of high precision and strong adaptability, and significantly improve the testing efficiency and reliability.

[0005] The present application provides a simulation model and test bench signal synchronization correction method, which comprises: Based on the synchronization mark, the instruction signal sent by the simulation model and the feedback signal returned by the test bench are collected, wherein the synchronization mark is the same identification code carried by the signal frame corresponding to the instruction signal and the signal frame corresponding to the feedback signal; Determine the delay time between the instruction signal and the feedback signal; When the delay time is greater than the preset delay threshold, generate a signal compensation amount according to the delay time; Based on the signal compensation amount, the instruction signal sent by the simulation model is compensated in advance on the time axis, so as to make the simulation model send the corrected instruction signal.

[0006] Optionally, when the delay time is greater than the preset delay threshold, the signal compensation amount is generated according to the delay time, comprising: inputting the delay time into a preset delay prediction model; using the delay prediction model, determining a predicted delay time of a next simulation step according to a historical variation trend of the delay time, and generating a corresponding signal compensation amount according to the predicted delay time; sending the corrected instruction signal to the gantry for execution, and receiving a corrected feedback signal returned by the gantry; when the delay time between the corrected instruction signal and the corrected feedback signal is greater than the preset delay threshold, returning to execute the step of inputting the delay time into a preset delay prediction model until the delay time is less than or equal to the preset delay threshold.

[0007] Optionally, the signal synchronization correction method of the simulation model and the gantry further comprises: at the simulation model end, triggering at a first preset period and inserting the synchronization marker into a sequence of instruction signals generated by the simulation model; at the gantry hardware end, triggering at a second preset period and inserting the synchronization marker into a sequence of feedback signals returned by the gantry, wherein the second preset period is the same as the first preset period.

[0008] Optionally, the synchronization marker is a data frame with a fixed format, and the data frame comprises in sequence: a frame header field, the content of the frame header field being a predefined fixed value, wherein the frame header field is used to identify the data frame as a synchronization marker frame according to the fixed value; a timestamp field, the content of the timestamp field being generated by a local clock of the simulation model or the gantry generating the data frame; a signal identification field, the content of the signal identification field being used to distinguish signal types, wherein the signal identification field of the instruction signal is different from the signal identification field of the feedback signal and has a pairing relationship; a check field, used to verify the integrity of the data frame in the transmission process.

[0009] Optionally, the determination of the delay time between the instruction signal and the feedback signal comprises: based on the signal identification field in the synchronization marker, screening out a target instruction signal frame and a target feedback signal frame; extracting the timestamp field from the target instruction signal frame and the target feedback signal frame; determining the delay time according to the difference between the sending timestamp of the target instruction signal frame and the receiving timestamp of the target feedback signal frame.

[0010] Optionally, the specific implementation of the lead compensation comprises: a difference between the delay time and the preset buffer time as an advance amount of the instruction signal; sending a control instruction to the simulation model, so that the simulation model outputs the instruction signal originally scheduled to be output in a next simulation cycle at a time point of a current simulation cycle minus the advance amount.

[0011] Optionally, the signal compensation amount-based advance compensation of the instruction signal output by the simulation model in the time axis to make the simulation model output a corrected instruction signal comprises: delay processing of a time at which the feedback signal is output by the test bench based on the signal compensation amount, so that the test bench returns a corrected feedback signal, wherein the signal compensation amount is a difference between the delay time and the preset delay threshold.

[0012] The application further provides a signal synchronization correction device for a simulation model and a test bench, the device comprising: a signal acquisition module configured to acquire an instruction signal output by the simulation model and a feedback signal returned by the test bench based on a synchronization mark, wherein the synchronization mark is a same identification code carried by a signal frame corresponding to the instruction signal and a signal frame corresponding to the feedback signal; a first calculation module configured to determine a delay time between the instruction signal and the feedback signal; a second calculation module configured to generate a signal compensation amount according to the delay time when the delay time is greater than a preset delay threshold; a signal correction module configured to perform advance compensation of the instruction signal output by the simulation model in the time axis based on the signal compensation amount, so that the simulation model outputs a corrected instruction signal.

[0013] The application further provides an electronic device comprising a memory and a processor, wherein the memory stores a computer program, and the processor implements the signal synchronization correction method for a simulation model and a test bench according to any one of the above-mentioned embodiments when executing the computer program.

[0014] The application further provides a computer readable storage medium storing a computer program, wherein the computer program is executed by a processor to implement the signal synchronization correction method for a simulation model and a test bench according to any one of the above-mentioned embodiments.

[0015] The application has at least the following beneficial effects: The technical solution realizes accurate association of the instruction signal and the feedback signal through synchronous marking, and ensures the correspondence of the signal frame. The instruction signal of the simulation model is pre-compensated by accurately measuring the delay time and generating a compensation amount, and the signal time deviation is effectively corrected. This correction method based on synchronous marking can accurately identify signal delay, adapt to signal changes in different test environments, and has strong adaptability. At the same time, the pre-compensation ensures that the instruction signal and the feedback signal are time-synchronized, and improves the test accuracy. The whole process is automated and efficient, reduces manual intervention, significantly improves the test efficiency and reliability, and meets the test requirements of high precision and strong adaptability. BRIEF DESCRIPTION OF DRAWINGS

[0016] The accompanying drawings are used to provide a further understanding of the technical solutions of the present application, and constitute a part of the specification, and are used to explain the technical solutions of the present application together with embodiments of the present application, and do not constitute a limitation on the technical solutions of the present application.

[0017] Figure 1 It is a step flow chart of a signal synchronization correction method of a simulation model and a test bench. Figure 2 It is a step flow chart of step S102 in the signal synchronization correction method of the simulation model and the test bench. Figure 3 It is a step flow chart of step S103 in the signal synchronization correction method of the simulation model and the test bench. Figure 4 It is a structural schematic diagram of a signal synchronization correction device of a simulation model and a test bench. Figure 5 It is a structural schematic diagram of an electronic device. DETAILED DESCRIPTION

[0018] In order to make the purpose, technical solutions and advantages of the present application clearer, the present application will be further described in detail below in combination with the drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present application, and do not limit the present application.

[0019] Before describing the embodiments of the technical solution, it needs to be explained that the hardware-in-the-loop test technology (Hardware-in-the-Loop, HIL) is the core verification means of chassis electronic control system development, and is widely used in the function and performance test of steering, braking, suspension and other controllers. Its core principle is to simulate the vehicle dynamics environment (such as road resistance, steering load) through a simulation model, output the command signal to the bench hardware (such as steering motor, torque sensor), and then verify the control logic accuracy of the controller through the bench feedback signal. At present, the mainstream HIL test system (such as dSPACE SCALEXIO, NIVeriStand) has realized the signal transmission rate of 1ms level, but in the high-precision test scene of chassis electronic control (such as steering torque dynamic response test), it still faces the problem of signal synchronization. In the prior art, the solutions for HIL test signal synchronization mainly include two types: Hardware-level synchronization optimization based on real-time operating system (RTOS). For example, the patent CN202210324567.8 “Real-time synchronization control method of HIL test system” proposes to implant an RTOS kernel in the simulation model and the bench hardware, optimize the task scheduling priority, and reduce the scheduling delay of signal transmission. However, additional deployment of RTOS software (such as VxWorks) is required, and the hardware needs to support real-time scheduling function, resulting in an increase of more than 30% in the cost of the test system; and the task scheduling logic of RTOS is complex and needs to be debugged by professional personnel, so ordinary HIL test engineers are difficult to quickly start, and the adaptation period is as long as 2-3 weeks.

[0020] Fixed delay compensation method. For example, the paper “Static compensation technology of signal delay in chassis HIL test” (Automotive Engineering, No. 4, 2023) proposes to pre-calibrate the fixed delay value (such as 30ms) between the simulation model and the bench, and directly add a fixed compensation amount when the simulation command is output, to realize the matching of “command-feedback”. However, it can only compensate for “fixed delay”, and cannot cope with the dynamically changing delay in HIL test (such as when the bench motor load increases, the feedback signal delay increases from 30ms to 50ms), resulting in compensation failure.

[0021] Please refer to Figure 1 , Figure 1 A step flowchart of a signal synchronization correction method for a simulation model and a bench.

[0022] The embodiment provides a signal synchronization correction method for a simulation model and a bench, which comprises the following steps: S101, based on the synchronization mark, the command signal sent by the simulation model and the feedback signal returned by the bench are collected, wherein the synchronization mark is the same identification code carried by the signal frame corresponding to the command signal and the signal frame corresponding to the feedback signal.

[0023] S102. Determine the delay time between the command signal and the feedback signal.

[0024] S103. When the delay time is greater than the preset delay threshold, generate a signal compensation amount based on the delay time.

[0025] S104. Based on the signal compensation amount, perform time-axis advance compensation on the command signal issued by the simulation model so that the simulation model issues a corrected command signal.

[0026] In some embodiments, a preset delay threshold (which can be adjusted via the host computer interface, default 20ms) is used: if Δt≤20ms, no correction is required; if Δt>20ms, correction is initiated.

[0027] Understandably, this embodiment achieves precise correlation between command and feedback signals through synchronization markers, ensuring the correspondence of signal frames. By accurately measuring the delay time and generating a compensation amount, the command signal of the simulation model is compensated in advance, effectively correcting signal time deviation. This correction method based on synchronization markers can accurately identify signal delays, adapt to signal changes under different test environments, and possesses strong adaptability. Simultaneously, the advance compensation ensures time synchronization between the command and feedback signals, improving test accuracy. The entire process is automated and efficient, reducing manual intervention, significantly improving test efficiency and reliability, and meeting the requirements of high precision and strong adaptability in testing.

[0028] In some embodiments, a method for signal synchronization correction between a simulation model and a test bench further includes: On the simulation model side, a synchronization marker is inserted into the sequence of instruction signals generated by the simulation model at a first preset period.

[0029] On the test bench hardware side, a synchronization marker is inserted into the feedback signal sequence triggered and returned to the test bench at a second preset period, wherein the second preset period is the same as the first preset period.

[0030] In this embodiment, on the simulation model side, a custom S-function is added after the "command signal output" module of the Simulink model. The function triggers the insertion of a marker frame every 10ms (the insertion period can be adjusted by the host computer parameters, ranging from 5 to 20ms). After insertion, the marker frame is packaged and sent with the command signal frame (including torque value, speed value, etc.).

[0031] On the bench hardware side, in the "Signal Acquisition" module, a "Marker Frame Insertion Script" is added using VeriStand software. Every 10ms (consistent with the synchronization period of the simulation model), a synchronization marker frame is appended after the feedback signal frame to ensure that the marking periods of the two are matched.

[0032] In some embodiments, the synchronization marker is a data frame with a fixed format, the data frame comprising: The frame header field contains predefined fixed values. The frame header field is used to identify data frames as synchronization marker frames based on these fixed values.

[0033] The timestamp field's content is generated by the local clock of the simulation model or bench that produced the data frame.

[0034] The signal identifier field is used to distinguish the signal type. The signal identifier field of the command signal is different from that of the feedback signal and they are paired.

[0035] The validation field is used to verify the integrity of the data frame during transmission.

[0036] In some embodiments, the synchronization tag frame structure adopts a fixed format of "frame header (2 bytes) + timestamp (4 bytes) + signal ID (2 bytes) + checksum (1 byte)," specifically defined as follows: Frame header: fixed at 0xAA55, used by the host computer to identify the synchronization marker frame (distinguished from ordinary data frames).

[0037] Timestamp: The format is "year-month-day-hour-minute-second-millisecond" (e.g., 20241001143000000, accurate to 1ms), generated by the local clock module of the simulation model / bench.

[0038] Signal ID: The simulation model command signal ID is 0x0001 (such as steering torque command), and the bench feedback signal ID is 0x0002 (such as steering motor torque feedback). These are used by the host computer to match the commands and feedback of the "same test item".

[0039] Check bit: CRC8 check is used to verify the integrity of frame data by the host computer and avoid delay calculation deviations caused by transmission errors.

[0040] Understandably, this embodiment ensures the synchronization of the signal sequence by inserting synchronization markers at the same period on both the simulation model and the test bench. The synchronization markers use fixed-format data frames, including a frame header, timestamp, signal identifier, and checksum field, which can accurately identify the signal type and verify data integrity. This improvement makes signal synchronization more precise, enhances the system's adaptability and fault tolerance, further improves testing efficiency and reliability, and better meets the requirements of high-precision, highly adaptive testing.

[0041] Please refer to Figure 2 , Figure 2 This is a flowchart of step S102 in a method for signal synchronization correction between a simulation model and a test bench.

[0042] In some embodiments, step S102 includes: S201. Based on the signal identifier field in the synchronization tag, filter out the target command signal frame and the target feedback signal frame.

[0043] S202. Extract the timestamp field from the target instruction signal frame and the target feedback signal frame.

[0044] S203. Determine the delay time based on the difference between the transmission timestamp of the target instruction signal frame and the reception timestamp of the target feedback signal frame.

[0045] In some embodiments, "simulation command frames (including synchronization markers)" and "bench feedback frames (including synchronization markers)" are received via Ethernet. Commands and feedback frames at the same time are matched based on "signal ID" and "timestamp range" (e.g., command frames and feedback frames with timestamps between 10:00:00.000 and 10:00:00.010). The timestamps of the matched frames are extracted, and the time difference between the two is calculated as follows: Delay time Δt = bench feedback frame timestamp - simulation command frame timestamp For example, if the timestamp of the simulation command frame is 10:00:00.000 and the timestamp of the bench feedback frame is 10:00:00.050, then Δt = 50ms.

[0046] Understandably, this embodiment filters target signal frames through a signal identifier field to ensure that the processed signal frames accurately correspond to the target commands and feedback signals. Extracting the timestamp field and calculating the delay time allows for more precise quantification of signal transmission delay. This improvement makes the determination of delay time more accurate, reduces errors, further improves the accuracy and reliability of signal synchronization, significantly enhances testing efficiency and the system's adaptability, and better meets the requirements of high-precision and highly adaptive testing.

[0047] Please refer to Figure 3 , Figure 3 This is a flowchart of step S103 in a method for signal synchronization correction between a simulation model and a test bench.

[0048] In some embodiments, step S103 includes: S301. Input the delay time into the preset delay prediction model.

[0049] S302. Using the delay prediction model, determine the predicted delay time for the next simulation step based on the historical trend of the delay time, and generate the corresponding signal compensation amount based on the predicted delay time.

[0050] S303. Send the calibrated command signal to the test bench for execution, and receive the calibrated feedback signal returned by the test bench.

[0051] S304. When the delay time between the corrected command signal and the corrected feedback signal is greater than the preset delay threshold, return to step S301 until the delay time is less than or equal to the preset delay threshold.

[0052] Understandably, this embodiment achieves dynamic adjustment by inputting the delay time into the delay prediction model, using historical data to predict the delay time for the next simulation step, and generating a corresponding compensation amount. The corrected signal is sent to the test bench and feedback is received. If the delay still exceeds the threshold, iterative optimization continues until the requirements are met. This improvement enables the system to adapt to dynamically changing delay conditions in real time, further improving signal synchronization accuracy and testing efficiency, significantly enhancing system stability and reliability, and better meeting the needs of high-precision, highly adaptive testing.

[0053] In some embodiments, the specific implementation methods of advance compensation include: The difference between the delay time and the preset buffer time is used as the advance of the command signal; control commands are sent to the simulation model so that the simulation model outputs the command signal originally scheduled to be output in the next simulation cycle at the time of the current simulation cycle minus the advance.

[0054] In this embodiment, an "early output command" is sent to the simulation model to adjust the command output timing. The advance time is Δt - 10ms (leaving a 10ms redundancy to avoid overcompensation). For example, if Δt = 50ms, the advance time is 50ms - 10ms = 40ms. The command originally output at 10:00:00.100 is changed to be output at 10:00:00.060, ensuring that the actual time difference between the bench feedback frame (10:00:00.110) and the command frame is reduced to 10ms (≤20ms threshold). This embodiment is applicable to simulation models whose command output timing cannot be adjusted (such as third-party fixed models), and also achieves "command-feedback" synchronization, equivalent to the original solution.

[0055] Understandably, this embodiment achieves precise lead compensation by using the difference between the delay time and the preset buffer time as the advance of the command signal and adjusting the output time of the command signal. This compensation method enables the simulation model to dynamically adjust the output time of the command signal based on the real-time calculated advance, ensuring precise alignment of the command signal and the feedback signal on the time axis. Combined with dynamic delay prediction and cyclic optimization mechanisms, the system's adaptability and synchronization accuracy are further improved. Overall, this technical solution significantly improves the efficiency and reliability of testing, ensuring high-precision signal synchronization even in complex dynamic environments, and better meeting the testing requirements for high precision and strong adaptability.

[0056] In some embodiments, step S104 includes: Based on the signal compensation amount, the time when the test bench sends the feedback signal is delayed so that the test bench returns the corrected feedback signal. The signal compensation amount is the difference between the delay time and the preset delay threshold.

[0057] In some embodiments, if the delay time is less than or equal to a preset delay threshold, no correction is performed; if the delay time is greater than the preset delay threshold, the instruction is not output in advance, but the bench feedback signal is delayed. For example, after the host computer receives the feedback frame, it delays by Δt - threshold time before sending it to the chassis controller.

[0058] Understandably, this embodiment ensures precise time alignment between the feedback signal and the command signal by applying signal compensation to the timing adjustment of the bench feedback signal. Combined with lead compensation and dynamic delay prediction, this scheme achieves end-to-end synchronization optimization from command to feedback, enhancing the overall coordination and stability of the system. This bidirectional correction mechanism significantly improves signal synchronization accuracy, further enhancing testing efficiency and reliability, and enabling the system to possess stronger adaptability in complex testing environments, better meeting the demands of high-precision, highly adaptive testing.

[0059] Please refer to Figure 4 , Figure 4 This is a schematic diagram of a signal synchronization correction device for a simulation model and a test bench.

[0060] This embodiment also provides a signal synchronization correction device for simulation model and test bench, including: The signal acquisition module 401 is used to acquire the command signal issued by the simulation model and the feedback signal returned by the test bench based on the synchronization mark. The synchronization mark is the same identification code carried by the signal frame corresponding to the command signal and the signal frame corresponding to the feedback signal.

[0061] The first calculation module 402 is used to determine the delay time between the instruction signal and the feedback signal.

[0062] The second calculation module 403 is used to generate a signal compensation amount based on the delay time when the delay time is greater than a preset delay threshold.

[0063] The signal correction module 404 is used to perform time-axis advance compensation on the command signal issued by the simulation model based on the signal compensation amount, so that the simulation model can issue a corrected command signal.

[0064] In some embodiments, the signal acquisition module 401 can acquire command signals through the simulation model terminal module and feedback signals through the bench hardware terminal module. The functions of the first calculation module 402, the second calculation module 403, and the signal correction module 404 are implemented by a host computer.

[0065] In one specific embodiment, a steering system dynamics model, such as the steering torque command signal, built based on MATLAB / Simulink, is tested on a hardware-in-the-loop (HIL) test bench. VeriStand is installed on the host computer and configured with a "synchronous correction module," which includes functions for parsing marker frames, calculating delays, and outputting correction commands. The preset parameters are a synchronous marker period of 10ms and a delay threshold of 20ms.

[0066] Implementation steps: (1) For the simulation model, add a synchronization marker S-function after the Simulink "Torque Command Output" module, compile the model and download it to the simulation computer.

[0067] (2) For the bench end, add a “feedback signal marker script” in VeriStand, set it to insert a synchronization marker frame every 10ms, and start the bench hardware.

[0068] (3) Simulation model outputs torque command (e.g., 30N) m), instruction frame timestamp 10:00:00.000, including synchronization flag (ID=0x0001).

[0069] (4) The test bench motor receives and responds to the command, and the torque sensor collects the feedback signal (29.8N). m), feedback frame timestamp 10:00:00.055, including synchronization flag (ID=0x0002).

[0070] (5) The host computer matches two frames and calculates Δt=55ms>20ms to trigger correction.

[0071] (6) The host computer sends a correction command, with an advance time of 55ms - 10ms = 45ms; the next command in the simulation model (35N) The original output of 10:00:00.100 has been changed to 10:00:00.055.

[0072] Corrected instruction output time (T1) = Original instruction time - Δt = 10:00:00.100 - 0:00:00.055 = 10:00:00.045.

[0073] The timestamp of the bench feedback frame (T2) = T1 + Δt = 10:00:00.045 + 0:00:00.055 = 10:00:00.100.

[0074] Ultimately, Δt = T2 - original instruction time = 0ms, achieving complete synchronization.

[0075] Understandably, in this embodiment, by using 10ms periodic marker frames, the host computer can obtain the timestamps of instructions and feedback in real time, dynamically calculate the delay, avoid the limitations of fixed compensation, and directly improve test accuracy. The correction logic is implemented through Simulink S functions and VeriStand scripts, requiring no RTOS or high-end hardware, and is directly integrated into ordinary HIL software, thus reducing costs and operational complexity. Delay calculation and correction are automatically triggered without manual intervention, adapting to dynamic delay changes and improving flexibility.

[0076] It will be understood by those skilled in the art that all or some of the steps and apparatuses in the methods disclosed above can be implemented as software, firmware, hardware, and suitable combinations thereof. Some or all of the physical components can be implemented as software executed by a processor, such as a central processing unit, digital signal processor, or microprocessor, or as hardware, or as an integrated circuit, such as an application-specific integrated circuit. Such software can be distributed on a computer-readable medium, which can include computer storage media (or non-transitory media) and communication media (or transient media). As is known to those skilled in the art, the term computer storage media includes volatile and non-volatile, removable and non-removable media implemented in any method or technology for storing information (such as computer-readable instructions, data structures, program modules, or other data). Computer storage media includes, but is not limited to, RAM, ROM, EEPROM, flash memory or other memory technologies, CD-ROM, digital versatile disc (DVD) or other optical disc storage, magnetic cartridges, magnetic tape, disk storage or other magnetic storage devices, or any other medium that can be used to store desired information and is accessible to a computer. As is known to those skilled in the art, communication media typically contain computer-readable instructions, data structures, program modules, or other data in modulated data signals such as carrier waves or other transmission mechanisms, and may include any information delivery medium.

[0077] It is understood that the content of the above method embodiments is applicable to the present device embodiments. The specific functions implemented by the present device embodiments are the same as those of the above method embodiments, and the beneficial effects achieved are also the same as those achieved by the above method embodiments.

[0078] This application also provides an electronic device, which includes a memory and a processor. The memory stores a computer program, and the processor executes the computer program to implement the signal synchronization correction method between the simulation model and the test bench as described above.

[0079] refer to Figure 5 , Figure 5 The hardware structure of an electronic device according to another embodiment is illustrated. The electronic device includes: The processor 501 can be implemented using a general-purpose CPU (Central Processing Unit), microprocessor, application-specific integrated circuit (ASIC), or one or more integrated circuits, and is used to execute relevant programs to implement the technical solutions provided in the embodiments of this application. The memory 502 can be implemented as a read-only memory (ROM), static storage device, dynamic storage device, or random access memory (RAM). The memory 502 can store operating devices and other application programs. When the technical solutions provided in the embodiments of this specification are implemented through software or firmware, the relevant program code is stored in the memory 502 and is called by the processor 501 to execute the signal synchronization correction method for the simulation model and test bench of the embodiments of this application. The input / output interface 503 is used to implement information input and output; The communication interface 504 is used to enable communication and interaction between this device and other devices. Communication can be achieved through wired means (such as USB, Ethernet cable, etc.) or wireless means (such as mobile network, WIFI, Bluetooth, etc.). Bus 505 transmits information between various components of the device (e.g., processor 501, memory 502, input / output interface 503, and communication interface 504); The processor 501, memory 502, input / output interface 503, and communication interface 504 are connected to each other within the device via bus 505.

[0080] It is understood that the content of the above method embodiments is applicable to the embodiments of this electronic device. The specific functions implemented by the embodiments of this electronic device are the same as those of the above method embodiments, and the beneficial effects achieved are also the same as those achieved by the above method embodiments.

[0081] This application also provides a computer-readable storage medium storing a processor-executable program, which, when executed by a processor, is used to implement the signal synchronization correction method for the simulation model and the test bench as described in any of the above specific embodiments.

[0082] This application also discloses a computer program product, including a computer program or computer instructions, which are stored in a computer-readable storage medium. The processor of the computer device reads the computer program or computer instructions from the computer-readable storage medium and executes the computer program or computer instructions, causing the computer device to perform the signal synchronization correction method for the simulation model and the test bench as described in any of the preceding embodiments.

[0083] It is understood that the content of the above method embodiments is applicable to this storage medium embodiment. The specific functions implemented in this storage medium embodiment are the same as those in the above method embodiments, and the beneficial effects achieved are also the same as those achieved in the above method embodiments.

[0084] The terms “first,” “second,” “third,” “fourth,” etc. (if present) in the specification and accompanying drawings of this application are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that the embodiments of this application described herein can be implemented, for example, in orders other than those illustrated or described herein. Furthermore, the terms “comprising” and “having,” and any variations thereof, are intended to cover non-exclusive inclusion; for example, a process, method, apparatus, product, or device that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or devices. It should be understood that in this application, “at least one” means one or more, and “more than one” means two or more.

[0085] In the several embodiments provided in this application, it should be understood that the disclosed apparatus, devices, and methods can be implemented in other ways. For example, the apparatus embodiments described above are merely illustrative; for instance, the division of units is only a logical functional division, and in actual implementation, there may be other division methods. For example, multiple units or components may be combined or integrated into another device, or some features may be ignored or not executed. Furthermore, the coupling or direct coupling or communication connection shown or discussed may be indirect coupling or communication connection through some interfaces, devices, or units, and may be electrical, mechanical, or other forms.

[0086] The units described as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the units can be selected to achieve the purpose of this embodiment according to actual needs.

[0087] Furthermore, the functional units in the various embodiments of this application can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit. The integrated unit can be implemented in hardware or as a software functional unit.

[0088] If the integrated unit is implemented as a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of this application, in essence, or the part that contributes to the prior art, or all or part of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute all or part of the steps of the methods described in the various embodiments of this application. The aforementioned storage medium includes various media capable of storing program code, such as USB flash drives, portable hard drives, read-only memory (ROM), random access memory (RAM), magnetic disks, or optical disks.

[0089] Although the description of this application has been quite detailed and particularly focused on several of the described embodiments, it is not intended to limit itself to any of these details or embodiments or any particular embodiment. Rather, it should be considered as effectively covering the intended scope of this application by referring to the appended claims and taking into account the prior art, which provides for a broad possible interpretation of these claims. Furthermore, the foregoing description of this application with respect to embodiments foreseeable by the inventors is intended to provide a useful description, and non-substantial modifications to this application that have not yet been foreseen may still represent equivalent modifications.

Claims

1. A method for signal synchronization correction of a simulation model and a bench, characterized in that, The method comprises: Based on the synchronization mark, the instruction signal sent by the simulation model and the feedback signal returned by the test bench are collected, wherein the synchronization mark is the same identification code carried by the signal frame corresponding to the instruction signal and the signal frame corresponding to the feedback signal; The delay time between the instruction signal and the feedback signal is determined; When the delay time is greater than a preset delay threshold, a signal compensation amount is generated according to the delay time; Based on the signal compensation amount, the instruction signal sent by the simulation model is compensated in advance on the time axis, so as to make the simulation model send a corrected instruction signal.

2. The method of claim 1, wherein, When the delay time is greater than a preset delay threshold, a signal compensation amount is generated according to the delay time, which comprises: The delay time is input into a preset delay prediction model; Using the delay prediction model, the predicted delay time of the next simulation step is determined according to the historical change trend of the delay time, and the corresponding signal compensation amount is generated according to the predicted delay time; The corrected instruction signal is sent to the test bench for execution, and the corrected feedback signal returned by the test bench is received; When the delay time between the corrected instruction signal and the corrected feedback signal is greater than the preset delay threshold, the step of inputting the delay time into the preset delay prediction model is returned to execute until the delay time is less than or equal to the preset delay threshold.

3. The method according to claim 1 or 2, characterized in that, The method further comprises: At the simulation model end, the synchronization mark is inserted into the instruction signal sequence generated by the simulation model at a first preset period; At the test bench hardware end, the synchronization mark is inserted into the feedback signal sequence returned by the test bench at a second preset period, wherein the second preset period is the same as the first preset period.

4. The method of claim 3, wherein, The synchronization mark is a data frame with a fixed format, which comprises in turn: A frame header field, the content of which is a predefined fixed value, wherein the frame header field is used to identify the data frame as a synchronization mark frame according to the fixed value; A timestamp field, the content of which is generated by the local clock of the simulation model or the test bench generating the data frame; A signal identification field, the content of which is used to distinguish signal types, wherein the signal identification field of the instruction signal is different from and has a pairing relationship with the signal identification field of the feedback signal; A check field for verifying the integrity of the data frame during transmission.

5. The method of claim 4, wherein, The determination of the delay time between the instruction signal and the feedback signal comprises: Based on the signal identification field in the synchronization mark, the target instruction signal frame and the target feedback signal frame are screened out; The timestamp field is extracted from the target instruction signal frame and the target feedback signal frame; The delay time is determined according to the difference between the sending timestamp of the target instruction signal frame and the receiving timestamp of the target feedback signal frame.

6. The method of claim 1, wherein, The specific implementation mode of the advance compensation comprises: The difference between the delay time and the preset buffer time is used as the advance amount of the instruction signal; The control instruction is sent to the simulation model, so that the simulation model outputs the instruction signal originally output in the next simulation cycle at a time point of the current simulation cycle minus the advance amount.

7. The method of claim 1, wherein, The signal compensation amount is used to compensate the instruction signal output by the simulation model in the time axis, so that the simulation model outputs a corrected instruction signal. The signal compensation amount is used to delay the time of the feedback signal output by the simulation model, so that the simulation model returns a corrected feedback signal, wherein the signal compensation amount is the difference between the delay time and the preset delay threshold.

8. A signal synchronization correction device for a simulation model and a bench, characterized by, The device comprises: A signal acquisition module is configured to acquire the instruction signal output by the simulation model and the feedback signal returned by the test bench based on a synchronization mark, wherein the synchronization mark is the same identification code carried by the signal frame corresponding to the instruction signal and the signal frame corresponding to the feedback signal. A first calculation module is configured to determine the delay time between the instruction signal and the feedback signal. A second calculation module is configured to generate a signal compensation amount according to the delay time when the delay time is greater than a preset delay threshold. A signal correction module is configured to compensate the instruction signal output by the simulation model in the time axis based on the signal compensation amount, so that the simulation model outputs a corrected instruction signal.

9. An electronic device, comprising: The electronic device comprises a memory and a processor, the memory stores a computer program, and the processor implements the simulation model and the test bench signal synchronization correction method of any one of claims 1 to 7 when executing the computer program.

10. A computer-readable storage medium storing a computer program, the computer program comprising instructions that, when executed by a computer, cause the computer to perform the method of any one of claims 1 to 9. The computer program is executed by the processor to implement the simulation model and the test bench signal synchronization correction method of any one of claims 1 to 7.

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