Circuit device

Abstract

A circuit arrangement. The circuit device includes: a bias voltage generation circuit that generates a first bias voltage and a second bias voltage based on a power supply voltage, outputs the first bias voltage to a first bias node, and outputs the second bias voltage to a second bias node; a first follower circuit that outputs a first output voltage that follows the first bias voltage; a second follower circuit that outputs a second output voltage that follows the second bias voltage; and a first potential fixing circuit that fixes the potential of the first bias node to the potential of the power supply node when the power supply voltage rises.

Description

TECHNICAL FIELD

[0001] The present application relates to a circuit device or the like. BACKGROUND

[0002] Patent Document 1 discloses a voltage adjustment system including a voltage adjustment unit and a plurality of stages connected in parallel to the output of the voltage adjustment unit. The voltage adjustment unit generates a voltage through an amplification circuit. The generated voltage is input to the gate of a source follower of each stage, and the source follower of each stage outputs an output voltage. In this way, the plurality of stages outputs a plurality of output voltages. These plurality of output voltages are generated with reference to a ground voltage.

[0003] Patent Document 1: Japanese Patent Application Publication No. 2009-301087

[0004] In a circuit that generates an output voltage with a given potential difference with respect to a power supply voltage, that is, outputs an output voltage with reference to a power supply voltage, it is necessary to output an appropriate output voltage in response to a change in the power supply voltage at the time of power supply activation. Patent Document 1 does not describe a case where an output voltage is output with reference to a power supply voltage, but outputs an output voltage with reference to a ground voltage. SUMMARY

[0005] One embodiment of the present disclosure relates to a circuit device that generates a first output voltage and a second output voltage lower than the first output voltage from a power supply voltage supplied to a power supply node, the circuit device including: a bias voltage generation circuit that generates a first bias voltage and a second bias voltage with reference to the power supply voltage, outputs the first bias voltage to a first bias node, and outputs the second bias voltage to a second bias node; a first follower circuit that outputs the first output voltage that follows the first bias voltage to a first output node; a second follower circuit that outputs the second output voltage that follows the second bias voltage to a second output node; and a first potential fixing circuit that fixes a potential of the first bias node to a potential of the power supply node when the power supply voltage rises.

[0006] Further, another embodiment of the present disclosure relates to a circuit device that generates a first output voltage and a second output voltage lower than the first output voltage from a power supply voltage supplied to a power supply node, the circuit device including: a bias voltage generation circuit that generates a first bias voltage and a second bias voltage with reference to the power supply voltage, outputs the first bias voltage to a first bias node, and outputs the second bias voltage as the second output voltage to a second output node that is a second bias node; a first follower circuit that outputs the first output voltage that follows the first bias voltage to a first output node; and a first potential fixing circuit that fixes a potential of the first bias node to a potential of the power supply node when the power supply voltage rises. Attached Figure Description

[0007] Figure 1 This is a first structural example of a voltage generation circuit included in a circuit device.

[0008] Figure 2 This is a structural example of a circuit device that includes a voltage generation circuit and a subsequent circuit.

[0009] Figure 3 This is the first detailed structural example of a voltage generation circuit.

[0010] Figure 4 This is the second detailed structural example of a voltage generation circuit.

[0011] Figure 5 This is a signal waveform example illustrating the operation of the second detailed structural example of the voltage generation circuit.

[0012] Figure 6 This is a structural example of a comparison example.

[0013] Figure 7 This is a comparative example of signal waveforms.

[0014] Figure 8 This is the first other structural example of the first potential fixed circuit.

[0015] Figure 9 This is another example of the structure of the second reference voltage setting circuit.

[0016] Figure 10 These are other structural examples of the second potential fixed circuit.

[0017] Figure 11 This is the second other structural example of the first potential fixed circuit.

[0018] Figure 12 This is the first other structural example of a bias voltage generation circuit.

[0019] Figure 13 This is the second other structural example of a bias voltage generation circuit.

[0020] Figure 14 This is a second structural example of a voltage generation circuit included in a circuit device.

[0021] Figure 15 This is a more detailed structural example of the second structural example of the voltage generation circuit.

[0022] Label Explanation

[0023] 100 Circuit device; 200 Voltage generation circuit; 210 Bias voltage generation circuit; 211, 211b, 211c First reference voltage setting circuit; 212, 212b Second reference voltage setting circuit; 215, 215b, 215c Bias circuit; 231 First potential fixing circuit; 232 Second potential fixing circuit; 251 First follower circuit; 252 Second follower circuit; 300 Circuit; 310 Level shifter; 321 First pre-drive circuit; 322 Second pre-drive circuit; 330 Drive circuit; 331 First drive transistor; 332 Second drive transistor; BP2 NPN bipolar transistor; CK1 capacitor; GND ground voltage; NGND ground node; NOUT1 first output node; NOUT2 second output node; NPS power supply node; NR1 first bias node; NR2 second bias node; RK1 resistor; VOUT1 first output voltage; VOUT2 second output voltage; VPS power supply voltage; VR1 first bias voltage; VR2 second bias voltage; ZD1 Zener diode. Detailed Implementation

[0024] The preferred embodiments of this disclosure will now be described in detail. Furthermore, the embodiments described below are not intended to unduly limit the scope of the claims, and not all structures described in these embodiments are necessarily essential structural elements. Additionally, the connections in these embodiments include electrical connections. Electrical connections are connections capable of transmitting electrical signals, voltages, or currents, including connections capable of transmitting information via electrical signals. Electrical connections can also be connections via passive or active components.

[0025] 1. Example of the first structure

[0026] Figure 1 This is a first structural example of the voltage generation circuit 200 included in the circuit device of this embodiment. The voltage generation circuit 200 includes a bias voltage generation circuit 210, a first potential fixing circuit 231, a second potential fixing circuit 232, a first follower circuit 251, and a second follower circuit 252. Alternatively, the second potential fixing circuit 232 may be omitted. The circuit device may include only the voltage generation circuit 200, or it may include other circuits. The circuit device is, for example, an integrated circuit device in which multiple circuit elements are integrated on a semiconductor substrate.

[0027] The power node NPS is the node from which the power supply voltage VPS is supplied. The ground node NGND is the node from which the power supply ground voltage GND is supplied. The power supply voltage VPS also includes transient voltage variations, such as the power supply voltage before, during, and after power-on. The power supply voltage after power-on and stabilization is recorded as the given power supply voltage VBB. The power supply can be located externally to the circuit device or internally within the circuit device.

[0028] The bias voltage generation circuit 210 generates a first bias voltage VR1 and a second bias voltage VR2 based on the power supply voltage VPS. The first bias voltage VR1 is output to the first bias node NR1, and the second bias voltage VR2 is output to the second bias node NR2. Here, the power supply voltage VPS is a given power supply voltage VBB. The voltage based on the given power supply voltage VBB is generated in such a way that there is a given voltage difference relative to the given power supply voltage VBB. The first bias voltage VR1 and the second bias voltage VR2 are set such that the second output voltage VOUT2 (described later) is lower than the first output voltage VOUT1. For example, the second bias voltage VR2 is lower than the first bias voltage VR1.

[0029] The first follower circuit 251 outputs a first output voltage VOUT1 that follows the first bias voltage VR1 to the first output node NOUT1. That is, the first follower circuit 251 outputs a first output voltage VOUT1 that maintains a given voltage difference relative to the first bias voltage VR1, or outputs a first output voltage VOUT1 with the same voltage value as the first bias voltage VR1. The first follower circuit 251 is, for example,... Figure 3 The source follower circuit described in the text is not limited to this; it can also be a voltage follower circuit, etc. A voltage follower circuit is a circuit that connects the negative input terminal and the output terminal of an operational amplifier. The positive input terminal of the operational amplifier becomes the input of the voltage follower circuit, and the output terminal of the operational amplifier becomes the output of the voltage follower circuit.

[0030] The second follower circuit 252 outputs a second output voltage VOUT2 that follows the second bias voltage VR2 to the second output node NOUT2. That is, the second follower circuit 252 outputs a second output voltage VOUT2 that maintains a given voltage difference relative to the second bias voltage VR2, or outputs a second output voltage VOUT2 with the same voltage value as the second bias voltage VR2. The second follower circuit 252 is, for example,... Figure 3 The source follower circuit described in the document is not limited to this; it can also be a voltage follower circuit, etc.

[0031] The first potential fixing circuit 231 fixes the potential of the first bias node NR1 to the potential of the power supply node NPS when the power supply voltage VPS rises. That is, when the power supply voltage VPS rises from near ground voltage GND to a given power supply voltage VBB during power-on, the first potential fixing circuit 231 fixes the potential of the first bias node NR1 such that the first bias voltage VR1 is equal to the power supply voltage VPS during the rise. Furthermore, the rise of the power supply voltage VPS includes at least the period until the power supply voltage VPS reaches the given power supply voltage VBB. For example, as in... Figure 3As explained in the documentation, after the power supply voltage VPS becomes the given power supply voltage VBB, the bias voltage generation circuit 210 becomes "enabled" and begins to generate the bias voltage. At this time, the rise of the power supply voltage VPS can also be the period until the bias voltage generation circuit 210 becomes "enabled".

[0032] When the power supply voltage VPS rises, the second potential fixing circuit 232 fixes the potential of the second bias node NR2 to the potential of the power supply node NPS. That is, when the power supply starts up and causes the power supply voltage VPS to rise from a low voltage such as near 0V to a given power supply voltage VBB, the second potential fixing circuit 232 fixes the potential of the second bias node NR2 in such a way that the second bias voltage VR2 is equal to the power supply voltage VPS during the rise.

[0033] According to this embodiment, when the power supply voltage VPS rises, the first bias voltage VR1 is fixed to the power supply voltage VPS, and consequently, the first output voltage VOUT1 is also fixed to the power supply voltage VPS. This reduces the impact on subsequent circuits using the first output voltage VOUT1. For example, malfunctions or failures in subsequent circuits can be considered. Similarly, by fixing the second bias voltage VR2 to the power supply voltage VPS, the second output voltage VOUT2 is also fixed to the power supply voltage VPS. This reduces the impact on subsequent circuits using the second output voltage VOUT2.

[0034] Figure 2 This is a structural example of a circuit device 100 that includes a voltage generation circuit 200 and a subsequent circuit 300. Here, as an example of a circuit 300 using a first output voltage VOUT1 and a second output voltage VOUT2, a bridge circuit and its driving circuit are described, but the circuit 300 is not limited to this. The circuit 300 includes a level shifter 310, a first pre-drive circuit 321, a second pre-drive circuit 322, and a driving circuit 330.

[0035] The drive circuit 330 is a bridge circuit. That is, the drive circuit 330 includes: a first drive transistor 331 on the high side, connected between the power supply node NPS and the output node of the drive voltage; and a second drive transistor 332 on the low side, connected between the output node of the drive voltage and the ground node NGND. The first drive transistor 331 is a P-type MOS transistor, and the second drive transistor 332 is an N-type MOS transistor. The first drive transistor 331 and the second drive transistor 332 are alternately turned on or off, thereby driving loads such as motors. Additionally, an example of a half-bridge circuit is shown here, but the drive circuit 330 can also be an H-bridge circuit.

[0036] The level shifter 310 includes an inverter circuit INV, P-type MOS transistors TL1-TL4, and N-type MOS transistors TL5 and TL6. The connection relationship is shown in the figure. The operation is explained below.

[0037] Level shifter 310 levels-shifts the control signal HCK from a control circuit (not shown), outputting the result as signal LSQ. The control signal HCK is used to control the first driving transistor 331 of the drive circuit 330 to be on or off. The power supply voltage VPS is the given power supply voltage VBB. A high level of the control signal HCK is a logic power supply voltage lower than the given power supply voltage VBB, and a low level is the ground voltage GND. A high level of signal LSQ is the given power supply voltage VBB, and a low level is a voltage approximately higher than the second output voltage VOUT2 by the threshold voltage of the P-type MOS transistor TL4. The second output voltage VOUT2 is, for example, approximately lower than the threshold voltage of the P-type MOS transistor TL4 by the first output voltage VOUT1. Therefore, the low level of signal LSQ is approximately the same as the first output voltage VOUT1.

[0038] The first pre-drive circuit 321 is composed of one or more stages of inverter circuits, etc., and drives the gate of the first drive transistor 331 of the drive circuit 330 by buffering the signal LSQ. The high-potential side power supply node of the first pre-drive circuit 321 is connected to the power supply node NPS, and the low-potential side power supply node is connected to the first output node NOUT1 of the voltage generation circuit 200.

[0039] The second pre-drive circuit 322 is composed of one or more stages of inverter circuits, etc., and drives the gate of the second drive transistor 332 of the drive circuit 330 by buffering the control signal LCK from a control circuit (not shown). The control signal LCK is a signal used to control the second drive transistor 332 to be turned on or off. The high-potential side power supply node of the second pre-drive circuit 322 is supplied with a power supply voltage VREG, and the low-potential side power supply node is connected to the ground node NGND. The power supply voltage VREG is supplied, for example, from a regulator that steps down a given power supply voltage VBB. The power supply voltage VREG is a voltage that is higher than the ground voltage GND and lower than the first output voltage VOUT1.

[0040] When the power supply voltage VPS rises, it is assumed that VOUT1 < VPS. Consequently, the output of the first pre-drive circuit 321 becomes unstable, potentially causing a malfunction such as the first drive transistor 331 of the drive circuit 330 turning on. When the first drive transistor 331 is on, current flows from the power node NPS through the first drive transistor 331 to the load, and either the first drive transistor 331 or the load may fail. According to this embodiment, when the power supply voltage VPS rises, the first output voltage VOUT1 is fixed to the power supply voltage VPS by the first potential fixing circuit 231 of the voltage generation circuit 200. Therefore, the output of the first pre-drive circuit 321 is determined to be the power supply voltage VPS, maintaining the first drive transistor 331 of the drive circuit 330 off, thus preventing malfunctions or failures.

[0041] Furthermore, when the power supply voltage VPS rises, it is assumed that VOUT2 < VPS. Consequently, the signal LSQ output by the level shifter 310 to the first pre-drive circuit 321 becomes unstable, potentially causing the same malfunctions or failures as described above. According to this embodiment, when the power supply voltage VPS rises, the second output voltage VOUT2 is fixed to the power supply voltage VPS by the second potential fixing circuit 232 of the voltage generation circuit 200. Therefore, the signal LSQ output by the level shifter 310 is determined to be the power supply voltage VPS, preventing malfunctions or failures. Furthermore, regarding these issues and solutions, in Figures 4-7 A more specific structural example will be provided again.

[0042] Figure 3 This is the first detailed structural example of the voltage generation circuit 200. Additionally, regarding... Figure 1 For parts with the same structure as the example, explanations should be omitted appropriately.

[0043] The bias voltage generation circuit 210 includes a first reference voltage setting circuit 211, a second reference voltage setting circuit 212, and a bias circuit 215.

[0044] The first reference voltage setting circuit 211 is connected between the power supply node NPS and the first bias node NR1. When the bias current flows, it sets the potential difference between the given power supply voltage VBB and the first bias voltage VR1 as the first reference voltage. The first reference voltage setting circuit 211 can be, for example, a reverse-biased Zener diode, or multiple reverse-biased Zener diodes connected in series. "Reverse" means that the anode is connected to the node on the low potential side, and the cathode is connected to the node on the high potential side. In this case, the first reference voltage is set by the Zener voltage of the Zener diode. Alternatively, the first reference voltage setting circuit 211 can also be one or more reverse-biased Zener diodes and one or more forward-biased diodes connected in series. "Forward" means that the anode is connected to the node on the high potential side, and the cathode is connected to the node on the low potential side. In this case, the first reference voltage is set by the Zener voltage and the forward voltage of the Zener diode.

[0045] The second reference voltage setting circuit 212 is connected between the first bias node NR1 and the second bias node NR2, and sets the potential difference between the first bias voltage VR1 and the second bias voltage VR2 as the second reference voltage when the bias current flows. The second reference voltage setting circuit 212 is, for example, a forward-biased diode or multiple forward-biased diodes connected in series. Alternatively, the second reference voltage setting circuit 212 may also be one or more forward-biased diodes and one or more reverse-biased Zener diodes connected in series.

[0046] Bias circuit 215 supplies bias current to the first reference voltage setting circuit 211 and the second reference voltage setting circuit 212. Specifically, bias circuit 215 includes a current source IB that allows bias current to flow from the second bias node NR2 to the ground node NGND. Through the current source IB, bias current flows from the power supply node NPS through the first reference voltage setting circuit 211 and the second reference voltage setting circuit 212 to the second bias node NR2. This generates a first bias voltage VR1 and a second bias voltage VR2. Bias circuit 215 supplies bias current when the enable signal EN from a control circuit (not shown) is "enabled".

[0047] The first follower circuit 251 is a source follower circuit, comprising a resistor RF1 and a P-type MOS transistor TF1. Resistor RF1 is connected between the power supply node NPS and the first output node NOUT1. The source of the P-type MOS transistor TF1 is connected to the first output node NOUT1, its drain is connected to the ground node NGND, and its gate is connected to the first bias node NR1. The first output voltage VOUT1 is approximately higher than the first bias voltage VR1 by the threshold voltage of the P-type MOS transistor TF1. That is, the potential difference between the given power supply voltage VBB and the first output voltage VOUT1 is approximately lower than the first reference voltage set by the first reference voltage setting circuit 211 by the threshold voltage of the P-type MOS transistor TF1.

[0048] The second follower circuit 252 is a source follower circuit, comprising a resistor RF2 and a P-type MOS transistor TF2. Resistor RF2 is connected between the power supply node NPS and the second output node NOUT2. The source of the P-type MOS transistor TF2 is connected to the second output node NOUT2, its drain is connected to the ground node NGND, and its gate is connected to the second bias node NR2. The second output voltage VOUT2 is approximately higher than the second bias voltage VR2 by the threshold voltage of the P-type MOS transistor TF2. If the threshold voltages of the P-type MOS transistors TF1 and TF2 are the same, then the potential difference between the first output voltage VOUT1 and the second output voltage VOUT2 is the second reference voltage set by the second reference voltage setting circuit 212.

[0049] Figure 4 This is the second detailed structural example of the voltage generation circuit 200. Additionally, regarding... Figure 1 or Figure 3 For parts with the same structure as the example, explanations should be omitted appropriately.

[0050] The first reference voltage setting circuit 211 includes a Zener diode ZD1. The anode of the Zener diode ZD1 is connected to the first bias node NR1, and the cathode is connected to the power supply node NPS.

[0051] The second reference voltage setting circuit 212 includes a diode-connected NPN bipolar transistor BP2. The collector and base of the NPN bipolar transistor BP2 are connected to the first bias node NR1, and the emitter is connected to the second bias node NR2.

[0052] The bias circuit 215 includes resistors R1 and R2 and an N-type MOS transistor M1. One end of resistor R1 is connected to the power supply node NPS, and the other end is connected to the drain of the N-type MOS transistor M1. One end of resistor R2 is connected to the second bias node NR2, and the other end is connected to the drain of the N-type MOS transistor M1. The source of the N-type MOS transistor M1 is connected to the ground node NGND. The gate of the N-type MOS transistor M1 is given an enable signal EN. When the enable signal EN is low, the N-type MOS transistor M1 is off, and the bias circuit 215 is disabled, supplying no bias current. When the enable signal EN is high, the N-type MOS transistor M1 is on, and the bias circuit 215 is enabled, supplying bias current.

[0053] The first potential fixing circuit 231 includes a resistor RK1 disposed between the power supply node NPS and the first bias node NR1. One end of the resistor RK1 is connected to the power supply node NPS, and the other end is connected to the first bias node NR1. The resistance value of the resistor RK1 is set to the degree to which the Zener diode ZD1 conducts when a bias current flows through the bias circuit 215. That is, the resistance value of the resistor RK1 is set such that the voltage drop when the bias current flows through the resistor RK1 exceeds the Zener voltage.

[0054] The second potential fixing circuit 232 includes a capacitor CK2 disposed between the power supply node NPS and the second bias node NR2. One end of the capacitor CK2 is connected to the power supply node NPS, and the other end is connected to the second bias node NR2.

[0055] Figure 5 This is a signal waveform example illustrating the operation of the second detailed structural example of the voltage generation circuit 200. First, using... Figure 6 and Figure 7 Explain the structural example and signal waveform example of the comparison example, and explain while comparing them. Figure 5 Waveform example.

[0056] Figure 6 This is a structural example of a comparison example. The comparison example is... Figure 4 The first potential fixing circuit 231 and the second potential fixing circuit 232 are omitted in the structural example. A parasitic capacitance CP1 exists between the first bias node NR1 and the ground node NGND, and a parasitic capacitance CP2 exists between the second bias node NR2 and the ground node NGND. These parasitic capacitances are generated by the wiring parasitic capacitance of each bias node or the parasitic capacitance of the circuit elements connected to each bias node, etc.

[0057] Figure 7This is a comparative example of signal waveforms. The enable signal EN changes from low to high after the power supply voltage VPS becomes the given power supply voltage VBB upon power-on. The bias circuit 215 is disabled during the period when the enable signal EN is low, and does not supply bias current to the first reference voltage setting circuit 211 and the second reference voltage setting circuit 212. Hereinafter, the ground voltage GND is assumed to be 0V.

[0058] Before power-on, the power supply voltage VPS is 0V. Therefore, the first bias voltage VR1, the second bias voltage VR2, the first output voltage VOUT1, and the second output voltage VOUT2 are all 0V. At this time, the potential difference between the parasitic capacitors CP1 and CP2 is 0V.

[0059] When the power supply starts up, the supply voltage VPS rises from 0V to a given supply voltage VBB. The waveform of the bias voltage IDA represents the waveforms of the first bias voltage VR1 and the second bias voltage VR2 ideally following the supply voltage VPS. In practice, before the supply voltage VPS exceeds the Zener voltage of the Zener diode ZD1, the first bias voltage VR1 is maintained near 0V through the parasitic capacitance CP1. After the supply voltage VPS rises and the Zener diode ZD1 turns on, the parasitic capacitance CP1 is charged, and the first bias voltage VR1 rises. Similarly, before the supply voltage VPS exceeds the voltage obtained by adding the Zener voltage and the forward voltage of the NPN bipolar transistor BP2, the second bias voltage VR2 is maintained near 0V through the parasitic capacitance CP2. Furthermore, since resistor R1 is a high resistor, the charging of the parasitic capacitance CP2 through resistors R1 and R2 can be ignored. After the power supply voltage VPS rises and Zener diode ZD1 and diode turn on, parasitic capacitance CP2 is charged, and the second bias voltage VR2 rises.

[0060] The waveform of the output voltage IDB represents the waveforms when the first output voltage VOUT1 and the second output voltage VOUT2 ideally follow the power supply voltage VPS. In reality, as described above, when the power supply voltage VPS rises, a potential difference is created between VPS and the first bias voltage VR1, and a potential difference is created between VPS and the second bias voltage VR2. When these potential differences are higher than the threshold voltages of N-type transistors TF1 and TF2, N-type transistors TF1 and TF2 conduct. Therefore, when the power supply voltage VPS rises, the first output voltage VOUT1 and the second output voltage VOUT2 become lower than the power supply voltage VPS. If the power supply voltage VPS is taken as a reference, VPS-VOUT1 and VPS-VOUT2 are temporarily below 0V when the power supply voltage VPS rises. Thus, when the first output voltage VOUT1 and the second output voltage VOUT2 are lower than the power supply voltage VPS when the power supply voltage VPS rises, ... Figure 2As explained in the document, the circuit 300 following the first output voltage VOUT1 and the second output voltage VOUT2 may malfunction or fail.

[0061] return Figure 5 Example of a signal waveform in this embodiment. For example, in... Figure 4 As described above, in this embodiment, a resistor RK1 of the first potential fixing circuit 231 and a capacitor CK2 of the second potential fixing circuit 232 are provided.

[0062] When the power supply voltage VPS rises, the enable signal EN is low. During the period when the enable signal EN is low, the bias circuit 215 does not supply bias current to the first reference voltage setting circuit 211 and the second reference voltage setting circuit 212. At this time, the first bias node NR1 is connected to the power supply node NPS via resistor RK1, so the first bias voltage VR1 follows the power supply voltage VPS by approximately the same voltage. The resistance value of resistor RK1 is set to be able to... Figure 6 The degree to which the parasitic capacitance CP1 is charged. Furthermore, the second bias node NR2 is connected to the power supply node NPS via capacitor CK2, so the second bias voltage VR2 follows the power supply voltage VPS by approximately the same voltage. The capacitance value of capacitor CK2 is... Figure 6 The parasitic capacitance CP2 is large enough.

[0063] When the power supply voltage VPS rises, there is almost no potential difference between VPS and the first bias voltage VR1; therefore, the P-type MOS transistor TF1 does not conduct. Consequently, the first output voltage VOUT1 follows the power supply voltage VPS by approximately the same voltage. Similarly, there is almost no potential difference between VPS and the second bias voltage VR2; therefore, the P-type MOS transistor TF2 does not conduct. Consequently, the second output voltage VOUT2 follows the power supply voltage VPS by approximately the same voltage. When the power supply voltage VPS rises, neither the first output voltage VOUT1 nor the second output voltage VOUT2 decreases relative to VPS, thus preventing [further issues]. Figure 2 The following describes the malfunction or fault of the subsequent circuit 300.

[0064] When the enable signal EN changes from low to high, the bias circuit 215 supplies bias current. This sets the potential difference between the given power supply voltage VBB and the first bias voltage VR1 based on the Zener voltage of the Zener diode ZD1. Furthermore, the potential difference between the first bias voltage VR1 and the second bias voltage VR2 is set based on the forward voltage of the diode based on the NPN bipolar transistor BP2. Then, the first follower circuit 251 outputs a first output voltage VOUT1 following the first bias voltage VR1, and the second follower circuit 252 outputs a second output voltage VOUT2 following the second bias voltage VR2.

[0065] Figure 8 This is a first alternative structural example of the first potential fixing circuit 231. The first potential fixing circuit 231 includes a resistor RK1 and a capacitor CK1 connected in parallel between the power supply node NPS and the first bias node NR1. Specifically, one end of the resistor RK1 and one end of the capacitor CK1 are connected to the power supply node NPS, and the other end is connected to the first bias node NR1.

[0066] Figure 9 This is another example of the structure of the second reference voltage setting circuit 212. The second reference voltage setting circuit 212 includes an NPN bipolar transistor BP2 and a P-type MOS transistor TP2 connected in series between the first bias node NR1 and the second bias node NR2. Each transistor is diode-connected. Specifically, the collector and base of the NPN bipolar transistor BP2 are connected to the first bias node NR1, and the emitter is connected to the second bias node NR2. The source of the P-type MOS transistor TP2 is connected to the emitter of the NPN bipolar transistor BP2, and the drain and gate are connected to the second bias node NR2.

[0067] In this structural example, the potential difference between the first bias voltage VR1 and the second bias voltage VR2, i.e., the second reference voltage, is the voltage obtained by adding the forward voltage of the diode of the NPN bipolar transistor BP2 and the forward voltage of the diode of the P-type MOS transistor TP2.

[0068] Figure 10 This is another example of the structure of the second potential fixing circuit 232. The second potential fixing circuit 232 includes a P-type MOS transistor TK2 disposed between the power supply node NPS and the second bias node NR2. Specifically, the source of the P-type MOS transistor TK2 is connected to the power supply node NPS, and the drain is connected to the second bias node NR2. The gate of the P-type MOS transistor TK2 is input with an enable signal EN. The P-type MOS transistor TK2 is turned on when the enable signal EN is low, fixing the second bias voltage VR2 to the power supply voltage VPS, and is turned off when the enable signal EN is high.

[0069] Figure 11 This is a second alternative structural example of the first potential fixing circuit 231. The first potential fixing circuit 231 includes a P-type MOS transistor TK1 disposed between the power supply node NPS and the first bias node NR1. Specifically, the source of the P-type MOS transistor TK1 is connected to the power supply node NPS, and the drain is connected to the first bias node NR1. The gate of the P-type MOS transistor TK1 is input with an enable signal EN. The P-type MOS transistor TK1 is turned on when the enable signal EN is low, fixing the first bias voltage VR1 to the power supply voltage VPS, and is turned off when the enable signal EN is high.

[0070] Figure 12 This is a first other structural example of the bias voltage generation circuit 210. The bias voltage generation circuit 210 includes a first reference voltage setting circuit 211b, a second reference voltage setting circuit 212b, and a bias circuit 215b.

[0071] The bias circuit 215b supplies a first bias current to the first reference voltage setting circuit 211b and a second bias current to the second reference voltage setting circuit 212b. The bias circuit 215b includes a first bias circuit 217 and a second bias circuit 218.

[0072] The first bias circuit 217 supplies a first bias current to the first reference voltage setting circuit 211b. Specifically, the first bias circuit 217 includes a current source IB1 that causes the first bias current to flow from the first bias node NR1 to the ground node NGND. The first bias current flows through the current source IB1, and the bias current flows from the power supply node NPS through the first reference voltage setting circuit 211b to the first bias node NR1.

[0073] The second bias circuit 218 supplies a second bias current to the second reference voltage setting circuit 212b. Specifically, the second bias circuit 218 includes a second current source IB2 that causes the second bias current to flow from the second bias node NR2 to the ground node NGND. The second bias current flows through the second current source IB2, and the bias current flows from the power supply node NPS through the second reference voltage setting circuit 212b to the second bias node NR2.

[0074] The first bias circuit 217 and the second bias circuit 218 are respectively connected to the... Figure 1 , Figure 3 or Figure 4 The bias circuit 215 described in the previous section is constructed in the same manner.

[0075] The first reference voltage setting circuit 211b is connected between the power supply node NPS and the first bias node NR1. When the first bias current flows through it, it sets the potential difference between the given power supply voltage VBB and the first bias voltage VR1 as the first reference voltage.

[0076] The second reference voltage setting circuit 212b is connected between the power supply node NPS and the second bias node NR2. When the second bias current flows, it sets the potential difference between the given power supply voltage VBB and the second bias voltage VR2 as the second reference voltage. In this example, the second reference voltage is greater than the first reference voltage.

[0077] The first reference voltage setting circuit 211b and in Figure 3 or Figure 4 The first reference voltage setting circuit 211 described in the previous section is similarly configured. The second reference voltage setting circuit 212b, for example, comprises... Figure 3 or Figure 4 It is configured as the first reference voltage setting circuit 211 and the second reference voltage setting circuit 212 described in the above.

[0078] Figure 13 This is a second alternative configuration of the bias voltage generation circuit 210. The bias voltage generation circuit 210 includes a first reference voltage setting circuit 211c, a second reference voltage setting circuit 212b, and a bias circuit 215.

[0079] The first reference voltage setting circuit 211c is a voltage divider circuit. The voltage divider circuit divides the power supply voltage VPS and the second output voltage VOUT2, and outputs the result as the first bias voltage VR1 to the first bias node NR1. The first reference voltage setting circuit 211c includes resistors RD1 and RD2 connected in series between the power supply node NPS and the second output node NOUT2. The node between resistors RD1 and RD2 is connected to the first bias node NR1.

[0080] In this example, the first bias voltage VR1 is higher than the second output voltage VOUT2. Therefore, the first output voltage VOUT1, which follows the first bias voltage VR1, is higher than the second output voltage VOUT2.

[0081] In this embodiment, the circuit device 100 generates a first output voltage VOUT1 and a second output voltage VOUT2, which is lower than the first output voltage VOUT1, based on the power supply voltage VPS provided to the power node NPS. The circuit device 100 includes a bias voltage generation circuit 210, a first follower circuit 251, a second follower circuit 252, and a first potential fixing circuit 231. The bias voltage generation circuit 210 generates a first bias voltage VR1 and a second bias voltage VR2 based on the power supply voltage VPS, outputting the first bias voltage VR1 to the first bias node NR1 and the second bias voltage VR2 to the second bias node NR2. The first follower circuit 251 outputs the first output voltage VOUT1, which follows the first bias voltage VR1, to the first output node NOUT1. The second follower circuit 252 outputs the second output voltage VOUT2, which follows the second bias voltage VR2, to the second output node NOUT2. When the power supply voltage VPS rises, the first potential fixing circuit 231 fixes the potential of the first bias node NR1 to the potential of the power supply node NPS.

[0082] In this embodiment, a first bias voltage VR1 is generated based on the power supply voltage VPS, and a first output voltage VOUT1 following the first bias voltage VR1 is generated. That is, the first output voltage VOUT1 is generated based on the power supply voltage VPS. In this case, as... Figure 6 and Figure 7 As explained in the previous section, when the power supply voltage VPS rises, the first output voltage VOUT1 may become lower than the power supply voltage VPS. Therefore, the subsequent circuit 300 using the first output voltage VOUT1 may malfunction or fail when the power supply voltage VPS rises. According to this embodiment, the first potential fixing circuit 231 fixes the potential of the first bias node NR1 to the potential of the power supply node NPS when the power supply voltage VPS rises. The first output voltage VOUT1 follows the first bias voltage VR1 fixed to the power supply voltage VPS, and therefore follows the power supply voltage VPS. Thus, no difference between the first output voltage VOUT1 and the power supply voltage VPS occurs when the power supply voltage VPS rises, and the subsequent circuit 300 using the first output voltage VOUT1 does not malfunction or fail.

[0083] Furthermore, in this embodiment, the circuit device 100 may also include a second potential fixing circuit 232. The second potential fixing circuit 232 may also fix the potential of the second bias node NR2 to the potential of the power supply node NPS when the power supply voltage VPS rises.

[0084] According to this embodiment, the second output voltage VOUT2 follows the second bias voltage VR2, which is fixed to the power supply voltage VPS, and therefore follows the power supply voltage VPS. As a result, no difference between the second output voltage VOUT2 and the power supply voltage VPS is generated when the power supply voltage VPS rises, and the subsequent circuit 300 using the second output voltage VOUT2 does not malfunction or fail.

[0085] exist Figure 3 In other embodiments, the bias voltage generation circuit 210 may also include a first reference voltage setting circuit 211 and a second reference voltage setting circuit 212. The first reference voltage setting circuit 211 may also be located between the power supply node NPS and the first bias node NR1, setting the potential difference between the power supply node NPS and the first bias node NR1 as the first reference voltage. The second reference voltage setting circuit 212 may also be located between the first bias node NR1 and the second bias node NR2, setting the potential difference between the first bias node NR1 and the second bias node NR2 as the second reference voltage.

[0086] According to this embodiment, the first reference voltage setting circuit 211 sets the potential difference between the power supply node NPS and the first bias node NR1 as the first reference voltage, thereby generating a first bias voltage VR1 based on the power supply voltage VPS. Consequently, a first output voltage VOUT1 following the first bias voltage VR1 is generated based on the power supply voltage VPS. Furthermore, according to this embodiment, the second reference voltage setting circuit 212 sets the potential difference between the first bias node NR1 and the second bias node NR2 as the second reference voltage, thereby generating a second bias voltage VR2 based on the first bias voltage VR1, wherein the first bias voltage VR1 is based on the power supply voltage VPS. Consequently, a second output voltage VOUT2 following the second bias voltage VR2 is generated based on the power supply voltage VPS.

[0087] In addition, Figure 4 In the embodiments described above, the first reference voltage setting circuit 211 can also generate the first reference voltage using the Zener voltage of the Zener diode ZD1. The second reference voltage setting circuit 212 can also generate the second reference voltage using the forward voltage of the diode. Furthermore, in... Figure 4 In the NPN bipolar transistor BP2, which has been diode-connected, the base-emitter voltage corresponds to the forward voltage of the diode.

[0088] According to this embodiment, a first bias voltage VR1, which is lower than the power supply voltage VPS by a Zener voltage, can be generated. Furthermore, a second bias voltage VR2, which is lower than the power supply voltage VPS by the sum of the Zener voltage and the forward voltage of the diode, can be generated.

[0089] In addition, Figure 3 In other embodiments, the bias voltage generation circuit 210 may also include a bias circuit 215 that provides bias current to the first reference voltage setting circuit 211 and the second reference voltage setting circuit 212.

[0090] According to this embodiment, the bias circuit 215 supplies bias current to the first reference voltage setting circuit 211 and the second reference voltage setting circuit 212, thereby enabling the first reference voltage setting circuit 211 to set a first reference voltage and the second reference voltage setting circuit 212 to set a second reference voltage. For example, by supplying bias current to the Zener diode ZD1, the Zener diode ZD1 generates a Zener voltage as the first reference voltage. Furthermore, by supplying bias current to the diode, the diode generates a forward voltage as the second reference voltage.

[0091] In addition, Figure 3 In other embodiments, the bias circuit 215 may also not supply bias current to the first reference voltage setting circuit 211 and the second reference voltage setting circuit 212 when the power supply voltage VPS rises.

[0092] According to this embodiment, the first reference voltage and the second reference voltage are not set when the power supply voltage VPS rises. Therefore, the first potential fixing circuit 231 can fix the first bias voltage VR1 to the power supply voltage VPS, and the second potential fixing circuit 232 can fix the second bias voltage VR2 to the power supply voltage VPS.

[0093] In addition, Figure 12 In this embodiment, the bias voltage generation circuit 210 may also include a first reference voltage setting circuit 211b and a second reference voltage setting circuit 212b. The first reference voltage setting circuit 211b may also be located between the power supply node NPS and the first bias node NR1, setting the potential difference between the power supply node NPS and the first bias node NR1 as the first reference voltage. The second reference voltage setting circuit 212b may also be located between the power supply node NPS and the second bias node NR2, setting the potential difference between the power supply node NPS and the second bias node NR2 as the second reference voltage.

[0094] In addition, Figure 12 In some implementations, the bias voltage generation circuit 210 may also include a bias circuit 215b that provides bias current to the first reference voltage setting circuit 211 and the second reference voltage setting circuit 212.

[0095] According to this embodiment, a first bias voltage VR1 is generated based on the power supply voltage VPS, and a first output voltage VOUT1 following the first bias voltage VR1 is generated based on the power supply voltage VPS. Similarly, a second bias voltage VR2 is generated based on the power supply voltage VPS, and a second output voltage VOUT2 following the second bias voltage VR2 is generated based on the power supply voltage VPS.

[0096] In addition, Figure 12 In one implementation, the bias circuit 215b may also not supply bias current to the first reference voltage setting circuit 211b and the second reference voltage setting circuit 212b when the power supply voltage VPS rises.

[0097] According to this embodiment, the first reference voltage and the second reference voltage are not set when the power supply voltage VPS rises. Therefore, the first potential fixing circuit 231 can fix the first bias voltage VR1 to the power supply voltage VPS, and the second potential fixing circuit 232 can fix the second bias voltage VR2 to the power supply voltage VPS.

[0098] exist Figure 4 , Figure 8 or Figure 11 In other embodiments, the first potential fixing circuit 231 may also be composed of at least one of a resistor, a capacitor, and a transistor. Furthermore, when a transistor is used, the transistor turns on when the power supply voltage VPS rises.

[0099] According to this embodiment, the power supply node NPS and the first bias node NR1 are connected by at least one of a resistor, a capacitor and a transistor, thereby fixing the first bias voltage VR1 to the power supply voltage VPS when the power supply voltage VPS rises.

[0100] exist Figure 4 or Figure 10 In other embodiments, the second potential fixing circuit 232 may also be composed of at least one of a capacitor and a transistor.

[0101] According to this embodiment, the power supply node NPS and the second bias node NR2 are connected by at least one of a capacitor and a transistor, thereby fixing the second bias voltage VR2 to the power supply voltage VPS when the power supply voltage VPS rises.

[0102] In addition, Figure 2 In embodiments such as these, the circuit device 100 may also include a circuit that operates with the power supply voltage VPS as the high-potential side power supply voltage and the first output voltage VOUT1 as the low-potential side power supply voltage. Furthermore, in Figure 2In the example, the first pre-drive circuit 321 is a circuit that operates with the power supply voltage VPS as the high-potential side power supply voltage and the first output voltage VOUT1 as the low-potential side power supply voltage.

[0103] If the first output voltage VOUT1 is lower than the power supply voltage VPS when the power supply voltage VPS rises, the circuit operating with the first output voltage VOUT1 as the low-potential side power supply voltage may malfunction. Furthermore, due to this malfunction, circuit elements within the circuit device 100, external circuits, or external components may fail. According to this embodiment, when the power supply voltage VPS rises, the first output voltage VOUT1 is fixed at the power supply voltage VPS; therefore, malfunctions or failures will not occur.

[0104] In addition, Figure 2 In this embodiment, the circuit device 100 may also include: a first pre-drive circuit 321 that drives the first drive transistor 331 of the drive circuit 330; and a level shifter 310 that levels-shifts the control signal HCK of the first pre-drive circuit 321 and outputs it to the first pre-drive circuit 321. The first drive transistor 331 may also be disposed between the power supply node NPS and the output node of the drive voltage. The first pre-drive circuit 321 may also operate with the power supply voltage VPS as the high-potential side power supply voltage and the first output voltage VOUT1 as the low-potential side power supply voltage. The level shifter 310 may also output the power supply voltage VPS as a high level and output a voltage referenced to the second output voltage VOUT2 as a low level.

[0105] When the power supply voltage VPS rises, if the first output voltage VOUT1 is lower than the power supply voltage VPS, the first pre-drive circuit 321 operates, and the first drive transistor 331 turns on, causing a malfunction or failure. Alternatively, when the power supply voltage VPS rises, if the second output voltage VOUT2 is lower than the power supply voltage VPS, the low level of the output of the level shifter 310 is lower than the power supply voltage VPS, and this low level is input to the first pre-drive circuit 321, causing a malfunction or failure. According to this embodiment, when the power supply voltage VPS rises, the first output voltage VOUT1 is fixed to the power supply voltage VPS. Therefore, the output of the first pre-drive circuit 321, which uses the first output voltage VOUT1 as the low-potential side power supply voltage, is fixed to the power supply voltage VPS. Furthermore, when the power supply voltage VPS rises, the second output voltage VOUT2 is fixed to the power supply voltage VPS. Therefore, the output of the level shifter 310, which uses the voltage based on the second output voltage VOUT2 as the low-level output, is fixed to the power supply voltage VPS. Therefore, there will be no malfunctions or failures when the power supply voltage VPS rises.

[0106] 2. Example of the second structure

[0107] Figure 14 This is a second structural example of the voltage generation circuit 200 included in the circuit device 100 of this embodiment. Hereinafter, for... Figures 1-13 The description of the parts that are the same as those in the first structural example is omitted appropriately, and the description mainly focuses on the parts that are different from those in the first structural example.

[0108] The voltage generation circuit 200 includes a bias voltage generation circuit 210, a first potential fixing circuit 231, a second potential fixing circuit 232, and a first follower circuit 251. In the second structural example, the second follower circuit 252 is omitted from the first structural example, and the second bias node NR2 becomes the second output node NOUT2. That is, the bias voltage generation circuit 210 outputs the second bias voltage VR2 as the second output voltage VOUT2 to the second output node NOUT2.

[0109] Figure 15 This is a more detailed structural example of the second structural example of the voltage generation circuit 200. The bias voltage generation circuit 210 includes a first reference voltage setting circuit 211, a second reference voltage setting circuit 212, and a bias circuit 215c.

[0110] The bias circuit 215c includes a resistor R2 and an N-type MOS transistor M1. One end of the resistor R2 is connected to the second bias node NR2, and the other end is connected to the drain of the N-type MOS transistor M1. The source of the N-type MOS transistor M1 is connected to the ground node NGND. The gate of the N-type MOS transistor M1 is given an enable signal EN.

[0111] In this embodiment, the circuit device 100 generates a first output voltage VOUT1 and a second output voltage VOUT2, which is lower than the first output voltage VOUT1, based on the power supply voltage VPS provided to the power node NPS. The circuit device 100 includes a bias voltage generation circuit 210, a first follower circuit 251, and a first potential fixing circuit 231. The bias voltage generation circuit 210 generates a first bias voltage VR1 and a second bias voltage VR2 based on the power supply voltage VPS, outputting the first bias voltage VR1 to the first bias node NR1, and outputting the second bias voltage VR2 as the second output voltage VOUT2 to the second output node NOUT2, which is the second bias node NR2. The first follower circuit 251 outputs the first output voltage VOUT1, which follows the first bias voltage VR1, to the first output node NOUT1. The first potential fixing circuit 231 fixes the potential of the first bias node NR1 to the potential of the power node NPS when the power supply voltage VPS rises.

[0112] According to this embodiment, when the power supply voltage VPS rises, the first potential fixing circuit 231 fixes the potential of the first bias node NR1 to the potential of the power supply node NPS. The first output voltage VOUT1 follows the first bias voltage VR1 fixed to the power supply voltage VPS, and therefore follows the power supply voltage VPS. Thus, no difference between the first output voltage VOUT1 and the power supply voltage VPS is generated when the power supply voltage VPS rises, and the subsequent circuit 300 using the first output voltage VOUT1 does not malfunction or fail.

[0113] Furthermore, in this embodiment, the second bias voltage VR2 is output to the second output node NOUT2 without passing through a follower circuit. In this case, the second potential fixing circuit 232 can also fix the potential of the second output node NOUT2 to the potential of the power supply node NPS when the power supply voltage VPS rises. Therefore, no difference between the second output voltage VOUT2 and the power supply voltage VPS is generated when the power supply voltage VPS rises, and the subsequent circuit 300 using the second output voltage VOUT2 does not malfunction or fail.

[0114] Furthermore, while this embodiment has been described in detail above, those skilled in the art will readily understand that various modifications can be made without substantially departing from the new aspects and effects of this disclosure. Therefore, all such modifications are included within the scope of this disclosure. For example, in the specification or drawings, a term described at least once with a broader or synonymous term can be replaced with that different term anywhere in the specification or drawings. Additionally, all combinations of this embodiment and its modifications are also included within the scope of this disclosure. Furthermore, the structure and operation of the circuit device, voltage generation circuit, subsequent circuit, bias voltage generation circuit, first follower circuit, second follower circuit, first potential fixing circuit, and second potential fixing circuit are not limited to those described in this embodiment, and various modifications can be implemented.

Claims

1. A circuit device that generates a first output voltage and a second output voltage lower than the first output voltage from a power supply voltage supplied to a power supply node, characterized by comprising: a bias voltage generating circuit that generates a first bias voltage and a second bias voltage based on the power supply voltage, outputs the first bias voltage to a first bias node, and outputs the second bias voltage to a second bias node; a first follower circuit that outputs the first output voltage that follows the first bias voltage to a first output node; a second follower circuit that outputs the second output voltage that follows the second bias voltage to a second output node; and a first potential fixing circuit that fixes a potential of the first bias node to a potential of the power supply node when the power supply voltage rises.

2. A circuit device that generates a first output voltage and a second output voltage lower than the first output voltage from a power supply voltage supplied to a power supply node, characterized by comprising: a bias voltage generating circuit that generates a first bias voltage and a second bias voltage based on the power supply voltage, outputs the first bias voltage to a first bias node, and outputs the second bias voltage as the second output voltage to a second output node that is a second bias node; a first follower circuit that outputs the first output voltage that follows the first bias voltage to a first output node; and a first potential fixing circuit that fixes a potential of the first bias node to a potential of the power supply node when the power supply voltage rises.

3. The circuit device according to claim 1 or 2, characterized by comprising a second potential fixing circuit that fixes a potential of the second bias node to a potential of the power supply node when the power supply voltage rises.

4. The circuit device according to claim 1 or 2, characterized in that the bias voltage generating circuit comprises: a first reference voltage setting circuit that is provided between the power supply node and the first bias node, and sets a potential difference between the power supply node and the first bias node to a first reference voltage; and a second reference voltage setting circuit that is provided between the first bias node and the second bias node, and sets a potential difference between the first bias node and the second bias node to a second reference voltage.

5. The circuit device according to claim 4, characterized in that the first reference voltage setting circuit generates the first reference voltage from a Zener voltage of a Zener diode, and the second reference voltage setting circuit generates the second reference voltage from a forward voltage of a diode.

6. The circuit device according to claim 4, characterized in that the bias voltage generating circuit comprises a bias circuit that supplies a bias current to the first reference voltage setting circuit and the second reference voltage setting circuit.

7. The circuit device according to claim 6, characterized in that ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ The bias circuit does not supply the bias current to the first reference voltage setting circuit and the second reference voltage setting circuit when the power supply voltage is rising.

8. The circuit device according to claim 1 or 2, wherein The bias voltage generating circuit includes: a first reference voltage setting circuit which is provided between the power supply node and the first bias node, and sets a potential difference between the power supply node and the first bias node to a first reference voltage; and a second reference voltage setting circuit which is provided between the power supply node and the second bias node, and sets a potential difference between the power supply node and the second bias node to a second reference voltage.

9. The circuit device according to claim 8, wherein The bias voltage generating circuit includes a bias circuit which supplies a bias current to the first reference voltage setting circuit and the second reference voltage setting circuit.

10. The circuit device according to claim 9, wherein The bias circuit does not supply the bias current to the first reference voltage setting circuit and the second reference voltage setting circuit when the power supply voltage is rising.

11. The circuit device according to claim 1 or 2, wherein The first potential fixing circuit is constituted by at least one of a resistor, a capacitor, and a transistor.

12. The circuit device according to claim 3, wherein The second potential fixing circuit is constituted by at least one of a capacitor and a transistor.

13. The circuit device according to claim 1 or 2, wherein The circuit device includes a circuit which operates with the power supply voltage as a high-potential side power supply voltage and the first output voltage as a low-potential side power supply voltage.

14. The circuit device according to claim 1 or 2, wherein The circuit device includes: a first pre-driver circuit which drives a first drive transistor of a drive circuit having the first drive transistor provided between the power supply node and an output node of a drive voltage; and a level shifter which performs level shifting on a control signal of the first pre-driver circuit, the first pre-driver circuit operates with the power supply voltage as a high-potential side power supply voltage and the first output voltage as a low-potential side power supply voltage, the level shifter outputs the power supply voltage as a high level and a voltage which is referenced to the second output voltage as a low level.

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