Mirror image LDO circuit and image sensor

Abstract

The invention provides a mirror image LDO circuit and an image sensor, the mirror image LDO circuit is connected by a drive circuit, a bias voltage circuit and a state feedback circuit, when the mirror image LDO circuit works in a first working state, the state feedback circuit outputs a first trigger signal to trigger the bias voltage circuit to output a first bias voltage, and when the mirror image LDO circuit works in a second working state, the bias voltage circuit outputs a second bias voltage; and when the mirror image LDO circuit works in a second working state, the state feedback circuit outputs a second trigger signal to trigger the bias voltage circuit to output a second bias voltage, the driving circuit maintains outputting the first load current after receiving the first bias voltage, and the driving circuit maintains outputting the second load current after receiving the second bias voltage. And the voltage of the output end of the driving circuit is maintained to be stabilized at the preset voltage, constant-voltage output is achieved, the output voltage of the mirror image LDO circuit is prevented from fluctuating, and therefore the working stability and reliability of the mirror image LDO circuit are improved.

Description

Technical Field

[0001] This invention belongs to the field of image sensor technology, and particularly relates to a mirrored LDO circuit and an image sensor. Background Technology

[0002] Low dropout linear regulators (LDOs) are DC linear regulators with an input voltage greater than their output voltage. They have advantages such as fast input / output response, low output noise, fewer external components, ease of use, and low cost. They are widely used in automotive electronics, portable electronic devices, communication equipment, industrial and medical equipment. The integration of LDO circuits is also an important development direction for them.

[0003] Traditional mirrored LDOs have the advantage of a wide range of output capacitor compatibility, but their output voltage fluctuates under different load currents, such as... Figure 1 As shown, when the output load changes, the load current changes, and the output voltage of the traditional mirrored LDO circuit will have a significant rise or fall. Voltage fluctuations will affect the normal operation of the traditional mirrored LDO circuit, causing it to malfunction. Summary of the Invention

[0004] The purpose of this invention is to provide a mirrored LDO circuit, which aims to solve the problem of output voltage fluctuation in traditional mirrored LDO circuits.

[0005] A first aspect of this invention provides a mirrored LDO circuit, which operates in a first operating state of outputting a first load current or in a second operating state of outputting a second load current, wherein the first load current is greater than the second load current.

[0006] The mirrored LDO circuit includes:

[0007] The driving circuit includes a power transistor and a first resistor connected in sequence between a positive voltage terminal and a ground terminal. The connection node of the power transistor and the first resistor constitutes the output terminal of the mirror LDO circuit and is used to output driving power to the load circuit. The power transistor receives a bias voltage to generate load current.

[0008] A bias voltage circuit is connected to the control terminal of the power transistor. It outputs a first bias voltage when triggered by a first trigger signal and outputs a second bias voltage when triggered by a second trigger signal. The absolute value of the first bias voltage is greater than the absolute value of the second bias voltage.

[0009] A state feedback circuit is connected to the bias voltage circuit. The state feedback circuit is used to detect the state of the load circuit and output the first trigger signal when the mirror LDO circuit is detected to be in a first operating state, and output the second trigger signal when the load circuit is detected to be in a second operating state.

[0010] Optionally, the bias voltage circuit includes:

[0011] A first bias voltage generating circuit is used to generate the first bias voltage;

[0012] The second bias voltage generating circuit is used to generate the second bias voltage;

[0013] The switching circuit is connected to the first bias voltage generating circuit, the second bias voltage generating circuit, the power transistor, and the state feedback circuit, respectively. The switching circuit is triggered by the first trigger signal to connect the first bias voltage generating circuit and the power transistor, and is triggered by the second trigger signal to connect the second bias voltage generating circuit and the power transistor.

[0014] Optionally, the switch circuit includes:

[0015] A first switch is connected between the first bias voltage generating circuit and the control terminal of the power transistor. The control terminal of the first switch is connected to the state feedback circuit. The first switch is turned on by the first trigger signal and turned off by the second trigger signal. The first trigger signal and the second trigger signal are opposite level signals.

[0016] The second switch is connected between the second bias voltage generating circuit and the control terminal of the power transistor. The control terminal of the second switch is connected to the state feedback circuit. The second switch is turned on by the second trigger signal and turned off by the first trigger signal.

[0017] Optionally, the mirrored LDO circuit further includes:

[0018] The delayed output circuit is connected to the state feedback circuit, the first switch, and the second switch respectively. The delayed output circuit is used to output the first trigger signal and the second trigger signal to the first switch and the second switch with a delay.

[0019] Optionally, the first switch includes a first transmission gate connected between the first bias voltage generation circuit and the control terminal of the power transistor, the first transmission gate including a first NMOS transistor and a first PMOS transistor connected in parallel;

[0020] The second switch includes a second transmission gate connected between the second bias voltage generating circuit and the control terminal of the power transistor. The second transmission gate includes a second NMOS transistor and a second PMOS transistor connected in parallel. The gate of the first NMOS transistor and the gate of the second PMOS transistor are connected together to form a first control terminal, and the gate of the first PMOS transistor and the gate of the second NMOS transistor are connected together to form a second control terminal.

[0021] The delayed output circuit includes:

[0022] A delay circuit is connected between the state feedback circuit and the second control terminal. The delay circuit is used to delay the received trigger signal for a preset duration before outputting it.

[0023] An inverting circuit is connected between the state feedback circuit and the first control terminal. The inverting circuit is used to invert the received trigger signal and output it.

[0024] Optionally, the delay circuit includes a delay unit, and the input and output terminals of the delay unit constitute the input and output terminals of the delay circuit, respectively.

[0025] Optionally, the inverting circuit includes an inverter, and the input and output terminals of the inverter constitute the input and output terminals of the inverter, respectively.

[0026] Optionally, the first bias voltage generating circuit includes a first transistor, a second resistor, and a first operational amplifier;

[0027] The drain of the first transistor is connected to a positive voltage terminal, the gate of the first transistor is connected to the output terminal of the first operational amplifier, the source of the first transistor, the second resistor and the inverting input terminal of the first operational amplifier are connected, the second terminal of the second resistor is grounded, and the non-inverting input terminal of the first operational amplifier is used to input a first reference voltage.

[0028] Optionally, the first bias voltage generating circuit further includes:

[0029] Multiple first branches are connected in parallel between the drain and source of the first transistor. Each first branch includes a second transistor and a third switch connected sequentially between the drain and source of the first transistor. The gates of the multiple second transistors are connected to the gate of the first transistor. The multiple third switches are triggered to turn on or off by a first switch selection signal.

[0030] Multiple second branches are connected in parallel across the second resistor. Each second branch includes a fourth switch and a third resistor connected sequentially across the second resistor. The multiple fourth switches are triggered to turn on or off by a selection signal from the second switch.

[0031] Optionally, the second bias voltage generating circuit includes a third transistor, a fourth resistor, and a second operational amplifier;

[0032] The drain of the third transistor is connected to a positive voltage terminal, the gate of the third transistor is connected to the output terminal of the second operational amplifier, the source of the third transistor, the fourth resistor and the inverting input terminal of the second operational amplifier are connected, the second terminal of the fourth resistor is grounded, and the non-inverting input terminal of the second operational amplifier is used to input a second reference voltage.

[0033] Optionally, the second bias voltage generating circuit further includes:

[0034] Multiple third branches are connected in parallel between the drain and source of the third transistor. Each third branch includes a fourth transistor and a fifth switch connected sequentially between the drain and source of the third transistor. The gates of the multiple fourth transistors are shared with the gate of the third transistor. The multiple fifth switches are triggered to turn on or off by a third switch selection signal.

[0035] Multiple fourth branches are connected in parallel across the fourth resistor. Each fourth branch includes a sixth switch and a fifth resistor connected sequentially across the fourth resistor. The multiple sixth switches are triggered to turn on or off by a selection signal from the fourth switch.

[0036] A second aspect of the present invention provides an image sensor, including a load circuit and a mirrored LDO circuit as described above, wherein the load circuit is connected to the mirrored LDO circuit.

[0037] The beneficial effects of the embodiments of the present invention compared with the prior art are as follows: The above-mentioned mirror LDO circuit is connected by a driving circuit, a bias voltage circuit and a state feedback circuit. When the mirror LDO circuit is working in the first working state, the state feedback circuit outputs a first trigger signal to trigger the bias voltage circuit to output a first bias voltage. When the mirror LDO circuit is working in the second working state, the state feedback circuit outputs a second trigger signal to trigger the bias voltage circuit to output a second bias voltage. After receiving the first bias voltage, the driving circuit maintains the output of the first load current. After receiving the second bias voltage, the driving circuit maintains the output of the second load current and maintains the output voltage of the driving circuit at a preset voltage, thereby achieving constant voltage output and preventing the output voltage of the mirror LDO circuit from fluctuating, thereby improving the working stability and reliability of the mirror LDO circuit. Attached Figure Description

[0038] To more clearly illustrate the technical solutions in the embodiments of this application, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0039] Figure 1 This is a circuit diagram of a traditional mirrored LDO circuit;

[0040] Figure 2 This is a schematic diagram of a first structure of a mirrored LDO circuit provided in an embodiment of the present invention;

[0041] Figure 3 This is a schematic diagram of voltage waveforms under different operating states provided in an embodiment of the present invention;

[0042] Figure 4 This is a schematic diagram of a second structure of a mirrored LDO circuit provided in an embodiment of the present invention;

[0043] Figure 5 This is a schematic diagram of a third structure of the mirrored LDO circuit provided in an embodiment of the present invention;

[0044] Figure 6 This is a schematic diagram of the fourth structure of the mirrored LDO circuit provided in the embodiments of the present invention;

[0045] Figure 7 This is a first circuit diagram of a mirrored LDO circuit provided in an embodiment of the present invention;

[0046] Figure 8 A schematic diagram of the delayed output circuit provided in an embodiment of the present invention;

[0047] Figure 9 This is a second circuit diagram of a mirrored LDO circuit provided in an embodiment of the present invention;

[0048] Figure 10 A circuit diagram of the first bias voltage generating circuit provided in an embodiment of the present invention;

[0049] Figure 11 A circuit diagram of the second bias voltage generating circuit provided in an embodiment of the present invention;

[0050] Figure 12 A circuit diagram of a state feedback circuit provided in an embodiment of the present invention. Detailed Implementation

[0051] To make the technical problems to be solved, the technical solutions, and the beneficial effects of the present invention clearer, the present invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the present invention and are not intended to limit the present invention.

[0052] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of this invention, "a plurality of" means two or more, unless otherwise explicitly specified.

[0053] A first aspect of the present invention provides a mirrored LDO circuit 100 for providing load current to load current. The mirrored LDO circuit 100 can operate in different operating states according to the operating control command or the state of the load circuit 200, and output load current of different magnitudes in different operating states. In an optional embodiment, the mirrored LDO circuit 100 operates in a first operating state that outputs a first load current or in a second operating state that outputs a second load current, wherein the first operating state can be a normal output state and the second operating state can be a standby state.

[0054] In normal output mode, the load current output by the mirror LDO circuit 100 is relatively large. In standby mode, the load current output by the mirror LDO circuit 100 is relatively small. That is, the first load current is greater than the second load current.

[0055] like Figure 1 As shown, when the conventional mirrored LDO circuit 100 switches from the normal output state to the standby state, the first load current decreases to the second load current. The load current is related to the gate-source voltage of the power transistor Md of the mirrored LDO circuit 100. When the gate voltage of the power transistor Md remains unchanged, in order to adapt to the change of load current, the output voltage of the power transistor Md rises or falls, causing the output voltage Vo of the mirrored LDO circuit 100 to fluctuate.

[0056] Alternatively, when the mirrored LDO circuit 100 switches from standby state to normal output state, the second load current rises to the first load current. When the gate voltage of the power transistor Md remains unchanged, in order to adapt to the change in load current, the output voltage of the power transistor Md decreases or increases, causing the output voltage Vo of the mirrored LDO circuit 100 to fluctuate.

[0057] To avoid output voltage fluctuations caused by changes in the operating state of the mirrored LDO circuit 100 and to ensure the normal operation of the mirrored LDO circuit 100, in this embodiment, as follows: Figure 2As shown, the mirrored LDO circuit 100 includes:

[0058] The drive circuit 10 includes a power transistor Md and a first resistor R1 connected in sequence between the positive voltage terminal VDD and the ground terminal. The connection node of the power transistor Md and the first resistor R1 forms the output terminal of the mirror LDO circuit 100 and is used to output drive power to the load circuit 200. The power transistor Md receives a bias voltage to generate load current.

[0059] The bias voltage circuit 20 is connected to the control terminal of the power transistor Md. It is triggered by a first trigger signal to output a first bias voltage Vgate1 and triggered by a second trigger signal to output a second bias voltage Vgate2. The absolute value of the first bias voltage Vgate1 is greater than the absolute value of the second bias voltage Vgate2.

[0060] The status feedback circuit 30 is connected to the bias voltage circuit 20. The status feedback circuit 30 is used to detect the status of the load circuit 200, and outputs a first trigger signal when the mirror LDO circuit 100 is detected to be in a first working state, and outputs a second trigger signal when the load circuit 200 is detected to be in a second working state.

[0061] In this embodiment, in the initial state, the mirror LDO circuit 100 can operate in the first operating state or the second operating state. Assuming that in the initial state, the mirror LDO circuit 100 operates in the first operating state, the bias voltage circuit 20 outputs the first bias voltage Vgate1 to the power transistor Md, and the power transistor Md triggers the output of the first load current.

[0062] The status feedback circuit 30 can directly obtain the working control command of the mirror LDO or detect the status of the load circuit 200 to determine the current working status of the mirror LDO circuit 100. When the mirror LDO circuit 100 is detected to be working in the first working state, that is, when the current mirror LDO circuit 100 outputs the first load current to the load circuit 200, the status feedback circuit 30 outputs the first trigger signal to trigger the bias voltage circuit 20 to continue to output the first bias voltage Vgate1, maintain the output of the first load current and maintain the output voltage of the power transistor Md constant.

[0063] When a change in the operating state of the mirror LDO circuit 100 is detected, i.e., after the mirror LDO circuit 100 switches to the second operating state, the output current of the power transistor Md decreases, and the state feedback circuit 30 switches the output of the second trigger signal to the bias voltage circuit 20, such as... Figure 3As shown, the bias voltage circuit 20 switches the second bias voltage Vgate2, whose absolute value is less than the absolute value of the first bias voltage Vgate1, to the power transistor Md. The gate-source voltage of the power transistor Md decreases, and the gate voltage of the power transistor Md also decreases, thereby keeping the output voltage of the power transistor Md constant. This avoids fluctuations in the output voltage Vo of the mirror LDO circuit 100 and improves the working stability and reliability of the mirror LDO circuit 100.

[0064] And assuming that the mirrored LDO circuit 100 is operating in the second operating state in the initial state, the bias voltage circuit 20 outputs the second bias voltage Vgate2 to the power transistor Md, and the power transistor Md triggers the output of the second load current.

[0065] When the state feedback circuit 30 detects that the mirror LDO circuit 100 is operating in the second operating state, that is, when the current mirror LDO circuit 100 outputs the second load current to the load circuit 200, the state feedback circuit 30 outputs the second trigger signal to trigger the bias voltage circuit 20 to continue to output the second bias voltage Vgate2, maintain the output of the second load current and maintain the output voltage of the power transistor Md constant.

[0066] When a change in the operating state of the mirror LDO circuit 100 is detected, i.e., after the mirror LDO circuit 100 switches to the first operating state, the output current of the power transistor Md increases. The state feedback circuit 30 switches to output the first trigger signal to the bias voltage circuit 20. The bias voltage circuit 20 switches to output the first bias voltage Vgate1, whose absolute value is greater than the absolute value of the second bias voltage Vgate2, to the power transistor Md. The gate-source voltage of the power transistor Md increases, and the gate voltage of the power transistor Md also increases, thereby keeping the output voltage of the power transistor Md constant. This avoids fluctuations in the output voltage Vo of the mirror LDO circuit 100 and improves the operating stability and reliability of the mirror LDO circuit 100.

[0067] In this circuit, the power transistor Md can be an NMOS transistor or a PMOS transistor. Assuming it is an NMOS transistor, the output current of the power transistor Md is positively correlated with the gate-source voltage. That is, the larger the gate-source voltage, the larger the output current of the power transistor Md, and the smaller the gate-source voltage, the smaller the output current of the power transistor Md. At this time, the first bias voltage Vgate1 and the second bias voltage Vgate2 are positive voltages, and the source voltage of the power transistor Md constitutes the output terminal of the mirror LDO circuit 100.

[0068] Assuming it is a PMOS transistor, the output current of the power transistor Md is negatively correlated with the gate-source voltage. The source of the PMOS transistor is connected to the positive voltage terminal VDD, and its voltage remains constant. The drain of the power transistor Md forms the output terminal of the mirror LDO circuit 100. At this time, the first bias voltage Vgate1 and the second bias voltage Vgate2 are negative voltages.

[0069] When the power transistor Md is an NMOS transistor, when the mirror LDO circuit 100 switches from the first operating state to the second operating state, the mirror LDO circuit 100 is initially operating in the first operating state. The bias voltage circuit 20 outputs a positive first bias voltage Vgate1 to the power transistor Md, and the power transistor Md triggers the output of the first load current.

[0070] When the state feedback circuit 30 detects a change in the operating state of the mirror LDO circuit 100, i.e., after the mirror LDO circuit 100 switches to the second operating state, the output current of the power transistor Md decreases. The state feedback circuit 30 then switches to output a second trigger signal to the bias voltage circuit 20. The bias voltage circuit 20 then switches to output a second bias voltage Vgate2, which is lower than the first bias voltage Vgate1, to the power transistor Md. As a result, the gate-source voltage of the power transistor Md decreases, and the gate voltage of the power transistor Md also decreases. This allows the source voltage of the power transistor Md to remain constant, preventing fluctuations in the output voltage Vo of the mirror LDO circuit 100 and improving the operating stability and reliability of the mirror LDO circuit 100.

[0071] And when the mirror LDO circuit 100 switches from the second operating state to the first operating state, in the initial state the mirror LDO circuit 100 operates in the second operating state, the bias voltage circuit 20 outputs a positive second bias voltage Vgate2 to the power transistor Md, and the power transistor Md triggers the output of the second load current.

[0072] When the state feedback circuit 30 detects a change in the operating state of the mirror LDO circuit 100, i.e., after the mirror LDO circuit 100 switches to the first operating state, the output current of the power transistor Md decreases. The state feedback circuit 30 then switches to output a first trigger signal to the bias voltage circuit 20. The bias voltage circuit 20 then switches to output a first bias voltage Vgate1, which is greater than the second bias voltage Vgate2, to the power transistor Md. As a result, the gate-source voltage of the power transistor Md increases, and the gate voltage of the power transistor Md also increases. This allows the source voltage of the power transistor Md to remain constant, preventing fluctuations in the output voltage Vo of the mirror LDO circuit 100 and improving the operating stability and reliability of the mirror LDO circuit 100.

[0073] And when the power transistor Md is a PMOS transistor, when the mirror LDO circuit 100 switches from the first operating state to the second operating state, the mirror LDO circuit 100 is initially operating in the first operating state, and the bias voltage circuit 20 outputs a negative first bias voltage Vgate1 to the power transistor Md, and the power transistor Md triggers the output of the first load current.

[0074] When the state feedback circuit 30 detects a change in the operating state of the mirror LDO circuit 100, i.e., after the mirror LDO circuit 100 switches to the second operating state, the output current of the power transistor Md decreases. The state feedback circuit 30 then switches to output a second trigger signal to the bias voltage circuit 20. The bias voltage circuit 20 then switches to output a second bias voltage Vgate2, which is greater than the first bias voltage Vgate1, to the power transistor Md. That is, the absolute value of the first bias voltage Vgate1 is greater than the absolute value of the second bias voltage Vgate2. The source voltage of the power transistor Md remains unchanged, the gate-source voltage of the power transistor Md decreases, and the gate voltage of the power transistor Md increases. This keeps the drain voltage of the power transistor Md constant, avoids fluctuations in the output voltage Vo of the mirror LDO circuit 100, and improves the operating stability and reliability of the mirror LDO circuit 100.

[0075] And when the mirror LDO circuit 100 switches from the second operating state to the first operating state, in the initial state the mirror LDO circuit 100 operates in the second operating state, the bias voltage circuit 20 outputs a negative second bias voltage Vgate2 to the power transistor Md, and the power transistor Md triggers the output of the second load current.

[0076] When the state feedback circuit 30 detects a change in the operating state of the mirror LDO circuit 100, i.e., after the mirror LDO circuit 100 switches to the first operating state, the output current of the power transistor Md decreases. The state feedback circuit 30 then switches to output a first trigger signal to the bias voltage circuit 20. The bias voltage circuit 20 then switches to output a first bias voltage Vgate1, which is less than the second bias voltage Vgate2, to the power transistor Md. That is, the absolute value of the second bias voltage Vgate2 is less than the first bias voltage Vgate1. The source voltage of the power transistor Md remains unchanged, while the gate-source voltage of the power transistor Md increases. This keeps the drain voltage of the power transistor Md constant, preventing fluctuations in the output voltage Vo of the mirror LDO circuit 100 and improving the operating stability and reliability of the mirror LDO circuit 100.

[0077] The bias voltage circuit 20 can adopt a voltage source, voltage generator or other structure, and can trigger different bias voltages according to different received trigger signals.

[0078] The status feedback circuit 30 can adopt a controller, sampling circuit, comparator and other structures to determine the current working state of the mirror LDO circuit 100 by obtaining the load current magnitude or the working control command of the mirror LDO circuit 100. In an optional embodiment, the status feedback circuit 30 includes a current detection circuit, which is connected to the output terminal of the mirror LDO circuit 100 and detects the magnitude of the load current. When a first load current is detected, a first trigger signal is output, and when a second load current is detected, a second trigger signal is output.

[0079] The current detection circuit can employ structures such as current transformers and voltage divider resistors. In one optional embodiment, such as... Figure 12 As shown, the current detection circuit includes a sixth resistor R6, a seventh resistor R7, and a comparator AMP3. The first end of the sixth resistor R6 is connected to the output terminal of the power transistor Md. The second end of the sixth resistor R6 and the first end of the seventh resistor R7 are connected to the inverting input terminal of the comparator AMP3. The non-inverting input terminal of the comparator AMP3 is used to input the third reference voltage. The second end of the seventh resistor R7 is grounded. The output terminal of the comparator AMP3 constitutes the output terminal of the current detection circuit.

[0080] When the power transistor Md outputs the first load current, the voltage at the connection node of the sixth resistor R6 and the seventh resistor R7 is greater than the third reference voltage, and the comparator AMP3 outputs a low level. When the power transistor Md outputs the second load current, the voltage at the connection node of the sixth resistor R6 and the seventh resistor R7 is less than the third reference voltage, and the comparator AMP3 outputs a high level.

[0081] like Figure 4 As shown, in an optional embodiment, the bias voltage circuit 20 includes:

[0082] The first bias voltage generating circuit 21 is used to generate the first bias voltage Vgate1;

[0083] The second bias voltage generating circuit 22 is used to generate the second bias voltage Vgate2;

[0084] The switching circuit 23 is connected to the first bias voltage generating circuit 21, the second bias voltage generating circuit 22, the power transistor Md, and the state feedback circuit 30, respectively. The switching circuit 23 is triggered by the first trigger signal to connect the first bias voltage generating circuit 21 and the power transistor Md, and is triggered by the second trigger signal to connect the second bias voltage generating circuit 22 and the power transistor Md.

[0085] In this embodiment, the first input terminal of the switching circuit 23 is connected to the first bias voltage generating circuit 21 and is used to receive the first bias voltage Vgate1. The second input terminal of the switching circuit 23 is connected to the second bias voltage generating circuit 22 and is used to receive the second bias voltage Vgate2. The output terminal of the switching circuit 23 is connected to the gate of the power transistor Md, and selects to output either the first bias voltage Vgate1 or the second bias voltage Vgate2 to the power transistor Md according to the received trigger signal.

[0086] When the mirrored LDO circuit 100 is operating in the first operating state, the state feedback circuit 30 outputs the first trigger signal to the switch switching circuit 23. The switch switching circuit 23 connects its own first input terminal and output terminal, and the first bias voltage Vgate1 is output to the power transistor Md, and controls the power transistor Md to output the first load current and the preset output voltage.

[0087] When the mirrored LDO circuit 100 switches to the second operating state, the state feedback circuit 30 outputs the second trigger signal to the switch switching circuit 23. The switch switching circuit 23 connects its own second input terminal and output terminal. The second bias voltage Vgate2 is output to the power transistor Md, and the power transistor Md is controlled to output the second load current and output a constant preset voltage.

[0088] The switch switching circuit 23 can employ a multi-input single-output switching device, or different switch combinations. In an optional embodiment, such as... Figure 5 As shown, the switch switching circuit 23 includes:

[0089] The first switch S1 is connected between the first bias voltage generating circuit 21 and the control terminal of the power transistor Md. The control terminal of the first switch S1 is connected to the state feedback circuit 30. The first switch S1 is turned on by a first trigger signal and turned off by a second trigger signal. The first trigger signal and the second trigger signal are opposite level signals.

[0090] The second switch S2 is connected between the second bias voltage generating circuit 22 and the control terminal of the power transistor Md. The control terminal of the second switch S2 is connected to the state feedback circuit 30. The second switch S2 is turned on by the second trigger signal and turned off by the first trigger signal.

[0091] In this embodiment, at the same time, the switching states of the first switch S1 and the second switch S2 are different. When the mirror LDO circuit 100 is working in the first working state, the state feedback circuit 30 outputs the first trigger signal to the first switch S1 and the second switch S2. The first switch S1 is turned on, the second switch S2 is turned off, and the first bias voltage generation circuit 21 and the power transistor Md are connected. The first bias voltage Vgate1 is output to the power transistor Md, and the power transistor Md is controlled to output the first load current and the preset voltage.

[0092] When the mirrored LDO circuit 100 switches to the second operating state, the state feedback circuit 30 outputs a second trigger signal to the first switch S1 and the second switch S2. The first switch S1 is turned off, the second switch S2 is turned on, the second bias voltage Vgate2 is output to the power transistor Md, and the power transistor Md is controlled to output the second load current and maintain a constant preset voltage.

[0093] The first switch S1 and the second switch S2 can be switching devices with controlled on / off states, and the two switches are of opposite types. The first trigger signal and the second trigger signal can be high-level signals and low-level signals, respectively.

[0094] Meanwhile, when outputting the first trigger signal and the second trigger signal, at the critical switching point of the two signals, there is a possibility that the first switch S1 and the second switch S2 may be turned on simultaneously, causing the first bias voltage generation circuit 21 and the second bias voltage generation circuit 22 to be directly connected, resulting in voltage signal backflow and posing a risk of damaging the bias voltage generation circuit. Therefore, in an optional embodiment, such as Figure 6 As shown, the mirrored LDO circuit 100 also includes:

[0095] The delayed output circuit 40 is connected to the state feedback circuit 30, the first switch S1 and the second switch S2 respectively. The delayed output circuit 40 is used to delay the output of the first trigger signal and the second trigger signal to the first switch S1 and the second switch S2.

[0096] In this embodiment, when the mirror LDO circuit 100 is operating in the first operating state, the state feedback circuit 30 outputs the first trigger signal, the delayed output circuit 40 delays the output of the first trigger signal, the first switch S1 is turned on, the second switch S2 is turned off, and the first bias voltage generating circuit 21 and the power transistor Md are connected. The first bias voltage Vgate1 is output to the power transistor Md, and the power transistor Md is controlled to output the first load current and the preset voltage.

[0097] When the mirrored LDO circuit 100 switches to the second operating state, the state feedback circuit 30 outputs the second trigger signal. At this time, the second trigger signal is output with a delay. The first switch S1 is turned off first, and the second switch S2 is turned on afterward, thereby preventing the two bias voltage generation circuits from having a shoot-through problem. The second bias voltage Vgate2 is output to the power transistor Md, and controls the power transistor Md to output the second load current and maintain a constant preset voltage.

[0098] Similarly, when the mirrored LDO circuit 100 switches to the first operating state again, the state feedback circuit 30 outputs the first trigger signal. The first trigger signal is delayed by the delay output circuit 40 and then output. The second switch S2 is turned off first, and the first switch S1 is turned on later, thereby preventing the two bias voltage generation circuits from having a shoot-through problem. The first bias voltage Vgate1 is output to the power transistor Md and controls the power transistor Md to output the second load current and maintain a constant preset voltage.

[0099] In an alternative embodiment, such as Figure 7 As shown, the first switch S1 includes a first transmission gate TG1 connected between the first bias voltage generation circuit 21 and the control terminal of the power transistor Md. The first transmission gate TG1 includes a first NMOS transistor and a first PMOS transistor connected in parallel.

[0100] The second switch S2 includes a second transmission gate TG2 connected between the second bias voltage generation circuit 22 and the control terminal of the power transistor Md. The second transmission gate TG2 includes a second NMOS transistor and a second PMOS transistor connected in parallel. The gate of the first NMOS transistor and the gate of the second PMOS transistor are connected together to form a first control terminal, and the gate of the first PMOS transistor and the gate of the second NMOS transistor are connected together to form a second control terminal.

[0101] Specifically, the first NMOS transistor and the second NMOS transistor are triggered to turn on when they receive a high level and to turn off when they receive a low level; the first PMOS transistor and the second PMOS transistor are triggered to turn off when they receive a high level and to turn on when they receive a high level.

[0102] like Figure 8 As shown, the delay output circuit 40 includes:

[0103] The delay circuit 41 is connected between the status feedback circuit 30 and the second control terminal. The delay circuit 41 is used to delay the received trigger signal for a preset time before outputting it.

[0104] The inverting circuit 42 is connected between the state feedback circuit 30 and the first control terminal. The inverting circuit 42 is used to invert the received trigger signal and output it.

[0105] In this embodiment, in the first working state, the first trigger signal is at a low level, and in the second working state, the second trigger signal is at a high level.

[0106] In the initial state, the first trigger signal is output high level through the inverting circuit 42 to the first NMOS transistor of the first transmission gate TG1 and the second PMOS transistor of the second transmission gate TG2. At this time, the delay circuit 41 delays and outputs low level to the first PMOS transistor of the first transmission gate TG1 and the second NMOS transistor of the second transmission gate TG2. The first transmission gate TG1 is turned on and the second transmission gate TG2 is turned off. At this time, the first bias voltage Vgate1 is transmitted to the power transistor Md through the first transmission gate TG1 and controls the power transistor Md to output the first load current and the preset voltage.

[0107] When the mirrored LDO circuit 100 switches to the second operating state, the state feedback circuit 30 outputs a second trigger signal. At this time, the second trigger signal is inverted by the inverting circuit 42 and output as a low level to the first NMOS transistor of the first transmission gate TG1 and the second PMOS transistor of the second transmission gate TG2. The first NMOS transistor is turned off, the first transmission gate TG1 is turned off, and after a preset delay, the delay circuit 41 outputs a high level to the first PMOS transistor of the first transmission gate TG1 and the second NMOS transistor of the second transmission gate TG2. The second transmission gate TG2 is delayed in turning on, thereby preventing the two bias voltage generation circuits from having a shoot-through problem. The second bias voltage Vgate2 is output to the power transistor Md and controls the power transistor Md to output the second load current and maintain a constant preset voltage.

[0108] Similarly, when the mirrored LDO circuit 100 switches to the first operating state again, the state feedback circuit 30 outputs a first trigger signal. The first trigger signal is inverted by the inverter circuit 42 and output as a high level to the first NMOS transistor of the first transmission gate TG1 and the second PMOS transistor of the second transmission gate TG2. The second PMOS transistor is turned off, the second transmission gate TG2 is turned off, and after a preset delay, the delay circuit 41 outputs a low level to the first PMOS transistor of the first transmission gate TG1 and the second NMOS transistor of the second transmission gate TG2. The first transmission gate TG1 is delayed in turning on, thereby preventing the two bias voltage generation circuits from having a shoot-through problem. The first bias voltage Vgate1 is output to the power transistor Md and controls the power transistor Md to output the first load current and maintain a constant preset voltage.

[0109] The delay circuit 41 can be composed of multiple inverters or a delay unit. In order to simplify the circuit structure, in an optional embodiment, the delay circuit 41 includes a delay unit. The input and output terminals of the delay unit constitute the input and output terminals of the delay circuit 41, respectively. The delay unit outputs the input trigger signal to the first PMOS transistor of the first transmission gate TG1 and the second NMOS transistor of the second transmission gate TG2 after delaying the input trigger signal for a preset time, so as to control the first PMOS transistor of the first transmission gate TG1 and the second NMOS transistor of the second transmission gate TG2 to turn on or off during the delay, so as to prevent the two bias voltage generation circuits from being directly connected.

[0110] The inverting circuit 42 can employ one or more inverters or level conversion circuits. To simplify the circuit structure, in an optional embodiment, the inverting circuit 42 includes an inverter. The input and output terminals of the inverter constitute the input and output terminals of the inverter, respectively. The inverter inverts the input trigger signal and outputs it to the first NMOS transistor of the first transmission gate TG1 and the second PMOS transistor of the second transmission gate TG2, so as to control the first NMOS transistor of the first transmission gate TG1 and the second PMOS transistor of the second transmission gate TG2 to be turned on or off.

[0111] The first bias voltage generating circuit 21 and the second bias voltage generating circuit 22 can be voltage sources, mirror source circuits, etc., as shown in an optional embodiment. Figure 9 As shown, the first bias voltage generating circuit 21 includes a first transistor M1, a second resistor R2, and a first operational amplifier AMP1;

[0112] The drain of the first transistor M1 is connected to the positive voltage terminal VDD, the gate of the first transistor M1 is connected to the output terminal of the first operational amplifier AMP1, the source of the first transistor M1, the second resistor R2 and the inverting input terminal of the first operational amplifier AMP1 are connected, the second terminal of the second resistor R2 is grounded, and the non-inverting input terminal of the first operational amplifier AMP1 is used to input the first reference voltage Vref1.

[0113] The second bias voltage generating circuit 22 includes a third transistor M3, a fourth resistor R4, and a second operational amplifier AMP2.

[0114] The drain of the third transistor M3 is connected to the positive voltage terminal VDD, and the gate of the third transistor M3 is connected to the output terminal of the second operational amplifier AMP2. The source of the third transistor M3, the fourth resistor R4, and the inverting input terminal of the second operational amplifier AMP2 are connected. The second terminal of the fourth resistor R4 is grounded, and the non-inverting input terminal of the second operational amplifier AMP2 is used to input the second reference voltage Vref2.

[0115] In this embodiment, the power transistor Md, the first transistor M1, and the third transistor are NMOS transistors. When the first switch S1 is turned on, the first transistor M1, the second resistor R2, and the first operational amplifier AMP1 form a negative feedback network, and together with the power transistor Md and the first resistor R1, they form a mirror LDO circuit 100. When the voltage input at the positive voltage terminal VDD changes, the voltage at the terminal of the second resistor R2 increases or decreases. At this time, the first operational amplifier AMP1 performs negative feedback adjustment, thereby outputting a changing gate voltage, changing the current on the second resistor R2, and finally realizing that the voltage at the terminal of the second resistor R2 is equal to the first reference voltage Vref1, and realizing that the first operational amplifier AMP1 outputs a constant first bias voltage Vgate1.

[0116] Similarly, when the second switch S2 is turned on, the third transistor M3, the fourth resistor R4, and the second operational amplifier AMP2 form a negative feedback network, and together with the power transistor Md and the first resistor R1, they form a mirror LDO circuit 100. When the voltage input at the positive voltage terminal VDD changes, the voltage at the terminal of the fourth resistor R4 increases or decreases. At this time, the second operational amplifier AMP2 performs negative feedback regulation, thereby outputting a changing gate voltage, changing the current on the fourth resistor R4, and finally realizing that the voltage at the terminal of the fourth resistor R4 is equal to the second reference voltage Vref2, and realizing that the second operational amplifier AMP2 outputs a constant second bias voltage Vgate2.

[0117] The first reference voltage Vref1 may be equal to or unequal to the second reference voltage Vref2, and the second resistor R2 and the fourth resistor R4 may be equal to or unequal. In order to achieve different bias voltage outputs, at least one of the reference voltages and resistors of the two bias voltage generating circuits must have different parameters.

[0118] Due to factors such as testing, power supply fluctuations, process offsets, and load current drift, a bias voltage generating circuit composed of a single resistor and a single transistor may not be able to meet the output requirements caused by these variations. The magnitude of the bias voltage output may change, and a constant bias voltage cannot be output. Therefore, in an optional embodiment, such as... Figure 10 As shown, the first bias voltage generating circuit 21 further includes:

[0119] Multiple first branches 211 are connected in parallel between the drain and source of the first transistor M1. Each first branch 211 includes a second transistor M2 and a third switch S3 connected sequentially between the drain and source of the first transistor M1. The gates of the multiple second transistors M2 are connected to the gate of the first transistor M1. The multiple third switches S3 are triggered to be turned on or off by the first switch selection signal bit0.

[0120] Multiple second branches 212 are connected in parallel across the second resistor R2. Each second branch 212 includes a fourth switch S4 and a third resistor R3 connected in sequence across the second resistor R2. The multiple fourth switches S4 are turned on or off by the corresponding second selection signal bit1.

[0121] In this embodiment, the second transistor M2 is an NMOS transistor. When a parameter change causes a change in the output of the first bias voltage Vgate1, the first switch selection signal bit0 is output to change the number of second transistors M2 connected in parallel with the first transistor M1, thereby changing the overall equivalent impedance of the first transistor M1 and the second transistor M2, thus changing the terminal voltage of the second resistor R2, and changing the magnitude of the output first bias voltage Vgate1.

[0122] And / or, output the second selection signal bit1 to change the number of third resistors R3 connected in parallel with the second resistor R2, thereby changing the overall impedance of the second resistor R2 and the third resistor R3, thereby changing the terminal voltage of the second resistor R2, and changing the magnitude of the output first bias voltage Vgate1, realizing the fine-tuning output of the first bias voltage Vgate1, so that the first bias voltage Vgate1 is stabilized at the initial set value, satisfying the constant voltage output.

[0123] Similarly, when different values ​​of the first bias voltage Vgate1 need to be output, the voltage across the second resistor R2 and the value of the output first bias voltage Vgate1 can be changed by altering the number of parallel connections of the second transistor M2 and the third resistor R3.

[0124] Correspondingly, such as Figure 11 As shown, in an optional embodiment, the second bias voltage generating circuit 22 further includes:

[0125] Multiple third branches 221 are connected in parallel between the drain and source of the third transistor M3. Each third branch 221 includes a fourth transistor M4 and a fifth switch S5 connected in sequence between the drain and source of the third transistor M3. The gates of the multiple fourth transistors M4 are connected to the gate of the third transistor M3. The multiple fifth switches S5 are turned on or off by the corresponding trigger of the third selection signal bit2.

[0126] Multiple second branches 212 are connected in parallel across the fourth resistor R4. Each second branch 212 includes a sixth switch S6 and a fifth resistor R5 connected sequentially across the fourth resistor R4. The multiple sixth switches S6 are turned on or off by the corresponding trigger of the fourth selection signal bit3.

[0127] In this embodiment, the fourth transistor is an NMOS transistor. When the parameter changes cause the output of the first bias voltage Vgate1 to change, the third selection signal bit2 is output to change the number of fourth transistors M4 connected in parallel with the third transistor M3, thereby changing the overall equivalent impedance of the third transistor M3 and the fourth transistor M4, thereby changing the terminal voltage of the fourth resistor R4, and changing the magnitude of the output second bias voltage Vgate2.

[0128] And / or, output the fourth selection signal bit3 to change the number of fifth resistors R5 connected in parallel with the fourth resistor R4, thereby changing the overall impedance of the fourth resistor R4 and the fifth resistor R5, thus changing the terminal voltage of the fourth resistor R4, and changing the magnitude of the output second bias voltage Vgate2, realizing the fine-tuning output of the second bias voltage Vgate2, so that the second bias voltage Vgate2 is stabilized at the initial set value, satisfying the constant voltage output.

[0129] Similarly, when different sizes of the second bias voltage Vgate2 need to be output, the voltage across the fourth resistor R4 and the size of the output second bias voltage Vgate2 can be changed by changing the number of parallel connections of the fourth transistor M4 and the fifth resistor R5.

[0130] The beneficial effects of the present invention embodiment compared with the prior art are as follows: The above-mentioned mirror LDO circuit 100 is connected by a driving circuit 10, a bias voltage circuit 20 and a state feedback circuit 30. When the mirror LDO circuit 100 is working in the first working state, the state feedback circuit 30 outputs a first trigger signal to trigger the bias voltage circuit 20 to output a first bias voltage Vgate1. When the mirror LDO circuit 100 is working in the second working state, the state feedback circuit 30 outputs a second trigger signal to trigger the bias voltage circuit 20 to output a second bias voltage Vgate2. After receiving the first bias voltage Vgate1, the driving circuit 10 maintains the output of the first load current. After receiving the second bias voltage Vgate2, the driving circuit 10 maintains the output of the second load current and maintains the output voltage of the driving circuit 10 at a preset voltage, thereby achieving constant voltage output and preventing the output voltage Vo of the mirror LDO circuit 100 from fluctuating, thereby improving the working stability and reliability of the mirror LDO circuit 100.

[0131] This invention also proposes an image sensor, which includes a load circuit 200 and a mirror LDO circuit 100. The specific structure of the mirror LDO circuit 100 is as described in the above embodiments. Since this image sensor adopts all the technical solutions of all the above embodiments, it has at least all the beneficial effects brought about by the technical solutions of the above embodiments, and will not be described in detail here. The load circuit 200 is connected to the mirror LDO circuit 100.

[0132] The above-described embodiments are only used to illustrate the technical solutions of the present invention, and are not intended to limit it. Although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of the present invention, and should all be included within the protection scope of the present invention.

Claims

1. A mirrored LDO circuit, characterized by, The mirror LDO circuit works in a first working state of outputting a first load current or a second working state of outputting a second load current, the first load current being greater than the second load current; The mirror LDO circuit comprises: A driving circuit comprising a power tube and a first resistor connected in sequence between a positive voltage terminal and a ground terminal, a connection node of the power tube and the first resistor constituting an output terminal of the mirror LDO circuit and being used for outputting a driving power to a load circuit, the power tube receiving a bias voltage to generate a load current; A bias voltage circuit connected with a control terminal of the power tube, the bias voltage circuit being triggered to output a first bias voltage by a first trigger signal and to output a second bias voltage by a second trigger signal, an absolute value of the first bias voltage being greater than an absolute value of the second bias voltage; A state feedback circuit connected with the bias voltage circuit, the state feedback circuit being used for detecting a state of the load circuit and outputting the first trigger signal when detecting that the mirror LDO circuit is in the first working state and outputting the second trigger signal when detecting that the load circuit is in a second working state.

2. The mirrored LDO circuit of claim 1, wherein, The bias voltage circuit comprises: A first bias voltage generating circuit used for generating the first bias voltage; A second bias voltage generating circuit used for generating the second bias voltage; A switch switching circuit connected with the first bias voltage generating circuit, the second bias voltage generating circuit, the power tube and the state feedback circuit respectively, the switch switching circuit being triggered to connect the first bias voltage generating circuit and the power tube by the first trigger signal and to connect the second bias voltage generating circuit and the power tube by the second trigger signal.

3. The mirrored LDO circuit of claim 2, wherein, The switch switching circuit comprises: A first switch connected between the first bias voltage generating circuit and a control terminal of the power tube, a control terminal of the first switch being connected with the state feedback circuit, the first switch being triggered to turn on by the first trigger signal and to turn off by the second trigger signal, the first trigger signal and the second trigger signal being opposite level signals; A second switch connected between the second bias voltage generating circuit and the control terminal of the power tube, a control terminal of the second switch being connected with the state feedback circuit, the second switch being triggered to turn on by the second trigger signal and to turn off by the first trigger signal.

4. The mirrored LDO circuit of claim 3, wherein, The mirror LDO circuit further comprises: A delay output circuit connected with the state feedback circuit, the first switch and the second switch respectively, the delay output circuit being used for delaying output of the first trigger signal and the second trigger signal to the first switch and the second switch.

5. The mirrored LDO circuit of claim 4, wherein, The first switch comprises a first transmission gate connected between the first bias voltage generating circuit and the control terminal of the power tube, the first transmission gate comprising a first NMOS tube and a first PMOS tube connected in parallel; The second switch comprises a second transmission gate connected between the second bias voltage generating circuit and the control end of the power tube, the second transmission gate comprises a second NMOS tube and a second PMOS tube connected in parallel, the gate of the first NMOS tube is connected with the gate of the second PMOS tube to form a first control end, and the gate of the first PMOS tube is connected with the gate of the second NMOS tube to form a second control end; The delay output circuit comprises: a delay circuit connected between the state feedback circuit and the second control end, the delay circuit being configured to delay a received trigger signal for a preset time length and output; an inverter circuit connected between the state feedback circuit and the first control end, the inverter circuit being configured to perform inverting conversion on a received trigger signal and output.

6. The mirrored LDO circuit of claim 5, wherein, The delay circuit comprises a delay timer, and the input end and the output end of the delay timer form the input end and the output end of the delay circuit respectively.

7. The mirrored LDO circuit of claim 5, wherein, The inverter circuit comprises an inverter, and the input end and the output end of the inverter form the input end and the output end of the inverter respectively.

8. The mirrored LDO circuit of claim 2, wherein, The first bias voltage generating circuit comprises a first transistor, a second resistor and a first operational amplifier; the drain of the first transistor is connected to a positive voltage end, the gate of the first transistor is connected to the output end of the first operational amplifier, the source of the first transistor, the second resistor and the inverting input end of the first operational amplifier are connected, the second end of the second resistor is grounded, and the non-inverting input end of the first operational amplifier is configured to input a first reference voltage.

9. The mirrored LDO circuit of claim 8, wherein, The first bias voltage generating circuit further comprises: a plurality of first branches connected in parallel between the drain and the source of the first transistor, the first branch comprising a second transistor and a third switch connected in sequence between the drain and the source of the first transistor, the gates of the plurality of second transistors being connected with the gate of the first transistor, and the plurality of third switches being triggered to be turned on or turned off by a first switch selection signal; a plurality of second branches connected in parallel across the second resistor, the second branch comprising a fourth switch and a third resistor connected in sequence across the second resistor, and the plurality of fourth switches being triggered to be turned on or turned off by a second switch selection signal.

10. The mirrored LDO circuit of claim 2, wherein, The second bias voltage generating circuit comprises a third transistor, a fourth resistor and a second operational amplifier; the drain of the third transistor is connected to a positive voltage end, the gate of the third transistor is connected to the output end of the second operational amplifier, the source of the third transistor, the fourth resistor and the inverting input end of the second operational amplifier are connected, the second end of the fourth resistor is grounded, and the non-inverting input end of the second operational amplifier is configured to input a second reference voltage.

11. The mirrored LDO circuit of claim 10, wherein, The second bias voltage generating circuit further comprises: A plurality of third branches connected in parallel between the drain and the source of the third transistor, the third branch comprising a fourth transistor and a fifth switch connected in sequence between the drain and the source of the third transistor, the gates of the plurality of fourth transistors being connected to the gate of the third transistor, the plurality of fifth switches being triggered on or off by a third switch selection signal; A plurality of fourth branches connected in parallel across the fourth resistor, the fourth branch comprising a sixth switch and a fifth resistor connected in sequence across the fourth resistor, the plurality of sixth switches being triggered on or off by a fourth switch selection signal.

12. An image sensor, comprising: A load circuit and a mirror LDO circuit as claimed in any one of claims 1 to 11, the load circuit being connected to the mirror LDO circuit.

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