Reset control method and system
By introducing a reset control management module, the target functional modules are controlled to perform preprocessing operations, which solves the problems of system instability and data loss caused by reset operations. This enables collaborative processing of each module before reset, ensuring system stability and data integrity.
Patent Information
- Application Number
- CN202511695387.1
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-11-18
- Publication Date
- 2026-03-10
AI Technical Summary
In modern complex system-on-a-chip designs, reset operations may lead to functional malfunctions, data corruption, or communication deadlocks. Existing technologies lack hardware-level coordination for service convergence and state preservation of various modules before a reset, resulting in the loss of critical data.
A reset control management module is introduced. By sending a preprocessing request signal, the target functional module performs preprocessing operations and sends back a response signal. The reset control management module determines whether the preset reset conditions are met before sending a reset signal, ensuring that each module completes the reset in a stable state.
At the hardware level, it prevents critical data transaction interruptions and bus access timeouts, ensuring system stability and data integrity, and improving the safety and reliability of reset operations.
Smart Images
Figure CN121635645A_ABST
Abstract
Description
TECHNICAL FIELD
[0001] The present application relates to the technical field of integrated circuits, in particular to a reset control method and system. BACKGROUND
[0002] In modern complex system-on-chip design, adopting multi-power domain and multi-reset domain architecture has become a basic technology for realizing fine power management, functional safety isolation and hardware modularized debugging. This architecture supports independent local reset for specific functional blocks without restarting the entire chip. However, when performing a reset operation on a certain reset domain, it may cause functional disorder, data corruption or communication deadlock through the system bus. In view of this, in the related art, after receiving an internal or external reset request, the central reset generator directly broadcasts a reset signal to the target circuit after simple synchronization processing. This reset method forcibly resets all logic units in the domain within a very short time, regardless of the current transaction state of each module, which is likely to cause the ongoing memory write operation to be interrupted, causing write data conflicts and critical data loss. Therefore, how to ensure data safety after reset is a problem to be solved. SUMMARY
[0003] Therefore, the present application provides a reset control method and system to solve the problem of data loss after reset.
[0004] In a first aspect, the present application provides a reset control method applied to a reset control system, wherein the reset control system at least includes a reset control management module and a target functional module. The method includes the following steps: The reset control management module sends a preprocessing request signal to the target functional module in response to a reset request; The target functional module performs a preset preprocessing operation in response to the preprocessing request signal, and sends a first response signal to the reset control management module after the preset preprocessing operation is completed; The reset control management module judges whether all target functional modules meet a preset reset condition in response to the first response signal; If all target functional modules meet the preset reset condition, the reset control management module sends a reset signal to all target functional modules, and the target functional module performs a reset operation in response to the reset signal.
[0005] In an optional embodiment, if the target functional module is a random access memory, the preset preprocessing operation includes the following steps: The target functional module invalidates a write enable signal in response to the preprocessing request signal, and activates a bus reply function to return a second response signal to a received bus access request.
[0006] In an optional implementation, if the target functional module includes a non-random access memory, the step of performing a preset preprocessing operation includes: The target functional module stops receiving new service requests and processes the service requests that have already been received.
[0007] In one optional implementation, the step of performing the preset preprocessing operation further includes: If the target functional module receives a new bus access request, it returns a third response signal, which includes at least an error response or an empty response.
[0008] In one optional implementation, if all the target functional modules meet the preset reset conditions, the reset control management module sends a reset signal to all the target functional modules, including: If the response status register of the reset control management module shows that all target functional modules have returned the first response signal, then it is determined that all target functional modules meet the preset reset conditions, and the reset control management module sends a reset signal to all target functional modules; the response status register is used to store the first response signal sent by the target functional modules.
[0009] In one optional implementation, if all the target functional modules meet the preset reset conditions, the reset control management module sends a reset signal to all the target functional modules, including: Determine whether the maximum response time of the target functional module is greater than or equal to the preset time. The maximum response time represents the time from when the reset control management module sends the preprocessing request signal to when it receives the first response signal from all the target functional modules. If the maximum response time is greater than or equal to the preset time, then all the target functional modules are determined to meet the preset reset conditions, and the reset control management module sends a reset signal to all the target functional modules.
[0010] In an optional implementation, after the reset control management module sends a reset signal to all the target functional modules, the method further includes: The reset control management module clears its internal state.
[0011] In a second aspect, the present invention provides a reset control system, the reset control system being used to execute the reset control method described in the first aspect or any corresponding embodiment thereof, the reset control system comprising: A reset control management module, comprising a preprocessing signal sending unit, a reset condition judgment unit, and a reset signal output unit; The preprocessing signal sending unit is used to send a preprocessing request signal to the target functional module in response to a reset request; the reset condition judging unit is used to judge whether all the target functional modules meet the preset reset condition in response to the first response signal; the reset signal output unit is used to send a reset signal to all the target functional modules if all the target functional modules meet the preset reset condition. The target function module is connected to the reset control management module, and the target function module includes a preprocessing execution unit, a response signal feedback unit, and a reset execution unit. The preprocessing execution unit is used to perform a preset preprocessing operation in response to the preprocessing request signal, and send a first response signal to the reset control management module after the preset preprocessing operation is completed; the response signal feedback unit is used to send a first response signal to the reset control management module after the preset preprocessing operation is completed; the reset execution unit is used to perform a reset operation in response to the reset signal.
[0012] In an optional implementation, if the target functional module is a random access memory, the preprocessing execution unit includes a first execution subunit, which is configured to, in response to the preprocessing request signal, set the write enable signal to an invalid state and activate the bus response function to return a second response signal to the received bus access request.
[0013] In one optional implementation, if the target functional module includes a non-random access memory, the preprocessing execution unit includes a second execution subunit, which is used to stop receiving new service requests and process the already received service requests.
[0014] The reset control method and reset control system provided in this embodiment include: a reset control management module responding to a reset request by sending a preprocessing request signal to a target functional module; the target functional module responding to the preprocessing request signal by performing a preset preprocessing operation and sending a first response signal to the reset control management module after the preset preprocessing operation is completed; the reset control management module responding to the first response signal by determining whether all target functional modules meet preset reset conditions; if all target functional modules meet the preset reset conditions, the reset control management module sends a reset signal to all target functional modules, and the target functional modules responding to the reset signal by performing a reset operation. This method introduces a reset control management module to control the target functional modules to perform preset preprocessing operations before a formal reset, thereby ensuring at the hardware level that the reset operation will not interrupt critical data transactions or cause bus access timeouts. Simultaneously, by ensuring that the target functional modules meet the preset reset conditions, the reset control management module sends a reset signal to all target functional modules, ensuring that the reset operation can be completed under normal collaborative conditions among the target functional modules, guaranteeing both system stability and data integrity. Attached Figure Description
[0015] To more clearly illustrate the specific embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the specific embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of the present invention. For those skilled in the art, other drawings can be obtained from these drawings without creative effort.
[0016] Figure 1 This is a flowchart illustrating the reset control method according to an embodiment of the present invention; Figure 2 This is a schematic diagram of a reset control system according to an embodiment of the present invention; Figure 3 This is a schematic diagram of the control logic state machine of the reset control management module according to an embodiment of the present invention; Figure 4 This is a schematic diagram of the hardware structure of an electronic device according to an embodiment of the present invention. Detailed Implementation
[0017] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.
[0018] In modern, complex System-on-a-Chip (SoC) designs, a multi-power-domain and multi-reset-domain architecture is commonly employed. This architecture has become a fundamental technical means for achieving fine-grained power management, functional safety isolation, and modular hardware debugging. This architecture allows for independent power supply control and reset operations on specific functional blocks within the system—a process known as "partial reset" or "hot reset"—without requiring a complete chip reboot. However, this technological advantage also presents significant design challenges: how to ensure that when a reset operation is performed on a specific reset domain, the operation itself does not trigger system-level functional malfunctions, data corruption, or communication deadlocks through shared resources (such as the system bus or memory subsystem). Related reset control schemes have inherent limitations. First, simple synchronous reset mechanisms or reset sequence control schemes with a certain degree of coordination are still considered forced interruptions at the moment the reset takes effect. They lack a hardware-level collaborative preprocessing stage to coordinate service convergence and state saving among modules before a physical reset, making it highly susceptible to interrupting ongoing data transactions and leading to the corruption of critical data. Secondly, software-participatory reset schemes based on bus interaction heavily rely on the normal execution of the processor and the smooth operation of the system bus for their preprocessing, lacking hardware-level determinism and reliability guarantees in the event of system anomalies. Furthermore, decentralized local protection mechanisms, lacking a global perspective and unified scheduling, cannot form a coherent "safety state window" at the system level. In summary, related technologies typically treat reset management as a passive event triggered by a single signal, making it difficult to guarantee system stability and data integrity during reset operations. Based on this, this invention provides a reset control method applied to a reset control system, which includes at least a reset control management module and a target function module. This reset control system is a SoC (System-on-a-Chip) system.
[0019] According to an embodiment of the present invention, a reset control method embodiment is provided. It should be noted that the steps shown in the flowchart in the accompanying drawings can be executed in a computer system such as a set of computer-executable instructions. Furthermore, although a logical order is shown in the flowchart, in some cases, the steps shown or described may be executed in a different order than that shown here.
[0020] This embodiment provides a reset control method applied to a reset control system, which includes at least a reset control management module and a target function module. Figure 1 This is a flowchart of a reset control method according to an embodiment of the present invention, such as... Figure 1 As shown, the process includes the following steps: In step S101, the reset control management module responds to the reset request by sending a preprocessing request signal to the target function module.
[0021] The Reset Control Management (RCM) module is the core module of the reset control system described in this embodiment. It is connected to other target functional modules in the system via a control bus and an acknowledgment bus. The Reset Control Management module is the control center of the system, internally including control logic, a configurable timeout timer, and an acknowledgment status register. The control logic can be implemented by a state machine to manage the state transitions throughout the reset process. The configurable timeout timer is used for timing during the preprocessing phase, and the timeout period can be configured via a register. The acknowledgment status register is a bitmap register, with each bit corresponding to a hardware functional module, used to record its preprocessing completion status.
[0022] When the reset control management module detects a reset request from the watchdog, software write, or other sources, it first switches its internal state from idle to preprocessing state and drives its output port to send a preprocessing request signal (preprocess_req signal) to all pre-configured target function modules via the parallel control bus.
[0023] The target functional module can include RAM (Random Access Memory) and non-RAM (Non-Random Access Memory). For RAM, the reset control management module also issues the ram_write_disable signal (disables write enable) and the ram_proxy_enable signal (enables proxy function). For non-RAM, the reset control management module only issues a preprocessing request signal.
[0024] In step S102, the target function module responds to the preprocessing request signal, performs a preset preprocessing operation, and sends a first response signal to the reset control management module after the preset preprocessing operation is completed.
[0025] Each target functional module's internal preprocessing logic circuit is immediately triggered upon detecting a valid preprocessing request signal. Each module executes a series of predefined hardware operations in parallel according to its own hardware design. For example, random access memory (RAM) will momentarily disable its write enable path via combinational logic and switch its bus interface to acknowledgment mode. Non-RAM will pause instruction fetching or transaction issuance and wait for its internal pipeline to be cleared. When each target functional module confirms through its internal state machine or flags that all preprocessing operations have been completed, it sends a first acknowledgment signal indicating preprocessing completion to the reset control management module via an independent acknowledgment signal line.
[0026] In step S103, the reset control management module responds to the first response signal and determines whether all target function modules meet the preset reset conditions.
[0027] Simultaneously with issuing a preprocessing request signal, the reset control management module starts a configurable hardware timer for timeout monitoring. Subsequently, the reset control management module continuously monitors whether it has received the first response signal from all target functional modules and compares the current count value of the timeout timer with whether it has reached a preset threshold. Both are preset reset conditions; if either is met, the target functional module is considered to have met the preset reset condition.
[0028] Step S104: If all target function modules meet the preset reset conditions, the reset control management module sends a reset signal to all target function modules, and the target function modules respond to the reset signal by performing a reset operation.
[0029] If all target functional modules meet the preset reset conditions, the reset control management module drives the global reset signal output port to send a reset signal to all target functional modules. After receiving the reset signal, the target functional modules forcibly restore all their internal triggers, state machines, and control logic to the initial state defined in the chip design, thereby completing the reset operation.
[0030] The reset control method provided in this embodiment is applied to a reset control system. It includes a reset control management module responding to a reset request by sending a preprocessing request signal to a target functional module; the target functional module responding to the preprocessing request signal by performing a preset preprocessing operation and sending a first response signal to the reset control management module after the preset preprocessing operation is completed; the reset control management module responding to the first response signal by determining whether all target functional modules meet preset reset conditions; if all target functional modules meet the preset reset conditions, the reset control management module sends a reset signal to all target functional modules, and the target functional modules responding to the reset signal perform a reset operation. This method introduces a reset control management module to control the target functional modules to perform preset preprocessing operations before a formal reset, thereby ensuring at the hardware level that the reset operation will not interrupt critical data transactions or cause bus access timeouts. Simultaneously, by ensuring that the target functional modules meet the preset reset conditions, the reset control management module sends reset signals to all target functional modules, ensuring that the reset operation can be completed under normal collaborative conditions among the target functional modules, guaranteeing both system stability and data integrity.
[0031] In some optional implementations, if the target functional module is a random access memory, performing a preset preprocessing operation includes: the target functional module responding to the preprocessing request signal by setting the write enable signal to an invalid state and activating the bus response function to return a second response signal to the received bus access request.
[0032] When the random access memory (RAM) receives a preprocessing request signal from the reset control management module, its internal write enable control logic invalidates the write enable signal leading to the memory cell. For example, it pulls the signal high in a low-active circuit. This operation cuts off the data write path at the hardware level, ensuring that no new write operations are performed during subsequent resets, thus physically preventing data corruption risks caused by reset timing conflicts. Simultaneously, the RAM's internal bus acknowledgment logic is activated. In this state, regardless of whether a read or write request is received, this acknowledgment logic bypasses the normal memory array access process and directly and immediately returns a preset second acknowledgment signal to the bus. For read requests, the second acknowledgment signal can be a pre-defined safe data mode (e.g., returning all zeros or a specific padding value). For write requests, it can return an acknowledgment signal indicating that the operation is complete.
[0033] In this embodiment, the reset control management module disables the write enable of the random access memory during the preprocessing stage, completely cutting off the path for accidental writes to the memory during reset instability at the hardware level. This eliminates the risk of write data conflicts and ensures the security of critical user data and configuration information. Furthermore, the preprocessing stage forcibly enables the proxy response function, ensuring that even during reset preparation, any bus access from non-reset areas receives an immediate and compliant response. This avoids bus timeouts and system-level deadlocks, guaranteeing the continuous and stable operation of other parts of the system.
[0034] In some optional implementations, if the target functional module includes a non-random access memory, performing a preset preprocessing operation includes: the target functional module suspending the reception of new service requests and processing the already received service requests.
[0035] Furthermore, performing the preset preprocessing operation also includes: if the target functional module receives a new bus access request, it returns a third response signal, which includes at least an error response or an empty response.
[0036] Non-random access memory (NRAM) can be a CPU (Central Processing Unit), a DMA (Direct Memory Access) controller, etc. When NRAM receives a preprocessing request signal, its internal hardware state machine immediately triggers business abort logic. This logic controls its front-end pipeline or task scheduler to stop receiving new instructions or transaction requests from upstream, achieving hardware-level abort of new business requests. Simultaneously, transaction clearing logic is activated. This logic ensures that business requests that have entered the module's internal processing pipeline and are marked as received upon receiving a preprocessing request continue execution until completion, thus avoiding state inconsistencies caused by residual incomplete transactions.
[0037] To ensure the stability of the system bus during preprocessing, this module synchronously activates the acknowledgment logic on its bus interface side. Once this logic is activated, the non-random access memory no longer performs substantive processing on any newly arriving bus access requests; instead, the acknowledgment logic directly intercepts and immediately returns a third acknowledgment signal. This third acknowledgment signal is preset at the hardware level to a specific invalid response mode, typically including an error response indicating operation failure or an empty response returning meaningless data. This implementation achieves logical decoupling from the non-reset domain at the physical level, maintaining normal bus activity.
[0038] In some optional implementations, step S104 includes: if the response status register of the reset control management module shows that all target functional modules have returned a first response signal, then it is determined that all target functional modules meet the preset reset conditions, and the reset control management module sends a reset signal to all target functional modules. The response status register is used to store the first response signals sent by the target functional modules.
[0039] The reset control management module internally includes an acknowledgment status register with a bit width corresponding to the number of target functional modules. Each binary bit of this register is fixedly mapped to a specific target functional module via hardware wiring, used to latch and display the status of its first acknowledgment signal in real time. When a target functional module returns its first acknowledgment signal, its corresponding register bit is automatically set by hardware. During the preprocessing stage, the control logic within the reset control management module continuously polls or monitors the value of the acknowledgment status register in real time through combinational logic circuits. When the monitoring logic detects that all bits configured to require acknowledgment in the register have been set, i.e., their values match a preset full acknowledgment mask value, it generates a valid full acknowledgment ready flag signal. This flag signal directly drives the state machine of the reset control management module to immediately jump from the waiting acknowledgment state to the triggered reset state, and sets its global reset signal drive port to an active level, thereby broadcasting the final physical reset signal to all target functional modules.
[0040] In some optional implementations, step S104 includes: determining whether the maximum response time of the target functional module is greater than or equal to a preset time, wherein the maximum response time represents the time from when the reset control management module sends a preprocessing request signal to when it receives the first response signal from all target functional modules; if the maximum response time is greater than or equal to the preset time, then it is determined that all target functional modules meet the preset reset conditions, and the reset control management module sends a reset signal to all target functional modules.
[0041] The reset control management module integrates a configurable timeout timer. This timeout timer automatically starts counting in the same clock cycle as the reset control management module sends a preprocessing request signal. Simultaneously, the response status register within the reset control management module continuously monitors the feedback status of the first response signals from all target functional modules. The control logic compares the timer's current count value with a preset duration stored in the configuration register. When the circuit detects that the timer count value is greater than or equal to the preset duration (i.e., the maximum response duration is greater than or equal to the preset duration), it determines that all target functional modules meet the preset reset conditions and drives the state machine to switch to the reset trigger state to send reset signals to all target functional modules.
[0042] In some optional implementations, after step S104 above, the method further includes: resetting the control management module to clear its internal state.
[0043] After the reset is complete, the reset control management returns to the idle state, clears all internal states, and waits for the next reset request.
[0044] This invention designs differentiated preprocessing strategies for the hardware characteristics of random access memory (RAM) and non-RAM, thereby achieving targeted optimal protection while ensuring security and balancing the processing efficiency of different modules. This method ensures that a partial reset operation does not affect other parts of the system, making online debugging, fault isolation, and system recovery safer and more convenient. Specific functional domains can be reset without worrying about causing a system-wide crash, thus improving chip development efficiency and reliability during operation and maintenance.
[0045] This invention also provides a reset control system, which includes: a reset control management module; and a target function module connected to the reset control management module. Figure 2 This is a schematic diagram of a reset control system. The master device includes components such as the CPU and DMA, while slave devices may include peripheral controllers, specific registers, and other modules that respond to requests from the master device. The reset control management module is connected to other target function modules via a control bus and an acknowledgment bus. Mem write isolation means that during the reset preprocessing stage, all write paths to memory are forcibly cut off through hardware logic; Mem read acknowledgment means that after memory is isolated, read requests to that memory are taken over.
[0046] The reset control management module first commands the relevant modules to disable write enable, physically blocking write operations. It then activates the response function of each module (RAM), providing an immediate response to any access request and maintaining bus activity. Bus decoupling means logically disconnecting the modules within the target reset domain from the system bus, achieving isolation and ensuring that the reset operation does not affect other normally functioning modules. Finally, it suspends non-RAM hardware functional modules, i.e., pauses the operation of non-RAM, allowing them to enter a static state after completing their current task.
[0047] Figure 3 This is a schematic diagram of the control logic state machine of the reset control management module. The idle state represents the initial and steady state of the reset control management module, in which it waits for a reset request. Upon receiving a reset request, the reset control management module sends a preprocessing request signal to the target function module. Simultaneously, the reset control management module starts its internal configurable timeout timer to monitor the response signals from each module. If the reset control management module receives responses from all target function modules, it indicates that all target function modules have completed preprocessing and responded with response signals. At this point, a reset signal is issued, and the target function module responds by performing a reset operation. After issuing the reset signal, the state machine automatically transitions back to the idle state, waiting for the next reset request, thus forming a complete closed-loop control.
[0048] In some alternative implementations, the reset control system includes: A reset control management module, comprising a preprocessing signal sending unit, a reset condition judgment unit, and a reset signal output unit; The preprocessing signal sending unit is used to send a preprocessing request signal to the target functional module in response to a reset request; the reset condition judging unit is used to judge whether all the target functional modules meet the preset reset condition in response to the first response signal; the reset signal output unit is used to send a reset signal to all the target functional modules if all the target functional modules meet the preset reset condition. The target function module is connected to the reset control management module, and the target function module includes a preprocessing execution unit, a response signal feedback unit, and a reset execution unit. The preprocessing execution unit is used to perform a preset preprocessing operation in response to the preprocessing request signal, and send a first response signal to the reset control management module after the preset preprocessing operation is completed; the response signal feedback unit is used to send a first response signal to the reset control management module after the preset preprocessing operation is completed; the reset execution unit is used to perform a reset operation in response to the reset signal.
[0049] In some optional implementations, if the target functional module is a random access memory, the preprocessing execution unit includes a first execution subunit, which is used to respond to the preprocessing request signal by setting the write enable signal to an invalid state and activating the bus response function to return a second response signal to the received bus access request.
[0050] In some optional implementations, if the target functional module includes a non-random access memory, the preprocessing execution unit includes a second execution subunit, which is used to stop receiving new service requests and process the already received service requests.
[0051] This invention also provides an electronic device having the above-described reset control system.
[0052] Please see Figure 4 , Figure 4 This is a schematic diagram of the structure of an electronic device provided in an optional embodiment of the present invention, such as... Figure 4 As shown, the electronic device includes one or more processors 10, memory 20, and interfaces for connecting the components, including high-speed interfaces and low-speed interfaces. The components communicate with each other via different buses and can be mounted on a common motherboard or otherwise as required. The processors can process instructions executed within the electronic device, including instructions stored in or on memory to display graphical information of a GUI on external input / output devices (such as display devices coupled to the interfaces). In some alternative implementations, multiple processors and / or multiple buses can be used with multiple memories and multiple memory modules, if desired. Similarly, multiple electronic devices can be connected, each providing some of the necessary operations (e.g., as a server array, a group of blade servers, or a multiprocessor system). Figure 4 Take a processor 10 as an example.
[0053] Processor 10 may be a central processing unit, a network processor, or a combination thereof. Processor 10 may further include a hardware chip. The hardware chip may be an application-specific integrated circuit (ASIC), a programmable logic device (PLD), or a combination thereof. The programmable logic device may be a complex programmable logic device (CAMP), a field-programmable gate array (FPGA), a general-purpose array logic (GDA), or any combination thereof.
[0054] The memory 20 stores instructions executable by at least one processor 10 to cause the at least one processor 10 to perform the method shown in the above embodiments.
[0055] The memory 20 may include a program storage area and a data storage area. The program storage area may store the operating system and applications required for at least one function; the data storage area may store data created based on the use of the electronic device. Furthermore, the memory 20 may include high-speed random access memory and may also include non-transitory memory, such as at least one disk storage device, flash memory device, or other non-transitory solid-state storage device. In some alternative embodiments, the memory 20 may optionally include memory remotely located relative to the processor 10, and these remote memories may be connected to the electronic device via a network. Examples of such networks include, but are not limited to, the Internet, intranets, local area networks, mobile communication networks, and combinations thereof.
[0056] The memory 20 may include volatile memory, such as random access memory; the memory may also include non-volatile memory, such as flash memory, hard disk or solid-state drive; the memory 20 may also include a combination of the above types of memory.
[0057] The electronic device also includes a communication interface 30 for communicating with other devices or communication networks.
[0058] This invention also provides a computer-readable storage medium. The methods described above according to embodiments of the invention can be implemented in hardware or firmware, or implemented as computer code that can be recorded on a storage medium, or implemented as computer code downloaded via a network and originally stored on a remote storage medium or a non-transitory machine-readable storage medium and then stored on a local storage medium. Thus, the methods described herein can be processed by software stored on a storage medium using a general-purpose computer, a dedicated processor, or programmable or dedicated hardware. The storage medium can be a magnetic disk, optical disk, read-only memory, random access memory, flash memory, hard disk, or solid-state drive, etc.; further, the storage medium can also include combinations of the above types of memory. It is understood that computers, processors, microprocessor controllers, or programmable hardware include storage components capable of storing or receiving software or computer code, which, when accessed and executed by the computer, processor, or hardware, implements the methods shown in the above embodiments.
[0059] Although embodiments of the invention have been described in conjunction with the accompanying drawings, those skilled in the art can make various modifications and variations without departing from the spirit and scope of the invention, and all such modifications and variations fall within the scope defined by the invention.
Claims
1. A reset control method characterized by comprising: The method is applied to a reset control system, and the reset control system at least comprises a reset control management module and a target function module. The reset control management module sends a preprocessing request signal to the target function module in response to a reset request; The target function module performs a preset preprocessing operation in response to the preprocessing request signal, and sends a first response signal to the reset control management module after the preset preprocessing operation is completed; The reset control management module determines whether all the target function modules meet a preset reset condition in response to the first response signal; If all the target function modules meet the preset reset condition, the reset control management module sends a reset signal to all the target function modules, and the target function module performs a reset operation in response to the reset signal.
2. The reset control method according to claim 1, characterized by, If the target function module is a random access memory, the preset preprocessing operation comprises: The target function module invalidates a write enable signal in response to the preprocessing request signal, and activates a bus reply function to return a second response signal to a received bus access request.
3. The reset control method according to claim 1, characterized by, If the target function module comprises a non-random access memory, the preset preprocessing operation comprises: The target function module suspends receiving a new service request and processes a received service request.
4. The reset control method according to claim 3, characterized by, The preset preprocessing operation further comprises: If the target function module receives a new bus access request, a third response signal is returned, and the third response signal at least comprises an error response or an empty response.
5. The reset control method according to claim 1, wherein If a response state register of the reset control management module shows that all the target function modules return the first response signal, it is determined that all the target function modules meet the preset reset condition, and the reset control management module sends the reset signal to all the target function modules; the response state register is used to store the first response signal sent by the target function module. If the maximum response duration of the target function module is greater than or equal to a preset duration, it is determined that all the target function modules meet the preset reset condition, and the reset control management module sends the reset signal to all the target function modules.
6. The reset control method according to claim 1, wherein After the reset control management module sends the reset signal to all the target function modules, the method further comprises: The reset control management module clears an internal state. The reset control system is used to perform the reset control method in any one of claims 1 to 7, and the reset control system comprises:
7. The reset control method according to claim 1, wherein 8. A reset control system, characterized by, A reset control management module, comprising a preprocessing signal sending unit, a reset condition judging unit and a reset signal output unit; The preprocessing signal sending unit is configured to send a preprocessing request signal to the target function modules in response to a reset request; the reset condition judging unit is configured to judge whether all the target function modules satisfy a preset reset condition in response to the first response signal; and the reset signal output unit is configured to send a reset signal to all the target function modules if all the target function modules satisfy the preset reset condition. A target function module, connected with the reset control management module, comprising a preprocessing execution unit, a response signal feedback unit and a reset execution unit; The preprocessing execution unit is configured to execute a preset preprocessing operation in response to the preprocessing request signal, and send a first response signal to the reset control management module after the preset preprocessing operation ends; the response signal feedback unit is configured to send a first response signal to the reset control management module after the preset preprocessing operation ends; and the reset execution unit is configured to execute a reset operation in response to the reset signal.
9. The reset control system of claim 8, wherein, If the target function module is a random access memory, the preprocessing execution unit comprises a first execution subunit configured to disable a write enable signal and activate a bus reply function in response to the preprocessing request signal, so as to return a second response signal to a received bus access request.
10. The reset control system of claim 8, wherein If the target function module comprises a non-random access memory, the preprocessing execution unit comprises a second execution subunit configured to suspend receiving a new service request and process a received service request.