Chip, server single board, server cabinet, display system and display method

Abstract

The invention provides a chip, a server single board, a server cabinet, a display system and a display method, and relates to the technical field of computers, the chip comprises a plurality of graphic processing modules, a display interface and a switching module, and the display interface and the plurality of graphic processing modules are connected with the switching module. The graphic processing modules output system picture data of the hosts connected with the graphic processing modules to the switching module, and the switching module selects the graphic processing module corresponding to the target host from the graphic processing modules and conducts a transmission channel between the graphic processing module corresponding to the target host and the display interface. The switching module is used for switching the target host to output the system picture data of the graphic processing module corresponding to the target host to the display interface, and the display interface outputs the system picture data received from the switching module so as to display the system picture of the target host. Different system pictures can be switched and displayed by using one chip, an external KVM switcher is not needed, logic switching can be completed in the chip, the cost is reduced, and resources are saved.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of computers, and in particular to a chip, a server single board, a server cabinet, a display system and a display method. BACKGROUND

[0002] A board management controller (BMC) chip is a chip deployed in a computing device. The BMC chip can manage a master chip in the computing device as a management chip, or the BMC chip itself can control as a master chip in the computing device.

[0003] In related technologies, a BMC chip includes a graphics processing module and a display interface. The graphics processing module is connected to an operating system, and the display interface is connected to a display device. The operating system provides system picture data to the graphics processing module. The graphics processing module transmits the system picture data to the display interface, which outputs the system picture data to the display device. The display device presents a system picture of the operating system based on the system picture data.

[0004] However, in the above method, if it is desired to switch and display two different system pictures on the same display device, two BMC chips need to be deployed. A keyboard video and mouse (KVM) switch is deployed between the display interfaces of the two BMC chips and the display device. The KVM switch is used to control the display device to display the system picture data output by the display interface of which BMC chip. However, this method has a high cost. SUMMARY

[0005] The present application provides a chip, a server single board, a server cabinet, a display system and a display method. Different system pictures can be switched and displayed by one chip, which can reduce costs and save resources. The technical solution is as follows:

[0006] In a first aspect, the present application provides a chip, wherein the chip includes a plurality of graphics processing modules, a display interface and a switching module. The plurality of graphics processing modules are connected to the display interface. The display interface and the plurality of graphics processing modules are connected to the switching module.

[0007] The plurality of graphics processing modules are respectively connected to a plurality of hosts, and are configured to output system picture data of the respective connected hosts to the switching module.

[0008] The switching module is configured to select, in response to a switching instruction, a graphic processing module corresponding to a target host from the plurality of graphic processing modules, and turn on a transmission path between the graphic processing module corresponding to the target host and the display interface, so as to output system picture data of the graphic processing module corresponding to the target host to the display interface, wherein the target host is a host corresponding to a system picture to be displayed.

[0009] The display interface is configured to output the system picture data received from the switching module.

[0010] In the chip, the plurality of graphic processing modules in the chip share one display interface, and the switching module can switch the system picture data output by which graphic processing module to provide to the display interface, and then the display interface outputs the system picture data to display the corresponding system picture. Therefore, only one chip is used to switch and display different system pictures, and there is no need to externally connect a KVM switch, and the switching logic can be completed in the chip, thereby reducing the cost and saving resources. Moreover, there is no need to deploy one display interface for each graphic processing module, thereby saving the number of display interfaces, reducing the cost of the chip, and saving the chip space.

[0011] Optionally, the switching module comprises a first multiplexer group and a control unit, and the plurality of graphic processing modules, the control unit and the display interface are connected with the first multiplexer group.

[0012] The control unit is configured to control the first multiplexer group to output, in response to the switching instruction, the system picture data from the graphic processing module indicated by the control unit to the display interface.

[0013] The first multiplexer group can select one path from multiple input paths as an output path, and the control unit can control the first multiplexer group to output which path of the system picture data, thereby dynamically switching which graphic processing module outputs the system picture data to the first multiplexer group, and facilitating to improve the flexibility and switching speed of the switching display picture.

[0014] Optionally, the first multiplexer group comprises a first multiplexer and a second multiplexer, the plurality of graphic processing modules and the control unit are connected with the first multiplexer, and the first multiplexer, the control unit and the display interface are connected with the second multiplexer.

[0015] The control unit is configured to instruct the first multiplexer to output, in response to the switching instruction, the system picture data received from the graphic processing module corresponding to the target host.

[0016] The control unit is further configured to instruct the second multiplexer to output preset system picture data if the phase-locked loop is not configured, and instruct the second multiplexer to output the system picture data received from the first multiplexer if the phase-locked loop is configured, the phase-locked loop being configured to provide a clock signal to the plurality of graphic processing modules;

[0017] The first multiplexer is configured to output the system picture data indicated by the control unit from the received system picture data to the second multiplexer.

[0018] The second multiplexer is configured to output the system picture data indicated by the control unit from the received system picture data to the display interface.

[0019] The control unit can control the first multiplexer to output the system picture data of which graphic processing module, and the control unit can control the second multiplexer to output preset system picture data or the system picture data of which graphic processing module. In the display switching process, the preset system picture data is outputted by the second multiplexer to display the preset system picture, so as to avoid the problem of display mura caused by the disorder of system picture data in the switching process.

[0020] Optionally, the plurality of graphic processing modules are further configured to output a vertical synchronization signal to the control unit after outputting a frame of system picture data.

[0021] The control unit is configured to instruct the second multiplexer to output the system picture data received from the first multiplexer if the phase-locked loop is configured and the vertical synchronization signal of the graphic processing module corresponding to the target host is received.

[0022] The vertical synchronization signal means that the graphic processing module has outputted a frame of complete system picture data, and will output a next frame of system picture data. When the vertical synchronization signal is detected, the control unit controls the second multiplexer to output the system picture data provided by the graphic processing module, so as to avoid the second multiplexer outputting the residual frame of system picture data, thereby ensuring that the system picture displayed after switching is a frame of complete system picture, and improving the switching display effect.

[0023] Optionally, the chip further comprises a phase-locked loop, the plurality of graphic processing modules are connected with the phase-locked loop, and the phase-locked loop is connected with the switching module.

[0024] The plurality of graphic processing modules are configured to output system picture data to the switching module based on the received clock signal, and output configuration information provided by the respective host to the switching module.

[0025] The switching module is further configured to turn on a transmission path between the target host corresponding graphic processing module and the phase-locked loop, so as to output the configuration information of the target host corresponding graphic processing module to the phase-locked loop.

[0026] The phase-locked loop is configured to receive the configuration information from the switching module, and output a clock signal to the plurality of graphic processing modules.

[0027] The plurality of graphic processing modules in the chip share one phase-locked loop, and the switching module can switch the configuration information output by which graphic processing module to provide to the display interface, so that the phase-locked loop outputs the clock signal required by the graphic processing module, and then the graphic processing module outputs accurate system picture data to display accurate system pictures. Therefore, the display picture needs to be switched to the system picture corresponding to which graphic processing module, and the phase-locked loop is configured based on the configuration information provided by which graphic processing module, thereby realizing the multiplexing of the phase-locked loop, without the need to deploy a phase-locked loop for each graphic processing module, thereby saving the number of phase-locked loops, saving not only resource costs but also chip space.

[0028] Optionally, the switching module comprises a second multiplexer group and a control unit, and the plurality of graphic processing modules, the control unit and the phase-locked loop are connected with the second multiplexer group.

[0029] The control unit is configured to instruct the second multiplexer group to output the configuration information received from the target host corresponding graphic processing module.

[0030] The second multiplexer group is configured to output the configuration information from the graphic processing module instructed by the control unit to the phase-locked loop.

[0031] The second multiplexer group can select one path from multiple input paths as output, and the control unit can control the second multiplexer group to output which path of configuration information, thereby dynamically switching which graphic processing module outputs configuration information to the first multiplexer group, which is conducive to improving the flexibility and switching speed of switching the configuration information of the phase-locked loop.

[0032] Optionally, the second multiplexer group comprises a third multiplexer and a fourth multiplexer, the plurality of graphic processing modules and the control unit are connected with the third multiplexer, and the third multiplexer, the control unit and the phase-locked loop are connected with the fourth multiplexer.

[0033] The control unit is configured to cache the configuration information of the host corresponding graphic processing module, and output the cached configuration information to the fourth multiplexer.

[0034] The control unit is further configured to instruct the third multiplexer to output configuration information received from a graphics processing module corresponding to the target host;

[0035] The control unit is further configured to instruct the fourth multiplexer to output configuration information received from the control unit if the phase-locked loop is not configured, and to output configuration information received from the third multiplexer if the phase-locked loop is configured;

[0036] The third multiplexer is configured to output configuration information indicated by the control unit from the received configuration information to the fourth multiplexer;

[0037] The fourth multiplexer is configured to output configuration information indicated by the control unit from the received configuration information to the phase-locked loop.

[0038] The configuration information of the graphics processing module may change during the configuration process of the phase-locked loop. If the configuration information of the graphics processing module is directly output to the phase-locked loop, the configuration process of the phase-locked loop will be incorrect if the configuration information of the graphics processing module changes during the configuration process. Therefore, the control unit buffers the configuration information of the graphics processing module in the present solution, controls the phase-locked loop to be configured based on the buffered configuration information first, that is, the control unit takes the configuration right of the phase-locked loop, and controls the phase-locked loop to be configured based on the configuration information of the graphics processing module after the configuration is completed, that is, the host takes back the configuration right of the phase-locked loop. In this way, the configuration information provided to the phase-locked loop during the configuration process is a set of accurate and unaltered information, which can improve the orderliness and accuracy of reconfiguring the phase-locked loop and is beneficial to reducing the error rate of the configuration process.

[0039] Optionally, the control unit is configured to output each item in the buffered configuration information to the fourth multiplexer one by one.

[0040] The configuration information includes a plurality of configuration items, and the configuration process of the phase-locked loop is performed step by step. The control unit outputs the plurality of configuration items to the phase-locked loop one by one, and outputs at least one configuration item to the phase-locked loop each time.

[0041] Optionally, the switching module further includes a plurality of configuration units, each of the graphics processing modules is connected with a corresponding configuration unit, and the control unit and the third multiplexer are connected with each of the configuration units.

[0042] The plurality of graphics processing modules are configured to output configuration information before switching starts and configuration information after switching starts to the configuration units connected therewith.

[0043] The control unit is configured to instruct each configuration unit to output configuration information after switching starts if the phase-locked loop configuration is successful.

[0044] The control unit is further configured to instruct each configuration unit to output configuration information before switching starts if the phase-locked loop configuration fails.

[0045] The plurality of configuration units are configured to output, to the third multiplexer, configuration information indicated by the control unit from among the received configuration information.

[0046] After the phase-locked loop configuration is completed, the configuration information cached by the control unit is used by the configured phase-locked loop. If the configuration information provided by the graphics processing module changes during the configuration process, the configuration information obtained by the phase-locked loop will be inconsistent with the currently used configuration information when the configuration right of the phase-locked loop is returned to the host, which will further cause an error. Therefore, in the present scheme, if the phase-locked loop configuration is successful, it indicates that the configuration information of the graphics processing module has not changed, and therefore the configuration information after switching starts is provided to the phase-locked loop. If the phase-locked loop configuration fails, it indicates that the configuration information provided by the graphics processing module has changed, and therefore the configuration information before switching starts is provided to the phase-locked loop. In this way, it can be ensured that the configuration information provided to the phase-locked loop before and after the handover of the configuration right is consistent, thereby completing the seamless handover of the configuration right.

[0047] Optionally, the configuration unit comprises a first register and a fifth multiplexer, and the graphics processing module, the third multiplexer, the control unit and the first register are connected with the fifth multiplexer, and the graphics processing module and the control unit are connected with the first register.

[0048] The graphics processing module is configured to output configuration information before switching starts to the first register and output configuration information after switching starts to the fifth multiplexer.

[0049] The first register is configured to store configuration information received from the graphics processing module and output the stored configuration information to the fifth multiplexer.

[0050] The fifth multiplexer is configured to output, to the third multiplexer, configuration information indicated by the control unit from among the received configuration information.

[0051] The configuration unit is designed to be composed of a first register and a fifth multiplexer corresponding to each graphics processing module. The first register stores configuration information before switching starts of the graphics processing module to realize backup of the configuration information before switching. The control unit controls the fifth multiplexer to output the configuration information before switching or the configuration information after switching, which is conducive to improving the flexibility and switching speed of the output configuration information switching.

[0052] Optionally, the graphics processing module comprises a second register, and the switching module further comprises a third register, and the second register stores configuration information of the graphics processing module;

[0053] The control unit is configured to store the configuration information in the second register into the third register;

[0054] The third register is configured to output the stored configuration information to the fourth multiplexer.

[0055] In the embodiment, the graphics processing module and the switching module have respective registers, and the switching module stores the configuration information in the second register of the graphics processing module into the third register of the switching module, so as to realize the caching of the configuration information of the graphics processing module. On the one hand, the configuration information of the graphics processing module is backed up, so as to prevent the error caused by the change of the configuration information during the switching process. On the other hand, the reading speed of the configuration information is improved.

[0056] Optionally, the switching module is configured to detect the state of the phase-locked loop, and if the phase-locked loop is in a non-configuration state, the transmission path between the graphics processing module corresponding to the target host and the phase-locked loop is turned on, so as to output the configuration information of the graphics processing module corresponding to the target host to the phase-locked loop.

[0057] The phase-locked loop is reconfigured when the phase-locked loop is in the non-configuration state, so as to prevent the original configuration progress of the phase-locked loop from being disturbed when the reconfiguration of the phase-locked loop is started when the phase-locked loop is in the configuration state, and the error rate of the whole process is reduced.

[0058] Optionally, the switching module is configured to, if the phase-locked loop is not configured completely, control the phase-locked loop to output a reference clock signal to the plurality of graphics processing modules.

[0059] The switching module is configured to, if the phase-locked loop is configured completely, control the phase-locked loop to output a clock signal generated after the configuration to the plurality of graphics processing modules.

[0060] The phase-locked loop is reconfigured when the switching is started, and the phase-locked loop cannot output a stable clock signal during the configuration process. Therefore, the reference clock signal is provided to the graphics processing module, so as to ensure the normal processing of the internal processing logic of the graphics processing module. After the configuration is completed, the phase-locked loop can output a stable clock signal, and therefore the stable clock signal is provided to the graphics processing module, so that the graphics processing module generates accurate system picture data based on the accurate clock signal, and the realizability and orderliness of the whole display switching process are ensured.

[0061] Optionally, the switching module comprises a logic circuit and a plurality of registers connected in sequence.

[0062] The logic circuit is used to assign a value to the first register to trigger the first control signal, and in response to the first control signal, to assign a value to the next register connected to the first register to trigger the next control signal; wherein, the control signal is used to connect the transmission path between the graphics processing module corresponding to the target host and the display interface, so as to output the system screen data of the graphics processing module corresponding to the target host to the display interface.

[0063] During the display switching process, the logic circuit triggers control signals by assigning values ​​to registers. The logic circuit then automatically assigns values ​​to the next register based on the control signals to trigger the next control signal, and so on. The logic circuit triggers multiple control signals in sequence, thereby controlling the output of the target host's system screen data to the display interface. This achieves hardware-based display switching. Since the hardware assigns values ​​to registers very quickly, it helps to improve the overall speed of display switching.

[0064] Optionally, the switching module includes a controller and multiple registers;

[0065] The controller is used to run a switching program, which sequentially reads and writes the plurality of registers to trigger a plurality of control signals; wherein, the control signals are used to connect the transmission path between the graphics processing module corresponding to the target host and the display interface, and output the system screen data of the graphics processing module corresponding to the target host to the display interface.

[0066] During the display switching process, registers are read and written sequentially according to the preset instructions in the switching program to trigger control signals, thereby controlling the output of the target host's system screen data to the display interface. This realizes software-based display switching. Because software is configurable, the control logic can be adjusted by changing the code or configuration, thus providing greater flexibility for the display switching control process. This allows the display switching control process to adapt to different scenarios and needs, and makes it easier to achieve customized control methods.

[0067] Optionally, the chip includes a processor, and the plurality of graphics processing modules are all connected to a host on the processor.

[0068] Multiple graphics processing modules within the chip are connected to the internal processor to process the system screen data of the internal processor. In this way, the internal processor can provide the graphics processing modules with a variety of different system screen data, thereby enabling the switching and display of multiple different system screens of the same system. This makes the chip suitable for multi-screen switching application scenarios of the same system.

[0069] Optionally, the chip is connected to multiple main control chips, and the multiple graphics processing modules are respectively connected to a host on one of the main control chips.

[0070] Multiple graphics processing modules in the chip can be connected to processors in other different main control chips. One chip can provide services for multiple different main control chips, enabling switching between system screens of multiple different main control chips. There is no need to deploy separate chips for each main control chip, saving the number of chips, which not only saves resource costs but also saves deployment space.

[0071] Secondly, this application provides a server board, which includes a circuit board and a management chip and a main control chip mounted on the circuit board. The management chip includes multiple graphics processing modules, a display interface, and a switching module. The management chip also includes an interface corresponding to each of the graphics processing modules, which is used to connect the graphics processing module to a host on any of the main control chips. All of the multiple graphics processing modules are connected to the display interface, and both the display interface and the multiple graphics processing modules are connected to the switching module.

[0072] The plurality of graphics processing modules are respectively connected to a plurality of hosts and are used to output the system screen data of the respective hosts to the switching module;

[0073] The switching module is used to respond to a switching command, select the graphics processing module corresponding to the target host from the plurality of graphics processing modules, and connect the transmission path between the graphics processing module corresponding to the target host and the display interface, so as to output the system screen data of the graphics processing module corresponding to the target host to the display interface, wherein the target host is the host corresponding to the system screen to be displayed;

[0074] The display interface is used to output system screen data received from the switching module.

[0075] Thirdly, this application provides a server rack, the server rack including a cabinet body, the cabinet body including a back panel, the server rack also including a plurality of server boards installed on the back panel, the server boards being equipped with a main control chip, the plurality of server boards being equipped with the same management chip, the management chip including a plurality of graphics processing modules, a display interface and a switching module, each of the graphics processing modules being connected to a host on a main control chip; the plurality of graphics processing modules being connected to the display interface, the display interface and the plurality of graphics processing modules being connected to the switching module;

[0076] The plurality of graphics processing modules are respectively connected to a plurality of hosts and are used to output the system screen data of the respective hosts to the switching module;

[0077] The switching module is used to respond to a switching command, select the graphics processing module corresponding to the target host from the plurality of graphics processing modules, and connect the transmission path between the graphics processing module corresponding to the target host and the display interface, so as to output the system screen data of the graphics processing module corresponding to the target host to the display interface, wherein the target host is the host corresponding to the system screen to be displayed;

[0078] The display interface is used to output system screen data received from the switching module.

[0079] Fourthly, this application provides a display system comprising a server rack and a display device. The server rack includes multiple server boards, each server board being equipped with a main control chip. The multiple server boards are equipped with the same management chip. The management chip includes multiple graphics processing modules, a display interface, and a switching module. Each graphics processing module is connected to a host on the main control chip. The display interface is connected to the display device. The multiple graphics processing modules are all connected to the display interface, and both the display interface and the multiple graphics processing modules are connected to the switching module.

[0080] The plurality of graphics processing modules are respectively connected to a plurality of hosts and are used to output the system screen data of the respective hosts to the switching module;

[0081] The switching module is used to respond to a switching command, select the graphics processing module corresponding to the target host from the plurality of graphics processing modules, and connect the transmission path between the graphics processing module corresponding to the target host and the display interface, so as to output the system screen data of the graphics processing module corresponding to the target host to the display interface, wherein the target host is the host corresponding to the system screen to be displayed;

[0082] The display interface is used to output system screen data received from the switching module.

[0083] Fifthly, this application provides a display method applied to a chip, the method comprising:

[0084] Receive system screen data from the first host and system screen data from the second host;

[0085] In response to a display command from a display device, the chip is controlled to output system screen data of the first host to the display device.

[0086] Receive a switching instruction from the display device, the switching instruction being used to switch the display screen of the display device from the system screen of the first host to the system screen of the second host;

[0087] In response to the switching command, the chip is controlled to output the system screen data of the second host to the display device.

[0088] Optionally, the step of controlling the chip to output the system screen data of the second host to the display device in response to the switching command includes:

[0089] In response to the switching command, the phase-locked loop is reconfigured so that the phase-locked loop provides the clock signal for the system screen data of the second host.

[0090] During the configuration process, the control chip outputs preset system screen data to the display device;

[0091] If the phase-locked loop is configured, the control chip outputs the system screen data of the second host to the display device.

[0092] Optionally, if the phase-locked loop configuration is complete, controlling the chip to output the system screen data of the second host to the display device includes:

[0093] If the phase-locked loop is configured and a vertical synchronization signal is detected, the chip is controlled to output the system screen data of the second host to the display device.

[0094] The vertical synchronization signal indicates that a complete frame of system screen data of the second host has been acquired.

[0095] Optionally, the method further includes:

[0096] Receive configuration information from the first host and configuration information from the second host;

[0097] In response to the switching command, the phase-locked loop is configured based on the configuration information of the second host.

[0098] Optionally, the step of configuring the phase-locked loop based on the configuration information of the second host in response to the switching command includes:

[0099] In response to the switching command, the configuration information of the second host is cached, and the phase-locked loop is configured based on the cached configuration information;

[0100] If the phase-locked loop is configured, the phase-locked loop is configured based on the configuration information of the second host.

[0101] Optionally, configuring the phase-locked loop based on the configuration information of the second host includes:

[0102] If the phase-locked loop (PLL) is configured successfully, the PLL is configured based on the configuration information of the second host after the start of the handover. If the PLL configuration fails, the PLL is configured based on the configuration information of the second host before the start of the handover.

[0103] Optionally, the step of configuring the phase-locked loop based on the configuration information of the second host in response to the switching command includes:

[0104] In response to the switching command, the state of the phase-locked loop (PLL) is detected. If the PLL is in a non-configured state, the PLL is configured based on the configuration information of the second host.

[0105] Optionally, the method further includes:

[0106] If the phase-locked loop is not configured, the phase-locked loop is controlled to output a reference clock signal to the graphics processing module;

[0107] If the phase-locked loop is configured, the phase-locked loop is controlled to output the clock signal obtained after configuration to the graphics processing module. Attached Figure Description

[0108] Figure 1 This is a schematic diagram of the structure of a chip provided in an embodiment of this application;

[0109] Figure 2 This is a schematic diagram of another chip structure provided in an embodiment of this application;

[0110] Figure 3 This is a schematic diagram of another chip structure provided in an embodiment of this application;

[0111] Figure 4 This is a schematic diagram of the state transition of a hardware state machine provided in an embodiment of this application;

[0112] Figure 5 This is a system architecture diagram of a display scene provided in an embodiment of this application;

[0113] Figure 6 This is a system architecture diagram of another display scenario provided in an embodiment of this application;

[0114] Figure 7 This is a flowchart of a display method provided in an embodiment of this application. Detailed Implementation

[0115] To make the objectives, technical solutions, and advantages of this application clearer, the embodiments of this application will be further described in detail below with reference to the accompanying drawings. It should be noted that all information (including but not limited to user equipment information, user personal information, etc.), data (including but not limited to data used for analysis, stored data, displayed data, etc.), and signals involved in this application are authorized by the user or fully authorized by all parties, and the collection, use, and processing of related data must comply with the relevant laws, regulations, and standards of the relevant countries and regions. For example, the chips, configuration information, system screen data, etc., involved in this application were all obtained under fully authorized conditions.

[0116] In order to switch the display screen on the same display device, this application relates to a chip that is used to switch which graphics processing module's system screen data is output to the display interface for display via a switching module.

[0117] The structure of the chip in this application is described below.

[0118] Figure 1 This is a schematic diagram of the structure of a chip provided in an embodiment of this application. See also... Figure 1 The chip 10 includes multiple graphics processing modules 11, a display interface 12, and a switching module 13. Each graphics processing module 11 is connected to the display interface 12, and both the display interface 12 and the multiple graphics processing modules 11 are connected to the switching module 13. Each graphics processing module 11 is connected to multiple hosts and is used to output system screen data of its respective host to the switching module 13. The switching module 13, in response to a switching command, selects the graphics processing module 11 corresponding to the target host from among the multiple graphics processing modules 11, establishes the transmission path between the graphics processing module 11 corresponding to the target host and the display interface 12, and outputs the system screen data of the graphics processing module 11 corresponding to the target host to the display interface 12. The target host is the host corresponding to the system screen to be displayed. The display interface 12 is used to output the system screen data received from the switching module 13.

[0119] It should be noted that, for ease of demonstration, Figure 1 Only two graphics processing modules 11 in chip 10 are shown; in reality, chip 10 may include more graphics processing modules 11. Figure 1 No limitations are imposed on this. The following sections will introduce the graphics processing module 11, the switching module 13, and the display interface 12 respectively.

[0120] (1) Graphics processing module 11

[0121] The graphics processing module 11 is a module in chip 10 with graphics processing capabilities. Multiple graphics processing modules 11 in chip 10 are independent of each other, and each graphics processing module 11 outputs different system screen data. Each graphics processing module 11 is connected to a host computer. The graphics processing module 11 provides image data processing functions to the connected host computer; that is, the host computer provides system operation data to the graphics processing module 11, and the graphics processing module 11 generates system screen data based on the system operation data provided by the host computer. This system screen data indicates a system screen that reflects the operation of the host computer, or a system screen generated based on operations performed on the host computer's system.

[0122] Optionally, the host connected to each graphics processing module 11 can be the same or different. Optionally, each graphics processing module 11 has the same structure. Optionally, the graphics processing module 11 can be any computing module with graphics processing capabilities, such as a graphics processing unit (GPU) or a neural processing unit (NPU).

[0123] (2) Switching module 13

[0124] The switching module 13 is a module within the chip 10 that has display switching capabilities. Although the chip 10 includes multiple graphics processing modules 11, and each graphics processing module 11 is connected to the display interface 12 through the switching module 13, during operation, only one graphics processing module 11 has a conductive transmission path to the display interface 12; the other graphics processing modules 11 have non-conductive transmission paths to the display interface 12. A conductive transmission path means that the system screen data output by the graphics processing module 11 can be transmitted to the display interface 12; a non-conductive path means that the system screen data output by the graphics processing module 11 cannot be transmitted to the display interface 12. The switching module 13 switches to make the transmission path between one of the multiple graphics processing modules 11 and the display interface 12 conductive, thereby outputting the system screen data of that graphics processing module 11 to the display interface 12. The switching module 13 can control internally within the chip 10 which graphics processing module 11's system screen data is output to the display interface 12. That is, multiple graphics processing modules 11 share a single display interface 12. At any given time, the display interface 12 can only receive system screen data output by one of the graphics processing modules 11. The switching module 13 can provide the display interface 12 with the system screen data of the graphics processing module 11 corresponding to a host requested by the display device.

[0125] In this embodiment, when the display device requests to switch the currently displayed system screen to the system screen of the target host, the switching module 13 connects the transmission path between the graphics processing module 11 corresponding to the target host and the display interface 12, thereby outputting the system screen data of the graphics processing module 11 corresponding to the target host to the display interface 12.

[0126] (3) Display Interface 12

[0127] The display interface 12 is connected to a display device outside the chip 10 via a wired or wireless means. The display interface 12 is used to transmit the received system screen data to the display device so that the display device can display the system screen based on the system screen data.

[0128] Optionally, the display interface 12 may be composed of at least one type of interface. For example, the display interface 12 may be composed of at least one of the following types of interfaces: a video graphics array (VGA) interface, a low-voltage differential serial signaling (LVDS) interface, a display port (DP), and a network port. The VGA interface is a video transmission standard used to transmit image data to the display device. The LVDS interface is a data transmission and interface technology characterized by low power consumption, low bit error rate, low crosstalk, and low radiation. DP is a protocol used for digital video and audio transmission. The network port serves as a bridge between the chip 10 and an external network, used to send data from the chip 10 to the network.

[0129] The display interface 12 in chip 10 may include one or more of the aforementioned VGA interface, LVDS interface, DP, or Ethernet port. The system screen can be displayed locally via the VGA interface, LVDS interface, or DP. The system screen data is processed by at least one of the VGA interface, LVDS interface, or DP and then sent to the display device via a wired connection. The display device displays the system screen based on the system screen data, thus achieving local display of the system screen. Alternatively, the system screen can be displayed remotely via the Ethernet port. Chip 10 can also deploy a video compression engine (VCE). The VCE compresses the system screen data and sends the compressed system screen data to the network via the Ethernet port. The system screen data is then wirelessly transmitted to the display device via the network. The display device displays the system screen based on the system screen data, thus achieving remote display of the system screen.

[0130] In the aforementioned chip 10, multiple graphics processing modules 11 are deployed, sharing a single display interface 12. A switching module 13 is added to the chip 10, which enables the transmission path between the graphics processing module 11 corresponding to any host and the display interface 12, thereby flexibly controlling which host's system screen data the display interface 12 receives. Therefore, this application uses only one chip 10 to achieve display switching between different system screens without the need for an external KVM switch. The switching logic can be completed internally within the chip 10, reducing display costs and saving resources. Furthermore, the multiple graphics processing modules 11 within the chip 10 can share a single display interface 12, eliminating the need to deploy a separate display interface 12 for each graphics processing module 11. This not only saves on the number of display interfaces 12 and reduces the cost of the chip 10 but also saves space. Moreover, since the chip 10 provides display switching capabilities, it only needs to be connected to one external display device to switch between different system screens, eliminating the need for multiple external display devices and further reducing display costs.

[0131] exist Figure 1 Based on this, the embodiments of this application provide Figure 2 The structural diagram shown below, in conjunction with... Figure 2 The internal structure and working principle of the switching module 13 used for switching system screen data are described below.

[0132] See Figure 2 The switching module 13 includes a first multiplexer group 131 and a control unit 132. Multiple graphics processing modules 11, the control unit 132, and the display interface 12 are all connected to the first multiplexer group 131. The control unit 132, in response to a switching command, controls the first multiplexer group 131 to output the system screen data received from the graphics processing modules 11 as indicated by the control unit 132 to the display interface 12.

[0133] The first multiplexer group 131 is a combinational logic circuit that selects one output from multiple inputs. In this embodiment, the inputs of the first multiplexer group 131 include system screen data output from multiple graphics processing modules 11, and the output of the first multiplexer group 131 is one of the received multiple system screen data. The first multiplexer group 131 can determine which system screen data to output in response to a control signal input to it.

[0134] The control unit 132 controls which system screen data is output by the first multiplexer group 131. The control unit 132 controls the first multiplexer group 131 to switch between multiple different system screen data streams by outputting different control signals to the first multiplexer group 131, thereby dynamically switching the output of the first multiplexer group 131. When the display device requests to switch the currently displayed system screen to the target host's system screen, the control unit 132 responds to the switching command by triggering a control signal for the first multiplexer group 131. This control signal instructs the first multiplexer group 131 to output the system screen data received from the graphics processing module 11 corresponding to the target host. Therefore, after the control unit 132 outputs the control signal to the first multiplexer group 131, the first multiplexer group 131 responds to the control signal by outputting the system screen data indicated by the control signal to the display interface 12, that is, outputting the system screen data received from the graphics processing module 11 corresponding to the target host to the display interface 12, thereby establishing the transmission path between the graphics processing module 11 corresponding to the target host and the display interface 12.

[0135] The above Figure 2 In the chip 10 shown, a first multiplexer group 131 is deployed between the graphics processing module 11 and the display interface 12. The control unit 132 dynamically switches which graphics processing module 11's system screen data is output to the display interface 12 by outputting different control signals to the first multiplexer group 131, thereby dynamically switching which transmission path between the graphics processing module 11 and the display interface 12 is activated, which helps to improve the flexibility and speed of the switching process.

[0136] Optionally, the first multiplexer group 131 includes at least one multiplexer. In one possible implementation, see [link to relevant documentation]. Figure 2 The first multiplexer group 131 includes a first multiplexer and a second multiplexer. Accordingly, multiple graphics processing modules 11 and control unit 132 are connected to the first multiplexer, and the first multiplexer, control unit 132 and display interface 12 are all connected to the second multiplexer.

[0137] In this structure, the control unit 132 is used to, in response to a switching command, instruct the first multiplexer to output system screen data received from the graphics processing module 11 corresponding to the target host; the control unit 132 is also used to, if the phase-locked loop 14 is not configured, instruct the second multiplexer to output preset system screen data, and if the phase-locked loop 14 is configured, instruct the second multiplexer to output system screen data received from the first multiplexer, the phase-locked loop 14 being used to provide clock signals to multiple graphics processing modules 11; the first multiplexer is used to output the system screen data indicated by the control unit 132 in the received system screen data to the second multiplexer; the second multiplexer is used to output the system screen data indicated by the control unit 132 in the received system screen data to the display interface 12.

[0138] The first multiplexer is used to select which graphics processing module 11's system screen data to output. The first multiplexer has multiple inputs, each being system screen data output by one of the graphics processing modules 11. The output of the first multiplexer is one of the received multiple system screen data streams. The first multiplexer can determine which system screen data stream to output in response to a control signal input to it. The first multiplexer is controlled by the control unit 132, which instructs the first multiplexer to output which system screen data stream by outputting different control signals. When the display device requests to switch the currently displayed system screen to the target host's system screen, the control unit 132, in response to the switching command, triggers the control signal of the first multiplexer, which instructs the first multiplexer to output the system screen data received from the graphics processing module 11 corresponding to the target host. Therefore, after the control unit 132 outputs the control signal to the first multiplexer, the first multiplexer responds to the control signal and outputs the system screen data indicated by the control signal to the second multiplexer, that is, it outputs the system screen data received from the graphics processing module 11 corresponding to the target host to the second multiplexer.

[0139] The second multiplexer is used to output system screen data or preset system screen data from the graphics processing module 11 under different conditions. The second multiplexer has two inputs: one is the preset system screen data, and the other is the system screen data output by the first multiplexer. The output of the second multiplexer is either the preset system screen data or the system screen data output by the first multiplexer. The second multiplexer can determine which system screen data to output in response to a control signal input to it. The second multiplexer is also controlled by the control unit 132, which instructs the second multiplexer to output which system screen data by outputting different control signals to it. When the display device requests to switch the currently displayed system screen to the target host's system screen, the control unit 132 needs to configure the phase-locked loop 14 according to the configuration information provided by the target host. This ensures that the phase-locked loop 14 provides the clock signal required by the graphics processing module 11 corresponding to the target host to acquire the system screen data of the target host. If the clock signal output to the graphics processing module 11 is incorrect, the system screen data output by the graphics processing module 11 will be incorrect. When the phase-locked loop 14 is not fully configured, it cannot provide an accurate clock signal to the graphics processing module 11. Only after the phase-locked loop 14 is fully configured can it provide an accurate clock signal to the graphics processing module 11. Therefore, the control process of the control unit 132 for the second multiplexer is divided into a phase where the phase-locked loop 14 is not fully configured and a phase-locked loop 14 is fully configured. During the incomplete configuration phase of phase-locked loop 14, phase-locked loop 14 cannot provide an accurate clock signal to graphics processing module 11. Therefore, the system screen data output by graphics processing module 11 is incorrect. Control unit 132 then instructs the second multiplexer to output the preset system screen data to display interface 12 by outputting a control signal to the second multiplexer. During the complete configuration phase of phase-locked loop 14, phase-locked loop 14 can provide an accurate clock signal to graphics processing module 11. Therefore, the system screen data output by graphics processing module 11 is correct. Control unit 132 then instructs the second multiplexer to output the system screen data received from the first multiplexer to display interface 12, that is, to output the system screen data of the graphics processing module 11 corresponding to the host computer to display interface 12.

[0140] Optionally, the preset system screen data can be any pre-stored system screen data, such as black screen data. Since the phase-locked loop 14 cannot provide an accurate clock signal to the graphics processing module 11 when it is not fully configured, resulting in inaccurate system screen data output by the graphics processing module 11, the control unit 132 controls the second multiplexer to output the black screen data to the display interface 12, thereby enabling black screen display.

[0141] In some embodiments, when the graphics processing module 11 outputs system screen data, a complete frame of system screen data is not output all at once, but in batches. For example, the graphics processing module 11 outputs only a quarter frame of system screen data each time, and performs four output operations in sequence to complete the output of a complete frame of system screen data. Therefore, after the graphics processing module 11 completes the output of a complete frame of system screen data, it outputs a vertical synchronization signal to the control unit 132 to notify the control unit 132 that the output of a frame of system screen data has been completed and the next frame of system screen data is about to be output. That is, the graphics processing module 11 outputs a vertical synchronization signal to the control unit 132 after outputting a complete frame of system screen data and before starting to output the next frame of system screen data. Then, in the above-mentioned phase-locked loop 14 configuration completion stage, if the control unit 132 switches the output of the second multiplexer from the preset system screen data to the system screen data of the graphics processing module 11 corresponding to the target host as soon as it detects that the phase-locked loop 14 configuration is complete, the system screen data currently output by the second multiplexer may be fragmented frame data, causing the display device to be unable to display a complete frame of system screen data. To avoid the aforementioned problems, when the phase-locked loop 14 is configured and the vertical synchronization signal from the graphics processing module 11 corresponding to the target host is received, the control unit 132 instructs the second multiplexer to output the system screen data received from the first multiplexer. That is, the timing for switching the output of the second multiplexer from preset system screen data to the system screen data from the graphics processing module 11 corresponding to the target host is when the phase-locked loop 14 is configured and the vertical synchronization signal from the graphics processing module 11 corresponding to the target host is received, thereby preventing the second multiplexer from outputting fragmented frame system screen data.

[0142] The vertical synchronization signal refers to the vsync signal. The vsync signal is a synchronization pulse signal emitted by the graphics processing module 11 when it completes the output of a frame of system screen data. Optionally, the graphics processing module 11 includes a digital visual interface (DVI) interface, and the graphics processing module 11 outputs the vsync signal to the control unit 132 through the DVI interface.

[0143] The completion of the phase-locked loop 14 configuration means that the system screen data currently received by the second multiplexer is accurate, and the receipt of the vertical synchronization signal means that the graphics processing module 11 has output one frame of system screen data and is about to output the next frame of system screen data. Therefore, when the above two conditions are met, the control unit 132 executes the logic to switch the output of the second multiplexer. This can both avoid displaying incorrect system screens and ensure that the displayed system screen is a complete frame, thus improving the display switching effect.

[0144] The following will continue to combine Figure 1 The working principle of the phase-locked loop 14 in chip 10 and its related internal structure is described below.

[0145] See Figure 1 The chip 10 also includes a phase-locked loop (PLL) 14, to which multiple graphics processing modules 11 are connected. The PLL 14 is connected to a switching module 13. The multiple graphics processing modules 11 are used to output system screen data to the switching module 13 based on received clock signals, and also to output configuration information provided by their respective connected hosts to the switching module 13. The switching module 13 is also used to establish a transmission path between the graphics processing module 11 corresponding to the target host and the PLL 14, so as to output the configuration information of the graphics processing module 11 corresponding to the target host to the PLL 14. The PLL 14 is used to configure the multiple graphics processing modules 11 using the configuration information received from the switching module 13 and output clock signals to the multiple graphics processing modules 11. The PLL 14 is described below.

[0146] (4) Phase-locked loop 14

[0147] Phase-locked loop 14 (PLL 14) is a component of chip 10 used to provide clock signals to graphics processing module 11. The clock signal is fundamental to the timing logic of graphics processing module 11, which generates system screen data based on the clock signal. Different clock signals used by graphics processing module 11 result in different resolutions of the output system screen data. The type of clock signal output by PLL 14 depends on its configuration. In this embodiment, the host can generate corresponding configuration information based on the user's required system screen resolution and output this information to graphics processing module 11. Graphics processing module 11 provides this configuration information to PLL 14, which then uses the configuration information to generate a clock signal and provides it to graphics processing module 11. Graphics processing module 11 then generates system screen data that meets the resolution requirements based on the clock signal.

[0148] Although each graphics processing module 11 in chip 10 is connected to phase-locked loop 14 via switching module 13, during operation, only one graphics processing module 11 has a conductive transmission path to phase-locked loop 14; the other graphics processing modules 11 have non-conductive transmission paths to phase-locked loop 14. A conductive transmission path means that the configuration information output by the graphics processing module 11 can be transmitted to phase-locked loop 14; a non-conductive path means that the configuration information output by the graphics processing module 11 cannot be transmitted to phase-locked loop 14. Switching module 13 switches to make the transmission path between one of the multiple graphics processing modules 11 and phase-locked loop 14 conductive, thereby outputting the configuration information of that graphics processing module 11 to phase-locked loop 14. Switching module 13 can control internally within chip 10 which graphics processing module 11's configuration information is output to phase-locked loop 14. That is, multiple graphics processing modules 11 share a single phase-locked loop 14. At any given time, the phase-locked loop 14 can only receive the configuration information output by one of the graphics processing modules 11. The switching module 13 can provide the phase-locked loop 14 with the configuration information of the graphics processing module 11 corresponding to a host requested by the display device.

[0149] In this embodiment of the application, when the display device requests to switch the currently displayed system screen to the system screen of the target host, the switching module 13 connects the transmission path between the graphics processing module 11 corresponding to the target host and the phase-locked loop 14, thereby outputting the configuration information of the graphics processing module 11 corresponding to the target host to the phase-locked loop 14.

[0150] In the aforementioned chip 10, a phase-locked loop (PLL) 14 is deployed, and multiple graphics processing modules 11 share this PLL 14. The switching module 13 can connect the transmission path between any host's corresponding graphics processing module 11 and the PLL 14, thereby enabling flexible control over which host's configuration information the PLL 14 receives, so that the PLL 14 outputs the clock signal required by the graphics processing module 11 corresponding to that host. Therefore, this embodiment only requires deploying one PLL 14 in the chip 10 to ensure the normal operation of the graphics processing module 11 corresponding to the host whose system screen is to be displayed, eliminating the need to deploy a separate PLL 14 for each graphics processing module 11. This not only saves on the number of PLLs 14 and reduces the cost of the chip 10, but also saves space in the chip 10.

[0151] In one possible implementation, if phase-locked loop 14 is in a configuration state, it indicates that a host is currently configuring phase-locked loop 14. If switching module 13 outputs the configuration information of the graphics processing module 11 corresponding to the target host to phase-locked loop 14 at this time, it will disrupt the original configuration progress of phase-locked loop 14, causing configuration errors in phase-locked loop 14. To avoid the above problem, in response to the switching command, switching module 13 first checks the state of phase-locked loop 14. If phase-locked loop 14 is in a non-configuration state, it establishes the transmission path between the graphics processing module 11 corresponding to the target host and phase-locked loop 14 to output the configuration information of the graphics processing module 11 corresponding to the target host to phase-locked loop 14. If phase-locked loop 14 is in a configuration state, switching module 13 enters a waiting state until it detects that phase-locked loop 14 is in a non-configuration state, at which point switching module 13 executes the logic to switch the configuration information output to phase-locked loop 14.

[0152] In this embodiment, the condition for the switching unit to reconfigure the phase-locked loop 14 includes that the phase-locked loop 14 is in a non-configuration state. This can prevent the control unit 132 from starting to reconfigure the phase-locked loop 14 when the host is in the configuration state, which would disrupt the original configuration progress of the phase-locked loop 14. This can ensure the orderly progress of the phase-locked loop 14 configuration process and help reduce the error rate in the display switching process.

[0153] In another possible implementation, the clock signal output by phase-locked loop 14 is obtained by frequency conversion of a reference clock signal according to configuration information. When phase-locked loop 14 is not fully configured, it cannot generate a clock signal; after configuration, it can generate an accurate clock signal based on the configuration information. Based on this, control unit 132 controls which clock signal phase-locked loop 14 outputs to the graphics processing module 11 according to its state. If phase-locked loop 14 is not fully configured, it means it cannot currently generate an accurate clock signal; therefore, switching module 13 controls phase-locked loop 14 to output a reference clock signal to multiple graphics processing modules 11. If phase-locked loop 14 is fully configured, it means it can currently generate an accurate clock signal; therefore, switching module 13 controls phase-locked loop 14 to output the clock signal generated after configuration to multiple graphics processing modules 11.

[0154] In this embodiment, the phase-locked loop 14 is reconfigured upon the start of the switching process. During configuration, the phase-locked loop 14 cannot output a stable clock signal, therefore a reference clock signal is provided to the graphics processing module 11 to ensure the normal operation of its internal processing logic. After configuration, the phase-locked loop 14 can output a stable clock signal, thus providing a stable clock signal to the graphics processing module 11. This enables the graphics processing module 11 to generate accurate system screen data based on an accurate clock signal, thereby ensuring the feasibility and orderliness of the entire display switching process.

[0155] In the above method, different clock signals are provided to the graphics processing module 11 under different circumstances. When the phase-locked loop 14 is unable to generate an accurate clock signal, a reference clock signal is provided to the graphics processing module 11 to ensure the normal operation of the internal processing logic of the graphics processing module 11. When the phase-locked loop 14 is able to generate an accurate clock signal, an accurate clock signal is provided to the graphics processing module 11 so that the graphics processing module 11 can generate accurate system screen data based on the accurate clock signal, thereby displaying an accurate system screen and ensuring the orderliness of the entire display switching process.

[0156] In another possible implementation, the switching module 13 is used to output each item in the configuration information of the graphics processing module 11 corresponding to the target host to the phase-locked loop 14 one by one. That is, the configuration information includes multiple configuration items, and the configuration process of the phase-locked loop 14 is carried out step by step. The switching module 13 outputs multiple configuration items to the phase-locked loop 14 one by one, and at least one configuration item can be output to the phase-locked loop 14 at a time.

[0157] Optionally, the graphics processing module 11 includes a second register, in which configuration information is stored. Different configuration items are stored in different bits of the second register, and the correspondence between the configuration items and the number of bits in the second register is as follows.

[0158] assign ppll2_bypass=pll_cntl_out

[29] ; ppll2_bypass represents the bypass signal of the reference clock inside the phase-locked loop 14. A low level indicates that the output is locked clock signal, and a high level indicates that the output is reference clock signal.

[0159] assign ppl12_fout2xpd = pll_cntl_out

[28] ; assign ppl12_fout2xpd represents the powerdown signal of the oscillator output clock inside the phase-locked loop 14. A low level indicates normal operation, and a high level indicates power-down.

[0160] assign ppll2_foutpostdivpd = pll_cntl_out

[27] ; ppll2_foutpostdivpd represents the powerdown signal of the main output clock inside the phase-locked loop 14. A low level indicates normal operation, and a high level indicates power-down.

[0161] assign ppll2_fout4phasepd=pll_cntl_out

[26] ; ppll2_fout4phasepd represents the powerdown signal of the two-frequency-division four-phase clock inside the phase-locked loop 14. A low level indicates normal operation, and a high level indicates power-down.

[0162] assign ppll2_mode = pll_cntl_out

[25] ; ppll2_mode represents the mode selection of phase-locked loop 14. Low level represents fractional mode, high level represents integer mode.

[0163] assign ppll2_pd = pll_cntl_out

[24] ; ppll2_pd represents the powerdown signal of the global clock inside the phase-locked loop 14. A low level indicates normal operation, and a high level indicates power-down.

[0164] assign ppll2_postdiv2 = pll_cntl_out[23:21]; ppll2_postdiv2 is used to configure the frequency division coefficient of the second-stage frequency divider inside the phase-locked loop 14.

[0165] assign ppll2_postdivl = pll_cntl_out[20:18]; ppll2_postdivl is used to configure the division coefficient of the first-stage frequency divider inside the phase-locked loop 14.

[0166] assign ppll2_fbdiv = pll_cntl_out[17:6]; ppll2_fbdiv is used to configure the feedback frequency division ratio of phase-locked loop 14.

[0167] assign ppll2_refdiv = pll_cntl_out[5:0]; ppll2_refdiv is used to configure the reference clock divider of phase-locked loop 14.

[0168] assign ppll2_frac = pll_cntl_out[63:32]; ppll2_frac is used to configure the output clock frequency of phase-locked loop 14.

[0169] assign gpu_bypass=pll_cntl out

[30] ; gpu_bypass is used to configure the switching of the reference clock signal. A low level indicates the output of the reference clock signal, and a high level indicates the output of the master clock signal of the phase-locked loop 14.

[0170] Optionally, the switching module 13 outputs each configuration item in the configuration information to the phase-locked loop 14 one by one according to the process in Table 1 below, so as to configure the phase-locked loop 14.

[0171] Table 1

[0172]

[0173]

[0174] exist Figure 1 Based on this, the embodiments of this application provide Figure 3 The structural diagram shown below, in conjunction with... Figure 3 The internal structure and working principle of the switching module 13 used for switching configuration information are described below.

[0175] See Figure 3 The switching module 13 includes a second multiplexer group 133 and a control unit 132. Correspondingly, multiple graphics processing modules 11, the control unit 132, and the phase-locked loop 14 are all connected to the second multiplexer group 133. In this configuration, the control unit 132 instructs the second multiplexer group 133 to output the configuration information received from the graphics processing module 11 corresponding to the target host; the second multiplexer group 133 outputs the configuration information from the graphics processing module 11 indicated by the control unit 132 to the phase-locked loop 14.

[0176] The second multiplexer group 133 is a combinational logic circuit that selects one output from multiple inputs. In this embodiment, the inputs of the second multiplexer group 133 include configuration information output from multiple graphics processing modules 11, and the output of the second multiplexer group 133 is one of the received configuration information. The second multiplexer group 133 can determine which configuration information to output in response to a control signal input to it.

[0177] Control unit 132 controls which configuration information the second multiplexer group 133 outputs. Control unit 132 controls the second multiplexer group 133 to switch between multiple different configuration information streams by outputting different control signals to the second multiplexer group 133, thereby dynamically switching the output of the second multiplexer group 133. When the display device requests to switch the currently displayed system screen to the target host's system screen, control unit 132 responds to the switching command by triggering a control signal for the second multiplexer group 133. This control signal instructs the second multiplexer group 133 to output the configuration information received from the graphics processing module 11 corresponding to the target host. Therefore, after control unit 132 outputs the control signal to the second multiplexer group 133, the second multiplexer group 133 responds to the control signal by outputting the configuration information indicated by the control signal to the phase-locked loop 14, that is, outputting the configuration information received from the graphics processing module 11 corresponding to the target host to the phase-locked loop 14, thereby establishing the transmission path between the graphics processing module 11 corresponding to the target host and the phase-locked loop 14.

[0178] The above Figure 3 In the chip 10 shown, a second multiplexer group 133 is deployed between the graphics processing module 11 and the phase-locked loop 14. The control unit 132 dynamically switches which graphics processing module 11's configuration information is output to the phase-locked loop 14 by outputting different control signals to the second multiplexer group 133. This enables dynamic switching of which transmission path between the graphics processing module 11 and the phase-locked loop 14 is activated, which helps to improve the flexibility and speed of the switching process.

[0179] Optionally, the second multiplexer group 133 includes at least one multiplexer. In one possible implementation, see [link to relevant documentation]. Figure 3 The second multiplexer group 133 includes a third multiplexer and a fourth multiplexer. Accordingly, multiple graphics processing modules 11 and control unit 132 are connected to the third multiplexer, and the third multiplexer, control unit 132 and phase-locked loop 14 are all connected to the fourth multiplexer.

[0180] In this structure, control unit 132 is used to cache the configuration information of the graphics processing module 11 corresponding to the target host and output the cached configuration information to the fourth multiplexer; control unit 132 is also used to instruct the third multiplexer to output the configuration information received from the graphics processing module 11 corresponding to the target host; control unit 132 is also used to instruct the fourth multiplexer to output the configuration information received from control unit 132 if the phase-locked loop 14 has not been configured, and to instruct the fourth multiplexer to output the configuration information received from the third multiplexer if the phase-locked loop 14 has been configured; the third multiplexer is used to output the configuration information indicated by control unit 132 in the received configuration information to the fourth multiplexer; the fourth multiplexer is used to output the configuration information indicated by control unit 132 in the received configuration information to the phase-locked loop 14.

[0181] For ease of explanation, the configuration information cached by the control unit 132 is referred to as configuration information a, and the configuration information of the graphics processing module 11 corresponding to the target host is referred to as configuration information b. Although configuration information a and configuration information b are essentially obtained from the graphics processing module 11 corresponding to the target host, configuration information a and configuration information b are not configuration information at the same time. The differences between configuration information a and configuration information b are explained in detail below: (1) Configuration information a is the configuration information before the start of switching. Before the start of switching means before the control unit 132 starts executing the display switching process in response to the switching command, which is also before the phase-locked loop 14 starts reconfiguring the phase-locked loop 14. Configuration information a is cached in the control unit 132. During the configuration process of the phase-locked loop 14, the configuration information a cached by the control unit 132 will not change. Therefore, the configuration information a received by the fourth multiplexer is stable and unchanged. (2) Configuration information b is the configuration information after the start of switching. After the start of switching means after the control unit 132 starts executing the display switching process in response to the switching command, which is also after the phase-locked loop 14 starts reconfiguring the phase-locked loop 14. Configuration information b is stored in the graphics processing module 11 corresponding to the target host. The target host can modify the configuration information stored in the graphics processing module 11 at any time. Therefore, configuration information b is dynamic and may change during the configuration of the phase-locked loop 14. Consequently, the configuration information b received by the fourth multiplexer may also change. If the target host modifies the configuration information stored in the graphics processing module 11 during the configuration of the phase-locked loop 14, the configuration information a input to the fourth multiplexer will be different from configuration information b. If the target host does not modify the configuration information stored in the graphics processing module 11 during the configuration of the phase-locked loop 14, the configuration information a input to the fourth multiplexer will be the same as configuration information b.

[0182] After understanding the differences between configuration information a and configuration information b, the working principles of the third and fourth multiplexers will be introduced below.

[0183] The third multiplexer is used to select which graphics processing module 11's configuration information to output. The third multiplexer has multiple inputs, each being configuration information output by one of the graphics processing modules 11. The output of the third multiplexer is one of the received configuration information streams. The third multiplexer can determine which configuration information to output in response to a control signal input to it. The third multiplexer is controlled by the control unit 132, which instructs the third multiplexer to output which configuration information stream by outputting different control signals. When the display device requests to switch the currently displayed system screen to the target host's system screen, the control unit 132, in response to the switching command, triggers the control signal of the third multiplexer, which instructs the third multiplexer to output the configuration information b received from the graphics processing module 11 corresponding to the target host. Therefore, after the control unit 132 outputs the control signal to the third multiplexer, the third multiplexer responds to the control signal and outputs the configuration information indicated by the control signal to the fourth multiplexer, that is, it outputs the configuration information b received from the graphics processing module 11 corresponding to the target host to the fourth multiplexer.

[0184] The fourth multiplexer is used to output configuration information b received from the third multiplexer or configuration information a received from the control unit 132 under different circumstances. The fourth multiplexer has two inputs: one is the configuration information b output from the third multiplexer, and the other is the configuration information a output from the control unit 132. The output of the fourth multiplexer is one of these two inputs. The fourth multiplexer can determine which configuration information to output in response to control signals input to it. The fourth multiplexer is also controlled by the control unit 132, which instructs the fourth multiplexer to output which configuration information by outputting different control signals. When the display device requests to switch the currently displayed system screen to the target host's system screen, the control unit 132 needs to configure the phase-locked loop 14 according to the configuration information provided by the target host, so that the phase-locked loop 14 provides the clock signal required by the graphics processing module 11 corresponding to the target host to acquire the system screen data of the target host. However, during the configuration process of phase-locked loop 14, the configuration information b output by the third multiplexer may change. If the configuration information b changes during the configuration process of phase-locked loop 14, the configuration information received by phase-locked loop 14 will be inaccurate, leading to errors in the configuration process. Therefore, the control process of the control unit 132 for the fourth multiplexer is divided into a phase where phase-locked loop 14 is not fully configured and a phase where phase-locked loop 14 is fully configured. In the phase where phase-locked loop 14 is not fully configured, the configuration information b provided in real time by the graphics processing module 11 corresponding to the target host may change, while the configuration information a output by the control unit 132 will not change. Therefore, the control unit 132 outputs a control signal to the fourth multiplexer to instruct it to output the configuration information a received from the control unit 132 to phase-locked loop 14, thereby avoiding configuration based on inconsistent configuration information. During the configuration completion phase of phase-locked loop 14, control unit 132 outputs a control signal to the fourth multiplexer to instruct the fourth multiplexer to output the configuration information b received from the third multiplexer to phase-locked loop 14, that is, to output the configuration information of the graphics processing module 11 corresponding to the target host, thereby returning the configuration right of phase-locked loop 14 from control unit 132 to the host.

[0185] This solution transfers the configuration control of PLL 14 from the host to the control unit 132 when switching the configuration information of PLL 14 begins. After completing the configuration switching, the configuration control of PLL 14 is returned from the control unit 132 to the host. This ensures that the configuration information provided to PLL 14 during the configuration process is accurate and unchanged, improving the orderliness and accuracy of reconfiguring PLL 14 and reducing the error rate during the configuration process.

[0186] In one possible implementation, the control unit 132 outputs each item in the cached configuration information to the fourth multiplexer sequentially. That is, the configuration information includes multiple configuration items, and the process of the control unit 132 configuring the phase-locked loop 14 is performed step-by-step. The switching module 13 sequentially outputs multiple configuration items to the phase-locked loop 14, with at least one configuration item output to the phase-locked loop 14 at a time. The process of the control unit 132 progressively configuring the phase-locked loop 14 is shown in Table 1 above and will not be repeated here.

[0187] In another possible implementation, see Figure 3 The switching module 13 also includes multiple configuration units 134. Each graphics processing module 11 is connected to its corresponding configuration unit 134. The control unit 132 and the third multiplexer are both connected to each configuration unit 134. In this structure, the multiple graphics processing modules 11 are used to output configuration information before and after the start of the switching to their respective connected configuration units 134. The control unit 132 is used to instruct each configuration unit 134 to output the configuration information after the start of the switching if the phase-locked loop 14 is successfully configured. The control unit 132 is also used to instruct each configuration unit 134 to output the configuration information before the start of the switching if the phase-locked loop 14 fails to be configured. The multiple configuration units 134 are used to output the configuration information indicated by the control unit 132 in the received configuration information to the third multiplexer.

[0188] Here, "before the start of switching" refers to the period before the control unit 132 responds to the switching command and begins executing the display switching process, which is also before the phase-locked loop 14 begins reconfiguration. "After the start of switching" refers to the period before the control unit 132 responds to the switching command and begins executing the display switching process, which is also before the phase-locked loop 14 begins reconfiguration. In fact, the configuration information before the start of switching is the same as the configuration information a above, and the configuration information after the start of switching is the same as the configuration information b above.

[0189] The configuration unit 134 is used to output configuration information received from the graphics processing module 11 before or after the start of the switch, under different circumstances. The fourth multiplexer has two inputs: one is the configuration information output by the graphics processing module 11 before the switch, and the other is the configuration information output by the graphics processing module 11 after the switch. The output of the fourth multiplexer is one of these two inputs. The configuration unit 134 can determine which configuration information to output in response to control signals input to it. The configuration unit 134 is also controlled by the control unit 132, which instructs the configuration unit 134 to output which configuration information by outputting different control signals. In this embodiment, during the configuration process of the phase-locked loop 14, the control unit 132 has the right to configure the phase-locked loop 14. The control unit 132 provides the cached configuration information to the phase-locked loop 14 for configuration. The cached configuration information is the configuration information before the switch, so the configuration process of the phase-locked loop 14 uses the configuration information before the switch. After configuration, the control unit 132 returns the configuration rights of the phase-locked loop 14 to the target host, and the graphics processing module 11 corresponding to the target host provides the configuration information to the phase-locked loop 14 for configuration. However, during the configuration process of the phase-locked loop 14, the target host can modify the configuration information stored in the graphics processing module 11 at any time. If the configuration information of the graphics processing module 11 changes during the configuration process, the configuration information after the start of the switch will be different from the configuration information currently used by the phase-locked loop 14, causing the configuration information obtained by the phase-locked loop 14 to change when the configuration rights of the phase-locked loop 14 are returned to the target host, thus leading to an error. Based on this, the control unit 132 controls the configuration unit 134 to output the configuration information before the start of the switch or the configuration information after the start of the switch to the third multiplexer according to the configuration status of the phase-locked loop 14, specifically in the following two cases.

[0190] In the first scenario, if the phase-locked loop 14 is successfully configured, it means that the target host has not changed the configuration information of the graphics processing module 11. Therefore, the configuration information after the start of the switch is consistent with the current configuration information used by the phase-locked loop 14. In this case, the control unit 132 controls the configuration unit 134 to output the configuration information after the start of the switch to the third multiplexer. In this case, after the configuration is completed, the configuration information output by the third multiplexer to the fourth multiplexer is the configuration information after the start of the switch.

[0191] In the second scenario, if the phase-locked loop 14 configuration fails, it indicates that the target host has changed the configuration information of the graphics processing module 11. Therefore, the configuration information after the start of the switch is inconsistent with the current configuration information used by the phase-locked loop 14, while the configuration information before the start of the switch is consistent with the current configuration information used by the phase-locked loop 14. In this case, the control unit 132 controls the configuration unit 134 to output the configuration information before the start of the switch to the third multiplexer. In this situation, after the configuration is completed, the configuration information output by the third multiplexer to the fourth multiplexer is the configuration information before the start of the switch.

[0192] By setting a configuration unit 134 between the graphics processing module 11 and the third multiplexer, the configuration information before or after the start of the switching can be controlled to be output to the third multiplexer according to the configuration of the phase-locked loop 14, so as to ensure that the configuration information provided to the phase-locked loop 14 before and after the configuration right of the phase-locked loop 14 is returned to the host is consistent, thereby completing the seamless switching of configuration right.

[0193] In another possible implementation, see Figure 3 The configuration unit 134 includes a first register and a fifth multiplexer. Correspondingly, the graphics processing module 11, the third multiplexer, the control unit 132, and the first register are all connected to the fifth multiplexer, and the graphics processing module 11 and the control unit 132 are both connected to the first register. In this structure, the graphics processing module 11 is used to output configuration information before the start of switching to the first register and to output configuration information after the start of switching to the fifth multiplexer; the first register is used to store the configuration information received from the graphics processing module 11 and to output the stored configuration information to the fifth multiplexer; the fifth multiplexer is used to output the configuration information indicated by the control unit 132 in the received configuration information to the third multiplexer.

[0194] The first register stores configuration information prior to the switching process and outputs the stored configuration information to the fifth multiplexer. Optionally, the graphics processing module 11 periodically outputs configuration information to the first register, which stores the received configuration information in response to a control signal input to it. The first register can be controlled by the control unit 132, which instructs the first register when to store the received configuration information by outputting different control signals to it. In this embodiment, the control unit 132 triggers the control signal of the first register in response to a switching command, and the control signal instructs the first register to store the received configuration information. Therefore, after the control unit 132 outputs the control signal to the first register, the first register stores the currently received configuration information in response to the control signal, thereby storing the configuration information prior to the switching process before it begins, and then outputting the configuration information prior to the switching process to the fifth multiplexer.

[0195] The fifth multiplexer is used to select whether to output configuration information before or after the switching begins. The fifth multiplexer has two inputs: one is the configuration information before the switching begins output from the first register, and the other is the configuration information after the switching begins output from the graphics processing module 11. The output of the fifth multiplexer is one of these two inputs. The fifth multiplexer can determine which configuration information to output in response to a control signal input to it. The fifth multiplexer is also controlled by the control unit 132, which instructs the fifth multiplexer to output which configuration information by outputting different control signals. If the phase-locked loop 14 is successfully configured, the configuration information after the switching begins is consistent with the configuration information currently used by the phase-locked loop 14. Therefore, the control unit 132 triggers a control signal indicating the output of the configuration information after the switching begins, outputting this control signal to the fifth multiplexer. The fifth multiplexer, in response to this control signal, outputs the configuration information after the switching begins to the third multiplexer. If the configuration of phase-locked loop 14 fails, the configuration information before the start of the switch is consistent with the configuration information currently used by phase-locked loop 14. Therefore, control unit 132 triggers a control signal to indicate the output of the configuration information before the start of the switch, and outputs the control signal to the fifth multiplexer. The fifth multiplexer responds to the control signal and outputs the configuration information before the start of the switch to the third multiplexer.

[0196] The configuration unit 134 is designed to consist of a register and a multiplexer corresponding to the graphics processing module 11. The register stores the configuration information of the graphics processing module 11 before the switching begins, thus backing up the configuration information before the switching begins. The multiplexer controls the output of the configuration information before or after the switching begins, which improves the flexibility and speed of switching the output configuration information.

[0197] In another possible implementation, see Figure 3 The graphics processing module 11 includes a second register, and the switching module 13 includes a third register. The second register stores the configuration information of the graphics processing module 11. In this structure, the control unit 132 is used to store the configuration information in the second register into the third register; the third register is used to output the stored configuration information to the fourth multiplexer.

[0198] In this embodiment of the application, each graphics processing module 11 and the switching module 13 have their own registers. The switching module 13 caches the configuration information of the graphics processing module 11 by storing the configuration information in the register of the graphics processing module 11 into its own register. On the one hand, it backs up the configuration information of the graphics processing module 11 to prevent errors caused by changes in the configuration information during the switching process. On the other hand, it can improve the reading speed of the configuration information.

[0199] Based on the above Figure 3 Based on this, the logic for display switching in chip 10 is mainly implemented by control unit 132 controlling the control signals of each multiplexer. In this case, switching module 13 also includes a control register connected to each multiplexer and a control register connected to a first register. The control register connected to the multiplexer stores the value of the control signal of that multiplexer, and the control register connected to the first register stores the value of the control signal of that first register. Control unit 132 outputs different control signals by changing the values ​​of the control registers, thereby controlling which channel of data the multiplexer outputs and when the first register stores configuration information.

[0200] As described above, the switching module 13 includes a first multiplexer, a second multiplexer, a third multiplexer, a fourth multiplexer, a fifth multiplexer, and a first register. Hereinafter, the control register connected to the first multiplexer is referred to as control register 1, the control register connected to the second multiplexer as control register 2, the control register connected to the third multiplexer as control register 3, the control register connected to the fourth multiplexer as control register 4, the control register connected to the fifth multiplexer as control register 5, and the control register connected to the first register as control register 6. Optionally, control registers 1 through 6 can be different registers or the same register; for example, the values ​​of control signals from different multiplexers can be stored in different bits of the same register.

[0201] To facilitate understanding, the processing logic when no display switching occurs will be explained first. Taking the chip 10, which includes a first graphics processing module 11 and a second graphics processing module 11, as an example, and taking the system screen corresponding to the first graphics processing module 11 as an example, the processing logic of the chip 10 when the display screen is the system screen corresponding to the first graphics processing module 11 is as follows:

[0202] 1. The first graphics processing module 11 stores its configuration information in its second register, and outputs the configuration information in the second register to the fifth multiplexer and the first register respectively.

[0203] 2. When the value stored in control register 1 is 0, the control signal gpu_sel[0]_0 is triggered. When the value stored in control register 2 is 1, the control signal gpu_sel[1]_1 is triggered. When the value stored in control register 3 is 0, the control signal pll_sel_0 is triggered. When the value stored in control register 4 is 0, the control signal switch_sel_0 is triggered. When the value stored in control register 5 is 0, the control signal switch_fail_0 is triggered. When the value stored in control register 6 is 0, the control signal switch_begin_0 is triggered. The configuration information currently stored in the third register is output to the fourth multiplexer. The configuration information stored in the third register is obtained by control unit 132 from the second register corresponding to the first graphics processing module 11.

[0204] The control signal gpu_sel[0]_0 is the control signal of the first multiplexer. The control signal gpu_sel[0]_0 is triggered when the configuration of the phase-locked loop 14 is completed. The control signal gpu_sel[0]_0 instructs the first multiplexer to output the system screen data received from the first graphics processing module 11.

[0205] The control signal gpu_sel[1]_1 is the control signal of the second multiplexer. The control signal gpu_sel[1]_1 is triggered when the configuration of the phase-locked loop 14 is completed and the vertical synchronization signal generated by the first graphics processing module 11 is detected. The control signal gpu_sel[1]_1 instructs the second multiplexer to output the system screen data received from the first multiplexer.

[0206] The control signal pll_sel_0 is the control signal of the third multiplexer. The control signal pll_sel_0 is triggered when the received switching command indicates that the system screen corresponding to the first graphics processing module 11 is displayed. The control signal pll_sel_0 instructs the third multiplexer to output the configuration information received from the fifth multiplexer corresponding to the first graphics processing module 11.

[0207] The control signal switch_sel_0 is the control signal for the fourth multiplexer. This control signal is triggered when the configuration of the phase-locked loop 14 is completed. The control signal switch_sel_0 instructs the fourth multiplexer to output the configuration information received from the third multiplexer.

[0208] The control signal switch_fail_0 is the control signal for the fifth multiplexer. This control signal is triggered when the phase-locked loop 14 is successfully configured. This control signal instructs the fifth multiplexer to output the configuration information received from the second register.

[0209] The control signal switch_begin_0 is the control signal for the first register. This control signal switch_begin_0 is triggered when the configuration of the phase-locked loop 14 is completed. This control signal switch_begin_0 indicates that the first register does not need to store the currently received configuration information.

[0210] 3. Upon receiving the control signal `switch_begin_0`, the first register does not need to store the configuration information currently received from the second register; it only needs to output the configuration information already stored in the first register to the fifth multiplexer. The fifth multiplexer receives the configuration information from the second register and the first register. Responding to the control signal `switch_fail_0`, the fifth multiplexer outputs the configuration information received from the second register to the third multiplexer. The third multiplexer receives the configuration information from each of the fifth multiplexers. Responding to the control signal `pll_sel_0`, the third multiplexer outputs the configuration information received from the fifth multiplexer corresponding to the first graphics processing module 11 to the fourth multiplexer. The fourth multiplexer receives the configuration information from the third multiplexer and the configuration information from the third register. Responding to the control signal `switch_sel_0`, the fourth multiplexer outputs the configuration information received from the third multiplexer to the phase-locked loop 14.

[0211] 4. The phase-locked loop 14 configures itself based on the received configuration information to generate a clock signal, which is then input to the first graphics processing module 11 and the second graphics processing module 11. In this case, based on steps 1-3 above, the configuration information received by the phase-locked loop 14 is actually the configuration information in the second register of the first graphics processing module 11, that is, the configuration information of the first graphics processing module 11. Therefore, based on the configuration information of the first graphics processing module 11, the phase-locked loop 14 can generate the clock signal required by the first graphics processing module 11.

[0212] 5. The first graphics processing module 11, based on the clock signal received from the phase-locked loop 14, acquires the system screen data of the host connected to the first graphics processing module 11 and outputs the system screen data to the first multiplexer. The first multiplexer receives the system screen data of the first graphics processing module 11 and the system screen data of the second graphics processing module 11. In response to the control signal gpu_sel[0]_0, the first multiplexer outputs the system screen data received from the first graphics processing module 11 to the second multiplexer. The second multiplexer receives the preset system screen data and the system screen data of the first multiplexer. In response to the control signal gpu_sel[1]_1, the second multiplexer outputs the system screen data received from the first multiplexer to the display interface 12.

[0213] 6. The display interface 12 outputs the received system screen data. In this case, the system screen data received by the display interface 12 is the system screen data of the first graphics processing module 11. Therefore, the final output is the system screen data of the first graphics processing module 11, thereby realizing the display of the system screen of the host connected to the first graphics processing module 11.

[0214] Furthermore, the process of changing the value of the aforementioned control register can be implemented based on the control unit 132, which can be a logic circuit or a controller running a switching program. That is, the process of switching the display screen can be implemented based on either a logic circuit or a switching program. Switching the display screen based on a logic circuit is equivalent to implementing the switching process in hardware, while switching the display screen based on a switching program is equivalent to implementing the switching process in software. Accordingly, the process of switching the display screen includes the following two methods.

[0215] The first method: The switching module 13 includes a logic circuit and multiple registers connected in sequence. The logic circuit is the aforementioned control unit 132. In this structure, in response to a switching command, the logic circuit assigns a value to the first register to trigger the first control signal. In response to the first control signal, it assigns a value to the next register connected to the first register to trigger the next control signal. The control signal is used to establish a transmission path between the graphics processing module 11 corresponding to the target host and the display interface 12, so as to output the system screen data of the graphics processing module 11 corresponding to the target host to the display interface 12. In this way, the values ​​of the registers can be changed through the logic circuit, thereby realizing the hardware switching process.

[0216] These multiple registers are the aforementioned control registers 1 to 6.

[0217] Taking the chip 10 as including a first graphics processing module 11 and a second graphics processing module 11 as an example, and taking the display screen as the system screen corresponding to the first graphics processing module 11 as an example, when the display screen is switched from the system screen corresponding to the first graphics processing module 11 to the system screen corresponding to the second graphics processing module 11 based on the logic circuit, the processing logic is as follows.

[0218] 1. The logic circuit receives a switching command, which instructs the display screen to switch from the system screen corresponding to the first graphics processing module 11 to the system screen corresponding to the second graphics processing module 11. In response to the switching command, the logic circuit sets the switch_direction register to 1. Specifically, a value of 0 in the switch_direction register indicates displaying the system screen corresponding to the first graphics processing module 11, and a value of 1 indicates displaying the system screen corresponding to the second graphics processing module 11.

[0219] 2. The logic circuit modifies the value of the control register 1 to trigger the control signal gpu_sel[0]_0, and modifies the value of the control register 2 to trigger the control signal gpu_sel[1]_0. The control signal gpu_sel[0]_0 is the control signal of the first multiplexer, which instructs the first multiplexer to output the system screen data received from the first graphics processing module 11. The control signal gpu_sel[1]_0 is the control signal of the second multiplexer, which instructs the second multiplexer to output the preset system screen data. By executing this step, the display screen of the display device is first switched to the preset system screen indicated by the preset system screen data.

[0220] The logic circuit modifies the value of control register 4 to trigger the control signal switch_sel_1, and modifies the value of control register 3 to trigger the control signal pll_sel_1. Control signal pll_sel_1 is the control signal for the third multiplexer, instructing it to output the configuration information received from the fifth multiplexer corresponding to the second graphics processing module 11. Control signal switch_sel_1 is also the control signal for the fourth multiplexer, instructing it to output the configuration information received from the third register corresponding to the control unit 132. By executing this step, the configuration control of the phase-locked loop 14 is transferred to the control unit 132.

[0221] 3. This logic circuit and control registers 1 through 6 constitute a hardware state machine, such as... Figure 4 As shown, the hardware state machine completes the configuration switching of the phase-locked loop 14 by sequentially jumping to the following states.

[0222] (1) Idle State: The control signal switch_begin is 0, and the control signal pll2_cfg_fms_en is 0. Specifically, switch_begin being 0 indicates that the configuration information of phase-locked loop 14 has not been switched, and switch_begin being 1 indicates that the configuration information of phase-locked loop 14 has been switched; pll2_cfg_fms_en being 0 indicates that the state machine is not working, and pll2_cfg_fms_en being 1 indicates that the state machine is working normally.

[0223] (2) First Prepared State: When the control signal switch_begin is switched to 1 and the control signal pll2_cfg_fms_en is switched to 1, the hardware state machine switches from the idle state to the first prepared state. In the first prepared state, the hardware state machine checks whether the control signals gpu0_pd and gpu1_pd are 0 and whether the control signal gpu_bypass is 1. If yes, it enters the next state; otherwise, it continues to wait until it detects that the control signals gpu0_pd and gpu1_pd are 0 and the control signal gpu_bypass is 1.

[0224] In this context, the control signal gpu0_pd is the power-down signal for the first graphics processing module 11, and the control signal gpu1_pd is the power-down signal for the second graphics processing module 11. A control signal gpu_bypass of 0 indicates that the current phase-locked loop 14 is in a configuration state, outputting a reference clock signal to the graphics processing module 11. A control signal gpu_bypass of 1 indicates that the current phase-locked loop 14 is in a non-configuration state, outputting a clock signal based on the configuration information to the graphics processing module 11. Therefore, detecting that control signals gpu0_pd and gpu1_pd are 0 and control signal gpu_bypass is 1 is equivalent to detecting that the phase-locked loop 14 is in a non-configuration state.

[0225] (3) Second preparation state (pre_step2 state): The hardware state machine sets the control signal gpu_bypass to 0, thereby outputting the reference clock signal to the first graphics processing module 11 and the second graphics processing module 11.

[0226] (4) First configuration state (step2 state): The hardware state machine executes the register assignment process in step 2 of Table 1, thereby powering down the phase-locked loop 14, and then enters the next state.

[0227] (5) Second Configuration State (Step 3): The hardware state machine executes the register assignment process in Step 3 of Table 2, thereby outputting each item in the configuration information to the phase-locked loop 14. When the control signal switch_direction is 1, the hardware state machine stores the configuration information in the second register corresponding to the first graphics processing module 11 into the third register, then performs a 5µs timer. After the timer completes, it enters the next state. It can be assumed that after the timer completes, the configuration information in the third register has been transmitted to the phase-locked loop 14.

[0228] (6) Third Configuration State (Step 4 State): The hardware state machine executes the register assignment process in Step 4 of Table 2, thereby powering on the phase-locked loop 14. Upon entering the third configuration state, the 5us timer in the second configuration state is cleared, and the control signal cnt_step3_5us_done is configured to 0. In the third configuration state, the hardware state machine assigns the control signal pll2_pd to 0, thereby powering on the phase-locked loop 14, and then enters the next state.

[0229] (7) Fourth Configuration State (Step 5): The hardware state machine executes the register assignment process in Step 5 of Table 2 to determine whether the phase-locked loop 14 has locked the clock signal. In the fourth configuration state, it waits for 20µs and cyclically queries the control signal lock. If the control signal lock is 1 for three consecutive queries, it enters the next state. If the query time exceeds 500µs, it reports a timeout and returns to the idle state.

[0230] (8) Fifth configuration state (step6 state): The hardware state machine executes the register assignment process in step 6 of Table 2, and at the same time assigns the control signal gpu_bypass to 1. After completion, it enters the next state.

[0231] (9) Judge State: This state is divided into the following two situations.

[0232] In the first scenario, if the pll2_fms_judge_enable register is 1, the following logic is executed: The value of the control signal host_intervene is checked. If host_intervene is 1, it indicates that other hosts have changed the configuration information of the graphics processing module 11 during the configuration of the phase-locked loop 14. In this case, the hardware state machine returns to the first ready state, waiting for the host configuration to complete before restarting the configuration process. If host_intervene is 0, it indicates that other hosts have not changed the configuration information of the graphics processing module 11 during the configuration of the phase-locked loop 14. In this case, the hardware state machine returns to the idle state, and the control signal pll2_switch_status is set to 1, indicating that the phase-locked loop 14 configuration is complete.

[0233] In the second scenario, if the pll2_fms_judge_enable register is 0, the above logic is unnecessary; the control signal pll2_switch_status is directly set to 1, indicating that the phase-locked loop 14 configuration is complete. After the configuration process is complete, if the control signal switch_fail is 1, it indicates configuration failure, meaning that other hosts have modified the configuration information of the graphics processing module 11 during the configuration of the phase-locked loop 14. If the control signal switch_fail is 0, it indicates configuration success, meaning that other hosts have not modified the configuration information of the graphics processing module 11 during the configuration of the phase-locked loop 14. In this case, the switching display process can be restarted by re-triggering the switching command.

[0234] The value of the aforementioned control signal switch_fail is also the value of control register 5. A switch_fail value of 0 is recorded as switch_fail_0, which instructs the fifth multiplexer to output the configuration information received from the second register. A switch_fail value of 1 is recorded as switch_fail_1, which instructs the fifth multiplexer to output the configuration information received from the first register.

[0235] The value of the aforementioned control signal switch_begin is also the value of control register 6. A switch_begin value of 0 is recorded as switch_begin_0, indicating that the first register does not need to store the currently received configuration information. A switch_begin value of 0 is recorded as switch_begin_1, indicating that the first register stores the currently received configuration information.

[0236] It should be noted that the assignment process of each of the above registers is implemented through logic circuits. When the value of a register changes in one state, the logic circuits will automatically trigger a change in the value of the register in the next state, thereby realizing the hardware-based switching process.

[0237] 4. After completing the configuration switching of the phase-locked loop 14, the logic circuit changes the value of the control register 4 to trigger the control signal switch_sel_0. The control signal switch_sel_0 instructs the fourth multiplexer to output the configuration information received from the third multiplexer. By executing this step, the configuration right of the phase-locked loop 14 is returned to the host. The logic circuit changes the value of the control register 1 to trigger the control signal gpu_sel[0]_1 and changes the value of the control register 2 to trigger the control signal gpu_sel[1]_0. The control signal gpu_sel[0]_1 is the control signal of the first multiplexer, which instructs the first multiplexer to output the system screen data received from the second graphics processing module 11. The control signal gpu_sel[1]_0 is the control signal of the second multiplexer, which instructs the second multiplexer to output the system screen data received from the first multiplexer. By performing this step, the display screen of the display device is switched to the system screen corresponding to the second graphics processing module 11.

[0238] 5. After completing the above process, the system screen corresponding to the second graphics processing module 11 is currently displayed. The host corresponding to the second graphics processing module 11 can change the configuration information of the second graphics processing module 11 to adjust the resolution of the system screen corresponding to the second graphics processing module 11.

[0239] In the above scheme, during the display switching process, the logic circuit triggers the control signal by assigning a value to the register. The logic circuit automatically assigns a value to the next register according to the control signal to trigger the next control signal, and so on. The logic circuit triggers multiple control signals in sequence, thereby controlling the output of the system screen data of the graphics processing module 11 corresponding to the target host to the display interface 12, realizing display switching based on hardware. Since the hardware assigns values ​​to the register very quickly, it is beneficial to improve the overall speed of display switching.

[0240] The second approach involves a switching module 13 comprising a controller and multiple registers. In this configuration, the controller runs a switching program that sequentially reads and writes to multiple registers to trigger multiple control signals. These control signals are used to establish a transmission path between the target host's graphics processing module 11 and the display interface 12, outputting the system screen data from the target host's graphics processing module 11 to the display interface 12. This allows the switching program in the controller to modify the register values, thus enabling a software switching process.

[0241] These multiple registers are the aforementioned control registers 1 to 6.

[0242] Taking chip 10, which includes a first graphics processing module 11 and a second graphics processing module 11, as an example, and taking the system screen corresponding to the first graphics processing module 11 as an example, the processing logic when switching the display screen from the system screen corresponding to the first graphics processing module 11 to the system screen corresponding to the second graphics processing module 11 based on the controller is as follows. Specifically, when the control signal pll2_cfg_fms_en is 0, the controller is used to implement the switching process.

[0243] 1. The controller receives a switching command, which instructs the display screen to switch from the system screen corresponding to the first graphics processing module 11 to the system screen corresponding to the second graphics processing module 11. In response to the switching command, the controller reads the pll2_switch_allow register. If the pll2_switch_allow register is 1, it indicates that the graphics processing module 11 is working normally and the phase-locked loop 14 is currently in a non-configured state, allowing the switching process to begin, and proceeding to the next step. If the pll2_switch_allow register is 0, it indicates that the phase-locked loop 14 is currently in a configuration state, and the switching process must wait for the phase-locked loop 14 to finish configuring before starting.

[0244] 2. The controller reads control register 6 by switching the program, writes control register 6 to 1, triggers the control signal switch_begin_1, and starts the configuration switching process of phase-locked loop 14.

[0245] 3. The controller reads control register 1 and control register 2 by switching programs. The value of control register 1 remains unchanged, and control register 2 is written to 0 to trigger the control signal gpu_sel[1]_0. The control signal gpu_sel[1]_0 instructs the second multiplexer to output the preset system screen data.

[0246] 4. The controller reads the switch_direction register by switching programs and writes the switch_direction register to 1. A switch_direction value of 1 indicates that the system screen corresponding to the second graphics processing module 11 is displayed.

[0247] 5. The controller reads bit

[30] of the BMC_PLL_CFG_0 register by switching programs, and writes bit

[30] of the BMC_PLL_CFG_0 register to 0. Bit

[30] of the BMC_PLL_CFG_0 register is used to store the value of the above control signal gpu_bypass. Writing bit

[30] of the BMC_PLL_CFG_0 register to 0 means that the control signal gpu_bypass is assigned a value of 0, thereby outputting the reference clock signal to the first graphics processing module 11 and the second graphics processing module 11.

[0248] 6. The controller reads bits [29:26] and bit

[24] of the BMC_PLL_CFG_0 register by switching programs, which is equivalent to executing step 2 in Table 1 above.

[0249] 7. The controller, through program switching, reads bits

[25] and [23:0] of the GPU1_PLL_INFO_0 register and bits [31:0] of the GPU1_PLL_INFO_1 register, and writes them to the corresponding bits in the BMC_PLL_CFG_0 and BMC_PLL_CFG_1 registers, which is equivalent to executing step 3 in Table 1 above. After executing this step, wait for 5us, and then execute the next step.

[0250] Among them, the GPU1_PLL_INFO_0 register is the second register corresponding to the second graphics processing module 11, and the BMC_PLL_CFG_0 register is the third register, thereby realizing the storage of the configuration information of the second graphics processing module 11 into the third register of the switching module 13.

[0251] 8. The controller reads bit

[24] of the BMC_PLL_CFG_0 register by switching the program and writes bit

[24] of the BMC_PLL_CFG_0 register to 0, which is equivalent to executing step 4 in Table 1 above.

[0252] 9. Wait 100µs, then proceed to the next step. Waiting 100µs assumes that PLL 14 has locked the clock signal; this step is equivalent to step 5 in Table 1 above.

[0253] 10. The controller reads bits [29:26] and bit

[30] of the BMC_PLL_CFG_0 register by switching the program, writes bits [29:26] of the BMC_PLL_CFG_0 register to 0, and writes bit

[30] of the BMC_PLL_CFG_0 register to 1, which is equivalent to executing step 6 in Table 1 above.

[0254] 11. The controller reads the switch_end register by switching the program and writes the switch_end register to 1, indicating that the configuration of phase-locked loop 14 is complete.

[0255] 12. The controller reads the pll2_switch_status register through the switching procedure. If the pll2_switch_status register is 1, it means the switching was successful and proceeds to the next step. If the pll2_switch_status register is 0, it means the switching failed and the configuration switching process of phase-locked loop 14 is re-executed.

[0256] 13. The controller, by switching programs, reads control register 1 and control register 2, writes the value of control register 1 to 1 to trigger control signal gpu_sel[0]_1, and writes control register 2 to 1 to trigger control signal gpu_sel[1]_1. Control signal gpu_sel[0]_1 instructs the first multiplexer to output system screen data received from the second graphics processing module 11. Control signal gpu_sel[1]_1 instructs the second multiplexer to output system screen data received from the first multiplexer.

[0257] 14. After completing the above process, the system screen corresponding to the second graphics processing module 11 is currently displayed. The host corresponding to the second graphics processing module 11 can change the configuration information of the second graphics processing module 11 to adjust the resolution of the system screen corresponding to the second graphics processing module 11.

[0258] It should be noted that the read and write processes of each of the above registers are all implemented through the switching program run by the controller. The values ​​of each register are read and written in sequence according to the switching program, thereby realizing the switching process based on software.

[0259] In the above scheme, during the display switching process, the registers are read and written sequentially according to the preset instructions in the switching program to trigger control signals, thereby controlling the output of the system screen data of the graphics processing module 11 corresponding to the target host to the display interface 12. This realizes display switching based on software. Since the software is configurable, the control logic can be adjusted by changing the code or configuration, thus providing greater flexibility for the display switching control process. This allows the display switching control process to adapt to different scenarios and needs, and makes it easier to achieve customized control methods.

[0260] The above-mentioned chip can be applied to various scenarios. The graphics processing module 11 in chip 10 can be connected to the host in different scenarios. The following describes two scenarios.

[0261] The first scenario: such as Figure 5As shown, the chip 10 also includes a processor 15, and multiple graphics processing modules 11 are connected to the host on the processor 15.

[0262] The chip 10 can be applied in industrial control scenarios, where it can serve as the main control chip in a computing device. For example, the chip 10 can be installed in a robot to control the robot as its main control chip.

[0263] In this scenario, the host connected to the multiple graphics processing modules 11 in chip 10 is located on chip 10. That is, the multiple graphics processing modules 11 in chip 10 are all connected to the same host inside chip 10. The host can provide different system screen data to each graphics processing module 11, thereby realizing the switching display of multiple different system screens on the same host. This makes chip 10 suitable for the use of dual-screen switching or multi-screen switching on the same host.

[0264] The second scenario: such as Figure 6 As shown, chip 10 is connected to multiple main control chips 20, and multiple graphics processing modules 11 are each connected to a host on one of the main control chips 20. For ease of demonstration, Figure 6 Taking the connection of two main control chips 20 as an example.

[0265] The chip 10 can be applied in server scenarios. In server scenarios, the chip 10 and multiple other main control chips 20 are installed on the server. The chip 10 can be used as a management chip to manage the main control chips 20 on the server.

[0266] In this scenario, the hosts connected to the multiple graphics processing modules 11 in chip 10 are located on other main control chips 20 outside of chip 10. Each graphics processing module 11 is connected to a different host on a different main control chip 20, and the hosts connected to different graphics processing modules 11 are different. Therefore, one chip 10 can provide services to multiple different main control chips 20, enabling the switching of system screens on hosts of multiple different main control chips 20, without the need to deploy separate chips for each main control chip 20, saving the number of chips, saving not only resource costs but also deployment space.

[0267] This application provides a server board, which includes a circuit board and a management chip and a main control chip mounted on the circuit board. The management chip includes multiple graphics processing modules, a display interface and a switching module. The management chip also includes an interface corresponding to each graphics processing module. The interface corresponding to each graphics processing module is used to connect the graphics processing module to the host on any main control chip. The multiple graphics processing modules are all connected to the display interface, and the display interface and the multiple graphics processing modules are all connected to the switching module.

[0268] Multiple graphics processing modules are connected to multiple hosts respectively, and are used to output the system screen data of the respective hosts to the switching module;

[0269] The switching module is used to respond to the switching command, select the graphics processing module corresponding to the target host from multiple graphics processing modules, and connect the transmission path between the graphics processing module corresponding to the target host and the display interface to output the system screen data of the graphics processing module corresponding to the target host to the display interface. The target host is the host corresponding to the system screen to be displayed.

[0270] The display interface is used to output system screen data received from the switching module.

[0271] The internal structure and processing logic of the management chip are the same as those described above. Figures 1-3 The chips shown are the same, so they will not be described in detail here.

[0272] This application embodiment also provides a server rack, which includes a rack body, a backplane, and multiple server boards mounted on the backplane. Each server board is equipped with a main control chip, and the multiple server boards are equipped with the same management chip. The management chip includes multiple graphics processing modules, a display interface, and a switching module. Each graphics processing module is connected to a host on a main control chip. The multiple graphics processing modules are all connected to the display interface, and the display interface and the multiple graphics processing modules are all connected to the switching module.

[0273] Multiple graphics processing modules are connected to multiple hosts respectively, and are used to output the system screen data of the respective hosts to the switching module;

[0274] The switching module is used to respond to the switching command, select the graphics processing module corresponding to the target host from multiple graphics processing modules, and connect the transmission path between the graphics processing module corresponding to the target host and the display interface to output the system screen data of the graphics processing module corresponding to the target host to the display interface. The target host is the host corresponding to the system screen to be displayed.

[0275] The display interface is used to output system screen data received from the switching module.

[0276] The internal structure and processing logic of the management chip are the same as those described above. Figures 1-3 The chips shown are the same, so they will not be described in detail here.

[0277] This application provides a display system including a server rack and a display device. The server rack includes multiple server boards, each equipped with a main control chip. The multiple server boards are equipped with the same management chip. The management chip includes multiple graphics processing modules, a display interface, and a switching module. Each graphics processing module is connected to a host on the main control chip, and the display interface is connected to the display device. All graphics processing modules are connected to the display interface, and both the display interface and the multiple graphics processing modules are connected to the switching module.

[0278] Multiple graphics processing modules are connected to multiple hosts respectively, and are used to output the system screen data of the respective hosts to the switching module;

[0279] The switching module is used to respond to the switching command, select the graphics processing module corresponding to the target host from multiple graphics processing modules, and connect the transmission path between the graphics processing module corresponding to the target host and the display interface to output the system screen data of the graphics processing module corresponding to the target host to the display interface. The target host is the host corresponding to the system screen to be displayed.

[0280] The display interface is used to output system screen data received from the switching module.

[0281] The internal structure and processing logic of the management chip are the same as those described above. Figures 1-3 The chips shown are the same, so they will not be described in detail here.

[0282] Figure 7 This is a flowchart of a display method provided in an embodiment of this application. The display method is applied to a chip, which can be the aforementioned... Figures 1-3 The chip shown, such as Figure 7 As shown, the method includes the following steps.

[0283] 701. Receive system screen data from the first host and system screen data from the second host, and receive configuration information from the first host and configuration information from the second host.

[0284] The system screen data of the first host is used to display the system screen of the first host, and the system screen data of the second host is used to display the system screen of the second host. The system screen data of the first host and the system screen data of the second host are different. The chip has the ability to receive different system screen data. In this embodiment, the chip can output one of the two received system screen data, one of which is the system screen data of the first host and the other is the system screen data of the second host, to display the system screen of one of the hosts.

[0285] The host's configuration information is used to configure the phase-locked loop (PLL). The PLL generates the clock signal required by the graphics processing module based on the configuration information, and the graphics processing module acquires system screen data based on the clock signal. Specifically, the PLL can generate different clock signals based on different configuration information, and the graphics processing module can acquire system screen data at different resolutions based on different clock signals. Therefore, by changing the configuration information provided by the PLL, the resolution of the acquired system screen data can be changed. In this embodiment, the first host can configure the resolution of its system screen data by providing configuration information, and the second host can configure the resolution of its system screen data by providing configuration information.

[0286] Optionally, the graphics processing module for acquiring system screen data of the first host and the graphics processing module for acquiring system screen data of the second host share a phase-locked loop. Then, after receiving the configuration information of the two hosts, the chip can provide the configuration information of the host corresponding to the system screen to be displayed to the phase-locked loop.

[0287] Optionally, the first host and the second host can be hosts inside the chip. In this case, the first host and the second host can be the same host, and the chip obtains two different system screen data provided by the same host.

[0288] Optionally, the first host and the second host can also be the host of other master control chips outside the chip. In this case, the first host and the second host are hosts of different master control chips.

[0289] 702. In response to the display command from the display device, the control chip outputs the system screen data of the first host to the display device.

[0290] The display instruction instructs the display of the system screen of the first host. The chip then provides the system screen data of the first host to the display device, and the display device displays the system screen of the first host based on the system screen data of the first host.

[0291] 703. Receive the switching command of the display device. The switching command is used to switch the display screen of the display device from the system screen of the first host to the system screen of the second host.

[0292] Among them, the switching command for the display device is triggered based on user operation.

[0293] For example, if a screen switching option is displayed on the display device, in response to the triggering operation of the screen switching option, the display device generates a switching command and sends the switching command to the chip.

[0294] 704. In response to the switching command, configure the phase-locked loop based on the configuration information of the second host.

[0295] Since it is necessary to switch the display screen to the system screen of the second host, the configuration information of the phase-locked loop (PLL) needs to be updated, changing the configuration information used by the PLL from the configuration information of the first host to the configuration information of the second host. This process of switching the configuration information used by the PLL from the configuration information of the first host to the configuration information of the second host is achieved through the control unit, configuration unit, third multiplexer, and fourth multiplexer within the chip in the above embodiment. These components enable the transmission path for transmitting the configuration information of the first host to the PLL.

[0296] In one possible implementation, in response to a switching command, the configuration information of the second host is cached, and the phase-locked loop (PLL) is configured based on the cached configuration information; if the PLL configuration is complete, the PLL is configured based on the configuration information of the second host.

[0297] During the display switching process, the configuration information of the second host may change, leading to configuration errors. To avoid this problem, the configuration information of the second host is cached before configuring the phase-locked loop (PLL). Since the cached configuration information does not change, configuring the PLL based on the cached information ensures a smooth PLL configuration process. After configuration is complete, the PLL is then configured using the second host's configuration information.

[0298] In this scheme, the configuration information of the second host is cached in advance. By providing the cached configuration information to the phase-locked loop (PLL), it can be ensured that the configuration information provided to the PLL during the configuration process is an accurate and unchanged set of information. This can improve the orderliness and accuracy of reconfiguring the PLL and help reduce the error rate in the configuration process.

[0299] Optionally, if the phase-locked loop (PLL) configuration is successful, the PLL is configured based on the configuration information of the second host after the start of the handover; if the PLL configuration fails, the PLL is configured based on the configuration information of the second host before the start of the handover.

[0300] If the phase-locked loop (PLL) configuration is successful, it means that the configuration information of the second host has not changed during the switching process. Therefore, the configuration information of the second host after the start of the switch is the same as the configuration information of the cache, which means that the configuration information of the second host after the start of the switch is the same as the configuration information currently used by the PLL. Therefore, the PLL is configured based on the configuration information of the second host after the start of the switch.

[0301] If the phase-locked loop (PLL) configuration fails, it means that the configuration information of the second host has changed during the switching process. The configuration information of the second host before the start of the switch is the same as the configuration information of the cache, which means that the configuration information of the second host before the start of the switch is the same as the configuration information currently used by the PLL. Therefore, the PLL is configured based on the configuration information of the second host before the start of the switch.

[0302] In this scheme, after the phase-locked loop (PLL) is configured, the configuration information provided to the PLL before or after the start of the switch is determined based on the PLL's configuration status. This ensures that the configuration information provided to the PLL before and after the switch is handed back to the host is consistent, thereby achieving a seamless switch of configuration rights.

[0303] In one possible implementation, in response to a switching command, the state of the phase-locked loop (PLL) is detected. If the PLL is in a non-configured state, the PLL is configured based on the configuration information of the second host. If the PLL is in a configuration state, the state of the PLL is continuously detected until it is detected to be in a non-configured state, at which point the step of configuring the PLL based on the configuration information of the second host is executed.

[0304] In this solution, the condition for reconfiguring the phase-locked loop (PLL) is that the PLL is in a non-configuration state. This prevents the PLL from being reconfigured when the host is in the configuration state, which would disrupt the original configuration progress of the PLL. This ensures the orderly progress of the PLL configuration process and helps reduce the error rate in the display switching process.

[0305] In one possible implementation, if the phase-locked loop (PLL) is not configured, the PLL is controlled to output a reference clock signal to the graphics processing module; if the PLL is configured, the PLL is controlled to output the clock signal obtained after configuration to the graphics processing module.

[0306] In this scheme, the phase-locked loop (PLL) is reconfigured upon the start of the switching process. During configuration, the PLL cannot output a stable clock signal, so a reference clock signal is provided to the graphics processing module to ensure the normal operation of its internal processing logic. After configuration, the PLL can output a stable clock signal, thus providing a stable clock signal to the graphics processing module. This allows the graphics processing module to generate accurate system screen data based on an accurate clock signal, thereby ensuring the feasibility and orderliness of the entire display switching process.

[0307] It should be noted that this embodiment only illustrates the process of switching the configuration information used by the phase-locked loop from the configuration information of the first host to the configuration information of the second host, using the example of different configuration information of the first host and the second host. In another embodiment, the configuration information of the first host and the configuration information of the second host can be the same, in which case step 704 above does not need to be performed.

[0308] 705. In response to the switching command, the control chip outputs the system screen data of the second host to the display device.

[0309] The process of switching the system screen data output by the display device from the system screen data of the first host to the system screen data of the second host is achieved through the control unit, the first multiplexer and the second multiplexer inside the chip in the above embodiment. The control unit, the first multiplexer and the second multiplexer can conduct the transmission path for transmitting the system screen data of the second host to the display device.

[0310] In one possible implementation, in response to a switching command, the phase-locked loop (PLL) is reconfigured to enable the PLL to provide a clock signal for the system screen data of the second host. During the configuration process, the control chip outputs preset system screen data to the display device. If the PLL configuration is complete, the control chip outputs the system screen data of the second host to the display device.

[0311] Optionally, if the phase-locked loop is configured and a vertical synchronization signal is detected, the control chip outputs the system screen data of the second host to the display device; wherein, the vertical synchronization signal indicates that a complete frame of system screen data of the second host has been acquired.

[0312] In this scheme, the completion of the phase-locked loop configuration means that the system screen data currently received by the second multiplexer is accurate, and the detection of the vertical synchronization signal means that the graphics processing module has output one frame of system screen data and is about to output the next frame of system screen data. Therefore, when the above two conditions are met, the logic of outputting the system screen data of the second host is executed. This can both avoid displaying incorrect system screens and ensure that the displayed system screen is a complete frame, thus improving the display switching effect.

[0313] In this embodiment, the chip receives system screen data from two hosts. Upon receiving a switching command, the chip's internal processing logic switches the output of system screen data from the first host to the second host, causing the display device to switch from displaying the system screen of the first host to displaying the system screen of the second host. Therefore, this application uses only one chip to achieve switching between different system screens on the display device, eliminating the need for an external KVM switch. The switching logic is completed internally within the chip, reducing costs and saving resources.

[0314] In this application, the terms "first," "second," etc., are used to distinguish identical or similar items with substantially the same function. It should be understood that there is no logical or temporal dependency between "first," "second," and "nth," nor does it limit the quantity or execution order. It should also be understood that although the following description uses the terms "first," "second," etc., to describe various elements, these elements should not be limited by the terms. These terms are merely used to distinguish one element from another. For example, without departing from the various examples described, a first operator can be referred to as a second operator, and similarly, a second operator can be referred to as a first operator. Both the first and second operators can be operators, and in some cases, they can be separate and distinct operators.

[0315] In this application, the term "at least one" means one or more, and the term "multiple" means two or more. For example, multiple operators means two or more operators.

[0316] The above description is merely a specific embodiment of this application, but the scope of protection of this application is not limited thereto. Any person skilled in the art can easily conceive of various equivalent modifications or substitutions within the technical scope disclosed in this application, and these modifications or substitutions should all be covered within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

[0317] In the above embodiments, implementation can be achieved, in whole or in part, through software, hardware, firmware, or any combination thereof. When implemented in software, it can be implemented, in whole or in part, in the form of program structure information. This program structure information includes one or more program instructions. When these program instructions are loaded and executed on a computing device, the processes or functions according to the embodiments of this application are generated, in whole or in part.

[0318] Those skilled in the art will understand that all or part of the steps of the above embodiments can be implemented by hardware or by a program instructing related hardware. The program can be stored in a computer-readable storage medium, such as a read-only memory, a disk, or an optical disk.

[0319] The above-described embodiments are only used to illustrate the technical solutions of this application, and are not intended to limit it. Although this application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of this application.

Claims

1. A chip, characterized by The chip comprises a plurality of graphic processing modules, a display interface and a switching module, the plurality of graphic processing modules are connected with the display interface, and the display interface and the plurality of graphic processing modules are connected with the switching module; The plurality of graphic processing modules are connected with a plurality of hosts respectively, and are used for outputting system picture data of the host connected respectively to the switching module; The switching module is used for selecting a graphic processing module corresponding to a target host from the plurality of graphic processing modules in response to a switching instruction, and conducting a transmission path between the graphic processing module corresponding to the target host and the display interface, so as to output system picture data of the graphic processing module corresponding to the target host to the display interface, wherein the target host is a host corresponding to a system picture to be displayed; The display interface is used for outputting the system picture data received from the switching module.

2. The chip according to claim 1, characterized in that, The switching module comprises a first multiplexer group and a control unit, the plurality of graphic processing modules, the control unit and the display interface are connected with the first multiplexer group; The control unit is used for controlling the first multiplexer group to output system picture data from the graphic processing module indicated by the control unit in the received system picture data to the display interface in response to the switching instruction.

3. The chip of claim 2, wherein, The first multiplexer group comprises a first multiplexer and a second multiplexer, the plurality of graphic processing modules and the control unit are connected with the first multiplexer, and the first multiplexer, the control unit and the display interface are connected with the second multiplexer; The control unit is used for instructing the first multiplexer to output system picture data received from the graphic processing module corresponding to the target host in response to the switching instruction; The control unit is also used for instructing the second multiplexer to output preset system picture data if a phase-locked loop is not configured, and instructing the second multiplexer to output system picture data received from the first multiplexer if the phase-locked loop is configured, wherein the phase-locked loop is used for providing a clock signal to the plurality of graphic processing modules; The first multiplexer is used for outputting the system picture data indicated by the control unit in the received system picture data to the second multiplexer; The second multiplexer is used for outputting the system picture data indicated by the control unit in the received system picture data to the display interface.

4. The chip of claim 3, wherein The plurality of graphic processing modules are also used for outputting a vertical synchronization signal to the control unit after outputting a frame of system picture data; The control unit is used for instructing the second multiplexer to output system picture data received from the first multiplexer if the phase-locked loop is configured and the vertical synchronization signal of the graphic processing module corresponding to the target host is received.

5. The chip of claim 1, wherein The chip further comprises a phase-locked loop, and the plurality of graphic processing modules are connected with the phase-locked loop, and the phase-locked loop is connected with the switching module; The plurality of graphic processing modules are configured to output system picture data to the switching module based on the received clock signal, and output configuration information provided by the host connected thereto to the switching module. The switching module is further configured to turn on a transmission path between the graphic processing module corresponding to the target host and the phase-locked loop, so as to output the configuration information of the graphic processing module corresponding to the target host to the phase-locked loop. The phase-locked loop is configured to be configured by the configuration information received from the switching module, and output a clock signal to the plurality of graphic processing modules.

6. The chip of claim 5, wherein, The switching module comprises a second multiplexer group and a control unit, and the plurality of graphic processing modules, the control unit and the phase-locked loop are connected to the second multiplexer group. The control unit is configured to instruct the second multiplexer group to output the configuration information received from the graphic processing module corresponding to the target host. The second multiplexer group is configured to output the configuration information from the graphic processing module instructed by the control unit in the received configuration information to the phase-locked loop.

7. The chip of claim 6, wherein The second multiplexer group comprises a third multiplexer and a fourth multiplexer, the plurality of graphic processing modules and the control unit are connected to the third multiplexer, and the third multiplexer, the control unit and the phase-locked loop are connected to the fourth multiplexer. The control unit is configured to cache the configuration information of the graphic processing module corresponding to the target host, and output the cached configuration information to the fourth multiplexer. The control unit is further configured to instruct the third multiplexer to output the configuration information received from the graphic processing module corresponding to the target host. The control unit is further configured to instruct the fourth multiplexer to output the configuration information received from the control unit if the phase-locked loop is not configured, and instruct the fourth multiplexer to output the configuration information received from the third multiplexer if the phase-locked loop is configured. The third multiplexer is configured to output the configuration information instructed by the control unit in the received configuration information to the fourth multiplexer. The fourth multiplexer is configured to output the configuration information instructed by the control unit in the received configuration information to the phase-locked loop.

8. The chip of claim 7, wherein, The control unit is configured to output each item of the cached configuration information to the fourth multiplexer one by one.

9. The chip of claim 7, wherein, The switching module further comprises a plurality of configuration units, each of the graphic processing modules is connected to a corresponding configuration unit, and the control unit and the third multiplexer are connected to each of the configuration units. The plurality of graphic processing modules are configured to output configuration information before switching and configuration information after switching to the configuration unit connected thereto. The control unit is configured to instruct each of the configuration units to output the configuration information after switching if the phase-locked loop is configured successfully. The control unit is further configured to instruct each of the configuration units to output the configuration information before switching if the phase-locked loop is configured unsuccessfully. The plurality of configuration units are configured to output the configuration information indicated by the control unit in the received configuration information to the third multiplexer.

10. The chip of claim 9, wherein, The configuration unit comprises a first register and a fifth multiplexer, the graphic processing module, the third multiplexer, the control unit and the first register are connected with the fifth multiplexer, and the graphic processing module and the control unit are connected with the first register. The graphic processing module is configured to output configuration information before switching to the first register and output configuration information after switching to the fifth multiplexer. The first register is configured to store the configuration information received from the graphic processing module and output the stored configuration information to the fifth multiplexer. The fifth multiplexer is configured to output the configuration information indicated by the control unit in the received configuration information to the third multiplexer.

11. The chip of claim 7, wherein, The graphic processing module comprises a second register, and the switching module further comprises a third register, and the second register stores configuration information of the graphic processing module. The control unit is configured to store the configuration information in the second register to the third register. The third register is configured to output the stored configuration information to the fourth multiplexer.

12. The chip of claim 5, wherein, The switching module is configured to detect the state of the phase-locked loop, and if the phase-locked loop is in a non-configuration state, turn on the transmission path between the graphic processing module corresponding to the target host and the phase-locked loop to output the configuration information of the graphic processing module corresponding to the target host to the phase-locked loop.

13. The chip of claim 5, wherein, The switching module is configured to control the phase-locked loop to output a reference clock signal to the plurality of graphic processing modules if the phase-locked loop is not configured. The switching module is configured to control the phase-locked loop to output a clock signal generated after configuration to the plurality of graphic processing modules if the phase-locked loop is configured.

14. The chip of claim 1, wherein, The switching module comprises a logic circuit and a plurality of registers connected in sequence. The logic circuit is configured to assign a first register to trigger a first control signal, and in response to the first control signal, assign a next register connected to the first register to trigger a next control signal; wherein the control signal is used to turn on the transmission path between the graphic processing module corresponding to the target host and the display interface to output system picture data of the graphic processing module corresponding to the target host to the display interface.

15. The chip of claim 1, wherein, The switching module comprises a controller and a plurality of registers. The controller is configured to run a switching program, and read and write the plurality of registers in sequence through the switching program to trigger a plurality of control signals; wherein the control signal is used to turn on the transmission path between the graphic processing module corresponding to the target host and the display interface to output system picture data of the graphic processing module corresponding to the target host to the display interface.

16. The chip of claim 1, wherein, The chip comprises a processor, and the plurality of graphic processing modules are connected with the host on the processor.

17. The chip of claim 1, wherein, The chip is connected with a plurality of master control chips, and the plurality of graphic processing modules are respectively connected with the host on one master control chip.

18. A server single board, characterized by The server single board comprises a circuit board and a management chip and a master control chip mounted on the circuit board, the management chip comprises a plurality of graphic processing modules, a display interface and a switching module, the management chip further comprises an interface corresponding to each graphic processing module, and the interface corresponding to the graphic processing module is used for connecting the graphic processing module with a host on any master control chip; the plurality of graphic processing modules are connected with the display interface, and the display interface and the plurality of graphic processing modules are connected with the switching module; The plurality of graphic processing modules are respectively connected with a plurality of hosts, and are used for outputting system picture data of the host connected with each graphic processing module to the switching module; The switching module is used for selecting a graphic processing module corresponding to a target host from the plurality of graphic processing modules in response to a switching instruction, and turning on a transmission path between the graphic processing module corresponding to the target host and the display interface, so as to output system picture data of the graphic processing module corresponding to the target host to the display interface, wherein the target host is a host corresponding to a system picture to be displayed; The display interface is used for outputting the system picture data received from the switching module.

19. A server cabinet characterized by The server cabinet comprises a cabinet body, the cabinet body comprises a back plate, and the server cabinet further comprises a plurality of server single boards mounted on the back plate, the server single boards are mounted with master control chips, the plurality of server single boards are mounted with the same management chip, the management chip comprises a plurality of graphic processing modules, a display interface and a switching module, each graphic processing module is connected with a host on a master control chip; the plurality of graphic processing modules are connected with the display interface, and the display interface and the plurality of graphic processing modules are connected with the switching module; The plurality of graphic processing modules are respectively connected with a plurality of hosts, and are used for outputting system picture data of the host connected with each graphic processing module to the switching module; The switching module is used for selecting a graphic processing module corresponding to a target host from the plurality of graphic processing modules in response to a switching instruction, and turning on a transmission path between the graphic processing module corresponding to the target host and the display interface, so as to output system picture data of the graphic processing module corresponding to the target host to the display interface, wherein the target host is a host corresponding to a system picture to be displayed; The display interface is used for outputting the system picture data received from the switching module.

20. A display system, comprising: The display system comprises a server cabinet and a display device, the server cabinet comprises a plurality of server single boards, the server single boards are mounted with master control chips, the plurality of server single boards are mounted with the same management chip, the management chip comprises a plurality of graphic processing modules, a display interface and a switching module, each graphic processing module is connected with a host on a master control chip, and the display interface is connected with the display device; the plurality of graphic processing modules are connected with the display interface, and the display interface and the plurality of graphic processing modules are connected with the switching module; The plurality of graphic processing modules are connected with a plurality of hosts respectively, and are configured to output system picture data of the host connected therewith to the switching module; The switching module is configured to select a graphic processing module corresponding to a target host from the plurality of graphic processing modules in response to a switching instruction, and to turn on a transmission path between the graphic processing module corresponding to the target host and the display interface, so as to output system picture data of the graphic processing module corresponding to the target host to the display interface, the target host being a host corresponding to a system picture to be displayed; The display interface is configured to output the system picture data received from the switching module.

21. A display method characterized by comprising: The method is applied to a chip, and the method comprises: receiving system picture data of a first host and system picture data of a second host; in response to a display instruction of a display device, controlling the chip to output the system picture data of the first host to the display device; receiving a switching instruction of the display device, the switching instruction being used to switch a display picture of the display device from the system picture of the first host to the system picture of the second host; in response to the switching instruction, controlling the chip to output the system picture data of the second host to the display device.

22. The method of claim 21, wherein, The response to the switching instruction and the control of the chip to output the system picture data of the second host to the display device comprise: in response to the switching instruction, starting reconfiguration of a phase-locked loop, so that the phase-locked loop provides a clock signal of the system picture data of the second host; in a configuration process, controlling the chip to output data of a preset system picture to the display device; if the phase-locked loop is configured, controlling the chip to output the system picture data of the second host to the display device.

23. The method of claim 22, wherein, The control of the chip to output the system picture data of the second host to the display device if the phase-locked loop is configured comprises: if the phase-locked loop is configured and a vertical synchronization signal is detected, controlling the chip to output the system picture data of the second host to the display device; wherein the vertical synchronization signal indicates that a complete frame of system picture data of the second host has been acquired.

24. The method of claim 21, wherein, The method further comprises: receiving configuration information of the first host and configuration information of the second host; in response to the switching instruction, configuring the phase-locked loop based on the configuration information of the second host.

25. The method of claim 24, wherein, The response to the switching instruction and the configuration of the phase-locked loop based on the configuration information of the second host comprise: in response to the switching instruction, buffering the configuration information of the second host, and configuring the phase-locked loop based on the buffered configuration information; if the phase-locked loop is configured, configuring the phase-locked loop based on the configuration information of the second host.

26. The method of claim 25, wherein, The configuration of the phase-locked loop based on the configuration information of the second host comprises: if the phase-locked loop is configured successfully, configuring the phase-locked loop based on configuration information of the second host after the switching starts, and if the phase-locked loop is configured unsuccessfully, configuring the phase-locked loop based on configuration information of the second host before the switching starts.

27. The method of claim 24, wherein, The response to the switching instruction, the configuration information of the second host based on the phase-locked loop, comprising: In response to the switching instruction, the state of the phase-locked loop is detected, and if the phase-locked loop is in a non-configuration state, the phase-locked loop is configured based on the configuration information of the second host.

28. The method of claim 24, wherein, The method further comprises: If the phase-locked loop is not configured, the phase-locked loop is controlled to output a reference clock signal to the graphics processing module; If the phase-locked loop is configured, the phase-locked loop is controlled to output a clock signal obtained after configuration to the graphics processing module.

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