Current type CMOS parallel prefix adder and multi-bit adder circuit

Abstract

The invention discloses a current type CMOS (Complementary Metal Oxide Semiconductor) parallel prefix adder and a multi-bit adder circuit. The current type CMOS parallel prefix adder comprises a weighted value generation circuit, an approximate carry generation circuit and a current type adder without carry output. According to the current type CMOS parallel prefix approximate adder provided by the invention, a carry chain is cut off, a small number of reserved low-order signals are subjected to self-defined weighting, and error accumulation caused by transistor mismatch during multi-stage connection of a current type adder circuit is reduced by applying approximate parallel prefix calculation of carry signals. Signal processing is based on a current signal comparator, and the characteristic that a comparison value is easy to change is achieved, so that a multi-bit addition circuit capable of controlling approximate tendency is easy to design without causing excessive extra overhead, a simple circuit structure can still be kept, and the accumulation problem of calculation errors can be remarkably reduced in accumulation application under the condition of effective control.

Description

Technical Field

[0001] This invention belongs to the field of circuit electronics technology and relates to a current-type CMOS parallel prefix adder and a multi-bit adder circuit. Background Technology

[0002] In the development of modern integrated circuits, the number of transistors integrated per unit area of ​​a chip is increasing daily. Simultaneously, with the development of fields such as deep learning and artificial intelligence, the number of bits required for information processing each year is exploding, reaching orders of magnitude. Efficiently processing this ever-increasing data demand has led to a sharp increase in power consumption and complexity. In the field of modern digital circuits and computer systems, adders are one of the important basic arithmetic units and the foundation for higher-order operations such as multiplication and integration. Traditional precise adders, while pursuing high-precision calculation results, often come at the cost of high hardware resource consumption, large power consumption, and relatively long computational latency. With the rapid development of technology, in many emerging application scenarios such as multimedia processing, artificial intelligence, big data analysis, and some embedded systems where computational accuracy requirements are not absolutely stringent but speed, power consumption, and resource utilization are strictly limited, the design concept of traditional precise adders faces new challenges and scrutiny.

[0003] As an innovative computational method, the approximate adder (AxA) circuit has emerged, relaxing the requirement for absolute accuracy in calculation results to some extent. Through clever algorithm optimization and circuit structure design, it can significantly improve computational speed or reduce hardware complexity and power consumption. In many practical applications, the data itself has a certain tolerance for error, and minor computational deviations will not have a substantial adverse impact on the final system performance or user experience. For example, in image and video processing, subtle approximations of color values ​​or pixel coordinates may not be perceptible to the human eye; similarly, in the training process of deep learning, approximations of some intermediate results may not significantly affect the convergence and accuracy of the model.

[0004] Compared to voltage-type circuits, current-mode circuits can operate at higher frequencies with less power consumption variation with frequency, resulting in a smaller increase in power consumption. They also eliminate the need for high-impedance nodes, reducing the number of transistors required. Since current signals can be added and subtracted relatively easily using only wires, and because current-mode signals are easier to identify and design within a wider signal range, they offer significant advantages in arithmetic and high-dimensional logic operations, while also allowing operation at lower voltages.

[0005] Furthermore, current-mode circuits possess unique high noise tolerance, and the swing and ripple of the output signal are less affected by voltage fluctuations. Their inherent characteristics, coupled with the ease of obtaining different logic values, make them highly promising for improving circuit speed and reducing power consumption. Adder circuits are an important part of combinational logic circuits, often serving as fundamental or frequently used units in computer devices and offline embedded systems.

[0006] With the development of integrated circuits, the integrated circuit industry continues to move towards smaller process nodes. The technological challenges of the post-Moore's Law era have shifted from simple scale reduction to the comprehensive optimization of power consumption, performance, and area (PPA). Traditional voltage-mode complementary metal-oxide-semiconductor (CMOS) design methods have shown significant limitations in practice: the rate of threshold voltage reduction lags behind the requirements of process size miniaturization, resulting in reduced dynamic voltage regulation margin; at the same time, the static power consumption problem caused by subthreshold leakage current is becoming increasingly prominent, and interconnect delay has become a key factor restricting system performance in deep submicron processes. These challenges are particularly pronounced in advanced application areas requiring high-throughput data processing, such as artificial intelligence accelerators, high-speed wireless communication baseband chips, and real-time image processing systems, which place almost contradictory design requirements on arithmetic units: achieving extremely high computational throughput while strictly controlling energy consumption budgets.

[0007] In terms of performance, replacing basic ripple carry adders with advanced structures such as carry-lookahead and parallel prefixes can significantly reduce critical path latency, supporting processor designs with higher clock speeds. In terms of power consumption, various researchers have proposed optimized carry chain logics that effectively reduce the number of transistors and switching activities, lowering dynamic power consumption. Continuously exploring optimization paths for adders has become a core technological direction for overcoming power wall limitations and extending Moore's Law performance curve. With the development of deep learning, computational demands have increased exponentially, and the increase in the number of bits has made parallel prefix logic increasingly large. The design complexity of precise parallel prefix adders is also increasing. Applications requiring high speed and efficiency, as well as fault tolerance, have driven the development of approximate parallel prefix adders (AxPPAs).

[0008] However, existing computational optimization schemes still have certain problems, such as: approximate calculations are always too small. Many researchers' designs consistently yield results smaller than the exact results, or the tendency for approximation remains constant, which can easily lead to error accumulation during multiple additions.

[0009] Therefore, this invention addresses the problem of always underestimating the value in approximate calculations by introducing an approximate parallel method based on dynamic control prediction through current-type threshold control technology. It discusses the nonlinear relationship between approximate accuracy and the number of parameters and proposes a CMOS current-type parallel prefix approximate adder. Summary of the Invention

[0010] The purpose of this invention is to address the shortcomings of existing technologies by proposing a current-type CMOS parallel prefix approximation adder and its design method, and to cascade m of the above-mentioned current-type CMOS parallel prefix adders to form an m-bit adder circuit; the aim is to reduce the cumulative deviation problem in approximation calculations by changing the circuit design.

[0011] A current-mode CMOS parallel prefix approximation adder includes a weighted value generation circuit, an approximate carry generation circuit, and a current-mode adder without carry output. The weighted value generation circuit uses one NMOS current mirror with the same width-to-length ratio and n PMOS current mirrors with width-to-length ratios corresponding to custom relative weighting values ​​to obtain output currents of different multiples of the input signal. Preferably, n=2 or 3.

[0012] The approximate carry generation circuit consists of an NMOS current mirror with the same aspect ratio and a current-type comparator with an externally controllable threshold. An external signal controls the comparator threshold, causing the output value of the approximate carry generation circuit to be correlated with both the output of the weighted value generation circuit and the external control signal. An additional input terminal and comparator are set up to detect the external control signal. The threshold is adjusted based on the external signal to make the carry generation result biased; increasing the threshold yields an approximate result less than or equal to the true value, while decreasing the threshold yields an approximate result greater than or equal to the true value. Furthermore, a specific comparator threshold is determined based on a preset carry chain cutoff number.

[0013] The current-mode adder without carry output is a current-mode full adder that discards carry output.

[0014] Each bit's weighting value generation circuit generates n relative weighting values ​​corresponding to n current mirrors, which are connected to the approximate carry generation circuits from the current stage to the corresponding higher (n-1) stages. The approximate carry value is then determined by the fixed threshold of the threshold comparator corresponding to each approximate carry generation circuit, resulting in the approximate input carry. The current stage's input signal and the approximate input carry output from the current stage's approximate carry generation circuit are input to the input of a current-type adder without carry output, and summed to obtain the current stage's output.

[0015] Furthermore, the approximate carry generation circuit shares the reference current with the current-type adder without carry output, which can save transistor and power consumption.

[0016] Furthermore, in the current-mode CMOS parallel prefix approximation adder, an NMOS transistor with the same width-to-length ratio as the input terminal of the current-mode adder is used to replicate the current input signal and compare it with the adder threshold to obtain the output of this stage.

[0017] Cascade m of the aforementioned current-mode CMOS parallel prefix adders to form an m-bit current-mode parallel prefix approximation adder circuit. In the m-bit adder circuit, the number of replicated currents generated by the different weighted values ​​of the input signal for each bit ranges from {1, n}. By connecting the corresponding weighted values ​​of the input signals of this stage and the lower n-1 stages to the input terminal of the approximate carry generation circuit of this stage, the values ​​are replicated by a current mirror and compared with a preset threshold to obtain the approximate input carry. The output of this bit is then calculated from the approximate input carry and the input signal. Furthermore, the preset threshold is dynamically changed by different external inputs.

[0018] Furthermore, a follower circuit is added to the circuit connection. The function of the follower circuit is to output the signal through a MOS transistor with a smaller aspect ratio, which can effectively reduce noise in the subsequent stages of the connection. The signal is received and replicated through a current mirror composed of NMOS transistors with a larger aspect ratio, reducing the error in the signal reception process. Then, the error at the next stage signal reception is reduced by replicating and outputting the signal through a current mirror composed of PMOS transistors with a smaller aspect ratio.

[0019] The design method for the current-mode CMOS parallel prefix approximation adder includes the following steps: First, based on the target accuracy and data characteristics, a relative weighting value is defined for each low-order bit corresponding to the high-order bit. A single-bit weighting value generation circuit is designed, which internally consists of current signals from multiple current mirrors with different transistor parameters.

[0020] The relative weighting value is the current mirror replication factor of adjacent lower bits. The current mirror replication factor for generating the first current signal is n, meaning the width-to-length ratio of the PMOS transistor flowing through the current mirror is n times that of the PMOS transistor flowing through the input current. The current mirror replication factor for generating the first current signal is 0.5n, meaning the width-to-length ratio of the PMOS transistor flowing through the current mirror is 0.5n times that of the PMOS transistor flowing through the input current.

[0021] Then, based on the relative weighting value and the target accuracy, the threshold of the comparator inside the approximate carry generation circuit is determined; based on the characteristics and quantity of the signal generated by the weighting value generation circuit, the difference between the two thresholds of the approximate carry generation circuit is determined.

[0022] Taking the weighted value generation circuit generating two current signals as an example, with replication factors of 1 and 2 respectively, the input signal of the carry generation circuit for the i-th bit is twice the input signal of the (i-1)-th bit and the sum of the input signals of the (i-2)-th bit, i.e., the input signal range is {0-6}. The approximate carry generation circuit internally sets two comparison thresholds, 2I0 and 3I0, corresponding to the high and low approximation bias of the carry generation circuit, respectively. An additional input terminal and comparator are set to detect external control signals. When the external signal is detected as high, the internal comparator threshold of the carry generation circuit is set to 3I0, i.e., the predicted carry is either too small or too accurate; when the external signal is detected as low, the internal comparator threshold of the carry generation circuit is set to 2I0, i.e., the predicted carry is either too large or too accurate.

[0023] Finally, the weighted value generation circuit, the approximate carry generation circuit, and the current-type adder without carry output are combined to obtain a current-type CMOS parallel prefix adder.

[0024] The current-mode CMOS parallel prefix approximation adder designed in this invention systematically integrates the high-speed switching characteristics of current logic, the computational parallelism advantages of parallel prefix networks, and the fault-tolerant design concept of approximation calculation theory, aiming to provide a new basic arithmetic unit architecture scheme for next-generation high-performance energy-sensitive chips.

[0025] Similar to voltage-mode parallel prefix adders, the design complexity and area overhead of current-mode parallel prefix adders remain highly dependent on the number of bits required for computation. Therefore, carry approximation of current-mode parallel prefix adders not only removes the nonlinear relationship between transistor overhead and the number of bits but also helps mitigate the impact of transistor mismatch. The current-mode CMOS parallel prefix approximation adder proposed in this invention reduces the error accumulation caused by transistor mismatch in multi-stage current-mode adder circuits by cutting off the carry chain and performing custom weighting on the few remaining low-order signals, using approximate parallel prefix calculation of the carry signal. Since its signal processing is based on a current signal comparator, which allows for easy modification of the comparison value, it is easy to design multi-bit adder circuits with controllable approximation bias without incurring excessive additional overhead, while maintaining a simple circuit structure. Under effective control, it can significantly reduce the accumulation of computational errors in accumulation applications.

[0026] Compared to traditional voltage-mode adder architectures, current-mode CMOS parallel prefix approximation adders exhibit significant differences in their operating mechanisms and performance characteristics. Traditional voltage-mode precise adders rely on full-swing charging and discharging of node capacitors to achieve logic state transitions. Their propagation delay is strongly correlated with the supply voltage, and simultaneous switching of large-scale gates leads to significant dynamic power consumption and synchronous switching noise. In contrast, current-mode approximation adders employ a constant bias operating mechanism. This operating mode allows for rapid state transitions with significantly reduced internal voltage swings, resulting in superior speed characteristics and frequency performance. Their symmetrical architecture not only provides inherent common-mode immunity and improves signal integrity but also provides a natural physical foundation for multi-signal transmission in parallel prefix tree structures. The parallel prefix algorithm optimizes the carry propagation path computationally, while the introduction of approximation methods effectively reduces circuit complexity and transistor count through selective precision compromises. This multi-level collaborative design approach ultimately optimizes key indicators such as speed, power consumption, and area at the system level, and its overall performance surpasses the conventional design methods of traditional voltage-type precise adders and existing approximate adder architectures.

[0027] Meanwhile, based on the current mirror to generate the required weighting value, the current mirror can be used to replicate the current. Under the same base connection, the drain current of the MOSFET is proportional to the channel width-to-length ratio. By adjusting the transistor size, a mirror current that is multiple can be obtained. Furthermore, the characteristic that current-type signals are easy to add also makes weighting easy to implement. Attached Figure Description

[0028] Figure 1 This is a block diagram of a four-bit current-mode CMOS parallel prefix approximation adder circuit. Figure 2 This is a circuit diagram of the weighted value generation circuit in the embodiment; Figure 3 The circuit diagram of the approximate carry generation circuit in the embodiment is shown below; Figure 4 The circuit diagrams for the approximate carry generation circuit and the current-type adder without carry output are shown in the embodiments. Detailed Implementation

[0029] The present invention will be further described below with reference to the accompanying drawings.

[0030] In this embodiment, as shown in... Figure 1 The following is an example of a four-bit current-mode CMOS parallel prefix approximation adder circuit to illustrate a specific implementation of the present invention. The external control signal and the two lower-level input signals of this bit jointly determine the output value of the carry generation circuit. This bit's input signal and the output of the carry generation circuit are connected to the input terminal of the adder, which calculates the sum of this bit.

[0031] like Figure 2 As shown, in this embodiment, the weighting value generation circuit for each bit includes one NMOS current mirror with the same width-to-length ratio and three PMOS current mirrors with custom relative weighting values ​​corresponding to the width-to-length ratio to obtain different multiples of the input signal output current.

[0032] In the diagram, the drain of N1 is used to receive the evaluation signal (In) of this stage. N2 has the same width-to-length ratio as N1, and P1 has the same width-to-length ratio as P2. P2 is connected to the local input terminal out1 for local summation. The width-to-length ratio of transistors P3 and P4 is set to the corresponding multiple of the current of the required output weight and the reference current of P1, so that the current with the required weight can be copied and connected to the prefix calculation circuit. In this embodiment, the width-to-length ratio of transistor P3 is 0.3 times that of P1, and its output out2 is connected to the carry generation circuit of the next higher stage. The width-to-length ratio of transistor P4 is 0.15 times that of P1, and its output out3 is connected to the carry generation circuit of the next two higher stages.

[0033] like Figure 3 As shown, in this embodiment, the approximate carry generation circuit for each bit includes two NMOS current mirrors with the same width-to-length ratio and four PMOS current mirrors with a width-to-length ratio customized according to the carry logic.

[0034] In the diagram, the drain of N3 is used to receive external control signals (Con). N3 and N4 have the same width-to-length ratio. The width-to-length ratio of P6 is set to 0.5 times that of P5. N5 and N6 have the same width-to-length ratio. The width-to-length ratio of P7 is set to 0.4 times that of P5. The width-to-length ratio of P8 is set to 0.1 times that of P5. The width-to-length ratio of P9 is the same as that of P5.

[0035] The approximate carry generation consists of two stages: external signal control of the internal threshold and threshold carry calculation of the carry signal. The external control signal Con is connected to the drain of transistor N1 and then to its gate. The current mirror formed by N1 and N2 replicates the same current and compares it with the reference current I0 threshold. When the input current is greater than the corresponding reference current, the corresponding internal threshold control transistor P10 is turned on; conversely, when the input current is less than the corresponding reference current, the corresponding internal threshold control transistor P10 is turned off. The low-order weighted signal is input to the drain of transistor N3 and then to its gate. The current mirror formed by N3 and N4 replicates the same current and compares it with the carry threshold current. When the input current is greater than the corresponding carry threshold current, the corresponding internal threshold control transistor P11 is turned on, outputting a carry signal of 10uA; conversely, when the input current is less than the corresponding reference current, the corresponding internal threshold control transistor P11 is turned off, outputting a carry signal of 0uA.

[0036] In is the low-order weighted input terminal, and Con is the control signal input terminal. When the Con input signal is high (10uA), the P10 transistor is turned on, and the low-order weighted value is compared with the threshold of 0.5 to determine the carry value. The output result is accurate or slightly smaller. When the Con input signal is low (0uA), the P10 transistor is turned off, and the low-order weighted value is compared with the threshold of 0.4. The output result is accurate or slightly larger.

[0037] like Figure 4 As shown, in this embodiment, the approximate carry generation circuit and the current-type adder without carry output share the reference current, which can save transistor and power consumption.

[0038] In the diagram, InC is the input terminal of the approximate carry generation circuit, and Cout is the output terminal of the approximate carry generation circuit, which is also the input carry signal. Cout, together with the two-bit summation input signal Out1, constitutes the input signal In, and S is the summation output of this bit.

[0039] The Monte Carlo analysis was performed on the 4-bit adder circuits designed by the approximate adder described in this invention and three existing approximate adders (voltage-type dynamic precision adjustable adder ACFA, variable precision approximate full adder DFMA, and voltage-type parallel prefix approximate adder AxPPA) in Matlab. The experimental data are shown in Table 1.

[0040] Table 1 Simulation results of 4-bit binary summation encoding Experimental results show that the addition circuit designed with the approximate adder proposed in this invention can effectively suppress the deviation of the result caused by the accumulation of error in the accumulation, and the total value error is significantly reduced in high-order accumulation calculations.

[0041] Those skilled in the art, upon learning of this invention, may make substitutions or modifications without departing from the scope of protection of the claims of this invention, all of which fall within the protection scope of this invention. The scope of protection of this invention shall be determined by the appended claims.

Claims

1. A current-mode CMOS parallel prefix approximate adder, characterized by: The current-mode adder without carry output is a current-mode full adder which discards carry output. The weighted value generating circuit of each bit generates n relative weighted values corresponding to n current mirrors, which are connected to the approximate carry generating circuits of the corresponding high n-1 levels from the current level. The approximate carry generating circuit judges the approximate carry value according to the fixed threshold of the threshold comparator, and obtains the approximate input carry. The comparator threshold value of a certain fixed value is determined according to the preset carry chain cutting bit number. The approximate carry generating circuit and the current-mode adder without carry output share a reference current. In the current-mode CMOS parallel prefix approximate adder, the NMOS tube with the same width-length ratio as the input end of the current-mode adder is used to copy the current input signal and compare it with the adder threshold to obtain the current output.

2. The current-mode CMOS parallel prefix approximate adder of claim 1, wherein: In the m-bit adder circuit, the number of different weighted value copy currents generated by each bit of input signal ranges from 1 to n; by connecting the corresponding weighted values of the current and low n-1 level input signals to the input end of the current level approximate carry generating circuit, the approximate input carry is obtained by comparing the copied current with the preset comparator threshold; then the approximate input carry and the input signal are used to calculate the current output.

3. The current-mode CMOS parallel prefix approximate adder of claim 1, wherein: The preset comparator threshold value is dynamically changed by different external input controls.

4. The current-mode CMOS parallel prefix approximate adder of claim 1, wherein: In the circuit connection, a follower circuit is added, which can effectively reduce the noise of the later stage in the connection by outputting the output signal from a MOS tube with a smaller width-length ratio; the error in the signal receiving process is reduced by receiving and copying the signal through a current mirror composed of a NMOS tube with a larger width-length ratio, and then the error at the next signal receiving place is reduced by copying and outputting through a current mirror composed of a PMOS tube with a smaller width-length ratio.

5. The m-bit current-mode parallel prefix approximate adder circuit is formed by cascading m current-mode CMOS parallel prefix adders; characterized in that: Specifically, the steps include:

6. The m-bit current-mode parallel-prefix approximate-addition circuit of claim 5, wherein: First, according to the target accuracy and data characteristics, the relative weighted values of each low bit corresponding to the high bit are defined; the weighted value generating circuit of a single bit is designed, which is composed of current signals of different transistor parameters composed of multiple current mirrors inside the single weighted value generating circuit; 7. The m-bit current-mode parallel-prefix approximate-addition circuit of claim 5, wherein: ​ 8. The design method of current-mode CMOS parallel prefix approximate adder as claimed in claim 1, wherein: ​ ​ Then, according to the relative weighting value and the target precision, the internal comparator threshold of the approximate carry generation circuit is determined; according to the characteristics and quantity of the signal generated by the weighting value generation circuit, the double threshold difference of the approximate carry generation circuit is determined; Finally, the weighting value generation circuit, the approximate carry generation circuit and the current-mode adder without carry output are combined to obtain the current-mode CMOS parallel prefix approximate adder.

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