Task processing method and device, electronic equipment and storage medium
By generating the mapping relationship between sample data and storage area through asynchronous processing of the central processing unit, the problem of low efficiency in sample data query and update during neural network model training is solved, thereby improving the efficiency of model training.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-12-12
- Publication Date
- 2026-03-10
AI Technical Summary
During the training of neural network models, the low efficiency of querying and updating sample data stored in GPU memory has become a bottleneck restricting the execution efficiency of model training tasks.
The central processing unit (CPU) asynchronously calls the first thread to perform address allocation operations, generates the mapping relationship between the sample data identifier and the storage area, and sends it to the target processor, such as the GPU, after the operation is completed, thereby reducing the frequency of the target processor's access to global memory.
It improved the efficiency of model training, reduced the time for data querying and updating, and increased the overall training speed.
Smart Images
Figure CN121636191A_ABST
Abstract
Description
Technical Field
[0001] This disclosure relates to the field of artificial intelligence technology, particularly to the fields of AI chips, deep learning, and large models, and specifically to task processing methods, devices, electronic devices, and storage media. Background Technology
[0002] With the widespread application of artificial intelligence technology in various fields, the amount of sample data required to train neural network models is increasing exponentially. For example, the sample data required for training a neural network model applied to the field of item recommendation can include massive amounts of user-item interaction feature data.
[0003] When performing model training tasks, how to efficiently query and update the sample data stored in the GPU memory has become a bottleneck restricting the execution efficiency of model training tasks. Summary of the Invention
[0004] This disclosure provides a task processing method, apparatus, electronic device, and storage medium.
[0005] According to one aspect of this disclosure, a task processing method is provided, comprising: for a first model training task using first sample data, invoking a first thread to perform a first address allocation operation based on the first sample data and first available storage area information of a target processor to obtain a first mapping relationship; the first mapping relationship indicating the mapping relationship between the identifier of the first sample data and a first storage address of a first storage area used to store the first sample data; and in response to receiving a first synchronization signal from the first thread, invoking a second thread to send the first mapping relationship to the target processor to control the target processor to read the first sample data from the first storage area based on the first mapping relationship, so that the target processor can use the first sample data to perform the first model training task; wherein the first synchronization signal indicates that the first address allocation operation has been completed.
[0006] According to another aspect of this disclosure, a task processing apparatus is provided, including: an allocation module and an execution module.
[0007] The allocation module is used to respond to receiving a first model training task for the first sample data, call the first thread to perform a first address allocation operation based on the first sample data and the first available storage area information of the target processor, and obtain a first mapping relationship; the first mapping relationship indicates the mapping relationship between the identifier of the first sample data and the first storage address of the first storage area used to store the first sample data.
[0008] An execution module is configured to, in response to receiving a first synchronization signal from a first thread, invoke a second thread to control the target processor to read first sample data from a storage area based on a first mapping relationship, so that the target processor can use the first sample data to execute a first model training task; wherein, the first synchronization signal indicates that the first address allocation operation has been completed.
[0009] According to another aspect of this disclosure, an electronic device is provided, comprising: at least one processor; and a memory communicatively connected to the at least one processor; wherein the memory stores instructions executable by the at least one processor, the instructions being executed by the at least one processor to enable the at least one processor to perform the methods described above.
[0010] According to another aspect of this disclosure, a non-transitory computer-readable storage medium is provided storing computer instructions, wherein the computer instructions are used to cause a computer to perform the methods described above.
[0011] According to another aspect of this disclosure, a computer program product is provided, including a computer program that, when executed by a processor, implements the method described above.
[0012] It should be understood that the description in this section is not intended to identify key or essential features of the embodiments of this disclosure, nor is it intended to limit the scope of this disclosure. Other features of this disclosure will become readily apparent from the following description. Attached Figure Description
[0013] The accompanying drawings are provided to better understand this solution and do not constitute a limitation of this disclosure. Wherein:
[0014] Figure 1 This illustration schematically shows an exemplary architecture of task processing methods and apparatus applicable according to embodiments of the present disclosure;
[0015] Figure 2 A flowchart illustrating a task processing method according to an embodiment of the present disclosure is shown schematically.
[0016] Figure 3 The illustration shows a schematic diagram of an address allocation operation performed in a relevant example according to an embodiment of the present disclosure;
[0017] Figure 4 The illustration shows a schematic diagram of an address allocation operation performed according to an embodiment of the present disclosure;
[0018] Figure 5 A schematic diagram of a task processing method according to an embodiment of the present disclosure is shown;
[0019] Figure 6 A schematic diagram of a task processing method according to another embodiment of the present disclosure is shown;
[0020] Figure 7 A schematic diagram of a task processing method according to yet another embodiment of the present disclosure is shown;
[0021] Figure 8 A block diagram of a task processing apparatus according to embodiments of the present disclosure is schematically shown; and
[0022] Figure 9 A block diagram of an electronic device suitable for implementing a task processing method according to an embodiment of the present disclosure is shown schematically. Detailed Implementation
[0023] The exemplary embodiments of this disclosure are described below with reference to the accompanying drawings, including various details of the embodiments to aid understanding, and should be considered merely exemplary. Therefore, those skilled in the art will recognize that various changes and modifications can be made to the embodiments described herein without departing from the scope and spirit of this disclosure. Similarly, for clarity and brevity, descriptions of well-known functions and structures are omitted in the following description.
[0024] Related examples typically employ data sorting to allocate memory addresses for sample features. This method requires frequent traversal of global memory and involves a large amount of data exchange during the sorting process. For instance, sorting 1 million data points takes approximately 10ms, a time that even exceeds the time required to train a model using a batch of sample data.
[0025] In view of this, the embodiments of this disclosure utilize the central processing unit to asynchronously call the first thread to perform an address allocation operation, thereby obtaining the mapping relationship between the identifier of the sample data and the storage address of the storage area used to store the sample data. After confirming that the address allocation operation has been completed, the mapping relationship is then sent to the target processor. This allows the target processor to read data from the storage area based on the mapping relationship when performing model training tasks, eliminating the need for frequent access to global memory and further improving model training efficiency.
[0026] Figure 1 The illustration schematically shows an exemplary architecture of task processing methods and apparatus applicable according to embodiments of the present disclosure.
[0027] It is important to note that Figure 1The examples shown are merely examples of system architectures that can be applied to the embodiments of this disclosure, to help those skilled in the art understand the technical content of this disclosure, but do not mean that the embodiments of this disclosure cannot be used in other devices, systems, environments, or scenarios. For example, in another embodiment, an exemplary system architecture to which the task processing method and apparatus can be applied may include a terminal device, but the terminal device can implement the task processing method and apparatus provided by the embodiments of this disclosure without interacting with the server.
[0028] like Figure 1 As shown, the system architecture 100 according to this embodiment may include a terminal device 101.
[0029] It should be noted that the task processing method provided in this embodiment can generally be executed by the terminal device 101. Accordingly, the task processing device provided in this embodiment can also be disposed in the terminal device 101.
[0030] First, a neural network model can be loaded into the terminal device 101. This neural network model can be any untrained network model or a large pre-trained model.
[0031] Then, the user can input the training task into the terminal device 101 and call the neural network model to execute the training task.
[0032] For example, this neural network model could be an item recommendation model. The embedding vectors in the embedding layer of this item recommendation model could be vectors used to represent the interaction features between objects and items.
[0033] Before performing model training, the terminal device's central processing unit (CPU) can create two threads. Thread A asynchronously performs address allocation to obtain the mapping between the identifiers and storage addresses of the first batch of sample data. Then, through parameter passing between threads, the mapping is sent to the target processor via thread B. This target processor can be a GPU (Graphics Processing Unit) or other processor used for model training. This allows the target processor to read sample data from storage based on the addresses in the mapping, enabling it to perform model training. The model training task can include the following iterative operations: convolving the read sample data to generate dense feature vectors; performing forward computation and backpropagation to obtain gradient values; and finally, updating the embedding vectors based on the gradient values.
[0034] It should be understood that Figure 1 The number of terminal devices shown is merely illustrative. Depending on implementation needs, any number of terminal devices can be used.
[0035] In the technical solution disclosed herein, the collection, storage, use, processing, sending, providing, disclosing and application of user personal information all comply with the provisions of relevant laws and regulations, necessary confidentiality measures have been taken, and they do not violate public order and good morals.
[0036] In the technical solution disclosed herein, the user's authorization or consent is obtained before acquiring or collecting the user's personal information.
[0037] Figure 2 A flowchart illustrating a task processing method according to an embodiment of the present disclosure is shown schematically.
[0038] like Figure 2 As shown, the method 200 includes operations S210 to S220.
[0039] In operation S210, for the first model training task based on the first sample data, the first thread is invoked to perform a first address allocation operation based on the first sample data and the first available storage area information of the target processor, thereby obtaining a first mapping relationship.
[0040] In operation S220, in response to receiving a first synchronization signal from the first thread, the second thread is invoked to send the first mapping relationship to the target processor, so as to control the target processor to read the first sample data from the first storage area based on the first mapping relationship, so that the target processor can use the first sample data to perform the first model training task.
[0041] The first sample data may include a set of sample data and sample labels corresponding to the first model training task. This sample data may include positive sample data and negative sample data. The type of sample data may include one or more of the following multimedia data: images, text, audio, video, etc.
[0042] The first model training task can be determined by the needs of the model application scenario. For example, in the case of item recommendation, the training objective can be to enable the model to output item information that the object is interested in based on the object's attributes or interactive behavior features.
[0043] A thread is the smallest unit of computation that an operating system can schedule. In this embodiment of the disclosure, for the first model training task using the first sample data, at least two threads can be created: a first thread and a second thread. The first thread can be used to perform address allocation operations, and the second thread can be used to control the target processor to perform model training operations.
[0044] The target processor can be any processor used to perform model training tasks, such as a GPU. The first available memory region information of the target processor can characterize the address information of a free memory region in the target processor's video memory. This address information can be a logical address, and may include, for example, a starting address identifier and an address offset.
[0045] In some embodiments, the first sample data may include multiple sample data. A hash function is first called to process each sample data to obtain its identifier. Then, the hash function is used to calculate the initial storage address of each sample data identifier in the available storage area of the target processor. Next, conflict detection is performed on the initial storage addresses of each sample data. If it is determined that two sample data have the same initial storage address, the random parameter value of the hash function is updated, and the operation of calculating the storage address using the updated hash function is returned. This process continues until the conflict between the calculated storage addresses disappears, resulting in a first mapping relationship. The first mapping relationship indicates the mapping relationship between the identifier of the first sample data and the first storage address of the first storage area used to store the first sample data.
[0046] When the first address allocation operation is completed, the first thread can send a first synchronization signal to the central processing unit (CPU) to indicate that the first address allocation operation has been completed. At this time, the CPU can call the second thread to send the first mapping relationship to the target processor.
[0047] For example, the first mapping relationship can be sent to the target processor via a second thread through parameter passing.
[0048] After receiving the first mapping relationship, the target processor can read the first sample data from the first storage area based on the first mapping relationship and use the first sample data to execute the first model training task.
[0049] For example, the first mapping relationship can be represented as a Key-Index, where Key represents the identifier of the first sample data and Index represents the first storage address used to store the first sample data. Then, when the target processor executes the first model training task, it only needs to query the storage address for storing the first sample data from the first sample relationship based on the first sample data required during task execution, read the first sample data from the first storage area according to the storage address for forward computation, and update the first sample data based on the gradient values during the backpropagation phase of model training. This reduces the time consumed by the target processor in frequently accessing global memory to resolve address conflicts during address allocation operations.
[0050] Therefore, in this embodiment, the central processing unit (CPU) asynchronously calls a first thread to perform an address allocation operation, obtaining a mapping relationship between the identifier of the sample data and the storage address of the storage area used to store the sample data. Once the address allocation operation is confirmed to be complete, the mapping relationship is sent to the target processor. This allows the target processor to read data from the storage area based on this mapping relationship when performing model training tasks, eliminating the need for frequent access to global memory and further improving model training efficiency.
[0051] Figure 3 The illustration shows a schematic diagram of an address allocation operation performed in a relevant example according to an embodiment of the present disclosure.
[0052] like Figure 3 As shown, the initial identifier sequence for multiple sample data can include 5, 7, 2, 5, 3, 4, 1. These initial identifiers can be sorted in ascending order to obtain the sorted identifier sequence "1, 2, 3, 4, 5, 5, 7". Next, the sorted identifier sequence is deduplicated to obtain the deduplicated identifier sequence "1, 2, 3, 4, 5, 7". Finally, address allocation is performed according to the deduplicated identifier sequence. For example, sample data with identifier "1" is allocated to the storage area with address "P1", sample data with identifier "2" is allocated to the storage area with address "P2", and so on.
[0053] However, this method of data sorting not only requires frequent traversal of global memory, but also involves a large amount of data exchange, which is very time-consuming.
[0054] Therefore, the embodiments of this disclosure use a hash mapping method to construct the first mapping relationship.
[0055] Figure 4 A schematic diagram illustrating the execution of an address allocation operation according to an embodiment of the present disclosure is shown.
[0056] like Figure 4 As shown, firstly, a hash function is used to calculate the initial storage address of each sample data identifier Key in the available storage area. For example, the initial storage address of Key1 is P1, and the initial storage address of Key2 is P2.
[0057] Next, a conflict detection is performed on the initial storage addresses. It is determined that Key3 and KeyN have the same initial storage address, indicating a storage address conflict. The random parameters of the hash function need to be updated and reallocated to determine the final storage address of each sample data.
[0058] In resolving conflicts, atomic read / write operations are required. Therefore, this embodiment utilizes asynchronous processing, where the central processing unit calls a first thread to pre-construct a first mapping relationship. This first mapping relationship represents a first function with the identifier of the first sample data as the independent variable and the first storage address as the dependent variable. The first mapping relationship is then sent to the target processor via parameter passing between threads. This effectively reduces the probability of the target processor accessing global memory during model training.
[0059] In this embodiment of the disclosure, in response to receiving a first synchronization signal from a first thread, a second thread is invoked to send a first mapping relationship to a target processor to control the target processor to read first sample data from a storage area based on the first mapping relationship, so that the target processor can use the first sample data to perform a first model training task. This may include the following operations: in response to receiving a first synchronization signal from a first thread, a second thread is invoked to send a first function to the target processor to control the target processor to process the identifier of the first sample data by calling the first function to obtain a first storage address; and the target processor is controlled to read the first sample data from the first storage area according to the first storage address.
[0060] In this embodiment of the disclosure, the first thread can send the first function to the target processor via the second thread through parameter passing. The first function can represent the functional relationship between the identifier of the first sample data and the first storage address.
[0061] After the target processor receives the first function, it can call the first function to process the identifier of the first sample data and obtain the first storage address. For example, this first storage address can represent the logical address of the first storage region used to store the first sample data. Then, the target processor determines the physical address of the first storage region according to the mapping relationship between the logical address and the physical address. The first sample data is then read from the first storage region of the target processor's video memory according to the physical region.
[0062] A first function, using the identifier of the first sample data as the independent variable and the first storage address as the dependent variable, represents the first mapping relationship. Compared to the address allocation operation through data sorting in related examples, this reduces the number of accesses to global memory. Furthermore, asynchronous threads can send the first mapping relationship to the target processor via parameter passing. This allows the target processor, when executing the first model training task, to obtain the first storage address by calling the first function to process the identifier of the first sample data, enabling data querying and updating, further improving the efficiency of data querying and updating.
[0063] When the second thread is invoked to control the target processor to execute the first model training task, the first thread is in an idle state. Therefore, in order to further reduce the time for executing the model training task using all sample data, the first thread can continue to be invoked to perform address allocation operations on the second batch of sample data without waiting for the processing results of the model training task on the first sample data by the second thread.
[0064] Therefore, in this embodiment of the present disclosure, the above task processing method may further include the following operation: in response to receiving a first synchronization signal, calling a first thread to perform a second address allocation operation based on the second sample data and the second available storage area information of the target processor, thereby obtaining a second mapping relationship.
[0065] According to embodiments of this disclosure, the second mapping relationship indicates the mapping relationship between the identifier of the second sample data and the second storage address of the second storage area used to store the second sample data.
[0066] The specific implementation method of the second address allocation operation is the same as that of the first address allocation operation, and will not be described in detail here.
[0067] It is understandable that when the first thread is called to perform the second address allocation operation, the second available storage area information of the target processor is the address information of the remaining storage area in the target processor's video memory after the first address allocation operation is completed.
[0068] Figure 5 A schematic diagram of a task processing method according to an embodiment of the present disclosure is shown.
[0069] like Figure 5 As shown, Batch 0 can represent the first sample data, and Batch 1 can represent the second sample data. The time interval gradually increases along the time axis.
[0070] In embodiment 500, the first thread in the CPU (Central Processing Unit) can represent the thread used to perform address allocation operations. The second thread can represent the thread used to control the target processor to perform model training tasks.
[0071] First, the first thread performs address allocation for Batch 0. Once this allocation is complete, the first thread sends a synchronization signal S1 to the second thread and simultaneously transmits the first mapping relationship F1(x) to the GPU via the second thread as a parameter. This first mapping relationship F1(x) represents the identifier key of each sample data in Batch 0. At this point, the GPU can read Batch 0 from its memory based on the first mapping relationship and use it to perform model training.
[0072] Upon receiving the first synchronization signal, the driver for the first thread has completed the first address allocation operation. At this point, the second thread, which controls the target processor to execute the first model training task, requires the first sample data, and the first thread, which executes the second address allocation operation, requires the second sample data. The second sample data represents another batch of sample data used for training the model. There is no data dependency between the first and second sample data.
[0073] Therefore, during the GPU's model training task using Batch 0, the first thread can be invoked to perform address allocation operations for Batch 1. When the address allocation operation for Batch 1 is completed, the first thread sends a synchronization signal S2 to the second thread, and simultaneously sends the second mapping relationship F2(x) to the GPU via the second thread through parameter passing. This second mapping relationship F2(x) can represent the identifier key of each sample data in Batch 1.
[0074] In this embodiment, the GPU can receive a synchronization signal S2 during the model training task using Batch 0, indicating that the central processing unit has already completed the address allocation operation for Batch 1. Therefore, after executing the model training task using Batch 0, the GPU can directly read Batch 1 from its video memory based on the second mapping relationship and execute the model training task using Batch 1. This reduces the time the GPU spends waiting for the address allocation operation result for Batch 1 after completing the model training task for Batch 0.
[0075] Therefore, calling the first thread to perform the second address allocation operation based on the second sample data and the second available storage area information of the target processor not only reduces the idle time of the first thread and makes full use of its computing resources, but also achieves overlap between the time when the central processing unit calls the first thread to perform address allocation and the time when the target processor performs model training tasks for the first batch. This further shortens the time required to perform model training tasks on all sample data and increases the overall time required to perform model training tasks on all sample data.
[0076] During model training on the target processor, different types of computational tasks need to be performed, such as scalar computation tasks and tensor computation tasks. Since there are some data dependencies between scalar and tensor computation tasks...
[0077] Therefore, in response to receiving the second synchronization signal from the first thread, the second thread is invoked to send the second mapping relationship to the target processor; and the task to be processed by the target processor is determined based on the task execution status of the first model training task.
[0078] According to an embodiment of this disclosure, the second synchronization signal indicates that the second address allocation operation has been completed.
[0079] For example, when the execution status of the first model training task is "completed", it means that the target processor used to execute the model training task is in an idle state. It can be determined that the task to be processed by the target processor is the second model training task for the second sample data.
[0080] For example, when the task execution status of the first model training task is "not completed", it means that the target processor used to execute the model training task is currently executing the first model training task.
[0081] When the execution status of the first model training task is determined to be incomplete, it can also be determined that the task to be processed by the target processor is the first model training task for the first sample data.
[0082] When the second thread is called to send the second mapping relationship to the target processor, the resources of the scalar computation core in the target processor, which is used to perform general tasks such as task scheduling and scalar computation, will be occupied.
[0083] Therefore, when the task execution status of the first model training task is determined to be incomplete, the task to be processed by the target processor can be determined to be the tensor computation task in the first model training task for the first sample data, thereby reducing the impact of the transmission of the second mapping relationship on the scalar computation task.
[0084] In this embodiment of the disclosure, determining the task to be processed by the target processor based on the task execution state may include the following operations: in response to determining that the task execution state indicates that the target processor is executing a first model training task, during the transmission of the second mapping relationship, controlling the scalar computation core of the target processor to suspend the execution of the scalar computation task in the first model training task, and controlling the tensor computation core of the target processor to execute the tensor computation task in the first model training task.
[0085] Figure 6A schematic diagram of a task processing method according to another embodiment of the present disclosure is shown.
[0086] like Figure 6 As shown, the difference between Embodiment 600 and Embodiment 500 is that when the CPU calls the second thread to transfer the second mapping relationship F2(x) for Batch 1 to the GPU, the GPU feedback signal indicates that the model training task for Batch 0 has not been completed. During the transfer of the second mapping relationship, the scalar computation core of the GPU can be controlled to suspend the execution of the scalar computation task in the model training task for Batch 0, thereby releasing resources to receive the second mapping relationship from the CPU.
[0087] At this point, since there is no complete data dependency between the scalar computation task and the tensor computation task, the tensor computation of the target processor and the execution of the tensor computation task in the model training task for Batch 1 can be controlled.
[0088] This allows the transmission time of the second mapping relationship to overlap with the time of the tensor computation task in the first model training task for the first sample data executed by the target processor, further improving the efficiency of model training for all sample data.
[0089] In practical applications, the transmission time of the second mapping relationship is usually shorter than the execution time of the first model training task. Therefore, in order to reduce the impact of the transmission of the second mapping relationship on the first model training task, the task to be processed by the target processor is determined according to the task execution status, and the following operation may also be included: in response to determining that the second mapping relationship has been sent to the target processor, the scalar computation core of the target processor is controlled to resume the execution of the scalar computation task in the first model training task.
[0090] Figure 7 A schematic diagram of a task processing method according to yet another embodiment of the present disclosure is shown.
[0091] like Figure 7 As shown, the difference between this embodiment 700 and embodiment 600 is that the feedback signal from the GPU to the CPU indicates that the model training task for Batch 0 has been completed, indicating that the resources of the scalar computing cores in the GPU have been released, and the GPU can be controlled to resume the execution of the scalar computing task in the first model training task.
[0092] Based on the task execution status of the first model training task indicated by the feedback signal from the target processor, dynamic allocation of scalar computation core resources is achieved by switching the running status of the scalar computation cores in the target processor. Furthermore, the transmission time of the second mapping relationship overlaps with the time of the tensor computation task in the first model training task for the first sample data executed by the target processor, further shortening the time required to perform model training on all sample data and improving the utilization rate of hardware resources.
[0093] For massive amounts of sample data, the time it takes for the CPU to perform address allocation operations may be similar to, or even exceed, the time it takes for the target processor to perform model training tasks.
[0094] In some embodiments, determining the task to be processed by the target processor based on the task execution status may include the following operation: in response to determining that the task execution status indicates that the first model training task has been completed, controlling the target processor to read the second sample data from the second storage area based on the second mapping relationship, so that the target processor can use the second sample data to execute the second model training task.
[0095] According to embodiments of this disclosure, the second mapping relationship represents a second function with the identifier of the second sample data as the independent variable and the second storage address as the dependent variable.
[0096] In embodiments of this disclosure, in response to determining that the task execution status indicates that the first model training task has been completed, controlling the target processor to read second sample data from the second storage area based on the second mapping relationship, so that the target processor can use the second sample data to execute the second model training task, may include the following operations: in response to determining that the task execution status indicates that the first model training task has been completed, controlling the target processor to process the identifier of the second sample data by calling a second function to obtain a second storage address; and controlling the target processor to read the second sample data from the second storage area according to the second storage address, so that the target processor can use the second sample data to execute the second model training task.
[0097] For example, the first thread can send the second function to the target processor via parameter passing. The second function can represent the functional relationship between the identifier of the second sample data and the second memory address.
[0098] After the target processor receives the second function, it can call the second function to process the identifier of the second sample data and obtain the second storage address.
[0099] For example, the second storage address can represent the logical address of the second storage area used to store the second sample data.
[0100] Then, the target processor determines the physical address of the second memory region according to the mapping relationship between logical addresses and physical addresses. The first sample data is then read from the second memory region of the target processor's video memory according to the physical address.
[0101] A second function, using the identifier of the second sample data as the independent variable and the second storage address as the dependent variable, represents the second mapping relationship. Compared to the address allocation operation through data sorting in related examples, this reduces the number of accesses to global memory. Furthermore, asynchronous threads can pass the second mapping relationship to the target processor via parameter passing. This allows the target processor, when executing the second model training task, to obtain the first storage address by calling the second function to process the identifier of the first sample data, thus enabling data querying and updating, further improving the efficiency of data querying and updating.
[0102] Figure 8 A block diagram of a task processing apparatus according to an embodiment of the present disclosure is shown schematically.
[0103] like Figure 8 As shown, the task processing device 800 may include an allocation module 810 and an execution module 820.
[0104] The allocation module 810 is used to respond to receiving a first model training task for the first sample data, call the first thread to perform a first address allocation operation based on the first sample data and the first available storage area information of the target processor, and obtain a first mapping relationship; the first mapping relationship indicates the mapping relationship between the identifier of the first sample data and the first storage address of the first storage area used to store the first sample data.
[0105] The execution module 820 is configured to, in response to receiving a first synchronization signal from the first thread, call the second thread to control the target processor to read the first sample data from the storage area based on the first mapping relationship, so that the target processor can use the first sample data to execute the first model training task; wherein, the first synchronization signal indicates that the first address allocation operation has been completed.
[0106] According to embodiments of this disclosure, the first mapping relationship represents a first function with the identifier of the first sample data as the independent variable and the first storage address as the dependent variable. The execution module 820 may include a first processing submodule and a first control submodule.
[0107] The first processing submodule is used to respond to receiving a first synchronization signal from the first thread by calling the second thread to send the first function to the target processor, so as to control the target processor to process the identifier of the first sample data by calling the first function and obtain the first storage address.
[0108] The first control submodule is used to control the target processor to read the first sample data from the first storage area according to the first storage address.
[0109] According to an embodiment of this disclosure, the task processing apparatus 800 may further include: an address allocation module, configured to, in response to receiving a first synchronization signal, invoke a first thread to perform a second address allocation operation based on second sample data and second available storage area information of the target processor, to obtain a second mapping relationship; wherein the second mapping relationship indicates the mapping relationship between the identifier of the second sample data and the second storage address of the second storage area used to store the second sample data.
[0110] According to embodiments of this disclosure, the task processing apparatus 800 may further include a sending module and a determining module.
[0111] The sending module is used to, in response to receiving a second synchronization signal from the first thread, call the second thread to send the second mapping relationship to the target processor; wherein, the second synchronization signal indicates that the second address allocation operation has been completed.
[0112] The determination module is used to determine the tasks to be processed by the target processor based on the task execution status of the first model training task.
[0113] According to an embodiment of this disclosure, the determining module includes: a second control submodule, configured to, in response to determining that the task execution state indicates that the target processor is executing a first model training task, during the transmission of the second mapping relationship, control the scalar computation core of the target processor to suspend the execution of the scalar computation task in the first model training task, and control the tensor computation core of the target processor to execute the tensor computation task in the first model training task.
[0114] According to an embodiment of this disclosure, the determining module further includes: a third control submodule, configured to, in response to determining that the second mapping relationship has been sent to the target processor, control the scalar computation core of the target processor to resume execution of the scalar computation task in the first model training task.
[0115] According to an embodiment of this disclosure, the determining module includes: a fourth control submodule, configured to, in response to determining that the task execution status indicates that the first model training task has been completed, control the target processor to read second sample data from the second storage area based on a second mapping relationship, so that the target processor uses the second sample data to execute the second model training task.
[0116] According to embodiments of this disclosure, the second mapping relationship represents a second function with the identifier of the second sample data as the independent variable and the second storage address as the dependent variable. The fourth control submodule includes a processing unit and a control unit.
[0117] The processing unit is configured to, in response to a determination that the task execution status indicates that the first model training task has been completed, control the target processor to process the identifier of the second sample data by calling a second function to obtain the second storage address.
[0118] The control unit is used to control the target processor to read the second sample data from the second storage area according to the second storage address, so that the target processor can use the second sample data to perform the second model training task.
[0119] According to embodiments of this disclosure, this disclosure also provides an electronic device, a readable storage medium, and a computer program product.
[0120] According to an embodiment of the present disclosure, an electronic device includes: at least one processor; and a memory communicatively connected to the at least one processor; wherein the memory stores instructions executable by the at least one processor, the instructions being executed by the at least one processor to enable the at least one processor to perform the methods described above.
[0121] According to embodiments of the present disclosure, a non-transitory computer-readable storage medium stores computer instructions, wherein the computer instructions are used to cause a computer to perform the methods described above.
[0122] According to an embodiment of this disclosure, a computer program product includes a computer program that, when executed by a processor, implements the method described above.
[0123] Figure 9 A schematic block diagram of an example electronic device 900 that can be used to implement embodiments of the present disclosure is shown. The electronic device is intended to represent various forms of digital computers, such as laptop computers, desktop computers, workstations, personal digital assistants, servers, blade servers, mainframe computers, and other suitable computers. The electronic device may also represent various forms of mobile devices, such as personal digital processors, cellular phones, smartphones, wearable devices, and other similar computing devices. The components shown herein, their connections and relationships, and their functions are merely illustrative and are not intended to limit the implementation of the present disclosure described and / or claimed herein.
[0124] like Figure 9As shown, device 900 includes a computing unit 901, which can perform various appropriate actions and processes based on a computer program stored in read-only memory (ROM) 902 or a computer program loaded from storage unit 908 into random access memory (RAM) 903. RAM 903 may also store various programs and data required for the operation of device 900. The computing unit 901, ROM 902, and RAM 903 are interconnected via bus 904. Input / output (I / O) interface 905 is also connected to bus 904.
[0125] Multiple components in device 900 are connected to I / O interface 905, including: input unit 906, such as keyboard, mouse, etc.; output unit 907, such as various types of monitors, speakers, etc.; storage unit 908, such as disk, optical disk, etc.; and communication unit 909, such as network card, modem, wireless transceiver, etc. Communication unit 909 allows device 900 to exchange information / data with other devices through computer networks such as the Internet and / or various telecommunications networks.
[0126] The computing unit 901 can be a variety of general-purpose and / or special-purpose processing components with processing and computing capabilities. Some examples of the computing unit 901 include, but are not limited to, a central processing unit (CPU), a graphics processing unit (GPU), various special-purpose artificial intelligence (AI) computing chips, various computing units running machine learning model algorithms, a digital signal processor (DSP), and any suitable processor, controller, microcontroller, etc. The computing unit 901 performs the various methods and processes described above, such as task processing methods. For example, in some embodiments, the task processing method may be implemented as a computer software program tangibly contained in a machine-readable medium, such as storage unit 908. In some embodiments, part or all of the computer program may be loaded and / or installed on device 900 via ROM 902 and / or communication unit 909. When the computer program is loaded into RAM 903 and executed by the computing unit 901, one or more steps of the methods described above may be performed. Alternatively, in other embodiments, the computing unit 901 may be configured to perform task processing methods by any other suitable means (e.g., by means of firmware).
[0127] Various embodiments of the systems and techniques described above herein can be implemented in digital electronic circuit systems, integrated circuit systems, field-programmable gate arrays (FPGAs), application-specific integrated circuits (ASICs), application-specific standard products (ASSPs), systems-on-a-chip (SoCs), complex programmable logic devices (CPLDs), computer hardware, firmware, software, and / or combinations thereof. These various embodiments may include implementations in one or more computer programs that can be executed and / or interpreted on a programmable system including at least one programmable processor, which may be a dedicated or general-purpose programmable processor, capable of receiving data and instructions from a storage system, at least one input device, and at least one output device, and transmitting data and instructions to the storage system, the at least one input device, and the at least one output device.
[0128] The program code used to implement the methods of this disclosure may be written in any combination of one or more programming languages. This program code may be provided to a processor or controller of a general-purpose computer, special-purpose computer, or other programmable data processing apparatus, such that when executed by the processor or controller, the program code causes the functions / operations specified in the flowcharts and / or block diagrams to be implemented. The program code may be executed entirely on a machine, partially on a machine, as a standalone software package partially on a machine and partially on a remote machine, or entirely on a remote machine or server.
[0129] In the context of this disclosure, a machine-readable medium can be a tangible medium that may contain or store a program for use by or in conjunction with an instruction execution system, apparatus, or device. A machine-readable medium can be a machine-readable signal medium or a machine-readable storage medium. A machine-readable medium can be, but is not limited to, electronic, magnetic, optical, electromagnetic, infrared, or semiconductor systems, apparatus, or devices, or any suitable combination of the foregoing. More specific examples of machine-readable storage media include electrical connections based on one or more wires, portable computer disks, hard disks, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), optical fiber, portable compact disk read-only memory (CD-ROM), optical storage devices, magnetic storage devices, or any suitable combination of the foregoing.
[0130] To provide interaction with a user, the systems and techniques described herein can be implemented on a computer having: a display device for displaying information to the user (e.g., a CRT (cathode ray tube) or LCD (liquid crystal display) monitor); and a keyboard and pointing device (e.g., a mouse or trackball) through which the user provides input to the computer. Other types of devices can also be used to provide interaction with the user; for example, feedback provided to the user can be any form of sensory feedback (e.g., visual feedback, auditory feedback, or tactile feedback); and input from the user can be received in any form (including sound input, voice input, or tactile input).
[0131] The systems and technologies described herein can be implemented in computing systems that include backend components (e.g., as a data server), or computing systems that include middleware components (e.g., an application server), or computing systems that include frontend components (e.g., a user computer with a graphical user interface or web browser through which a user can interact with implementations of the systems and technologies described herein), or any combination of such backend, middleware, or frontend components. The components of the system can be interconnected via digital data communication of any form or medium (e.g., a communication network). Examples of communication networks include local area networks (LANs), wide area networks (WANs), and the Internet.
[0132] Computer systems can include clients and servers. Clients and servers are generally located far apart and typically interact via communication networks. Client-server relationships are created by computer programs running on the respective computers and having a client-server relationship with each other. Servers can be cloud servers, distributed system servers, or servers incorporating blockchain technology.
[0133] It should be understood that the various forms of processes shown above can be used to rearrange, add, or delete steps. For example, the steps described in this disclosure can be executed in parallel, sequentially, or in different orders, as long as the desired result of the technical solution disclosed in this disclosure can be achieved, and this is not limited herein.
[0134] The specific embodiments described above do not constitute a limitation on the scope of protection of this disclosure. Those skilled in the art should understand that various modifications, combinations, sub-combinations, and substitutions can be made according to design requirements and other factors. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of this disclosure should be included within the scope of protection of this disclosure.
Claims
1. A task processing method, comprising: for a first model training task of first sample data, invoking a first thread, performing a first address allocation operation based on the first sample data and first available storage area information of a target processor, to obtain a first mapping relationship; wherein the first mapping relationship indicates a mapping relationship between an identifier of the first sample data and a first storage address of a first storage area for storing the first sample data; and in response to receiving a first synchronization signal from the first thread, invoking a second thread to send the first mapping relationship to the target processor, to control the target processor to read the first sample data from the storage area based on the first mapping relationship, so that the target processor performs the first model training task using the first sample data; wherein the first synchronization signal indicates that the first address allocation operation has been performed.
2. The method of claim 1, wherein, the first mapping relationship represents a first function with the identifier of the first sample data as an independent variable and the first storage address as a dependent variable; the response to receiving the first synchronization signal from the first thread, invoking the second thread to send the first mapping relationship to the target processor, to control the target processor to read the first sample data from the storage area based on the first mapping relationship, so that the target processor performs the first model training task using the first sample data, comprises: the response to receiving the first synchronization signal from the first thread, invoking the second thread to send the first function to the target processor, to control the target processor to process the identifier of the first sample data by calling the first function, to obtain the first storage address; and controlling the target processor to read the first sample data from the first storage area according to the first storage address.
3. The method of claim 1 or 2, further comprising: in response to receiving the first synchronization signal, invoking the first thread to perform a second address allocation operation based on second sample data and second available storage area information of the target processor, to obtain a second mapping relationship; wherein the second mapping relationship indicates a mapping relationship between an identifier of the second sample data and a second storage address of a second storage area for storing the second sample data.
4. The method of claim 3, further comprising: in response to receiving a second synchronization signal from the first thread, invoking a second thread to send the second mapping relationship to the target processor; and determining a to-be-processed task of the target processor according to a task execution state of the first model training task; wherein the second synchronization signal indicates that the second address allocation operation has been performed. the determination of the to-be-processed task of the target processor according to the task execution state, comprises:
5. The method of claim 4, wherein, In response to determining that the task execution state indicates that the target processor is executing the first model training task, during sending of the second mapping relationship, the scalar calculation core of the target processor is controlled to suspend execution of a scalar calculation task in the first model training task, and the tensor calculation core of the target processor is controlled to execute a tensor calculation task in the first model training task.
6. The method of claim 5, wherein, The determining the to-be-processed task of the target processor according to the task execution state further includes: In response to determining that the second mapping relationship has been sent to the target processor, the scalar calculation core of the target processor is controlled to resume execution of a scalar calculation task in the first model training task.
7. The method of claim 4, wherein, The determining the to-be-processed task of the target processor according to the task execution state includes: In response to determining that the task execution state indicates that the first model training task has been executed completely, the target processor is controlled to read second sample data from the second storage area based on the second mapping relationship, so that the target processor executes the second model training task by using the second sample data.
8. The method of claim 7, wherein, The second mapping relationship represents a second function with an identifier of second sample data as an independent variable and the second storage address as a dependent variable; The response to determining that the task execution state indicates that the first model training task has been executed completely, the target processor is controlled to read second sample data from the second storage area based on the second mapping relationship, so that the target processor executes the second model training task by using the second sample data, includes: The response to determining that the task execution state indicates that the first model training task has been executed completely, the target processor is controlled to read second sample data from the second storage area based on the second mapping relationship, so that the target processor executes the second model training task by using the second sample data, includes: The response to determining that the task execution state indicates that the first model training task has been executed completely, the target processor is controlled to read second sample data from the second storage area based on the second mapping relationship, so that the target processor executes the second model training task by using the second sample data, includes:
9. A task processing apparatus, comprising: an allocation module configured to, for a first model training task of first sample data, invoke a first thread to execute a first address allocation operation based on the first sample data and first available storage area information of a target processor, to obtain a first mapping relationship; wherein the first mapping relationship indicates a mapping relationship between an identifier of the first sample data and a first storage address of a first storage area for storing the first sample data; and an execution module configured to, in response to receiving a first synchronization signal from the first thread, invoke a second thread to control the target processor to read the first sample data from the storage area based on the first mapping relationship, so that the target processor executes the first model training task by using the first sample data; wherein the first synchronization signal indicates that the first address allocation operation has been executed completely.
10. An electronic device, comprising: at least one processor; and a memory connected with the at least one processor in communication; wherein, The memory stores instructions executable by the at least one processor, the instructions being executed by the at least one processor to enable the at least one processor to perform the method of any one of claims 1-8.
11. A non-transitory computer readable storage medium having stored thereon computer instructions, wherein, The computer instructions are for causing the computer to perform the method of any one of claims 1-8.
12. A computer program product comprising a computer program which, when executed by a processor, implements the method of any one of claims 1-8.