Verification system and method based on SOC software system and UVM hardware simulation interaction

Abstract

The invention discloses a verification system based on simulation interaction of an SOC software system and UVM hardware, and the system comprises an SOC side multi-core CPU module which is used for transmitting a control command in a predefined format to a UVM environment through a standard AMBA bus interface; the command parsing Agent module in the UVM environment is used for capturing and parsing the control command and realizing multi-core concurrency control of the SOC side multi-core CPU module through a thread ID routing mechanism, an independent command queue buffer and an atomic operation lock; and the verification component is used for executing the analyzed control command and writing a result into a predefined feedback address. According to the method, accurate distribution of the multi-core commands is realized through a thread ID routing mechanism, the stability of concurrency control is guaranteed by combining independent command queue buffering and an atomic operation lock, the problems of insufficient standardization of communication interfaces, conflict of the multi-core commands and high delay of information interaction in the prior art are effectively solved, and the method is suitable for popularization and application. The method has the advantages that the verification efficiency is improved, the multi-core concurrency control reliability is ensured, and the software and hardware interaction process is simplified.

Description

TECHNICAL FIELD

[0001] The application relates to the chip verification technical field, in particular to a verification system and method based on SOC software system and UVM hardware simulation interaction. BACKGROUND

[0002] With the continuous rise of the complexity of system-on-chip design, software and hardware co-verification plays an indispensable role in the chip development process. In verification practice, efficient communication between system-on-chip software system and hardware simulation environment is a key link to ensure verification accuracy and timeliness.

[0003] However, under the current technical framework, the interaction mechanism between the system-on-chip software system and the hardware simulation environment of the general verification methodology has many inherent defects, which seriously restricts the verification efficiency. The primary obstacle is the lack of standardization of the communication interface. Different design projects often rely on customized special interfaces, which not only significantly increases the development difficulty and maintenance cost of the verification platform, but also leads to the difficulty of reusing the interface logic. Each design iteration needs to be re-adapted, which greatly slows down the verification progress. The popularity of multi-core processor architecture further exacerbates the problem complexity. When multiple processor cores send control commands concurrently, the existing command parsing mechanism lacks effective thread identification routing capability, the independent command buffer space is insufficient, and the shared resource synchronization means is weak, which easily causes command conflict, data overlap or execution sequence disorder, resulting in unreliable verification results.

[0004] At the same time, the transmission path of software control information is long and the parsing process is complicated, the information interaction delay is high, and the software system has to frequently poll the state, which causes the verification period to be abnormally prolonged, which cannot meet the rapid iteration needs of modern high-complexity chip design. These technical bottlenecks make the verification process inefficient and the error rate high, which becomes the core pain point restricting the speed of chip development.

[0005] In view of the above problems, the prior art needs to be improved. SUMMARY

[0006] The purpose of the present application is to provide a verification system and method based on SOC software system and UVM hardware simulation interaction, which has the advantages of improving verification efficiency, ensuring multi-core concurrent control reliability and simplifying the software and hardware interaction process.

[0007] The above technical purpose of the present application is achieved by the following technical scheme:

[0008] A verification system based on SOC software system and UVM hardware simulation interaction, comprising:

[0009] The SOC side multi-core CPU module is used to send control commands in a predefined format to the UVM environment through a standard AMBA bus interface.

[0010] A command parsing Agent module in the UVM environment is configured to capture and parse the control commands, and to implement multi-core concurrent control of the SOC-side multi-core CPU module through a thread ID routing mechanism, an independent command queue buffer, and an atomic operation lock.

[0011] A verification component is configured to execute the parsed control commands and write the results to a predefined feedback address.

[0012] Further, the standard AMBA bus interface adopts an AXI or AHB protocol, and the control commands are written into a dynamically allocated AMBA address segment through memory-mapped I / O, with the address segment range being determined according to the maximum number of CPU cores.

[0013] Further, the parsing logic of the command parsing Agent module includes:

[0014] checking the command header validity of the control commands and filtering illegal commands;

[0015] extracting the thread ID, command type, and operation parameters in the control command format;

[0016] distributing the control commands to corresponding verification components based on the thread ID.

[0017] Further, the independent command queue allocates independent storage space for each CPU core or thread, and synchronizes the shared resource access through an atomic operation lock.

[0018] Further, the atomic operation lock adopts a hardware-supported synchronization mechanism, which is implemented through a test-and-set instruction or a compare-and-swap instruction, and is used to ensure data consistency and operation sequence when multiple threads access shared resources.

[0019] Further, the verification component executes the control commands by calling a predefined function library, the function library includes test functions or scripted automated test tools; and the execution results are written into the predefined feedback address through direct memory access or register mapping.

[0020] A verification method based on the interaction between a SOC software system and a UVM hardware simulation includes:

[0021] S1. Command writing: the SOC-side multi-core CPU module writes control commands into a predefined AMBA bus address segment through memory-mapped I / O;

[0022] S2. Transaction capture: the command parsing Agent module captures AMBA bus transactions in real time and extracts command data;

[0023] S3. Concurrent parsing:

[0024] Check the validity of the command header, return an error for illegal commands;

[0025] Parse the thread ID, command type and parameters;

[0026] Store the command in the corresponding independent queue based on the thread ID;

[0027] S4. Command execution: the queue triggers the verification component to execute the command and writes the result to the predefined feedback address;

[0028] S5. Result acquisition: the SOC side multicore CPU module polls the feedback address to obtain the execution result.

[0029] Further, in the S3 step, a hash table or direct mapping method is used to implement a command routing mechanism based on the thread ID, ensuring that the commands of each CPU core are accurately distributed to the corresponding processing path, and realizing isolated processing of multicore commands.

[0030] Further, the verification component in the S4 step calls different test functions or automation scripts to execute specific verification tasks according to the command type, and generates result information containing a status code and output data after execution, which is written to the feedback address area corresponding to the initiating core for independent reading by the SOC side CPU core.

[0031] A computer readable storage medium having a computer program / instruction stored thereon, wherein the computer program / instruction is executed by a processor to implement the above-mentioned verification method based on the interaction between the SOC software system and the UVM hardware simulation.

[0032] In summary, the present application has the following advantages:

[0033] Through the thread ID routing mechanism, precise distribution of multicore commands is realized, and the stability of concurrent control is guaranteed by combining independent command queue buffering and atomic operation locks, effectively solving the problems of insufficient communication interface standardization, multicore command conflict and high information interaction delay in the prior art, and having the advantages of improving verification efficiency, ensuring the reliability of multicore concurrent control and simplifying the soft and hardware interaction process. BRIEF DESCRIPTION OF DRAWINGS

[0034] Figure 1 is the overall architecture diagram of the verification system described in the present application.

[0035] Figure 2 is a control address distribution diagram of the SOC side described in the present application.

[0036] Figure 3 is a data format diagram of the access address described in the present application.

[0037] Figure 4is a definition reference diagram of the control command type described in the present application.

[0038] Figure 5 is a flowchart of the verification method described in the present application. DETAILED DESCRIPTION

[0039] In order to make the technical means, creative features, purposes and effects of the present application easy to understand, the present application will be further described below in combination with the drawings and specific embodiments.

[0040] Referring to Figure 1 A verification system based on SOC software system and UVM hardware simulation interaction, comprising:

[0041] The SOC side multi-core CPU module is used to send control commands in a predefined format to the UVM environment through a standard AMBA bus interface.

[0042] The command parsing Agent module in the UVM environment is used to capture and parse the control commands, and to realize multi-core concurrent control of the SOC side multi-core CPU module through thread ID routing mechanism, independent command queue buffer and atomic operation lock.

[0043] The verification component is used to execute the parsed control commands and write the results to a predefined feedback address.

[0044] The SOC side multi-core CPU module can realize its functions in various ways, such as using ARM Cortex-A series processors or multi-core RISC-V architecture processors, and its main purpose is to provide efficient multi-core computing power for SOC systems. Further, the standard AMBA bus interface can be understood as a general on-chip communication protocol, and its specific implementation can use lightweight protocols such as AXI-Lite or APB to meet the communication needs in different scenarios.

[0045] For the command parsing Agent module, its core function is to parse and distribute the control commands. Specifically, command parsing can be realized by hardware logic circuit, such as using finite state machine to check the command header, or using software algorithm to parse the command format. Further, the thread ID routing mechanism can be realized by using hash table or direct mapping, and its main purpose is to ensure that the commands of each thread can be accurately distributed to the corresponding processing path. The specific implementation of independent command queue buffer can use ring buffer or double-ended queue structure to support efficient data storage and access. In addition, the atomic operation lock can be realized by hardware semaphore or software mutex, and its main function is to ensure the access consistency of shared resources.

[0046] The function of the verification component is to execute the parsed command and feed back the result to the SOC side. Specifically, the command execution can be achieved by calling a predefined function library, such as a test function written in C language or a scripted automated test tool. Further, the writing of the feedback address can be completed through direct memory access or register mapping, and the main purpose is to establish a fast response closed-loop communication link.

[0047] The innovation of the present application is that through the standardized interface design and multi-core concurrent control mechanism, the problems of non-uniform interface, multi-core concurrent conflict and low efficiency in communication between the SOC software system and the UVM hardware simulation environment are solved. Among them, the SOC side multi-core CPU module sends control commands in a predefined format using a standard AMBA bus interface, avoiding the design complexity brought by customizing a special interface. The command parsing Agent module realizes multi-core concurrent control through thread ID routing mechanism, independent command queue buffer and atomic operation lock, eliminating the risk of command conflict and data loss. The verification component executes the parsed command and writes the result to the predefined feedback address, establishing an efficient software and hardware interaction process. The above features jointly build a multi-core parallel supported software and hardware co-verification platform, significantly improving the communication efficiency and verification reliability.

[0048] The working principle of the embodiment of the present application is as follows:

[0049] A verification system based on the interaction between the SOC software system and the UVM hardware simulation realizes its function through the cooperative operation of multiple modules. The SOC side multi-core CPU module sends control commands in a predefined format to the UVM environment using a standard AMBA bus interface, unifies the communication interface specification, avoids the design complexity brought by customizing a special interface, and ensures the standardization and efficiency of command transmission. Further, the command parsing Agent module in the UVM environment captures and parses the control commands, in which the captured control commands are accurately distributed to the corresponding processing path through the thread ID routing mechanism, independent command queue buffer provides exclusive storage space for each CPU core to isolate concurrent requests, and atomic operation lock synchronizes real-time shared resource access, all of which cooperatively realize multi-core concurrent control, completely eliminating the risk of command conflict and data loss. Specifically, the verification component executes the parsed control command and writes the result to the predefined feedback address, establishing a fast response closed-loop communication link, significantly improving the efficiency of software obtaining execution results. Thus, the above features work closely together, the SOC side module initiates standardized command transmission, the command parsing Agent module completes concurrent parsing and routing scheduling, and the verification component executes the command and feeds back the result, jointly building an efficient, reliable and multi-core parallel supported software and hardware interaction verification process, which fundamentally optimizes the communication mechanism.

[0050] Referring to Figure 2 and Figure 3This application further proposes that the standard AMBA bus interface adopts the AXI or AHB protocol, and that control commands are written to the dynamically allocated AMBA address segment through memory-mapped I / O, with the address segment range determined according to the maximum number of CPU cores.

[0051] In practical applications, the standard AMBA bus interface refers to a communication interface specification based on an advanced microcontroller bus architecture, which can be implemented using either the AXI or AHB protocols. Both protocols are industry-standard and ensure seamless integration between the SoC and the UVM environment, thereby reducing system integration complexity. In particular, the AXI and AHB protocols natively support multi-master communication, providing underlying protocol guarantees for concurrent multi-core CPU operations. Memory-mapped I / O refers to the technology of directly manipulating the address space using regular CPU memory access instructions. It simplifies the software programming model and improves communication efficiency by converting command transmissions into standard memory write operations. The dynamically allocated AMBA address range is designed to allow address resources to be flexibly adjusted according to the actual system configuration, avoiding the risk of overwriting that may be caused by hard-coded addresses. The strategy of determining the address range based on the maximum number of CPU cores allows for pre-allocation of address space during system initialization based on the maximum number of cores, thus naturally isolating access paths during concurrent multi-core writes and effectively preventing command-data contention and conflicts.

[0052] Specifically, this technical solution effectively solves the problems of communication interface uniformity and multi-core concurrent access conflicts through standardized protocol selection and dynamic address management mechanisms. Using AXI or AHB protocols as the standard AMBA bus interface, these protocols are industry-standard, allowing seamless integration between the SOC and UVM environments without the need for additional custom interface development, significantly reducing system integration complexity. Control commands are written via memory-mapped I / O, directly manipulating the address space using regular CPU memory access instructions, transforming command transmission into standard memory write operations. This eliminates the need for dedicated hardware or special instruction sets, simplifying the software programming model and improving communication efficiency. The dynamic allocation of AMBA address segments allows address resources to be flexibly adjusted according to the actual system configuration, rather than relying on fixed preset values, ensuring maximum address space utilization. The address segment range is determined based on the maximum number of CPU cores. During system initialization, address space is pre-allocated based on the maximum number of cores. Since address capacity is directly related to the number of cores, each CPU core obtains an independent and sufficient address region, naturally isolating access paths during multi-core concurrent writes and effectively preventing command data contention and conflicts.

[0053] In summary, the above technical solutions not only standardize the communication interface but also optimize multi-core concurrency control, fundamentally solving the synchronization problem of multi-core verification and significantly improving the efficiency of software and hardware collaborative verification.

[0054] See Figure 4 This application further proposes that the parsing logic of the command parsing Agent module includes:

[0055] Verify the validity of the command header of the control command and filter out illegal commands;

[0056] Extract the thread ID, command type, and operation parameters from the control command format;

[0057] Control commands are distributed to the corresponding verification components based on the thread ID.

[0058] Specifically, validating the command header validity and filtering out illegal commands refers to performing structural verification on the command header at the initial stage of command parsing. This can be achieved by recognizing predefined command header identifiers and format rules. The purpose is to quickly identify and discard invalid or incorrectly formatted commands, preventing them from entering subsequent processing stages and causing malfunctions in the verification components or system crashes. Extracting the thread ID, command type, and operation parameters from the control command format refers to parameter parsing based on a predefined standardized command format. This can be implemented using a fixed structure dependent on the command format. The purpose is to ensure the accurate acquisition of thread ID, command type, and operation parameters, providing precise instruction basis for subsequent command distribution and execution. In practical applications, distributing control commands to the corresponding verification components based on the thread ID means using the extracted thread ID as a routing basis. This can be achieved by dynamically matching verification components. The purpose is to ensure that commands on each CPU core are processed in isolation in a multi-core environment, avoiding resource conflicts or data inconsistencies caused by command misalignment during multi-core concurrency.

[0059] This parsing logic effectively solves the problems of illegal command interference and inaccurate multi-core concurrent routing during command parsing through a systematic command processing flow. First, the command header validity verification mechanism plays a role in the initial stage of command parsing, avoiding resource consumption by illegal commands and significantly improving the robustness of command processing. Second, parameter parsing based on a predefined standardized command format ensures reliable and efficient extraction of thread ID, command type, and operation parameters, providing accurate instruction basis for subsequent command distribution and execution. Finally, the thread ID-based command distribution mechanism enables targeted command distribution, ensuring that commands on each CPU core are processed in isolation in a multi-core environment, thereby guaranteeing the correct operation of the system in high-concurrency scenarios. Furthermore, this parsing logic works in conjunction with the multi-core CPU module on the SOC side and other modules in the UVM environment to effectively address the problem of imperfect command parsing and synchronization mechanisms during multi-core concurrent access, improving the efficiency of hardware and software co-verification.

[0060] This application further proposes an independent command queue that allocates independent storage space for each CPU core or thread, and synchronizes shared resource access through atomic operation locks.

[0061] Specifically, an independent command queue refers to a command storage area separately allocated for each CPU core or thread. This can be implemented using physically isolated storage partitions or logically independent address spaces. In practical applications, this design ensures that the command flows of each core do not interfere with each other at the storage level, thus avoiding resource contention issues in multi-core concurrent scenarios. An atomic operation lock can be understood as a hardware-supported synchronization mechanism that ensures only one thread can access shared resources at a time by locking the operation permissions of critical resources. This can be implemented using test-and-set or compare-and-swap instructions, aiming to guarantee data consistency and operation order during command parsing.

[0062] This solution, by allocating independent storage space for each CPU core or thread, fundamentally isolates command flow paths in multi-core concurrent scenarios, avoiding command overwriting or disordered processing order between different cores. Simultaneously, the introduction of atomic operation locks provides strict synchronization control for access to shared resources, effectively preventing data inconsistency or execution interruption caused by concurrent access when the command parsing agent module processes cross-core shared resources. Furthermore, the combination of independent storage space and atomic operation locks not only improves the real-time performance and accuracy of command parsing but also significantly enhances the stability and reliability of the system under high concurrency loads. This design, in conjunction with the multi-core CPU module on the SOC side and the command parsing agent module in the UVM environment, further optimizes the efficiency of multi-core concurrency control, providing efficient underlying support for hardware and software co-verification.

[0063] The above technical solutions solve the problems of conflict, data overwriting or loss caused by command queue resource contention during multi-core concurrent access, significantly improve the stability and reliability of the verification system, and provide a scalable technical foundation for software and hardware co-verification in complex SOC designs.

[0064] See Figure 5 This application also discloses a verification method based on the interaction between a SOC software system and UVM hardware simulation, applied to the aforementioned verification system. The method includes:

[0065] S1. Command writing: The multi-core CPU module on the SOC side writes control commands to the predefined AMBA bus address segment through memory-mapped I / O;

[0066] S2. Transaction Capture: The Command Parsing Agent module captures AMBA bus transactions in real time and extracts command data;

[0067] S3. Concurrency resolution:

[0068] Verify the validity of the command header and return an error for invalid commands;

[0069] Parse the thread ID, command type, and parameters;

[0070] Commands are stored in their corresponding independent queues based on thread IDs.

[0071] S4. Command Execution: The queue triggers the verification component to execute the command and writes the result to a predefined feedback address;

[0072] S5. Result Acquisition: The multi-core CPU module on the SOC side polls the feedback address to obtain the execution result.

[0073] The core innovation of this embodiment lies in combining the multi-core CPU module on the SOC side with the command parsing agent module through a standardized AMBA interface, and introducing a thread ID routing mechanism, an independent command queue buffer, and an atomic operation lock design. This effectively solves the problems of low communication efficiency between the SOC software system and the UVM hardware simulation environment, multi-core concurrent access conflicts, and complex command parsing, thereby improving the efficiency of software and hardware co-verification. Specifically, step S1 uses memory-mapped I / O to write control commands into a predefined AMBA bus address segment, unifying the communication interface, avoiding the complexity of custom interfaces, and improving command writing efficiency. Step S2 uses the command parsing agent module to capture AMBA bus transactions in real time and extract command data, ensuring timely command acquisition and transmission and reducing communication latency. Step S3's concurrent parsing mechanism first verifies the validity of the command header to filter out illegal commands and prevent erroneous commands from causing system anomalies. Then, it parses the thread ID, command type, and parameters to extract key information. Finally, based on the thread ID, it stores the command in the corresponding independent queue, realizing concurrent control of multi-core CPUs and avoiding command conflicts and data loss. Step S4 triggers the verification component to execute commands through the queue and writes the results to a predefined feedback address, ensuring the accuracy of command execution and the traceability of results. Step S5 uses the SOC-side multi-core CPU module to poll the feedback address to obtain the execution results, completing the interactive closed loop and improving result acquisition efficiency.

[0074] In practical applications, the multi-core CPU module on the SOC side can implement its functions in various ways, such as using ARM Cortex-A series processors or multi-core RISC-V architecture processors. Its main purpose is to provide the SOC system with efficient multi-core computing capabilities. Furthermore, the standard AMBA bus interface can be understood as a general on-chip communication protocol, and its specific implementation can use lightweight protocols such as AXI-Lite or APB to meet the communication needs of different scenarios. For the command parsing agent module, its core function is to parse and distribute control commands. Specifically, command parsing can be implemented through hardware logic circuits, such as using a finite state machine to verify the command header, or using software algorithms to parse the command format. Furthermore, the thread ID routing mechanism can be implemented using a hash table or direct mapping, its main purpose being to ensure that each thread's command can be accurately distributed to the corresponding processing path. The specific implementation of the independent command queue buffer can use a circular buffer or a double-ended queue structure to support efficient data storage and access. In addition, atomic operation locks can be implemented using hardware semaphores or software mutexes, their main function being to ensure the consistency of access to shared resources.

[0075] The verification component's function is to execute the parsed commands and feed the results back to the SOC side. Specifically, command execution can be achieved by calling predefined function libraries, such as test functions written in C or scripted automated testing tools. Furthermore, writing to the feedback address can be accomplished through direct memory access or register mapping, with the main purpose of establishing a fast-responding closed-loop communication link.

[0076] In summary, this embodiment solves the problems of inconsistent interfaces, multi-core concurrency conflicts, and low efficiency in communication between the SOC software system and the UVM hardware simulation environment through standardized interface design and multi-core concurrency control mechanism, significantly improving communication efficiency and verification reliability.

[0077] In this document, the terms "upper," "lower," "front," "back," "left," "right," "top," "bottom," "inner," "outer," "vertical," and "horizontal," etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are only used for the clarity of expressing the technical solution and for the convenience of description, and therefore should not be construed as limiting the present invention.

[0078] In this document, the terms “comprising,” “including,” or any other variations thereof are intended to cover non-exclusive inclusion, which includes not only the elements listed but also other elements not expressly listed.

[0079] The foregoing has shown and described the basic principles, main features, and advantages of the present invention. Those skilled in the art should understand that the present invention is not limited to the above embodiments. The embodiments and descriptions in the specification are merely illustrative of the principles of the invention. Various changes and modifications can be made to the invention without departing from its spirit and scope, and all such changes and modifications fall within the scope of the present invention as claimed. The scope of protection of this invention is defined by the appended claims and their equivalents.

Claims

1. A verification system based on SOC software system and UVM hardware simulation interaction, characterized in that, The method comprises the following steps: A SOC-side multi-core CPU module is used to send a control command in a predefined format to a UVM environment through a standard AMBA bus interface; A command analysis Agent module in the UVM environment is used to capture and analyze the control command, and the multi-core concurrent control of the SOC-side multi-core CPU module is realized through a thread ID routing mechanism, an independent command queue buffer and an atomic operation lock; A verification component is used to execute the analyzed control command and write the result into a predefined feedback address.

2. The verification system based on the interaction of the SOC software system and the UVM hardware simulation according to claim 1, characterized in that, The standard AMBA bus interface adopts an AXI or AHB protocol, and the control command is written into a dynamically allocated AMBA address segment through memory-mapped I / O, and the address segment range is determined according to the maximum number of CPU cores.

3. The verification system of SOC software system and UVM hardware simulation interaction based on claim 1, characterized in that, The analysis logic of the command analysis Agent module comprises the following steps: checking the command header validity of the control command and filtering illegal commands; extracting the thread ID, command type and operation parameters in the control command format; distributing the control command to the corresponding verification component based on the thread ID.

4. The verification system of SOC software system and UVM hardware simulation interaction based on claim 1, characterized in that, The independent command queue allocates independent storage space for each CPU core or thread, and synchronizes the shared resource access through an atomic operation lock.

5. The verification system of SOC software system and UVM hardware simulation interaction based on claim 4, characterized in that, The atomic operation lock adopts a hardware-supported synchronization mechanism and is realized through a test-and-set instruction or a compare-and-swap instruction, and is used to ensure data consistency and operation sequence when multiple threads access shared resources.

6. The verification system of claim 3, wherein, The verification component executes the control command by calling a predefined function library, and the function library comprises a test function or a scripted automated test tool; the execution result is written into the predefined feedback address through direct memory access or register mapping.

7. A verification method based on SOC software system and UVM hardware simulation interaction, applied to the verification system of any one of claims 1-6, characterized in that, The method comprises the following steps: S1. Command writing: the SOC-side multi-core CPU module writes the control command into a predefined AMBA bus address segment through memory-mapped I / O; S2. Transaction capture: the command analysis Agent module captures the AMBA bus transaction in real time and extracts the command data; S3. Concurrent analysis: checking the command header validity and returning an error for illegal commands; analyzing the thread ID, command type and parameters; storing the command into the corresponding independent queue based on the thread ID; S4. Command execution: the queue triggers the verification component to execute the command and writes the result into a predefined feedback address; S5. Result acquisition: the SOC-side multi-core CPU module polls the feedback address to obtain the execution result.

8. The verification method of interaction between SOC-based software system and UVM hardware simulation according to claim 1, characterized in that, In the S3 step, a hash table or direct mapping method is used to realize the command routing mechanism based on the thread ID, so as to ensure that the command of each CPU core is accurately distributed to the corresponding processing path and realize the isolated processing of multi-core commands.

9. The verification method of interaction between SOC-based software system and UVM hardware simulation according to claim 1, characterized in that, The verification component in the S4 step calls different test functions or automated scripts to execute specific verification tasks according to the command type, and generates result information containing a status code and output data after the execution is completed, and writes the result information into the feedback address region corresponding to the initiating core for independent reading by the SOC-side CPU core.

10. A computer readable storage medium having stored thereon computer programs / instructions, characterized in that, The computer program / instruction is executed by the processor to realize the verification method based on the SOC software system and UVM hardware simulation interaction according to claim 5.

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