Core particle interface circuit for core particle data transmission and related product

Abstract

The invention discloses a core particle interface circuit for core particle data transmission and a related product thereof, the core particle interface circuit comprises a core particle bus interface module, a format conversion module and a core particle interconnection interface module which are connected in sequence, the core particle bus interface module is used for receiving first bus data from a first bus, and the format conversion module is used for converting the first bus data into the first bus data; transmitting second bus data acquired from other core particles to the first bus; the format conversion module is used for converting the first bus data into first core particle data in a core particle data format suitable for transmission among core particles, and converting second core particle data in a core particle data format obtained from other core particles into second bus data in a bus data format suitable for bus transmission; the core particle interconnection interface module is used for transmitting the first core particle data to other core particles and receiving second core particle data transmitted by other core particles. By means of the core particle interface circuit in the scheme, data transmission between the core particles can be achieved, and therefore data transmission between buses connected with the core particles is achieved.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of chiplet data transmission. More particularly, the present application relates to a chiplet interface circuit, a chiplet, a chiplet-to-chiplet data transmission system and a method for chiplet-to-chiplet data transmission. BACKGROUND

[0002] In recent years, Moore's Law has gradually slowed down, and the update cycle has become longer. Therefore, the concept of chiplet has been proposed. With the continuous progress of manufacturing technology, the traditional single chip design faces the increase in size and complexity, leading to manufacturing difficulties and cost increases. The rise of chiplet is to split the entire system into multiple small chips, and through modular design and heterogeneous integration, a more flexible and customized solution is achieved, which adapts to the evolution of the industrial ecosystem and provides the possibility of finding a better balance between cost and efficiency.

[0003] The key of chiplet technology is to interconnect small chiplets through a unified and stable interconnection protocol. Therefore, it is necessary to provide a chiplet interface circuit, a chiplet, a chiplet-to-chiplet data transmission system and a method for chiplet-to-chiplet data transmission, which can realize data transmission between chiplets, thereby realizing data transmission between buses connected with chiplets, and further meeting data transmission requirements. SUMMARY

[0004] In order to at least solve one or more technical problems as mentioned above, the present application provides a chiplet interface circuit, a chiplet, a chiplet-to-chiplet data transmission system and a method for chiplet-to-chiplet data transmission.

[0005] In a first aspect, the present application provides a chiplet interface circuit for chiplet data transmission, comprising a chiplet bus interface module, a format conversion module and a chiplet interconnection interface module, which are connected in sequence, wherein: the chiplet bus interface module is configured to receive first bus data from a first bus, and transmit second bus data obtained by other chiplets to the first bus; the format conversion module is configured to convert the first bus data into first chiplet data in a chiplet data format suitable for chiplet-to-chiplet transmission, and convert second chiplet data in a chiplet data format obtained by other chiplets into the second bus data in a bus data format suitable for bus transmission; and the chiplet interconnection interface module is configured to transmit the first chiplet data to other chiplets, and receive the second chiplet data transmitted by other chiplets.

[0006] In one embodiment, the first bus comprises a plurality of data transmission channels, wherein each data transmission channel is used to transmit bus data in a format; and the die interface circuit further comprises a selection module electrically connected with the plurality of data transmission channels of the first bus and the die bus interface module and used to select a corresponding data transmission channel in the first bus to transmit corresponding first bus data and transmit the second bus data to the first bus.

[0007] In one embodiment, the selection module comprises a multiplexer electrically connected with each data transmission channel of the first bus and the die bus interface module respectively and used to select a corresponding data transmission channel to communicate with the die bus interface module and disconnect other data transmission channels from the die bus interface module, so as to transmit first bus data to other dies through the data transmission channel communicating with the die bus interface module and transmit the second bus data to the first bus; and a controller electrically connected with the multiplexer and used to control the multiplexer to select the corresponding data transmission channel of the first bus to communicate with the die bus interface module and disconnect other data transmission channels from the die bus interface module.

[0008] In one embodiment, the selection module is integrated with the die bus interface module or arranged outside the die bus interface module.

[0009] In one embodiment, the format conversion module is further used to compress the first die data into a compressed package, so as to transmit the compressed package to other dies through the die interconnection interface module; and decompress the received second die data, so as to convert the decompressed data into the second bus data.

[0010] In one embodiment, the die interface circuit further comprises a test module electrically connected with the die interconnection interface module and used to acquire test data transmitted by other die interface circuits through the die interconnection interface module; and compare the test data with standard data, so as to determine whether data transmission can be performed between two die interface circuits according to a comparison result.

[0011] In one embodiment, the die interconnection interface module is a high-speed interface module, and the test data comprises a pseudo-random binary sequence.

[0012] In a second aspect, the present application further provides a die comprising a die interface circuit according to any embodiment of the first aspect.

[0013] In a third aspect, the present application also provides a chiplet-to-chiplet data transmission system, comprising: a first chiplet according to the embodiment of the second aspect described above, configured to: convert third bus data transmitted by a first bus into third chiplet data for transmission to a second chiplet; and convert fourth chiplet data obtained from the second chiplet into bus data for transmission to the first bus; and a second chiplet according to the embodiment of the second aspect described above, electrically connected to the first chiplet and configured to: convert the third chiplet data into bus data for transmission to a second bus; and convert fourth bus data transmitted by the second bus into the fourth chiplet data for transmission to the first chiplet.

[0014] In a fourth aspect, the present application also provides a method of chiplet-to-chiplet data transmission, based on the chiplet-to-chiplet data transmission system according to the embodiment of the third aspect described above, the method comprising: the first chiplet converting third bus data transmitted by a first bus into third chiplet data; and the second chiplet converting the third chiplet data into bus data for transmission to a second bus; or the second chiplet converting fourth bus data transmitted by a second bus into fourth chiplet data; and the first chiplet converting the fourth chiplet data into bus data for transmission to the first bus.

[0015] By means of the chiplet interface circuit, the chiplet, the chiplet-to-chiplet data transmission system and the method of chiplet-to-chiplet data transmission as provided above, data transmission between chiplets can be achieved, thereby achieving data transmission between buses connected with the chiplets, and thus meeting the data transmission requirement. BRIEF DESCRIPTION OF DRAWINGS

[0016] The above and other objects, features and advantages of the present application will become more apparent from the following detailed description when taken in conjunction with the accompanying drawings in which a number of embodiments of the present application are shown by way of example, and like or corresponding reference numerals are used to refer to like or corresponding elements throughout. In the drawings:

[0017] Figure 1 A schematic block diagram of a chiplet interface circuit for chiplet data transmission is shown, which illustrates some embodiments of the present application;

[0018] Figure 2 A schematic block diagram of a chiplet interface circuit for chiplet data transmission is shown, which illustrates some other embodiments of the present application;

[0019] Figure 3 A schematic block diagram of a chiplet is shown, which illustrates some embodiments of the present application;

[0020] Figure 4 A schematic block diagram of a chiplet-to-chiplet data transmission system is shown, which illustrates some embodiments of the present application;

[0021] Figure 5A flowchart illustrating a method of inter-core data transmission of some embodiments of the present application is shown.

[0022] Figure 6 A flowchart illustrating a method of inter-core data transmission of some embodiments of the present application is shown. DETAILED DESCRIPTION

[0023] The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are some but not all of the embodiments of the present application. Based on the embodiments in the present application, all other embodiments obtained by a person of ordinary skill in the art without creative work fall within the protection scope of the present application.

[0024] It should be understood that the terms "comprise" and "include" used in the specification and claims of the present application indicate the presence of the described features, integers, steps, operations, elements, and / or components but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof.

[0025] It should also be understood that the terms used in the specification of the present application are only for the purpose of describing specific embodiments and are not intended to limit the present application. As used in the specification and claims of the present application, the singular forms "a", "an" and "the" are intended to include the plural forms unless the context clearly indicates otherwise. It should be further understood that the term "and / or" used in the specification and claims of the present application means any combination of one or more of the associated listed items and all possible combinations thereof, and includes these combinations.

[0026] As used in the specification and claims of the present application, the term "if" can be interpreted as "when" or "upon" or "in response to determining" or "in response to detecting" depending on the context. Similarly, the phrases "if it is determined" or "if [a described condition or event] is detected" can be interpreted to mean "upon determining" or "in response to determining" or "upon detecting [a described condition or event]" or "in response to detecting [a described condition or event]" depending on the context.

[0027] The specific embodiments of the present application will be described in detail below with reference to the accompanying drawings.

[0028] When data transmission is performed between the corelets, one corelet can convert the data format of the input data into another data format (e.g., corelet data format) suitable for the inter-corelet transmission, and then transmit the data into the opposite corelet. The corelet data format can be, for example, [179:164] data crc check information; [163:128] data sel, valid, yummy information; or [127:0] data information. After the opposite corelet receives the corelet data in the corelet data format, in order to output the data externally (e.g., to the bus), the data is converted into another data format (e.g., bus data format) suitable for the data format requirement of the external device connected to the corelet. For example, when corelet 1 and corelet 2 transmit bus data (transmit data from the first bus to the second bus, the first bus is connected to corelet 1, and the second bus is connected to corelet 2), corelet 1 can first convert the bus data transmitted from the first bus into corelet data, and transmit the corelet data to corelet 2. Corelet 2 converts the corelet data into bus data and transmits the bus data to the second bus, thereby achieving data transmission from the first bus to the second bus.

[0029] The above describes one-way data transmission from the first bus to the second bus. In order to also achieve reverse data transmission (e.g., data transmission from the second bus to the first bus) when the corelet connection relationship does not change, corelet 1 can have the function of corelet 2 described above, and corelet 2 can have the function of corelet 1 described above, i.e., the functions of corelet 1 and 2 are reversed. That is, corelet 1 can convert corelet data into bus data, and corelet 2 can convert bus data into corelet data. In this way, corelet 2 can receive bus data transmitted from the second bus, convert the bus data into corelet data, and transmit the corelet data to corelet 1. Corelet 1 converts the corelet data into bus data and transmits the bus data from the first bus.

[0030] In short, each corelet can have the bidirectional data conversion function of converting data in a first data format into data in a second data format and converting data in the second data format into data in the first data format.

[0031] It can be understood that, in addition to being able to perform data transmission between buses, the corelet can also achieve data transmission between other types of external devices, as long as the data format of the data transmitted by the external device is converted into the corelet data format.

[0032] In order to simplify the structure of the corelet, in one embodiment, the corelet interface circuit can be located inside the corelet and integrated with the corelet. In another embodiment, in order to facilitate replacement or installation, the corelet interface circuit can also be located outside the corelet, and the present embodiment does not limit this.

[0033] The following describes various embodiments of the present application in terms of the data transmission manner and structure between the above-mentioned corelets. The following embodiments are described by taking the corelets as an example to realize the data transmission between the buses.

[0034] Figure 1 A principle block diagram of a corelet interface circuit 100 for corelet data transmission of some embodiments of the present application is shown. As shown in Figure 1 The corelet interface circuit 100 of the present application can include a corelet bus interface module 101, a format conversion module 102 and a corelet interconnection interface module 103, which are connected in sequence, as shown in Figure 1 A first bus is also shown by way of example in

[0035] As described above, the corelet interface circuit 100 can be used to transmit bus data, based on which, in one embodiment, the above-mentioned corelet bus interface module 101 can be used to receive first bus data from the first bus (the corelet interface circuit 100 is connected with the first bus). Based on the different bus protocols, the first bus data can include but is not limited to data in formats such as AXI, NOC or TL protocols, etc.

[0036] In order to transmit the data transmitted by the opposite corelet to the first bus, the above-mentioned corelet bus interface module 101 can also be used to transmit second bus data acquired by other (opposite) corelets to the first bus (the opposite corelet is connected with the second bus).

[0037] In order to meet the data transmission format requirements between the corelets, the above-mentioned format conversion module 102 can be used to convert the first bus data into first corelet data in a corelet data format suitable for transmission between the corelets. In order to facilitate the transmission of the corelet data transmitted by the opposite corelet to the first bus, the format conversion module 102 can also convert second corelet data in a corelet data format acquired by other corelets into second bus data in a bus data format suitable for transmission by the bus.

[0038] In one embodiment, the above-mentioned corelet interconnection interface module 103 can be used to transmit the first corelet data to other corelets to realize the data transmission between the corelets. The above-mentioned corelet interconnection interface module 103 can also receive second corelet data transmitted by other corelets, so as to transmit the second corelet data to the first bus after converting the second corelet data into bus data by the corelet. In order to adapt to the high-speed data transmission between the corelets, the corelet interconnection interface module 103 can be a high-speed interface module.

[0039] As can be seen from the above description, the core particle interface circuit 100 according to the present solution can realize data transmission between core particles, thereby realizing data transmission between buses connected with the core particles, and further meeting the data transmission requirement.

[0040] In some implementation scenarios, the first bus can include a plurality of data transmission channels, wherein each data transmission channel can be used to transmit bus data of one format. For example, the first bus can include three data transmission channels, and the three data transmission channels can respectively transmit AXI, NOC or TL protocol data. In order for the core particle to transmit corresponding one kind of bus data, the core particle interface circuit 100 can further include a selection module (not shown in the figure), which can be electrically connected with the plurality of data transmission channels of the first bus and the core particle bus interface module and used to select a corresponding data transmission channel in the first bus to transmit corresponding first bus data.

[0041] As an example, the selection module can include a multiplexer and a controller. The multiplexer can be electrically connected with each data transmission channel of the first bus and the core particle bus interface module respectively and used to select one corresponding data transmission channel to communicate with the core particle bus interface module and disconnect the lines between other data transmission channels and the core particle bus interface module, so as to transmit first bus data to other core particles and second bus data to the first bus through the data transmission channel in communication with the core particle bus interface module. The type of the multiplexer can be selected according to the total data type of the first bus data to be transmitted, for example, if two protocols of first bus data are to be transmitted in total, a two-way multiplexer can be selected; if three protocols of first bus data are to be transmitted in total, a three-way multiplexer can be selected.

[0042] Taking the first bus including three data transmission channels as an example, it can transmit three protocols of first bus data, at this time the multiplexer can select a three-way multiplexer, and the three selection lines of the multiplexer can be connected with the three data transmission channels of the first bus respectively to form a first path corresponding to the first data transmission channel, a second path corresponding to the second data transmission channel and a third path corresponding to the third data transmission channel. Assuming that the first data transmission channel of the first bus transmits AXI protocol data, the second data transmission channel transmits NOC protocol data, and the third data transmission channel transmits TL protocol data, the first bus can transmit AXI protocol data to the opposite core particle through the first path, transmit NOC protocol data to the opposite core particle through the second path, and transmit TL protocol data to the opposite core particle through the third path. The multiplexer can select to use the corresponding path to transmit the corresponding bus data to the opposite core particle, thereby realizing transmission of multiple bus data.

[0043] The controller can be electrically connected with the multiplexer and used to control the multiplexer to select the corresponding data transmission channel of the first bus to be communicated with the die bus interface module and to disconnect the lines between other data transmission channels and the die bus interface module. For example, the controller controls the multiplexer to select the first data transmission channel of the first bus to be communicated with the die bus interface module and to disconnect the lines between the second data transmission channel and the third data transmission channel and the die bus interface module; or the controller controls the multiplexer to select the second data transmission channel of the first bus to be communicated with the die bus interface module and to disconnect the lines between the first data transmission channel and the third data transmission channel and the die bus interface module.

[0044] The controller can include a register, i.e., the control is realized by the register. In addition, the controller can also include a CPU (Central Processing Unit) or an MCU (Micro Control Unit) and the like, and at this time, the output of the corresponding control signal can be controlled by artificially inputting a signal to the controller. For example, when the AXI protocol data is to be transmitted, the first input signal is artificially input to the controller to control the output of the first control signal, so as to control the first data transmission channel of the first bus to transmit the AXI protocol data to the opposite die and subsequently transmit the second bus data to the first bus; similarly, when the first bus data to be transmitted is the NOC protocol data, the second input signal is artificially input to the controller to control the output of the second control signal, so as to control the second data transmission channel of the first bus to transmit the NOC protocol data to the opposite die and subsequently transmit the second bus data to the first bus; when the first bus data to be transmitted is the TL protocol data, the third input signal is artificially input to the controller to control the output of the third control signal, so as to control the third data transmission channel of the first bus to transmit the TL protocol data to the opposite die and subsequently transmit the second bus data to the first bus.

[0045] In addition to artificially inputting the signal to determine the control signal output by the controller, the input device can also be used to output the signal to the controller to determine the control signal output by the controller. For example, the first input signal is input to the controller by the input device to control the output of the first control signal; the second input signal is input to the controller by the input device to control the output of the second control signal; and the third input signal is input to the controller by the input device to control the output of the third control signal.

[0046] In order to make the die interface circuit simple in structure and small in size, the selection module can be integrated with the die bus interface module. In order to facilitate replacement and connection, the selection module can also be arranged outside the die bus interface module.

[0047] In order to meet the data transmission requirement between the corelets, save bandwidth and improve data transmission speed, the format conversion module can also be used to compress the first corelet data into a compressed package, so as to transmit the compressed package to other corelets through the corelet interconnection interface module. Similarly, the opposite corelet also transmits the second corelet data after compression, and therefore the format conversion module can also decompress the received compressed second corelet data, so as to convert the decompressed data into second bus data.

[0048] When data compression is performed, check code, package header, package tail and identification code can be added to the data. Still taking the first bus data including the three protocol data described above as an example, when the AXI bus data is transmitted, it can be packaged through 5 different channels, A bit check code, B bit package header, C bit package tail and D bit identification code are added, and then transmitted to the corelet interconnection interface module, and transmitted to the opposite corelet through die data transmission of N bit width; after the opposite corelet receives the encoded data package with AXI as the original protocol, the original AXI data is restored through format conversion, and then output to the corelet bus interface module of the opposite corelet, and finally output to the opposite bus (such as the second bus).

[0049] When the NOC bus data is transmitted, it is packaged through 7 different channels, E bit check code, F bit package header, G bit package tail and H bit identification code are added, and then transmitted to the corelet interconnection interface module, and transmitted to the opposite corelet through die data transmission of N bit width; after the opposite corelet receives the encoded data package with NOC as the original protocol, the original NOC data is restored through format conversion, and then output to the corelet bus interface module of the opposite corelet, and finally output to the opposite bus. It can be understood that the number of channels here is exemplary and not limiting, and the number of channels can also be increased or decreased as needed.

[0050] When the TL bus data is transmitted, it is packaged through 1 channel, I bit check code, J bit package header, K bit package tail and L bit identification code are added, and then transmitted to the corelet interconnection interface module, and transmitted to the opposite corelet through die data transmission of N bit width; after the opposite corelet receives the encoded data package with TL as the original protocol, the original TL data is restored through format conversion, and then output to the corelet bus interface module of the opposite corelet, and finally output to the opposite bus. It can be understood that the number of channels here is exemplary and not limiting, and the number of channels can also be increased as needed.

[0051] To ensure reliable chip transmission, the data transmission link between chips can be tested before data transmission. Since the chip interconnect interface module of the chip interface circuit is prone to failure, this solution mainly tests the connectivity of the link between the chip interconnect interface modules of two connected chip interface circuits. The following section will combine... Figure 2 The chip interface circuit for solving this problem is explained.

[0052] Figure 2 A schematic block diagram of a chip interface circuit 200 for chip data transmission according to other embodiments of the present invention is shown.

[0053] like Figure 2 As shown, the chip interface circuit 200 may include the chip bus interface module 101, format conversion module 102, chip interconnect interface module 103, and test module 104 described above. The chip bus interface module 101, format conversion module 102, and chip interconnect interface module 103 have been described above in conjunction with the embodiments, and will not be described in detail here.

[0054] like Figure 2 As shown, the test module 104 can be electrically connected to the chip interconnect interface module 103 and is used to acquire test data transmitted by other chip interface circuits via the chip interconnect interface module 103; and to compare the test data with standard data to determine whether data transmission is possible between the two chip interface circuits based on the comparison result.

[0055] Test data can include, but is not limited to, various test sequences, such as pseudo-random binary sequences (PRBS). Standard data can be sequences corresponding to (e.g., identical to) the PRBS. When the two sequences match (e.g., are identical), the data transmission link formed by the interconnect interface modules of the two cores is confirmed to be normal, and data transmission can proceed. Conversely, when the two sequences do not match (e.g., are different), the data transmission link formed by the interconnect interface modules of the two cores is confirmed to be abnormal, and data transmission cannot proceed.

[0056] In one embodiment, the test module 104 may include multiple XOR gates corresponding to multiple channels (corresponding to 80-bit wide pins). Each XOR gate includes a first input for receiving test data, a second input for receiving standard data, and an output for outputting the comparison result. The multiple channels are primarily for easier control; adjacent XOR gates are connected in pairs to quickly locate the failed channel. For example, if a channel fails, its XOR result will propagate upwards layer by layer, allowing for rapid determination of the result.

[0057] Figure 3A principle block diagram of the corelet 300 of some embodiments of the present application is shown. In order to describe the connection between the corelet 300 and the bus and the data transmission manner, Figure 3 A first bus connected with the corelet 300 is also exemplarily shown in the

[0058] As Figure 3 As shown in the

[0059] As described in the foregoing embodiments, the corelet interface circuit 301 can be located inside the corelet 300 and integrated with the corelet 300, or located outside the corelet 300. According to the foregoing description of the corelet interface circuit, the corelet 300 including the corelet interface circuit 301 adopting the present solution can realize the data transmission between the corelet 300 and the corelet on the opposite side (for example, the corelet on the opposite side has the same structure as the corelet described in the present application), so as to realize the data transmission between the first bus and the bus connected with the corelet on the opposite side, and further meet the data transmission requirement.

[0060] Figure 4 A principle block diagram of the inter-corelet data transmission system 400 of some embodiments of the present application is shown.

[0061] As Figure 4 As shown in the Figure 4

[0062] The corelet bus interface module 4011-1 of the first corelet 401 of the inter-corelet data transmission system 400 of the present embodiment is connected with the first bus, the corelet interconnection interface module 4011-3 thereof is electrically connected with the corelet interconnection interface module 4021-3 of the second corelet 402, and the corelet bus interface module 4021-1 of the second corelet 402 is connected with the second bus.

[0063] ​The first core 401 can be used to convert the third bus data transmitted by the first bus into third core data for transmission to the second core 402, and convert the fourth core data obtained from the second core 402 into bus data for transmission to the first bus.

[0064] The second core 402 can be electrically connected to the first core 401 and used to convert the third core data into bus data for transmission to the second bus, and convert the fourth bus data transmitted by the second bus into the fourth core data for transmission to the first core 401.

[0065] The third bus data and the fourth bus data can include, but are not limited to, the three types of protocol data described above. The first core 401 and the second core 402 can be arranged in the same way, for example, the core interface circuit 4011 of the first core 401 is integrated with the first core 401, and the core interface circuit 4021 of the second core 402 is integrated with the second core 402; or the core interface circuit 4011 of the first core 401 is located outside the first core 401, and the core interface circuit 4021 of the second core 402 is located outside the second core 402. In addition, the core interface circuits of the cores can be arranged differently from the cores, for example, the core interface circuit 4011 is integrated with the first core 401, and the core interface circuit 4021 is arranged outside the second core 402; or the core interface circuit 4011 is arranged outside the first core 401, and the core interface circuit 4021 is integrated with the second core 402.

[0066] According to the above description of the core part embodiments, the inter-core data transmission system 400 of the embodiments of the present application can realize data transmission between the first bus and the second bus, thereby meeting the data transmission requirements.

[0067] The inter-core data transmission method can be based on the inter-core data transmission system 400 described in the above embodiments. It can be understood that the inter-core data transmission can be data transmission from the first bus to the second bus, or data transmission from the second bus to the first bus, which can be realized by the inter-core data transmission system of the present application. Therefore, the method of the present application can include data transmission processes in two directions. The method of data transmission from the first bus to the second bus will be described first.

[0068] Figure 5 The flowchart of the inter-core data transmission method 500 of some embodiments of the present application is shown.

[0069] As Figure 5As shown in FIG. 5, the method 500 can include, at step S501, the first corelet converting third bus data transmitted by the first bus into third corelet data. Then, at step S502, the second corelet converts the third corelet data into bus data for transmission to the second bus. The method 500 of the embodiments of the present application can enable the first bus to transmit data to the second bus.

[0070] The present solution continues to describe the process of transmitting data from the second bus to the first bus.

[0071] Figure 6 A flowchart of a method 600 of transmitting data between corelets is shown for another embodiment of the present application.

[0072] As Figure 6 As shown in FIG. 6, the method 600 can include, at step S601, the second corelet converting fourth bus data transmitted by the second bus into fourth corelet data. Then, at step S602, the first corelet converts the fourth corelet data into bus data for transmission to the first bus. The method 600 of the embodiments of the present application can enable the second bus to transmit data to the first bus.

[0073] While the present application has been shown and described with reference to several embodiments thereof, it is to be understood that the application is not limited to the details of the embodiments described herein. Various other modifications and changes can be made thereto without departing from the spirit and scope of the application as set forth in the appended claims. It is intended that the scope of the application be defined by the claims appended hereto, rather than the description set forth above.

Claims

1. A chiplet interface circuit for chiplet data transmission, comprising a chiplet bus interface module, a format conversion module and a chiplet interconnect interface module, which are connected in sequence, wherein: the chiplet bus interface module is configured to receive first bus data from a first bus and transmit second bus data acquired by other chiplets to the first bus; the format conversion module is configured to convert the first bus data into first chiplet data in a chiplet data format suitable for inter-chiplet transmission, and convert second chiplet data in the chiplet data format acquired by other chiplets into the second bus data in a bus data format suitable for bus transmission; and the chiplet interconnect interface module is configured to transmit the first chiplet data to other chiplets and receive the second chiplet data transmitted by other chiplets.

2. The chiplet data transmission system according to claim 1, wherein the first bus comprises a plurality of data transmission channels, each of which is configured to transmit bus data in a format; and the chiplet interface circuit further comprises: a selection module electrically connected with the plurality of data transmission channels of the first bus and the chiplet bus interface module, and configured to select a corresponding data transmission channel in the first bus to transmit corresponding first bus data and transmit the second bus data to the first bus.

3. The chiplet data transmission system according to claim 2, wherein the selection module comprises: a multiplexer electrically connected with each data transmission channel of the first bus and the chiplet bus interface module respectively, and configured to select a corresponding data transmission channel to communicate with the chiplet bus interface module and disconnect lines between other data transmission channels and the chiplet bus interface module, so as to transmit first bus data to other chiplets and transmit the second bus data to the first bus through the data transmission channel communicating with the chiplet bus interface module; and a controller electrically connected with the multiplexer and configured to control the multiplexer to select the corresponding data transmission channel of the first bus to communicate with the chiplet bus interface module and disconnect lines between other data transmission channels and the chiplet bus interface module.

4. The chiplet data transmission system according to claim 2 or 3, wherein the selection module is integrated with the chiplet bus interface module or disposed outside the chiplet bus interface module.

5. The chiplet interface circuit according to claim 1, wherein the format conversion module is further configured to: compress the first chiplet data into a compressed package, so as to transmit the compressed package to other chiplets through the chiplet interconnect interface module; and decompress the received compressed second chiplet data, so as to convert the decompressed data into the second bus data.

6. The chiplet interface circuit according to claim 1, further comprising a test module electrically connected with the chiplet interconnect interface module and configured to: acquire test data transmitted by other chiplet interface circuits via the chiplet interconnect interface module; and transmit the acquired test data to other chiplet interface circuits via the chiplet interconnect interface module. ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ The test data is compared with standard data to determine whether data transmission between the two die interface circuits is possible based on the comparison result.

7. The die interface circuit of claim 6, wherein the die interconnect interface module is a high speed interface module, and the test data comprises a pseudo-random binary sequence.

8. A die comprising the die interface circuit of any one of claims 1-7.

9. A die-to-die data transmission system comprising: a first die according to claim 8, configured to: convert third bus data transmitted by a first bus into third die data for transmission to a second die; and convert fourth die data obtained from the second die into bus data for transmission to the first bus; and a second die according to claim 8, electrically connected to the first die and configured to: convert the third die data into bus data for transmission to a second bus; and convert fourth bus data transmitted by the second bus into the fourth die data for transmission to the first die.

10. A method of die-to-die data transmission based on the die-to-die data transmission system of claim 9, the method comprising: the first die converting third bus data transmitted by a first bus into third die data; and the second die converting the third die data into bus data for transmission to a second bus; or the second die converting fourth bus data transmitted by a second bus into fourth die data; and the first die converting the fourth die data into bus data for transmission to the first bus. ​ ​

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