Data transmission method, device, system, equipment, cluster, product and medium

Abstract

The invention provides a data transmission method, device and system, equipment, a cluster, a product and a medium. The method is applied to a transfer device, and comprises: receiving a first signaling sent by an input / output chip in a first channel, the first signaling comprising control information and data information, the first channel being one of a plurality of channels between the input / output chip and the transfer device, and the first signaling comprising control information and data information; the transfer equipment is a memory controller or a cache, and the control information is used for bearing an operation request of writing data in the data information into the transfer equipment by an input / output chip; and sending a first response to the input / output chip based on the first signaling. According to the scheme, the signaling interaction process can be effectively reduced, and the transmission efficiency is improved.

Description

Technical Field

[0001] This application relates to the field of computers, and more particularly to a data transmission method, apparatus, system, device, cluster, product, and medium. Background Technology

[0002] like Figure 1 As shown, the computing device may include a processor 110, a cache 120, a memory controller 130, and an input / output chip 140. The processor 110, cache 120, memory controller 130, and input / output chip 140 communicate with each other via a bus 150. The memory controller 130 is the memory controller used to control the memory. Between any two nodes, there are request channels, response channels, data channels, and listening channels. The request channel transmits signaling about requests, the response channel transmits signaling about responses, the data channel transmits signaling about data, and the listening channel transmits signaling about listening.

[0003] When the input / output chip 140 receives data, it needs to be sent to the processor 110 through the memory controller 130 and the cache 120. However, currently, these chips need to go through a very complicated handshake process to achieve data transmission, resulting in very low data transmission efficiency. Summary of the Invention

[0004] This application provides a data transmission method, apparatus, system, device, cluster, product, and medium that can effectively reduce signaling interaction processes and improve transmission efficiency.

[0005] Firstly, a data transmission method is provided. A relay device receives a first signaling message sent by an input / output chip (I / O chip) on a first channel, and sends a first response to the I / O chip based on the first signaling message. The first signaling message includes control information and data information. The first channel is one of multiple channels between the I / O chip and the relay device. The relay device is a memory controller or a cache. The control information carries an operation request from the I / O chip to write data from the data information to the relay device. For example, the first channel can be a request channel or a data channel between the I / O chip and the relay device. The first channel can also be a listening channel or a response channel between the I / O chip and the relay device, or even a newly established channel. In existing protocols, control information can be transmitted through a request channel between the I / O chip and the relay device, and data information can be transmitted through a data channel between the I / O chip and the relay device. However, in this application, the control information and data information are carried in a single signaling message and transmitted in one channel (e.g., a request channel or a data channel).

[0006] In the above scheme, the control information and data information that the original transmission protocol stipulated should be transmitted through two channels are merged into a single signaling message and transmitted through one channel, thereby reducing the complexity of signaling interaction and improving the efficiency of data transmission.

[0007] In some possible designs, the first response sent to the input / output chip based on the first signaling includes: if the number of signaling processed by the relay device is greater than or equal to a quantity threshold, sending a first failure response to the input / output chip to discard the first signaling; and if the number of signaling processed by the relay device is less than the quantity threshold, sending a first success response to the input / output chip. The quantity threshold is determined based on the processing capability of the relay device. Here, the relay device is a cache. The processing capability of the relay device can be determined based on the number of processors in the relay device, the clock frequency of the processors, the number of registers in the processors, etc.

[0008] In the above scheme, since the capacity of the cache is smaller than that of the main memory, the main memory unconditionally receives the data information received by the input / output chip. Therefore, the main memory will not send a failure response to the input / output chip. However, the cache only receives the data information received by the input / output chip when needed. Now, by bypassing the main memory and sending the data information directly to the cache through the input / output chip, it is assumed that the cache needs the data received by the output chip. Thus, the data received by the input / output chip is sent to the cache in advance. Therefore, the cache needs to have the ability to reject, that is, the ability to send a failure response to the input / output chip.

[0009] In some possible designs, the first opcode carried in the opcode field of the first failure response is different from the second opcode carried in the opcode field of the first success response.

[0010] In some possible designs, the data information includes the values ​​of data error field, data status field, data key step identifier field, data step count identifier field, data validity field, data field, and byte error field.

[0011] In some possible designs, the control information includes values ​​for a data size field, an address field, a non-security flag field, a memory attribute field, a listener attribute field, a logical processor identifier field, a expected completion confirmation field, and a memory partition monitoring field. The values ​​of the data size field, address field, non-security flag field, memory attribute field, listener attribute field, logical processor identifier field, and expected completion confirmation field of the control information are carried in reserved fields of the first signaling.

[0012] In some possible designs, the control information may further include one or more values ​​from the following: a prefetch target node identifier field, a prefetch target node valid identifier field, a prefetch logic processor identifier field, a prefetch logic processor valid identifier field, and a memory partition monitoring field. The values ​​of the prefetch target node identifier field and the prefetch target node valid identifier field of the control information are carried in either the master node identifier field or the data buffer identifier field of the first signaling; the values ​​of the prefetch logic processor identifier field and the prefetch logic processor valid identifier field of the control information are carried in the data validity field of the first signaling; and the value of the memory partition monitoring field of the control information is carried in the other of the master node identifier field and the data buffer identifier field of the first signaling.

[0013] In some possible designs, the relay device is a memory controller. After receiving the first signaling sent by the input / output chip, the method further includes: sending a second signaling to the cache via a second channel, and receiving a second response sent by the cache based on the second signaling. The second signaling includes listening information and data information. The second channel is one of multiple channels between the memory controller and the cache. The listening information is used to instruct the cache to ensure cache consistency with other caches and to notify the cache to retrieve data from the data information from the memory controller. The second channel can be a listening channel or a data channel between the memory controller and the cache. The second channel can also be a request channel or a response channel between the memory controller and the cache, or even a newly established channel. In existing protocols, listening information can be transmitted through a listening channel between the memory controller and the cache, and data information can be transmitted through a data channel between the memory controller and the cache. However, in this application, the listening information and data information are carried in a single signaling message and transmitted in one channel (e.g., a listening channel or a data channel).

[0014] In the above scheme, the monitoring information and data information that should have been transmitted through two channels according to the original transmission protocol are combined into the same signaling and transmitted through one channel, thereby reducing the complexity of signaling interaction and improving the efficiency of data transmission.

[0015] In some possible designs, the monitoring information includes the values ​​of a prefetch logic processor identifier field, a prefetch logic processor valid identifier field, an address field, and a non-security flag field. The values ​​of the prefetch logic processor identifier field and the prefetch logic processor valid identifier field of the monitoring information are carried in either the master node identifier field or the data buffer identifier field in the second signaling; the values ​​of the address field and the non-security flag field of the monitoring information are carried in the data validity field of the second signaling.

[0016] In some possible designs, the monitoring information also includes the value of a memory partition monitoring field, which is carried by either the master node identifier field or the data buffer identifier field in the second signaling.

[0017] Secondly, a data transmission method is provided. An input / output chip sends a first signaling message to a relay device via a first channel, and receives a first response from the relay device based on the first signaling message. The first signaling message includes control information and data information. The first channel is one of multiple channels between the input / output chip and the relay device. The relay device is a memory controller or a cache. The control information carries an operation request from the input / output chip to write data from the data information to the relay device.

[0018] In some possible designs, the first response sent to the input / output chip based on the first signaling includes:

[0019] If the number of signaling messages processed by the relay device exceeds a certain threshold, a first failure response is sent to the input / output chip, discarding the first signaling message. The certain threshold is determined based on the processing capacity of the relay device. If the number of signaling messages processed by the relay device is less than the certain threshold, a first success response is sent to the input / output chip. The processing capacity of the relay device is determined based on the number of processors, the processor clock frequency, the number of processor registers, etc.

[0020] In some possible designs, the first opcode carried in the opcode field of the first failure response is different from the second opcode carried in the opcode field of the first success response.

[0021] In some possible designs, the data information includes the values ​​of data error field, data status field, data key step identifier field, data step count identifier field, data validity field, data field, and byte error field.

[0022] In some possible designs, the control information includes values ​​for a data size field, an address field, a non-security flag field, a memory attribute field, a listener attribute field, a logic processor identifier field, and a expected completion acknowledgment field. The values ​​of the data size field, address field, non-security flag field, memory attribute field, listener attribute field, logic processor identifier field, and expected completion acknowledgment field of the control information are carried in reserved fields of the first signaling.

[0023] In some possible designs, the control information may further include one or more values ​​from the following: a prefetch target node identifier field, a prefetch target node valid identifier field, a prefetch logic processor identifier field, a prefetch logic processor valid identifier field, and a memory partition monitoring field. The values ​​of the prefetch target node identifier field and the prefetch target node valid identifier field of the control information are carried in either the master node identifier field or the data buffer identifier field of the first signaling; the values ​​of the prefetch logic processor identifier field and the prefetch logic processor valid identifier field of the control information are carried in the data validity field of the first signaling; and the value of the memory partition monitoring field of the control information is carried in the other of the master node identifier field and the data buffer identifier field of the first signaling.

[0024] Thirdly, a data transmission apparatus is provided, the apparatus comprising:

[0025] The receiving module is used to receive a first signaling sent by the input / output chip in a first channel. The first signaling includes control information and data information. The first channel is one of a plurality of channels between the input / output chip and the data transmission device. The data transmission device is a memory controller or a cache. The control information is used to carry an operation request from the input / output chip to write data in the data information to the relay device.

[0026] The sending module is used to send a first response to the input / output chip based on the first signaling.

[0027] Fourthly, a data transmission device is provided, the device comprising:

[0028] The sending module is used to send a first signaling to a relay device through a first channel, wherein the first signaling includes control information and data information, the first channel is one of a plurality of channels between the data transmission device and the relay device, the relay device is a memory controller or a cache, and the control information is used to carry an operation request from the input / output chip to write data in the data information to the relay device;

[0029] The receiving module is used to receive the first response sent by the relay device based on the first signaling.

[0030] Fifthly, a data transmission system is provided, the system comprising: a relay device and an input / output chip, the relay device being configured to perform the method as described in any of the first aspects, and the input / output chip being configured to perform the method as described in any of the second aspects.

[0031] A sixth aspect provides a computing device comprising a processor, a relay device, and an input / output chip, the relay device being configured to perform the method as described in any of the first aspects, and the input / output chip being configured to perform the method as described in any of the second aspects.

[0032] In a seventh aspect, a computing device cluster is provided, comprising multiple computing devices, at least the computing devices being the devices described in the sixth aspect.

[0033] Eighthly, a computer program product comprising instructions is provided, characterized in that, when the instructions are executed by a computing device, the computing device performs the operational steps of the method described in either the first or second aspect.

[0034] A ninth aspect provides a computer-readable storage medium including computer program instructions that, when executed by a computing device, cause the computing device cluster to perform operational steps as described in either the first or second aspect. Attached Figure Description

[0035] Figure 1 This is a schematic diagram of the structure of a computing device provided by existing technology;

[0036] Figure 2 This is a flowchart illustrating a data transmission method provided in this application;

[0037] Figure 3 This is a flowchart illustrating another data transmission method provided in this application;

[0038] Figure 4 This is a schematic diagram of a chip packaging method provided in this application;

[0039] Figure 5 This is a schematic diagram of the structure of a data transmission system provided in this application. Detailed Implementation

[0040] See Figure 2 , Figure 2 This is a flowchart illustrating a data transmission method provided in this application. The data transmission method in this embodiment transmits data from the input / output chips to the processor stage by stage. For example... Figure 2 As shown, the data transmission method in this embodiment includes:

[0041] S201: The input / output chip sends a first signaling message to the high-speed register through the first channel. Correspondingly, the high-speed register receives the first signaling message sent by the input / output chip through the first channel.

[0042] The first signaling is used to directly write data from the input / output chip into the cache. In existing technologies, because the capacity of the cache is usually relatively small, after the input / output chip receives data, it typically writes the data to a larger memory location. Then, the cache reads the data from memory, and the processor reads the data from the cache. However, in the data transmission method of this application, the processor bypasses memory and directly writes the data into the cache. The processor can then directly read the data from the cache without going through the process of the cache reading data from memory and then the processor reading data from the cache.

[0043] The first signaling message includes control information and data information. This first signaling message is transmitted through a first channel. The first channel is one of multiple channels between the input / output chip and the cache. The control information carries the operation request for the input / output chip to write data from the data information to the cache. For example, the first channel can be a request channel or a data channel between the input / output chip and the cache. The first channel can also be a listening channel or a response channel between the input / output chip and the cache, or even a newly established channel. In existing transmission protocols, control information can be transmitted through a request channel between the input / output chip and the cache, and data information can be transmitted through a data channel between the input / output chip and the cache. However, in this application, the control information and data information are carried in a single signaling message and transmitted through one channel (e.g., a request channel or a data channel). The transmission protocol can be a cache coherent interconnect (CHI) protocol, a modified, exclusive, shared, invalid, MESI protocol, etc. Taking a cache coherence protocol as an example, there are four channels between the input / output chip and the cache: a request channel, a response channel, a data channel, and a listener channel. The request channel is dedicated to transmitting signaling about requests (referred to as request signaling), the response channel is dedicated to transmitting signaling about responses (referred to as response signaling), the data channel is dedicated to transmitting signaling about data (referred to as data signaling), and the listener channel is dedicated to transmitting signaling about listening (referred to as listener signaling).

[0044] Under current technological conditions, directly writing data from an input / output chip into a cache typically requires two signaling processes. First, the input / output chip sends a "request signaling" through a request channel, notifying the cache that it is ready to send data, and the cache prepares to receive the data. Then, the input / output chip sends a "data signaling" through a data channel, sending the data to the cache. In this application, the first signaling process combines the "request signaling" and the "data signaling." That is, the first signaling simultaneously carries the content of the fields in the "request signaling" (i.e., control information) that the transmission protocol specifies should be transmitted through the request channel, and the content of the fields in the "data signaling" (i.e., data information) that the transmission protocol specifies should be transmitted through the data channel.

[0045] The input / output chip can send the first signaling to the cache via either a data channel or a request channel. However, the implementation methods for the first signaling transmitted via the data channel and the first signaling transmitted via the request channel are different. Specifically, when the first signaling is transmitted via the request channel, it can only be transmitted using the request channel format. When the first signaling is transmitted via the data channel, it can only be transmitted using the data channel format.

[0046] The control information includes values ​​for fields such as data size, address, non-security flag, memory attribute, listen attribute, logical processor identifier, expected completion confirmation, and memory partition monitoring, as specified in the agreement for transmission on the request channel. Optionally, the control information may also include one or more values ​​from fields such as prefetch target node identifier, prefetch target node valid identifier, prefetch logical processor identifier, prefetch logical processor valid identifier, and memory partition monitoring.

[0047] The data information includes the values ​​of data error fields, data status fields, data key marker fields, data count marker fields, data validity fields, data fields, byte error fields, etc., which are required to be transmitted in the data channel according to the agreement.

[0048] (1) When the first signaling is transmitted through the request channel, the first signaling may include the fields shown in Table 1:

[0049] Table 1 Fields of the First Signaling

[0050]

[0051]

[0052] The Service Quality Priority field indicates the priority level of the write-unique full storage request. The Target Node Identifier field identifies the target node for the write-unique full storage request; here, the target node is a cache. The Source Node Identifier field identifies the source node for the write-unique full storage request; here, the source node is an input / output chip. The Transaction Identifier identifies the transaction for the first signaling. The Prefetch Target Node Identifier (StashNID) identifies the cache used for caching. The Prefetch Target Node Validity Identifier indicates whether the cache is caching (STASH). The Prefetch Logic Processor Identifier identifies the logic processor used for caching (STASH). The Prefetch Logic Processor Validity Identifier indicates whether the logic processor is caching (STASH). The Opcode field carries the various opcodes for the first signaling. The Data Size field indicates the size of the data in the first signaling. The Address field carries the storage address. The Insecurity Flag field indicates whether the transaction is a secure transaction. The Memory Attribute field defines the memory access attributes. The Listen Attribute field defines the attributes of the listen operation. The logical processor identifier is used to identify the logical processor. The expected completion acknowledgment indicates whether a response signal is required for this first signaling instruction. The memory partition monitoring is used to partition and monitor memory resources. Reserved fields are reserved for other uses.

[0053] It is understood that the fields of the first signaling above are merely a specific example. In actual applications, more or fewer fields may be included, and no specific limitation is made here. Furthermore, the length of each field of the first signaling above is merely a specific example. In actual applications, the length of each field may include more or fewer bits, and no specific limitation is made here.

[0054] Therefore, control information (i.e., the values ​​of fields that the agreement specifies need to be transmitted in the request channel) can be carried in the corresponding fields of the first signaling. For example, the value of the data size field in the control information is carried in the data size field of the first signaling; the value of the non-security flag field in the control information is carried in the non-security flag field of the first signaling; and so on for other fields such as the address field, memory attribute field, listen attribute field, logical processor identifier field, expected completion confirmation field, and memory partition monitoring field. Data information is carried in the idle fields of the first signaling, such as reserved fields.

[0055] (2) When the first signaling is transmitted through the data channel, the first signaling may include the fields shown in Table 2:

[0056] Table 2 Fields of the First Signaling

[0057] Fields Bit Quality of Service (QoS) priority field 4 bits Target Node Identifier Field (TgtID) 7-12 bits Source node identifier field (SrcID) 7-12 bits Transaction identifier field (TxnID) 10 bits HomeNID (Home Node Identifier) 7-12 bits Opcode field 4 bits Data error field (RespErr) 2 bits Data Status Field (Resp) 3 bits Data source field (DataSource) 5 bits Busy status field (CBusy) 2 bits Data buffer identifier field (DBID) 10 bits Key Data Identifier (CCID) field 2 bits Data ID field (DataID) 2 bits TraceTag field 1 bit Reserved Fields (RSVDC) Custom Data Validation Field (BE) 64 bits Data field (Data) 512 bits Byte Error Field (Poison) 8 bits

[0058] The Service Quality Priority (QoS) field indicates the priority level of the first signaling. The Target Node Identifier field identifies the target node carrying the first signaling; here, the target node is a cache. The Source Node Identifier field identifies the source node carrying the first signaling; here, the source node is an input / output chip. The Transaction Identifier identifies the transaction carrying the first signaling. The Opcode field carries the various opcodes of the first signaling. The Master Node Identifier field marks the master node handling the request. In a read request, when data is not returned directly to the requesting node by the master node but by another node holding the data, bypassing the master node, this tells the requesting node which master node to send the completion response to. The Opcode field carries the various opcodes of the first signaling. The Data Error field indicates whether the data is erroneous. The Data Status field indicates the data status, such as shared, exclusive, modified, etc. The Data Source field identifies the data source. The Busyness field indicates the downstream busy level. The Data Buffer Identifier field indicates the buffer number prepared by the downstream node to receive write data when a write request is made, ensuring that data sent by the requesting node is written to the correct buffer. The Data Keystep Identifier identifies the keystep of the data. The Data Step Count Identifier identifies the number of data steps. The Tracking Identifier field indicates whether data is being tracked. The Reserved field is used to reserve data for other uses. The Data Validity field indicates whether each byte in the data is valid. The Data field carries the data. The Byte Error field indicates whether an error correction code (ECC) exists every 64 bits in the data.

[0059] It is understood that the fields of the first signaling above are merely a specific example. In actual applications, more or fewer fields may be included, and no specific limitation is made here. Furthermore, the length of each field of the first signaling above is merely a specific example. In actual applications, the length of each field may include more or fewer bits, and no specific limitation is made here.

[0060] Therefore, data information (i.e., the values ​​of fields that the agreement specifies need to be transmitted in the data channel) can be carried in the corresponding fields of the first signaling. For example, the value of the data error field in the data information is carried in the data error field of the first signaling, and the value of the data status field in the data information is carried in the data status field of the first signaling. The same applies to other fields such as the data keyframe identifier field, data frame count identifier field, data validity field, data field, byte error field, etc. Control information can be carried in the idle fields of the first signaling, such as one or more of the master node identifier field, data buffer identifier field, reserved field, and data validity field.

[0061] The master node identifier field in the first signaling is used to mark the master node that handles the request. In a read request, when the data is not returned directly to the requesting node by the master node but by another node holding the data, bypassing the master node, the master node is informed which master node to send the completion response to. The master node identifier field in the first signaling is not needed, therefore, the master node identifier field in the first signaling is an idle field.

[0062] The data buffer identifier field in the first signaling is the number of the buffer area prepared for receiving write data. Since the node allocates the buffer area itself when merging the "request signaling" and "data signaling" through the first signaling, and it is not necessary to determine the buffer area in advance, the data buffer identifier field is not needed. Therefore, the data buffer identifier field in the first signaling is an idle field.

[0063] The reserved fields in the first signaling are intended for other uses and are therefore unused fields. Thus, the reserved fields in the first signaling are idle fields.

[0064] The data validity field in the first signaling is used to indicate whether the bytes in the data field of the data signaling are valid. The content of the data validity field in the first signaling can be restored by combining the address field and the data size field. Therefore, in order to maximize the use of each field in the first signaling, the data validity field in the first signaling can be left empty as a free field.

[0065] It is understood that the above-mentioned free fields are merely a specific example. In actual applications, free fields may include more or fewer fields, or even other fields, without specific limitations here.

[0066] In one specific implementation, the control information can be carried in the free field of the first signaling as follows:

[0067] The values ​​of the prefetch target node identifier field and the prefetch target node valid identifier field are carried in either the master node identifier field or the data buffer identifier field of the first signaling. Since the data buffer identifier field in the first signaling is 10 bits long, and the value of the prefetch target node identifier field in the control information is 7-12 bits long, their sizes are roughly equivalent. Therefore, the content of the prefetch target node identifier field in the control information can be inserted into the data buffer identifier field of the first signaling. Of course, if the length of the prefetch target node identifier field is actually less than 10 bits, then the content of the prefetch target node valid identifier field (1 bit) can also be inserted into the data buffer identifier field of the first signaling. If the length of the data buffer identifier field in the first signaling is insufficient, a reserved field in the first signaling can be used.

[0068] The values ​​of the control information's data size field, address field, non-security flag field, memory attribute field, listen attribute field, logic processor identifier field, and expected completion acknowledgment field are carried in the data validity field of the first signaling. Additionally, the values ​​of the prefetch logic processor identifier field and the prefetch logic processor valid identifier field can also be carried in the data validity field of the first signaling. Since the data validity field in the first signaling is 64 bits long, while the control information's prefetch logic processor identifier field is 5 bits long, the prefetch logic processor valid identifier field is 1 bit long, the data size field is 3 bits long, the address field is 45-52 bits long, the non-security flag field is 2 bits long, the memory attribute field is 4 bits long, the listen attribute field is 5 bits long, and the expected completion acknowledgment field is 1 bit long, when the address field length is no more than 43 bits, the contents of the control information's prefetch logic processor identifier field, prefetch logic processor valid identifier field, data size field, address field, non-security flag field, memory attribute field, listen attribute field, logic processor identifier field, and expected completion acknowledgment field can all be inserted into the data validity field of the first signaling.

[0069] The value of the memory partition monitoring field in the control information is carried in either the master node identifier field or the data buffer identifier field in the first signaling. Since the master node identifier field in the first signaling is 7–12 bits long, while the memory partition monitoring field in the control information is 11 bits long, the value from the memory partition monitoring field in the control information can be inserted into the master node identifier field in the first signaling. If the master node identifier field is not long enough, a reserved field can be used, or the memory partition monitoring field can be trimmed.

[0070] The reserved field of the first signaling can be used to carry the first merging identifier, which indicates that the first signaling is a special signaling different from data signaling. The first merging identifier can occupy one or more bits. For example, the first merging identifier can occupy one bit, and when the first merging identifier is 1, it indicates that the signaling is the first signaling. Because the signaling originally transmitted from the data channel was ordinary data signaling, now the signaling transmitted from the data channel includes not only data signaling but also the first signaling, the first merging identifier needs to be carried in the reserved field to distinguish whether the signaling is ordinary signaling or the first signaling.

[0071] It is understandable that the above first signaling is only a specific example. In practical applications, it can also be implemented in other ways. For example, control information can be filled into the reserved field of the first signaling, or the prefetch target node identifier field and the prefetch target node valid identifier field can be filled into the data buffer identifier field of the first signaling, while other aspects remain unchanged, etc.

[0072] After receiving the first signaling, the cache reads the first merge identifier from the reserved field, determining that the signaling is not a regular data signaling but rather the first signaling. The cache then retrieves control and data information from this first signaling. Based on the control information, the cache prepares to receive data, and based on the data information, it stores the data in the cache. Since multiple caches can exist, to ensure consistency among them, data can only be stored in a cache if the cache has exclusive access to the data. Therefore, if a cache has exclusive access, it can directly store the data. If a cache does not have exclusive access, it first sends a consistency signaling to the memory controller. Upon receiving the consistency signaling, the memory controller determines that the cache requires exclusive access. After negotiating with other caches, the memory controller grants the cache exclusive access and sends this exclusive access message to the cache via a completion signaling.

[0073] If the number of signaling messages processed by the relay device is greater than or equal to a threshold, the first signaling message is discarded, and the process proceeds to step S202. The threshold is determined based on the processing capacity of the relay device. The processing capacity of the relay device can be determined based on the number of processors, the clock frequency of the processors, the number of registers of the processors, etc. If the number of signaling messages processed by the relay device is less than the threshold, the process proceeds to step S203.

[0074] S202: The cache sends a first failure response to the input / output chip via the response channel. Correspondingly, the input / output chip receives the first failure response sent by the cache via the response channel.

[0075] The first failure response is used to notify the input / output chip of a failure to write data to the cache. Since the cache capacity is smaller than the main memory capacity, the main memory unconditionally accepts data received by the input / output chip and therefore does not send a failure response to the input / output chip. However, the cache only accepts data received by the input / output chip when needed. This application uses a method where the input / output chip bypasses the main memory and writes data directly to the cache. This assumes that the cache needs the data received by the output chip, thus sending the data received by the input / output chip to the cache in advance. However, in reality, the cache may not necessarily need the data received by the output chip. For example, when the cache is busy, it may not need the input / output chip to send data to it. Therefore, the cache needs to have the ability to refuse, i.e., the ability to send a failure response to the input / output chip. The first failure response may include fields as shown in Table 3:

[0076] Table 3 Fields of the First Failure Response

[0077] Fields Bit Quality of Service (QoS) priority field 4 bits Target Node Identifier Field (TgtID) 7-12 bits Source node identifier field (SrcID) 7-12 bits Transaction identifier field (TxnID) 10 bits Opcode field 6 bits Data error field (RespErr) 2 bits Data Status Field (Resp) 3 bits Whether to retrieve data fields (DataPull) 1 bit Busy status field (CBusy) 2 bits TraceTag field 1 bit Data buffer identifier field (DBID) 10 bits

[0078] The Service Quality Priority (QoS) field indicates the priority level of the first failure response. The Target Node Identifier field identifies the target node carrying the first failure response; here, the target node is the input / output chip. The Source Node Identifier field identifies the source node carrying the first failure response; here, the source node is the cache. The Transaction Identifier identifies the transaction carrying the first failure response. The Opcode field carries the first opcode of the first failure response. The Data Error field indicates whether the data is erroneous. The Data Status field indicates the data status, such as shared, exclusive, modified, etc. The DataPull field indicates whether data needs to be pulled from the input / output chip. Since the input / output chip has already sent the data to the cache, data pulling is not required here. The Busy field indicates the downstream workload. The Tracking Identifier field indicates whether data tracking is performed. The Data Buffer Identifier field indicates the buffer number prepared by the downstream node to receive write data during a write request, ensuring that data sent by the requesting node is written to the correct buffer.

[0079] S203: The cache sends a SnpUniqueStash signal to the processor via the snip channel. Correspondingly, the processor receives the SnpUniqueStash signal sent by the cache via the snip channel.

[0080] The unique storage listening signal is used to notify the processor that data can be retrieved from the cache. In one specific embodiment, this unique storage listening signal can be similar to the unique storage listening signal sent by the cache to the processor in existing data transmission methods, and will not be elaborated further here.

[0081] After receiving a unique storage listener signal from the cache, the processor knows it can retrieve data from the cache. Similarly, since the memory address corresponding to this data might contain outdated data, upon receiving the unique storage listener signal, the processor needs to invalidate the outdated data at that memory address to ensure data consistency. This prevents the processor from incorrectly using invalidated data at that memory address, thus avoiding errors.

[0082] S204: The processor sends a data pull request (DataPull) to the cache via the request channel. Correspondingly, the cache receives the data pull request sent by the processor via the request channel.

[0083] A data fetch request is used to fetch data from the cache. In one specific embodiment, the data fetch request can be similar to the data fetch request sent by the processor to the cache in existing data transfer methods, which will not be elaborated further here.

[0084] When a processor needs to use data, it checks whether the data stored at the corresponding memory address in the processor's memory is valid. If the data at that memory address is valid, the processor can directly use the data at that memory address. If the data at that memory address is invalid, the processor cannot use the data at that memory address and instead sends a data fetch request to the cache. In this case, the data at that memory address in the processor's memory has been invalidated, so the processor needs to send a data fetch request to the memory controller.

[0085] S205: The cache sends a first success response to the input / output chip via the response channel. Correspondingly, the input / output chip receives the first success response sent by the cache via the response channel.

[0086] The first success response is used to notify the input / output chip that data was successfully written to the cache. The fields included in the first success response and the first failure response are the same; please refer to Table 3 for details. The difference between the first success response and the first failure response is that the opcode field value of the first success response is the first opcode, while the opcode field value of the first failure response is the second opcode. In other words, the value of the opcode field in the first success response is different from the value of the opcode field in the first failure response.

[0087] S206: The cache sends a data transfer (CompData) signaling message to the processor via the data channel. Correspondingly, the processor receives the data transfer signaling message sent by the cache via the data channel.

[0088] Data transmission signaling is used to send data to the processor. In one specific embodiment, the data transmission signaling can be similar to the data transmission signaling sent from the cache to the processor in existing data transmission methods, which will not be elaborated further here.

[0089] After receiving a data transfer signal from the cache, the processor can retrieve the data from the signal, store it in the corresponding memory address, and set the data at that address to be valid. The processor can then use the data at that memory address.

[0090] S207: The processor sends a completion acknowledgment (CompAck) to the cache via the response channel. Correspondingly, the cache receives the completion acknowledgment sent by the processor via the response channel.

[0091] The completion acknowledgment signal is used to notify the cache that data has been successfully received. In one specific embodiment, the completion acknowledgment signal can be similar to the completion acknowledgment signal sent by the processor to the cache in existing data transmission methods, and will not be elaborated further here.

[0092] See Figure 3 , Figure 3 This is a flowchart illustrating another data transmission method provided in this application. The data transmission method in this embodiment transmits data from the input / output chips to the processor stage by stage. For example... Figure 3 As shown, the data transmission method in this embodiment includes:

[0093] S301: The input / output chip sends a first signaling message to the memory controller through the first channel. Correspondingly, the memory controller receives the first signaling message sent by the input / output chip through the first channel.

[0094] The first signaling is used to directly write the data in the input / output chip into the memory controller, and then wait for the processor to read the data from the memory controller.

[0095] The first signaling message includes control information and data information. This first signaling message is transmitted through a first channel. The first channel is one of multiple channels between the input / output chip and the memory controller. The control information carries the operation request for the input / output chip to write data from the data information to the memory controller. For example, the first channel can be a request channel or a data channel between the input / output chip and the memory controller. The first channel can also be a listening channel or a response channel between the input / output chip and the memory controller, or even a newly established channel. In existing transmission protocols, control information can be transmitted through the request channel between the input / output chip and the memory controller, and data information can be transmitted through the data channel between the input / output chip and the memory controller. However, in this application, the control information and data information are carried in a single signaling message and transmitted through one channel (e.g., the request channel or the data channel). Because, according to the cache coherence protocol, there are four channels between the input / output chip and the memory controller: a request channel, a response channel, a data channel, and a listening channel.

[0096] Under current technological conditions, directly writing data from an input / output chip to a memory controller typically requires two signaling operations. First, the input / output chip sends a "request signaling" through a request channel, notifying the memory controller that it is ready to send data, thus preparing the memory controller to receive the data. Then, the input / output chip sends a "data signaling" through a data channel, thereby sending the data to the memory controller. In this application, the first signaling combines the "request signaling" and the "data signaling." That is, the first signaling simultaneously carries the content of the fields in the "request signaling" (i.e., control information) that the transmission protocol specifies should be transmitted through the request channel, and the content of the fields in the "data signaling" (i.e., data information) that the transmission protocol specifies should be transmitted through the data channel.

[0097] The input / output chip can send the first signaling to the memory controller via either a data channel or a request channel. However, the implementation methods for the first signaling transmitted via the data channel and the first signaling transmitted via the request channel are different. Specifically, when the first signaling is transmitted via the request channel, it can only be transmitted using the request channel format. When the first signaling is transmitted via the data channel, it can only be transmitted using the data channel format.

[0098] It can be understood that in the data transmission method of this embodiment, the first signaling in step S301 and Figure 2The first signaling in step S201 of the data transmission method shown is basically the same, except that the target node identifier field in the first signaling in step S301 is the identifier of the memory controller, while the target node identifier field in the first signaling in step S201 is the identifier of the cache.

[0099] S302: The memory controller sends a first success response to the input / output chip via the response channel. Correspondingly, the input / output chip receives the first success response sent by the memory controller via the response channel.

[0100] The first success response sent by the memory controller to the input / output chip via the response channel is used to notify the input / output chip that the memory controller has successfully received data. In a specific example, the first success response in step S302 of the data transmission method of this embodiment and Figure 2 The first successful response in step S205 of the data transmission method shown is basically the same, except that the source node identifier field in the first successful response in step S302 is the identifier of the memory controller, while the source node identifier field in the first successful response in step S205 is the identifier of the cache.

[0101] S303: The memory controller sends a second signaling message to the cache via the fourth channel. Correspondingly, the cache receives the second signaling message sent by the memory controller via the fourth channel.

[0102] The second signaling is used to write the data in the memory controller directly into the cache, and then wait for the processor to read the data from the cache.

[0103] The second signaling includes listening information and data information. The second channel is one of multiple channels between the memory controller and the cache. The listening information is used to instruct the cache to ensure cache consistency with other caches and to notify the cache to retrieve data from the data information from the memory controller. According to the cache coherency protocol, there are four channels between the memory controller and the cache: a request channel, a response channel, a data channel, and a listening channel.

[0104] Under current technological conditions, directly writing data from the memory controller to the cache typically requires two signaling signals. First, the memory controller sends a "listening signal" through the listening channel, notifying the cache that it is ready to send data, and the cache prepares to receive the data. Then, the memory controller sends a "data signal" through the data channel, thus sending the data to the cache. In this application, however, the second signaling signal combines the "listening signal" and the "data signaling." That is, the second signaling signal carries simultaneously the content of the fields in the "listening signal" (i.e., listening information) that the transmission protocol specifies should be transmitted through the listening channel, and the content of the fields in the "data signaling" (i.e., data information) that the transmission protocol specifies should be transmitted through the data channel.

[0105] The memory controller can send a second signaling message to the cache via either the data channel or the listener channel. However, the implementation of the second signaling message transmitted via the data channel differs from that transmitted via the listener channel. Specifically, when the first signaling message is transmitted via the listener channel, it can only be transmitted using the listener channel's format. When the second signaling message is transmitted via the data channel, it can only be transmitted using the data channel's format.

[0106] The monitoring information includes a prefetch logic processor identifier field, a prefetch logic processor valid identifier field, an address field, and a non-security flag field. Optionally, the monitoring information may also include the value of a memory partition monitoring field.

[0107] The data information includes the values ​​of data error fields, data status fields, data key marker fields, data count marker fields, data validity fields, data fields, byte error fields, etc., which are required to be transmitted in the data channel according to the agreement.

[0108] (1) When the second signaling is transmitted through the listening channel, the second signaling may include the fields shown in Table 4:

[0109] Table 4 Fields of the Second Signaling

[0110] Fields Bit Quality of Service (QoS) priority field 4 bits Target Node Identifier Field (TgtID) 7-12 bits Source node identifier field (SrcID) 7-12 bits Transaction identifier field (TxnID) 10 bits Prefetch the target node identifier field (StashNID) 7-12 bits Prefetch the target node's valid identifier field (StashNIDValid) 1 bit Prefetch logic processor identifier field (StashLPID) 5 bits Prefetch logic processor valid identifier field (StashLPIDValid) 1 bit Opcode field 5 bits Address field (Addr) 42-49 bits Non-security flag field (NS) 2 bits TraceTag field 1 bit Memory Partition Monitoring (MPAM) 11 bits Reserved Fields (RSVDC) Custom

[0111] The following fields are used to indicate the priority level of the second signaling: **Service Quality Priority** field: **Target Node Identifier** field: **Target Node Identifier** field: **Source Node Identifier** field: **Source Node Identifier** field: **Transaction Identifier** field: **Transaction Identifier** field: **Prefetch Target Node Identifier** (StashNID) field: **Prefetch Target Node Validity** field: **Prefetch Logic Processor Identifier** field: **Prefetch Logic Processor Validity** field: **Opcode** field: **Opcode** field: **Address** field: **Storage Address** field: **Insecure Flag** field: **Secure** field: **Tracking** field: **Tracking** field: **Memory Partition Monitoring** field: **Reserved** field: **Reserved for Other Use** field: **Preserved** field: **StashNID** field:** field: **Prefetch Target Node Validity** field: **Prefetch Target Node Validity** field: **Prefetch Logic Processor Validity** field: **Prefetch Logic Processor Validity** field: **Prefetch Logic Processor Validity** field: **Opcode** field: **Opcode** field: **Address** field: **Insecure** field:** field: **Secure** field: **Tracking** field: **Memory Partition Monitoring ...Reserved** field: **Reserved** field: **Reserved** field: **Reserved** field: **Reserved** field

[0112] It is understood that the fields of the second signaling described above are merely a specific example. In practical applications, more or fewer fields may be included, and no specific limitation is made here. Furthermore, the length of each field of the second signaling described above is merely a specific example. In practical applications, the length of each field may include more or fewer bits, and no specific limitation is made here.

[0113] Therefore, the monitoring information (i.e., the values ​​of fields that the agreement specifies need to be transmitted on the monitoring channel) can be carried in the corresponding fields of the second signaling. For example, the value of the prefetch target node identifier field in the monitoring information is carried in the prefetch target node identifier field of the second signaling; the value of the prefetch target node valid identifier field in the monitoring information is carried in the prefetch target node valid identifier field of the second signaling; and so on for other fields such as the address field, non-security flag field, and memory partition monitoring field of the monitoring information. Data information is carried in the idle fields of the second signaling, such as reserved fields.

[0114] (2) When the second signaling is transmitted through the data channel, the second signaling may include the fields shown in Table 2:

[0115] Therefore, data information (i.e., the values ​​of fields that the agreement specifies need to be transmitted in the data channel) can be carried in the corresponding fields of the second signaling. For example, the value of the data error field in the data information is carried in the data error field of the second signaling, and the value of the data status field in the data information is carried in the data status field of the second signaling. The same applies to other fields such as the data keyframe identifier field, data frame count identifier field, data validity field, data field, byte error field, etc. Meanwhile, monitoring information can be carried in the idle fields of the second signaling, such as one or more of the master node identifier field, data buffer identifier field, reserved field, and data validity field.

[0116] The master node identifier field in the second signaling is used to mark the master node that handles the request. In a read request, when the data is not returned directly to the requesting node by the master node but by another node holding the data, bypassing the master node, the master node is informed which master node to send the completion response to. The master node identifier field in the second signaling is not needed, therefore, the master node identifier field in the second signaling is an idle field.

[0117] The data buffer identifier field in the second signaling is the number of the buffer area prepared for receiving write data. Since the node allocates the buffer area itself when merging the "listening signaling" and "data signaling" through the second signaling, and it is not necessary to determine the buffer area in advance, the data buffer identifier field is not needed. Therefore, the data buffer identifier field in the second signaling is an idle field.

[0118] The reserved fields in the second signaling are also reserved for other uses; they are fields that are not used in the first place. Therefore, the reserved fields in the second signaling are idle fields.

[0119] The data validity field in the second signaling is used to indicate whether the bytes in the data field of the data signaling are valid. The content of the data validity field in the second signaling can be restored by combining the address field and the data size field. Therefore, in order to maximize the use of each field in the second signaling, the data validity field in the second signaling can be left empty as a free field.

[0120] It is understood that the above-mentioned free fields are merely a specific example. In actual applications, free fields may include more or fewer fields, or even other fields, without specific limitations here.

[0121] In one specific implementation, the monitoring information can be carried in the idle field of the second signaling as follows:

[0122] The values ​​of the prefetch logic processor identifier field and the prefetch logic processor valid identifier field are carried in either the master node identifier field or the data buffer identifier field in the second signaling. Since the data buffer identifier field in the second signaling is 10 bits long, and the prefetch target node identifier field in the monitoring information is 7-12 bits long, their sizes are roughly equivalent. Therefore, the content of the prefetch target node identifier field in the monitoring information can be inserted into the data buffer identifier field in the second signaling. Of course, if the length of the prefetch target node identifier field is actually less than 10 bits, then the content of the prefetch target node valid identifier field (1 bit) can also be inserted into the data buffer identifier field in the second signaling. If the data buffer identifier field is not long enough, a reserved field can be used.

[0123] The values ​​of the address field and the non-security flag field are carried in the data validity field of the second signaling. Since the data validity field can be 64 bits long, the address field is 45-52 bits long, and the non-security flag field is 2 bits long, the contents of the address field and the non-security flag field in the monitoring information can be inserted into the data validity field of the second signaling.

[0124] The value of the memory partition monitoring field in the monitoring information is carried in either the master node identifier field or the data buffer identifier field in the second signaling. Since the master node identifier field in the second signaling is 7-12 bits long, while the memory partition monitoring field in the control information is 11 bits long, the value from the memory partition monitoring field in the control information can be inserted into the master node identifier field in the first signaling. If the master node identifier field is not long enough, a reserved field can be used, or the memory partition monitoring field can be trimmed.

[0125] The reserved field for the second signaling can be used to carry a second merging identifier, indicating that the second signaling is a special signaling distinct from data signaling. The second merging identifier can occupy one or more bits; for example, it can occupy one bit, and when the second merging identifier is 1, it indicates that the signaling is second signaling. Because the signaling originally transmitted from the data channel was ordinary data signaling, but now it includes second signaling in addition to data signaling, the reserved field needs to carry a second merging identifier to distinguish between ordinary and second signaling.

[0126] It is understandable that the above-mentioned second signaling is only a specific example. In practical applications, it can also be implemented in other ways. For example, the listening information can be filled into the reserved field of the second signaling, or the prefetch target node identifier field and the prefetch target node valid identifier field can be filled into the data buffer identifier field of the second signaling, while other aspects remain unchanged, etc.

[0127] After receiving the second signaling, the cache reads the second merge identifier from the reserved field, determining that the signaling is not ordinary data signaling but a second signaling. The cache then retrieves the listening information and data information from the second signaling. Based on the listening information, the cache prepares to receive data and stores the data in the cache according to the data information. Since multiple caches can exist, to ensure consistency among them, data can only be stored in the cache if the cache has exclusive data access rights. Therefore, if the cache has exclusive data access rights, it can directly store the data. If the cache does not have exclusive data access rights, it first sends a consistency signaling to the memory controller. Upon receiving the consistency signaling, the memory controller determines that the cache requires exclusive data access rights. After negotiating with other caches, the memory controller grants the cache exclusive data access rights and sends this exclusive data access permission message to the cache via a completion signaling.

[0128] S304: The cache sends a second response to the memory controller via the response channel. Correspondingly, the memory controller receives the second response sent by the cache via the response channel.

[0129] The second response is used to notify the memory controller that the high-speed memory has successfully received data. In a specific real example, the second response in step S304 of the data transmission method of this embodiment and Figure 2 The completion confirmation signaling in step S206 of the data transmission method shown is basically the same. The difference is that the source node identifier field in the second response of step S304 is the identifier of the cache and the destination node identifier field is the identifier of the memory controller, while the source node identifier field in the completion confirmation signaling in the second response of step S206 is the identifier of the processor and the destination node identifier field is the identifier of the cache.

[0130] S305: The cache sends a unique memory listening signal to the processor via the listening channel. Correspondingly, the processor receives the unique memory listening signal sent by the cache via the listening channel.

[0131] The cache sends a unique storage listening signal to the processor via a listening channel to notify the processor that data can be retrieved from the cache. In one specific embodiment, this unique storage listening signal can be combined with... Figure 2 The unique storage signaling sent by the cache to the processor in step S203 of the data transmission method shown is the same, and will not be elaborated further here.

[0132] After receiving a unique storage listener signal from the cache, the processor knows it can retrieve data from the cache. Similarly, since the memory address corresponding to this data might contain outdated data, upon receiving the unique storage listener signal, the processor needs to invalidate the outdated data at that memory address to ensure data consistency. This prevents the processor from incorrectly using invalidated data at that memory address, thus avoiding errors.

[0133] S306: The processor sends a data fetch request to the cache via the request channel. Correspondingly, the cache receives the data fetch request sent by the processor via the request channel.

[0134] Data fetch requests can be combined with Figure 2 The data fetch request sent by the processor to the cache in step S204 of the data transfer method shown is the same, and will not be elaborated further here.

[0135] S307: The cache sends data transfer signaling to the processor via the data channel. Correspondingly, the processor receives the data transfer signaling sent by the cache.

[0136] Data transmission signaling can be with Figure 2 The data transmission signaling sent from the cache to the processor in step S206 of the data transmission method shown is the same, and will not be elaborated further here.

[0137] S308: The processor sends a completion acknowledgment signal to the cache via the response channel. Correspondingly, the cache receives the completion acknowledgment signal sent by the processor via the response channel.

[0138] The completion confirmation signal can be combined with Figure 2 The completion confirmation signaling in step S308 of the data transmission method shown is similar, and will not be elaborated here.

[0139] In one possible embodiment, Figure 1 The processor 110, cache 120, memory controller 130, and input / output chip 140 shown can be adopted Figure 4The packaging configuration is shown. The input / output chip 140 is located on the left side of the transmission channel, the cache 120 is located on the right side of the transmission channel, the memory controller 130 is located to the left of the cache 120, and the processor 110 is located to the right of the cache 120. Due to the packaging configuration, the distance between the input / output chip 140 and the memory controller 130, and the distance between the memory controller 130 and the processor 110, is very large. When the input / output chip 140 needs to communicate with the memory controller 130, it needs to pass through the transmission channel and the cache, resulting in a very long transmission time. Similarly, when the memory controller 130 needs to communicate with the processor 110, it needs to pass through the cache, also resulting in a very long transmission time. Therefore, when using existing data transmission methods to transmit data from the input / output chip to the processor step-by-step, the large number of handshakes leads to a very long communication delay. However, using the method described in this application... Figure 2 The data transmission method shown reduces communication latency by decreasing the number of handshakes when transmitting data from the input / output chips to the processor, and by allowing the input / output chips to directly write data to shorter caches instead of longer memory controllers. This is achieved by using the method described in this application. Figure 3 The data transmission method shown effectively reduces the number of handshakes and thus communication latency when transmitting data from the input / output chips to the processor step by step through two combined signaling signals: the first signaling and the second signaling.

[0140] See Figure 5 , Figure 5 This is a schematic diagram of the structure of a data transmission device provided in this application. Figure 5 As shown, the data transmission device provided in this application includes: an input / output chip and a relay device. The input / output chip includes a receiving module 211 and a transmitting module 212. The relay device includes a transmitting module 221 and a receiving module 222.

[0141] The input / output chip's transmitting module 212 sends a first signaling message to the receiving module 222 of the relay device via a first channel. Then, the relay device's transmitting module 221 sends a first signaling message to the input / output chip's receiving module 211 based on the first signaling message. The first signaling message includes control information and data information. The first channel is one of multiple channels between the input / output chip and the relay device, which is a memory controller or a cache. The control information carries the operation request for the input / output chip to write data from the data information to the relay device.

[0142] The sending module 212 can be used to perform Figure 2 The steps S201 shown or Figure 3The steps performed by the sender in step S301, which sends the first signaling, are shown below. The receiving module 222 can be used to perform these steps. Figure 2 The steps S201 shown or Figure 3 The steps performed by the receiver that sends the first signaling in step S301 shown.

[0143] The sending module 221 can be used to perform Figure 2 In step S202 shown, a first failure response is sent. Figure 2 In step S205 shown, a first success response is sent or Figure 3 The steps performed by the sender in step S302, which sends the first success response, are shown below. The receiving module 211 can be used to perform these steps. Figure 2 In step S202 shown, a first failure response is sent. Figure 2 In step S205 shown, a first success response is sent or Figure 3 The steps performed by the receiver that sends the first success response in step S302 shown.

[0144] For simplicity, a detailed description of the data transmission device is not provided here; please refer to [link to relevant documentation]. Figure 2 , Figure 3 And related descriptions.

[0145] This application also provides a computing device cluster. The computing device cluster includes at least one such... Figure 1 The computing device shown. This server can be a central server, an edge server, or a local server in a local data center, etc.

[0146] This application also provides a computer program product containing instructions. The computer program product may be a software or program product containing instructions capable of running on a computing device or stored on any usable medium. When the computer program product is run on at least one computing device, it causes the at least one computing device to execute a method to prevent the generation of redundant code.

[0147] This application also provides a computer-readable storage medium. The computer-readable storage medium can be any available medium that a computing device can store, or a data storage device such as a data center containing one or more available media. The available medium can be a magnetic medium (e.g., floppy disk, hard disk, magnetic tape), an optical medium (e.g., DVD), or a semiconductor medium (e.g., solid-state drive). The computer-readable storage medium includes instructions that instruct the computing device to execute a method to prevent the generation of redundant code.

[0148] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of this application, and are not intended to limit them. Although this application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the protection scope of the technical solutions of the embodiments of this application.

Claims

1. A data transmission method, characterized by, The method is applied to a relay device, and the method comprises: receiving first signaling sent by an input / output chip on a first channel, wherein the first signaling comprises control information and data information, the first channel is one of multiple channels between the input / output chip and the relay device, the relay device is a memory controller or a cache, and the control information is used to carry an operation request of the input / output chip to write data in the data information to the relay device; sending first response to the input / output chip based on the first signaling.

2. The method of claim 1, wherein, The sending of the first response to the input / output chip based on the first signaling comprises: in a case where the number of signaling processed by the relay device is greater than or equal to a number threshold, sending a first failure response to the input / output chip and discarding the first signaling, wherein the number threshold is determined according to the processing capability of the relay device; in a case where the number of signaling processed by the relay device is less than the number threshold, sending a first success response to the input / output chip.

3. The method of claim 2, wherein, The first operation code carried in the operation code field of the first failure response is different from the second operation code carried in the operation code field of the first success response.

4. The method according to any one of claims 1 to 3, characterized in that, The control information comprises the value of a data size field, an address field, a non-security flag field, a memory attribute field, a listening attribute field, a logical processor identification field, and a desired completion confirmation field, The value of the data size field, the address field, the non-security flag field, the memory attribute field, the listening attribute field, the logical processor identification field, and the desired completion confirmation field of the control information are carried in a reserved field of the first signaling.

5. The method of claim 4, wherein, The control information further comprises the value of one or more of a prefetch target node identification field, a prefetch target node valid identification field, a prefetch logical processor identification field, a prefetch logical processor valid identification field, and a memory partition monitoring field; The value of the prefetch target node identification field and the prefetch target node valid identification field is carried in any one of a master node identification field and a data buffer identification field of the first signaling; The value of the prefetch logical processor identification field and the prefetch logical processor valid identification field is carried in a data validity field of the first signaling; The value of the memory partition monitoring field of the control information is carried in the other one of the master node identification field and the data buffer identification field of the first signaling.

6. The method according to any one of claims 1 to 5, characterized in that, In a case where the relay device is a memory controller, after receiving the first signaling sent by the input / output chip on the first channel, the method further comprises: sending second signaling to a cache through a second channel, wherein the second signaling comprises listening information and the data information, the second channel is one of multiple channels between the memory controller and the cache, the listening information is used to instruct the cache to ensure cache coherence with other caches and notify the cache to pull data in the data information from the memory controller; and receiving second response sent by the cache based on the second signaling.

7. The method of claim 6, wherein, The monitoring information includes a pre-fetch logical processor identification field, a pre-fetch logical processor valid identification field, an address field of the monitoring information, and a non-secure flag field, Values of the pre-fetch logical processor identification field and the pre-fetch logical processor valid identification field are carried in any one of a master node identification field and a data buffer identification field in the second signaling; Values of the address field and the non-secure flag field are carried in a data validity field in the second signaling.

8. The method of claim 7, wherein, The monitoring information further includes a value of a memory partition monitoring field, and the value of the memory partition monitoring field of the monitoring information is carried in the other one of the master node identification field and the data buffer identification field in the second signaling.

9. A data transmission method, characterized by, The method is applied to an input / output chip, and the method comprises: sending, through a first channel, a first signaling to a relay device, wherein the first signaling includes control information and data information, the first channel is one of a plurality of channels between the input / output chip and the relay device, the relay device is a memory controller or a cache, and the control information is used to carry an operation request of the input / output chip to write data in the data information to the relay device; receiving a first response sent by the relay device based on the first signaling.

10. The method of claim 9, wherein, The receiving the first response sent by the relay device based on the first signaling comprises: in a case where a quantity of signalings processed by the relay device is greater than a quantity threshold value, receiving a first failure response sent by the relay device based on the first signaling, wherein the quantity threshold value is determined according to a processing capability of the relay device; in a case where the quantity of signalings processed by the relay device is less than the quantity threshold value, receiving a first success response sent by the relay device based on the first signaling.

11. The method of claim 10, wherein, A first operation code carried in an operation code field of the first failure response is different from a second operation code carried in an operation code field of the first success response.

12. The method according to any one of claims 9-11, characterized in that, The control information includes a data size field, an address field, a non-secure flag field, a memory attribute field, a listening attribute field, a logical processor identification field, and a value of an expected completion acknowledgement field, and before the first signaling is sent to the relay device through the first channel, the method further comprises: carrying the values of the data size field, the address field, the non-secure flag field, the memory attribute field, the listening attribute field, the logical processor identification field, and the expected completion acknowledgement field of the control information in a reserved field of the first signaling.

13. The method of claim 12, wherein, The control information further includes values of one or more of a pre-fetch target node identification field, a pre-fetch target node valid identification field, a pre-fetch logical processor identification field, a pre-fetch logical processor valid identification field, and a memory partition monitoring field, and the method further comprises: carrying the values of the pre-fetch target node identification field and the pre-fetch target node valid identification field of the control information in any one of a master node identification field and a data buffer identification field of the first signaling; The value of the pre-fetch logical processor identification field and the value of the pre-fetch logical processor valid identification field of the control information are carried in a reserved field of the first signaling; The value of the memory partition monitoring field of the control information is carried in the other one of the master node identification field and the data buffer identification field of the first signaling.

14. A data transmission apparatus, characterized by comprising: The apparatus comprises: The receiving module is configured to receive first signaling sent by an input / output chip through a first channel, wherein the first signaling comprises control information and data information, the first channel is one of a plurality of channels between the input / output chip and the data transmission apparatus, the data transmission apparatus is a memory controller or a cache, and the control information is used to carry an operation request of the input / output chip for writing data in the data information to the relay device. The sending module is configured to send first response to the input / output chip based on the first signaling.

15. A data transmission apparatus, characterized by comprising: The apparatus comprises: The sending module is configured to send first signaling to a relay device through a first channel, wherein the first signaling comprises control information and data information, the first channel is one of a plurality of channels between the data transmission apparatus and the relay device, the relay device is a memory controller or a cache, and the control information is used to carry an operation request of the input / output chip for writing data in the data information to the relay device. The receiving module is configured to receive first response sent by the relay device based on the first signaling.

16. A data transmission system, characterized by The system comprises a relay device and an input / output chip, the relay device is configured to perform the method of any one of claims 1 to 8, and the input / output chip is configured to perform the method of any one of claims 9 to 13.

17. A computing device, comprising: The computing device comprises a processor, a relay device, and an input / output chip, the relay device is configured to perform the method of any one of claims 1 to 8, and the input / output chip is configured to perform the method of any one of claims 9 to 13.

18. A cluster of computing devices, characterized in that, The system comprises a plurality of computing devices, at least one of the computing devices is the device of claim 17.

19. A computer program product comprising instructions, characterized in that, The instructions, when executed by a computing device, cause the computing device to perform the operational steps of the method of any one of claims 1 to 13.

20. A computer-readable storage medium, characterized in that, The computer program instructions, when executed by a computing device, cause the computing device cluster to perform the operational steps of the method of any one of claims 1 to 13.

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