Rendering method and device of circuit layout, storage medium and electronic equipment
By layering vertex data in the circuit layout's data buffer and reducing the number of draw calls, the problem of excessively long circuit layout rendering time and stuttering is solved, achieving efficient rendering results.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-08-15
- Publication Date
- 2026-03-10
AI Technical Summary
Existing technologies, when rendering circuit layouts, result in excessive Draw Calls, leading to an overload on the CPU and GPU, causing long rendering times and stuttering issues.
By acquiring the vertex data of the basic geometry on all layers of the circuit layout, the vertex data is cached separately in the data buffer according to different layers, and the vertex data belonging to the same layer is cached continuously. A Draw Call is executed for each segment of continuously cached vertex data.
Significantly reduces the number of draw calls, lowers the computational burden on the CPU and GPU, reduces rendering time, avoids stuttering, and maintains a high rendering frame rate.
Smart Images
Figure CN121638151A_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of circuit layout design, and in particular to a method, apparatus, storage medium, and electronic device for rendering circuit layouts. Background Technology
[0002] With the development of electronic technology, the complexity of circuits is increasing, leading to a growing number of basic geometric shapes in circuit layouts, often numbering in the tens of thousands or even hundreds of millions. Basic geometric shapes are the graphics used to draw circuit devices, including geometric figures such as line segments and polygons.
[0003] When rendering circuit layouts, current technology executes a draw call command once for each basic geometric shape. A draw call refers to the CPU calling the graphics programming interface to instruct the GPU to perform rendering. It is known that the number of draw calls is equal to the number of basic geometric shapes. When faced with a large number of basic geometric shapes, a large number of draw calls will greatly increase the computational burden on the CPU and GPU, resulting in excessively long rendering times, stuttering, or even complete malfunction. Summary of the Invention
[0004] The purpose of this invention is to provide a method, apparatus, storage medium, and electronic device for rendering circuit layouts, so as to solve the problem of excessively long rendering time in the prior art, reduce the computing burden of CPU and GPU, reduce rendering time, and avoid lag.
[0005] To solve the above technical problems, the present invention provides a method for rendering circuit layouts, comprising:
[0006] Obtain the vertex data of the basic geometry on all layers in the circuit layout. The vertex data includes the index and coordinates of the vertices of the basic geometry.
[0007] Vertex data belonging to the same layer are cached consecutively in the data cache area, while vertex data from different layers are cached separately in the data cache area.
[0008] The DrawCall command is executed once for each segment of continuously cached vertex data in the data buffer to complete the rendering of each layer.
[0009] Preferably, the step of continuously caching vertex data belonging to the same layer in the data cache area and separately caching vertex data from different layers in the data cache area includes:
[0010] Based on the number of layers in the circuit layout and the number of vertices in the vertex data of each layer, separate cache segments are set in the data cache area, and each address bit of the cache segment is used to cache one vertex coordinate;
[0011] Set the caching order of the basic geometry in each layer;
[0012] According to the caching order, the vertex data of the basic geometry of the corresponding layer are cached in each cache segment, wherein the vertex coordinates of each basic geometry are cached in consecutive address bits according to the vertex sequence number, and the address bits corresponding to adjacent basic geometries are consecutive.
[0013] Preferably, the caching order is the drawing order of the basic geometry in each layer.
[0014] Preferably, a different rendering style is used each time the Draw Call is executed.
[0015] Preferably, the rendering style includes a border style and / or a fill style.
[0016] Preferably, the rendering method further includes:
[0017] When a preset operation is triggered on the target basic geometry, a Draw Call is executed again on the target basic geometry using a preset rendering style to re-render the target basic geometry. The preset rendering style is different from the rendering style corresponding to any of the layers.
[0018] Preferably, the preset operation is to hover the mouse over the area of the target basic geometry or to select the target basic geometry with the mouse.
[0019] To solve the above-mentioned technical problems, the present invention also provides a circuit layout rendering apparatus, comprising:
[0020] The acquisition module is used to acquire vertex data of the basic geometric figures on all layers in the circuit layout. The vertex data includes the index and coordinates of the vertices of the basic geometric figures.
[0021] The caching module is used to cache vertex data belonging to the same layer continuously in the data cache area, and to cache vertex data from different layers separately in the data cache area.
[0022] The rendering module is used to execute a draw call command once for each segment of continuously cached vertex data in the data buffer area, so as to complete the rendering of each layer.
[0023] To address the aforementioned technical problems, the present invention also provides a storage medium storing a computer program configured to execute the circuit layout rendering method described in any of the preceding claims during runtime.
[0024] To address the aforementioned technical problems, the present invention also provides an electronic device, including a memory and a processor, wherein the memory stores a computer program, and the processor is configured to run the computer program to execute the circuit layout rendering method described in any of the preceding claims.
[0025] Unlike existing technologies, the circuit layout rendering method provided by this invention obtains the vertex data of the basic geometric figures on all layers of the circuit layout, caches the vertex data separately according to different layers in the data buffer, and caches the vertex data belonging to the same layer continuously. For each segment of continuously cached vertex data, a Draw Call is executed. Compared with the number of Draw Calls in existing technologies based on the number of basic geometric figures, the number of Draw Calls in this invention is the number of layers, which greatly reduces the number of Draw Calls. This reduces the computational burden on the CPU and GPU, reduces rendering time, and avoids stuttering.
[0026] The circuit layout rendering apparatus, storage medium, and electronic device provided by this invention belong to the same inventive concept as the circuit layout rendering method, and therefore have the same beneficial effects, which will not be repeated here. Attached Figure Description
[0027] Figure 1 A schematic flowchart illustrating the circuit layout rendering method provided in an embodiment of the present invention.
[0028] Figure 2 This is a rendering architecture diagram of the circuit layout rendering method of this invention in a practical application.
[0029] Figure 3 for Figure 1 The flowchart shown illustrates the specific process of step S2 in the process diagram.
[0030] Figure 4 This is a schematic diagram showing the address bits after caching vertex data of the same layer in the cache segment.
[0031] Figure 5 This is a schematic block diagram of a circuit layout rendering device. Detailed Implementation
[0032] The specific embodiments of the present invention will now be described in more detail with reference to the accompanying drawings. The advantages and features of the present invention will become clearer from the following description and claims. It should be noted that the drawings are all in a very simplified form and use non-precise proportions, and are only used to facilitate and clarify the illustration of the embodiments of the present invention.
[0033] In the description of this invention, it should be understood that the terms "center", "upper", "lower", "left", "right", etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are only for the convenience of describing this invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this invention.
[0034] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of this invention, "a plurality of" means at least two, such as two, three, etc., unless otherwise explicitly specified.
[0035] Please refer to Figure 1 This invention provides a method for rendering a circuit layout, which includes the following steps:
[0036] S1: Obtain the vertex data of the basic geometry on all layers in the circuit layout. The vertex data includes the index and coordinates of the vertices of the basic geometry.
[0037] Because integrated circuits are manufactured using a photolithography process, they are made layer by layer. Therefore, an integrated circuit has more than one layer, and correspondingly, the circuit layout also includes many layers, each containing basic geometric shapes. These basic geometric shapes include line segments and polygons; that is, any basic geometric shape has at least two vertices. The vertex numbers determine the order of connections between vertices, and the vertex coordinates determine their positions within the circuit layout.
[0038] S2: Cache vertex data belonging to the same layer consecutively in the data cache area, and cache vertex data from different layers separately in the data cache area.
[0039] The data buffer is a pre-allocated area in memory used to store vertex data for data communication between memory and the GPU. When caching vertex data, the vertex data for each layer is contiguous in memory. However, in adjacent layers, the last vertex data of the previous layer is separate from the first vertex data of the next layer; they are not contiguous. In short, the data buffer caches multiple segments of separate vertex data, each segment belonging to a layer, and the vertex data within each segment is contiguous.
[0040] S3: Execute a Draw Call once for each segment of continuously cached vertex data in the data buffer to complete the rendering of each layer.
[0041] For the GPU, a single Draw Call can only render contiguous data in memory. Since the vertex data of the same layer is contiguous, the vertex data of the same layer in the data buffer can be submitted to the GPU for rendering at once, thus completing the rendering of the corresponding layer. For the next layer, that is, the next contiguous cached vertex data, the next Draw Call is executed.
[0042] Please refer to Figure 2 This is a rendering architecture diagram of the circuit layout rendering method of this invention in practical application. In this rendering architecture, the basic geometric shapes and the cache segments in the data cache area are no longer in a one-to-one correspondence. Instead, each layer corresponds to one cache segment, and the number of cache segments equals the number of layers N. Therefore, the number of Draw Calls is also N, which is less than the number of basic geometric shapes M. Typically, the number of layers in a circuit layout will not exceed 1000, so the number of Draw Calls will not exceed 1000. Compared to tens of millions or even hundreds of millions of basic geometric shapes, the number of Draw Calls has been significantly reduced. In this rendering architecture, both graphic 1 and graphic 2 belong to layer 1, but the rendering architecture merges their cache segments. While ensuring rendering correctness, rendering layer 1 can be completed with a single Draw Call. Therefore, the rendering method of this embodiment significantly reduces the number of Draw Calls, thereby reducing the computational burden on the CPU and GPU, reducing rendering time, and avoiding stuttering. Moreover, the rendering method of this embodiment can maintain a high and stable rendering frame rate.
[0043] In the above manner, the circuit layout rendering method provided by the present invention obtains the vertex data of the basic geometric figures on all layers of the circuit layout, caches the vertex data separately according to different layers in the data buffer, and caches the vertex data belonging to the same layer continuously. A DrawCall is executed for each segment of continuously cached vertex data. Compared with the prior art, where the number of Draw Calls is the number of basic geometric figures, the present invention calculates the number of Draw Calls based on the number of layers, significantly reducing the number of Draw Calls. This reduces the computational burden on the CPU and GPU, decreases rendering wait time, and avoids stuttering.
[0044] Please refer to some embodiments of this application. Figure 3 Step S2 includes the following steps: caching vertex data belonging to the same layer contiguously in the data buffer, and caching vertex data from different layers separately in the data buffer.
[0045] S21: Based on the number of layers in the circuit layout and the number of vertices in the vertex data of each layer, separate cache segments are set in the data buffer area. Each address bit of the cache segment is used to cache one vertex coordinate.
[0046] The number of cache segments can be determined based on the number of layers in the circuit layout, and the number of address bits for each cache segment can be determined based on the number of vertices in the vertex data of each layer. For example, if a layer includes a line segment and a quadrilateral, and the vertex data contains six vertices, then the corresponding cache segment needs to occupy 6 address bits.
[0047] S22: Set the caching order of basic geometry in each layer.
[0048] When there are multiple basic geometric shapes in a layer, the vertex data of each basic geometric shape needs to be cached into the corresponding cache segment one by one. Therefore, there must be a caching order for the basic geometric shapes. This caching order can be set arbitrarily, for example, the caching order can be the drawing order of the basic geometric shapes in each layer.
[0049] S23: Cache the vertex data of the basic geometry of the corresponding layer in each cache segment according to the cache order. The vertex coordinates of each basic geometry are cached in consecutive address bits according to the vertex sequence number, and the address bits of adjacent basic geometry are consecutive.
[0050] Specifically, for a given cache segment, if the layer corresponding to that cache segment has multiple basic geometric shapes, the vertex data of each basic geometric shape is cached consecutively into the cache segment according to the caching order. Please refer to [reference needed]. Figure 4This is a diagram illustrating the address bits after caching vertex data of the same layer in the cache segment. Figures 1, 2, and 3 all belong to the same layer. Figure 1 is a line segment with two vertices, requiring 2 address bits. Starting from address 0 of the cache segment, the coordinates of the two vertices are cached at addresses 0 and 1. Figure 2 is a rectangle with four vertices, requiring 4 address bits. Starting from address 2 of the cache segment, the coordinates of the four vertices are cached at addresses 2, 3, 4, and 5. Figure 3 is a line segment with two vertices, requiring 2 address bits. Starting from address 6 of the cache segment, the coordinates of the four vertices are cached at addresses 6 and 7.
[0051] To facilitate differentiation of the rendering effects of each layer, in some embodiments of this application, a different rendering style is used each time a DrawCall is executed; that is, each layer has a unique rendering style. The rendering style may include a border style and / or a fill style. The border style includes line color, line type, line width, etc., and the fill style includes fill shape, fill color, etc.
[0052] Please continue to refer to this. Figure 1 In this embodiment of the application, the rendering method further includes, in addition to the aforementioned steps:
[0053] S4: When the target basic geometry is triggered by a preset operation, execute a Draw Call again on the target basic geometry using a preset rendering style to re-render the target basic geometry. The preset rendering style is different from the rendering style corresponding to any layer.
[0054] The target basic geometry has already been rendered, but when a preset operation is triggered, it needs to be re-rendered using the preset rendering style. In this embodiment, the preset operation is either hovering the mouse over the target basic geometry or selecting the target basic geometry. Accordingly, there are two preset rendering styles, corresponding to hovering the mouse over the target basic geometry and selecting the target basic geometry, respectively. In actual operation, hovering the mouse over the target basic geometry does not require clicking the left or right mouse button, while selecting the target basic geometry requires clicking the left or right mouse button.
[0055] In practical applications, the rendering method of this application embodiment and the rendering method of the prior art are tested and compared. The test object is a circuit layout containing one layer with 40,000 basic geometric shapes. The test results are shown in the table below.
[0056] Rendering methods Frame rate (frames per second) Memory usage (MB) Existing technology 6 1552 Examples of this application 100 1149
[0057] By comparison, it can be seen that rendering the circuit layout using the rendering method of the embodiments of this application can significantly improve the frame rate and significantly reduce memory usage.
[0058] Please refer to Figure 5 The present invention also provides a circuit layout rendering apparatus, the rendering apparatus comprising:
[0059] The acquisition module 11 is used to acquire vertex data of basic geometric figures on different layers of the circuit layout. The vertex data includes the index and coordinates of the vertices of the basic geometric figures. Since integrated circuits are manufactured layer by layer using photolithography, they are not limited to one layer. Correspondingly, the circuit layout also includes many layers, each containing basic geometric figures. Basic geometric figures include line segments and polygons; that is, any basic geometric figure has at least two vertices. The vertex index determines the connection order between vertices, and the vertex coordinates determine the position of the vertex in the circuit layout.
[0060] The caching module 12 is used to cache vertex data belonging to the same layer contiguously in the data cache area, and to cache vertex data from different layers separately in the data cache area. The data cache area can be a pre-allocated region in memory used for storing vertex data and facilitating data communication between memory and the GPU; this data cache area is also called a buffer. When caching vertex data, the vertex data of each layer is contiguous in memory, but in adjacent layers, the last data point of the vertex data in the previous layer is separate from the first data point of the vertex data in the next layer; they are not contiguous. In summary, the data cache area caches multiple segments of separated vertex data, each segment belonging to a layer, and the vertex data within each segment is contiguous.
[0061] The rendering module 13 executes a draw call command (Draw Call) on each segment of consecutively cached vertex data in the data buffer to render each layer. For the GPU, a single Draw Call can only render data in contiguous memory. Since the vertex data of the same layer is contiguous, the consecutively cached vertex data in the data buffer can be submitted to the GPU for rendering at once, thus rendering the corresponding layer. For the next layer, i.e., the next segment of consecutively cached vertex data, the next Draw Call is executed.
[0062] The aforementioned acquisition module 11 and cache module 12 can be integrated into the CPU of the computer architecture, and the aforementioned rendering module 13 can be integrated into the GPU of the computer architecture.
[0063] The circuit layout rendering apparatus of this embodiment may also include other technical features of the circuit layout rendering method of the foregoing embodiment, implement all the steps of the rendering method of the foregoing embodiment, and have the same technical effect as the rendering method of the foregoing embodiment, which will not be repeated here.
[0064] The present invention also provides a storage medium storing a computer program configured to execute the circuit layout rendering method of the foregoing embodiments at runtime.
[0065] Specifically, in this embodiment, the storage medium may include, but is not limited to, USB flash drives, read-only memory (ROM), random access memory (RAM), portable hard drives, magnetic disks, or optical disks, and other media capable of storing computer programs.
[0066] The present invention also provides an electronic device, including a memory and a processor, wherein the memory stores a computer program and the processor is configured to run the computer program to execute the circuit layout rendering method of the foregoing embodiments.
[0067] Specifically, the memory and processor can be connected via a data bus. Furthermore, the aforementioned electronic device may also include a transmission device and an input / output device, wherein the transmission device is connected to the processor, and the input / output device is connected to the processor.
[0068] In the description of this specification, references to terms such as "one embodiment," "some embodiments," "example," or "specific example," etc., indicate that a specific feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of the invention. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments. In addition, those skilled in the art can combine and integrate the different embodiments or examples described in this specification.
[0069] The above are merely preferred embodiments of the present invention and do not constitute any limitation on the present invention. Any equivalent substitutions or modifications made by those skilled in the art to the technical solutions and content disclosed in the present invention without departing from the scope of the present invention shall be deemed to have remained within the scope of protection of the present invention.
Claims
1. A method of rendering a circuit layout, characterized by, The method comprises the following steps: Obtaining vertex data of basic geometric figures on all layers of a circuit layout, wherein the vertex data comprises serial numbers and coordinates of vertices of the basic geometric figures; Continuously caching vertex data belonging to the same layer in a data cache area, and separately caching vertex data of different layers in the data cache area; Respectively executing a DrawCall on each piece of continuously cached vertex data in the data cache area to respectively complete rendering of each layer.
2. The rendering method of claim 1, wherein, The step of continuously caching vertex data belonging to the same layer in a data cache area, and separately caching vertex data of different layers in the data cache area comprises the following steps: According to the number of layers of the circuit layout and the number of vertices of vertex data of each layer, separately setting cache segments in a data cache area, wherein each address bit of the cache segment is used to cache a vertex coordinate; Setting a cache order of the basic geometric figures in each layer; Caching vertex data of the basic geometric figures of the corresponding layer in each cache segment according to the cache order, wherein the vertex coordinates of each basic geometric figure are cached in continuous address bits according to the vertex serial numbers, and the address bits corresponding to sequentially adjacent basic geometric figures are continuous.
3. The rendering method of claim 2, wherein, The cache order is a drawing order of the basic geometric figures in each layer.
4. The rendering method of claim 1, wherein, Different rendering styles are adopted each time the DrawCall is executed.
5. The rendering method of claim 4, wherein, The rendering styles comprise a border style and / or a filling style.
6. The rendering method of claim 1, wherein, The rendering method further comprises the following steps: When a target basic geometric figure is triggered by a preset operation, executing the DrawCall again on the target basic geometric figure by adopting a preset rendering style to respectively re-render the target basic geometric figure, wherein the preset rendering style is different from the rendering style corresponding to any layer.
7. The rendering method of claim 6, wherein, The preset operation is that a mouse stays in the range of the target basic geometric figure or the mouse selects the target basic geometric figure.
8. An apparatus for rendering a circuit layout, the apparatus comprising: The method comprises the following steps: An obtaining module is configured to obtain vertex data of basic geometric figures on all layers of a circuit layout, wherein the vertex data comprises serial numbers and coordinates of vertices of the basic geometric figures; A caching module is configured to continuously cache vertex data belonging to the same layer in a data cache area, and separately cache vertex data of different layers in the data cache area; A rendering module is configured to respectively execute a DrawCall on each piece of continuously cached vertex data in the data cache area to respectively complete rendering of each layer.
9. A storage medium, characterized by The storage medium stores a computer program, and the computer program is configured to execute the rendering method of the circuit layout according to any one of claims 1 to 7 when the computer program is run.
10. An electronic device, comprising: The circuit layout rendering device comprises a memory and a processor, wherein the memory stores a computer program, and the processor is configured to execute the rendering method of the circuit layout according to any one of claims 1 to 7 when the computer program is run.