Method for improving super-division operation performance of AI computing chip

Abstract

The invention relates to the technical field of computer data processing, and discloses a method for improving the super-division operation performance of an AI computing chip, and the method comprises the following steps: S1, collecting low-resolution image data, and carrying out the partitioning processing of the low-resolution image data, and obtaining image blocks; s2, performing data complexity analysis on the image blocks to quantify complexity information of the image blocks, and generating an entropy graph according to the complexity information obtained through analysis; s3, adaptively distributing the image blocks to a detailed calculation path or a low-complexity calculation path according to complexity information of the image blocks in the entropy graph so as to start asynchronous super-division operation; and S4, receiving an asynchronously output super-division operation result from the calculation path and the low-complexity calculation path. According to the method, the complexity of the image blocks is analyzed, and differential calculation path processing is adopted, so that the overall calculation amount and power consumption of super-division operation are reduced, and the operation performance of an AI calculation chip is improved.

Description

Technical Field

[0001] This invention relates to the field of computer data processing technology, specifically a method for improving the super-resolution computing performance of AI computing chips. Background Technology

[0002] With the widespread adoption of high-definition and ultra-high-definition display devices (such as 4K / 8K TVs and high-resolution smartphone screens), users' demands for visual experience quality are increasing. In daily life, people often need to watch low-resolution media content, such as classic old movies, standard-definition video streams, or compressed online images. Playing this content directly on high-definition devices results in blurry and distorted images, severely impacting the viewing experience. Image super-resolution computing technology was developed to solve this problem; it can restore low-resolution images to clear, detailed, high-resolution images.

[0003] Currently, super-resolution methods based on deep neural networks (especially convolutional neural networks) have become the mainstream technology. Compared to traditional image interpolation algorithms that only produce blurry or jagged results, deep learning methods have achieved breakthroughs in image reconstruction quality. These methods, trained on massive amounts of data, can learn complex mapping relationships from low to high resolution, thus realistically recovering high-frequency texture details lost in the original image and generating clear, natural object edges. This superior reconstruction effect makes deep learning-based super-resolution technology the preferred solution for achieving high-quality image restoration.

[0004] However, while pursuing superior reconstruction results, the aforementioned deep neural network methods typically employ a uniform processing approach, applying the same complete and complex neural network model to all regions of the input image. This approach fails to consider the spatial complexity variations within the image content itself. A typical image often contains both low-complexity regions with smooth content, such as the sky and walls, and high-complexity regions with rich textures, such as text and faces. This uniform processing approach imposes the same high computational load on these low-complexity regions as it does on the high-complexity regions, resulting in significant redundancy of computational resources and unnecessary power consumption. Furthermore, the complex neural network model implies a large number of parameters, requiring frequent data retrieval from slow external memory when processing the entire image, easily creating a memory bandwidth bottleneck and thus limiting the overall computing performance of the AI ​​chip. Summary of the Invention

[0005] To address the shortcomings of existing technologies, this invention provides a method for improving the super-resolution performance of AI computing chips. This method solves the problem that existing technologies, when using AI computing chips to perform image super-resolution operations, adopt a mode of uniformly calculating and processing the entire image without considering the complexity differences of image content in different regions. This results in unnecessary computational overhead and data transfer in smooth areas with less texture detail, ultimately limiting computing performance and increasing power consumption.

[0006] To achieve the above objectives, the present invention provides the following technical solution:

[0007] This invention provides a method for improving the super-resolution performance of AI computing chips, the method comprising the following steps:

[0008] S1. Acquire low-resolution image data and divide the low-resolution image data into blocks to obtain image blocks;

[0009] S2. Perform data complexity analysis on the image block to quantify the complexity information of the image block, and generate an entropy map based on the complexity information obtained from the analysis;

[0010] S3. Based on the complexity information of the image blocks in the entropy map, the image blocks are adaptively assigned to detailed computation paths or low-complexity computation paths to initiate asynchronous super-resolution operations.

[0011] S4. Receive the asynchronously output super-resolution operation results from the computation path and the low-complexity computation path;

[0012] S5. The received super-resolution operation results are spatially reorganized according to the original coordinate index, and the boundary between the super-resolution operation results of the calculation path and the low-complexity calculation path is smoothed to generate a high-resolution image.

[0013] In one specific embodiment, the step of segmenting the low-resolution image data includes: logically dividing the low-resolution image data into image blocks of fixed size that do not overlap, in order to adapt to the on-chip cache capacity of the AI ​​computing chip.

[0014] Preferably, the step of performing data complexity analysis on the image patch includes:

[0015] Calculate the variance of pixel values ​​for all pixels within the image block;

[0016] The calculated variance of the pixel values ​​is used as the quantized complexity information, which is used to characterize the richness of texture details of the image patch.

[0017] Furthermore, the pixel value variance E i,jDetermined by the following formula:

[0018]

[0019] In the formula, E i,j Let p(x,y) be the pixel value variance of the image patch with index [i,j]; W and H be the width and height of the image patch, respectively; p(x,y) be the pixel value at coordinates (x,y) within the image patch; μ i,j The average pixel value of the image block.

[0020] In one specific embodiment, the step of initiating asynchronous super-resolution computation includes:

[0021] The complexity information of the image patch is compared with at least one preset complexity threshold; and based on the comparison result, the target routing path of the image patch is determined to be the computation path or the low-complexity computation path.

[0022] Preferably, the technical difference between the computation path and the low-complexity computation path lies in:

[0023] The computational path is configured to execute a full, unsimplified super-resolution neural network model; while the low-complexity computational path is configured to execute a simplified super-resolution neural network model or a conventional image interpolation algorithm.

[0024] In one specific embodiment, the step of receiving the asynchronously output super-resolution operation result includes:

[0025] A result buffer unit is set up to receive and temporarily store the super-resolution operation results. When the super-resolution operation results are output from the calculation path or the low-complexity calculation path, the super-resolution operation results together with the corresponding original coordinate index are stored in the result buffer unit to achieve ordered management of the asynchronously arriving super-resolution operation results.

[0026] Furthermore, the ordered management specifically includes:

[0027] Create and maintain a completion status table corresponding to the spatial layout of the image blocks. The completion status table is used to record whether the super-resolution operation of each image block is completed.

[0028] When any of the super-resolution operation results is stored in the result buffer unit, the status of the corresponding entry in the completion status table is updated to the completion status according to its corresponding original coordinate index.

[0029] Furthermore, after all entries in the completion status table are updated to the completion status, a reconstruction ready signal is generated, which is used to trigger the subsequent spatial location reorganization and smoothing process.

[0030] In one specific embodiment, the step of reorganizing the spatial location based on the original coordinate index specifically includes:

[0031] Create a frame buffer for storing the final high-resolution image; traverse the two-dimensional spatial coordinates of the high-resolution image; and retrieve the super-resolution operation result with the corresponding original coordinate index from the result buffer unit according to the traversed two-dimensional spatial coordinates, and fill the retrieved super-resolution operation result into the corresponding position of the frame buffer.

[0032] Preferably, the step of smoothing the boundary between the super-resolution operation results of the computation path and the low-complexity computation path specifically includes:

[0033] A boundary region is determined between the super-resolution result obtained by the aforementioned computational path and the super-resolution result obtained by the aforementioned low-complexity computational path; and a weighted fusion calculation is performed on the pixels within the boundary region to eliminate visual discontinuities between the processing results of different computational paths. The weighted fusion calculation is implemented using the following formula:

[0034] P final =α·P A +(1-α)·P B ;

[0035] In the formula, P final P represents the final pixel value after pixel fusion within the boundary region. A P is the pixel value at this pixel location derived from the super-resolution operation result originating from the computation path; B α is the pixel value at this pixel location, derived from the super-resolution operation result of the low-complexity computation path; α is a weighting coefficient, the value of which is determined based on the relative position of the spatial location within the boundary region.

[0036] This invention provides a method for improving the super-resolution computing performance of AI computing chips. It has the following beneficial effects:

[0037] 1. This invention analyzes the data complexity of image blocks to be processed and assigns image blocks with complexity information below a preset threshold to low-complexity computation paths for processing, avoiding unnecessary full super-resolution neural network model operations on smooth areas of the image. This reduces the total computational load required to process the entire image, thereby improving the overall computing speed of the AI ​​computing chip and reducing power consumption without sacrificing the image quality of key detail areas.

[0038] 2. This invention reduces the need to read parameters of the complete super-resolution neural network model from off-chip memory by routing some image blocks to low-complexity computation paths that execute simplified models or traditional interpolation algorithms. Since the amount of data required by simplified models or interpolation algorithms is much smaller than that of the complete model, this method effectively reduces the memory bandwidth usage of AI computing chips when performing super-resolution tasks, alleviates data transfer bottlenecks, and further improves system performance.

[0039] 3. This invention effectively eliminates visual discontinuities or block artifacts that may arise from different processing methods by performing weighted fusion-based smoothing processing on the boundary regions between adjacent super-resolution operation results obtained from different computational paths during the final result fusion stage. This technical feature ensures that while achieving computational optimization, the final generated high-resolution image possesses good visual consistency and overall quality. Attached Figure Description

[0040] Figure 1 This is a schematic diagram of the method flow of the present invention;

[0041] Figure 2 This is a schematic diagram of the data complexity analysis and entropy graph generation process of the present invention;

[0042] Figure 3 This is a schematic diagram of the adaptive task allocation process of the present invention. Detailed Implementation

[0043] The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0044] Reference Figures 1-3 , Figure 1 This is a schematic flowchart of a method according to an embodiment of the present invention. The present invention provides a method for improving the super-resolution performance of AI computing chips, the method comprising the following steps:

[0045] In step S100, the system initiates the image acquisition and preprocessing process. This step begins by acquiring a complete frame of low-resolution image data from the image sensor or main memory. To facilitate efficient processing within the computationally limited AI chip, this method does not directly process the entire image but logically divides it into a two-dimensional grid composed of multiple fixed-size, non-overlapping image blocks. The size of each image block is pre-set to ensure that its data volume can be fully loaded into the high-speed on-chip cache within the AI ​​chip. This block-sharing strategy forms the basis for subsequent parallelization and streaming processing, transforming large-scale image data into a series of uniformly sized, easily manageable data units. Simultaneously with block division, the system assigns an original coordinate index to each image block, which precisely records its spatial location in the original image, providing a crucial basis for the final image reconstruction.

[0046] In step S200, the purpose is to quantitatively evaluate the richness of texture details within each image patch. Specifically, the analysis process calculates the degree of difference in pixel values ​​among all pixels within the image patch. If the pixel values ​​within an image patch vary drastically and are widely distributed, it means that it contains a large number of high-frequency details such as edges and textures, and its complexity information value is high. After analyzing all image patches, the system organizes these complexity information values ​​to construct an entropy map. This entropy map structurally corresponds perfectly to the grid of image patches, with each location storing the complexity value of the corresponding image patch, thus forming a metadata map depicting the global complexity distribution of the original image.

[0047] In step S300, the processing unit checks the complexity information of each image patch in the entropy map one by one and compares it with a preset complexity threshold. If the complexity information of an image patch is higher than the threshold, the system determines it to be a key region with rich details and sends its data and related instructions to the "computation path". This path is configured with a complete, unsimplified super-resolution neural network model and sufficient computing resources to perform high-precision super-resolution operations. If the complexity information of an image patch is not higher than the threshold, it is determined to be a smooth region and assigned to the "low-complexity computation path". The low-complexity computation path executes a simplified super-resolution model or a traditional image interpolation algorithm, with a computational overhead much smaller than that of the computation path. Because the processing load and algorithm complexity of the two paths are different, their computational delays are also significantly different. Therefore, the processing completion time of each image patch is asynchronous and unordered.

[0048] In step S400, the system is specifically responsible for receiving and managing these asynchronously arriving super-resolution operation results. Because the computation path is time-consuming while the low-complexity computation path is faster, the processed image patches will be output from these two paths in an unpredictable order. To manage this data in an orderly manner, the system sets up a result buffer unit, which is a temporary storage space used to temporarily store all processed super-resolution operation results. Each result carries its original coordinate index when stored, ensuring that its spatial location information is not lost. Step S400 uses a management mechanism to track which image patches have been processed, and only after the results of all image patches have been safely stored in the buffer unit will the subsequent final processing flow be triggered.

[0049] In step S500, the system generates a high-resolution image. This final stage includes two key operations. The first operation is spatial reassembly. The system creates a sufficiently large blank frame buffer and then iterates through each super-resolution operation result in the result buffer unit, precisely filling its pixel data into the corresponding position in the frame buffer based on its original coordinate index. The second operation is boundary smoothing. After reassembly, the system identifies adjacent image patches processed by different computational paths. At the seams of these image patches, visually unnatural edges may occur due to differences in processing precision. To eliminate this block effect, the system performs weighted fusion on the pixels in these boundary regions, that is, it smoothly blends and transitions their pixel values ​​based on the relative distance of the pixels to the two different regions. After completing these two operations, the data in the frame buffer constitutes a complete, clear, and visually continuous final high-resolution image.

[0050] Reference Figures 1-3 The system acquires a frame of low-resolution image data to be processed from an external image sensor or the system's main memory via the data interface of the AI ​​computing chip. This low-resolution image data exists in the form of a two-dimensional pixel matrix.

[0051] The acquired low-resolution image data is processed into blocks. This block processing logically divides the complete low-resolution image into a two-dimensional grid, where each unit is an image block. In this embodiment, all image blocks are set to a fixed, predefined size, such as W×H pixels, and adjacent image blocks do not overlap.

[0052] The size (W×H) of the image patch is determined to be compatible with the hardware resources within the AI ​​computing chip. Specifically, this size is set so that all pixel data of a single image patch (or a batch of image patch data required for one processing session) can be fully accommodated by the chip's high-speed on-chip cache (e.g., SRAM). This setting allows subsequent super-resolution operations to be performed in a streaming manner, with the processing unit only needing to interact with the high-speed on-chip cache, thereby reducing the number of accesses to low-speed off-chip main memory (e.g., DDR) and lowering latency caused by data transfer.

[0053] During the block processing, each generated image block is assigned a unique original coordinate index [i,j]. This index precisely records the row and column position of the image block in the two-dimensional grid of the original low-resolution image. This original coordinate index is passed down along with the image block data, and its core function is to provide accurate location information for spatial reassembly in the subsequent step S500, ensuring that all the asynchronously processed super-resolution operation results can be correctly stitched back to their positions in the final high-resolution image.

[0054] Reference Figures 1-3 After the low-resolution image data is segmented in step S100, the method enters the data complexity analysis stage. The core task of this stage is to calculate a quantifiable value that characterizes the richness of information within each independent image block, i.e., complexity information. In this embodiment, this complexity information is determined by calculating the variance of pixel values ​​within the image block. The variance of pixel values ​​can directly reflect the dispersion of pixel grayscale values: image blocks with larger variance values ​​have a wide distribution of pixel values ​​and frequent jumps, corresponding to regions containing rich textures, edges, or details; conversely, image blocks with smaller variance values ​​have pixel values ​​that tend to be consistent, corresponding to regions with smooth and uniform content.

[0055] For an image patch with index [i,j] obtained from step S100, the data complexity analysis specifically includes the following calculation process:

[0056] Calculate the average pixel value μ of all pixels within this image patch. i,j Let the size of the image patch be W×H pixels, and p(x,y) be the pixel value at coordinates (x,y) within the image patch. Then the formula for calculating the average pixel value is:

[0057]

[0058] In the formula, W and H are the width and height of the image patch, respectively; p(x,y) is the pixel value at coordinates (x,y) within the image patch; μ i,j The average pixel value of the image block.

[0059] Subsequently, based on the calculated average pixel value μ i,j Calculate the variance E of the pixel values ​​of this image patch. i,j This value serves as the final quantized complexity information. Its calculation formula is as follows:

[0060]

[0061] In the formula, E i,j Let p(x,y) be the pixel value variance of the image patch with index [i,j]; W and H be the width and height of the image patch, respectively; p(x,y) be the pixel value at coordinates (x,y) within the image patch; μ i,j The average pixel value of the image block.

[0062] After calculating the complexity information for all image blocks, this information is aggregated to generate an entropy map. The entropy map is a two-dimensional data structure whose dimensions completely correspond to the two-dimensional grid formed by image segmentation in step S100. Each element in the entropy map has coordinates [i,j], and stores the complexity information E of the corresponding original image block. i,j This entropy map constitutes a low-resolution metadata map depicting the global complexity distribution of the original image, providing a direct and quantitative basis for decision-making in the adaptive task allocation in the subsequent step S300.

[0063] Reference Figures 1-3 After obtaining the entropy map generated in step S200, the system performs an independent path selection and task allocation for each image patch to be processed, based on its corresponding complexity information. The decision-making process is completed by the comparator logic unit, which compares the complexity information of the image patch with one or more preset complexity thresholds.

[0064] In one specific embodiment, a complexity threshold θ is preset within the system. comp For an index [i,j] with a complexity of E... i,j The rules for determining the target routing path for an image patch are as follows:

[0065] If E i,j >θ comp If E is a high-complexity region, then the image patch is determined to be a high-complexity region and routed to the computation path; if E i,j ≤θ comp If the image patch is determined to be a low-complexity region, it will be routed to a low-complexity computation path.

[0066] The complexity threshold θ comp It is a parameter that can be configured by the system software, and its value can be set to balance image reconstruction quality and computational performance.

[0067] The computational path described herein differs significantly from the low-complexity computational path in its technical configuration. The computational path is configured to execute a complete, unsimplified super-resolution neural network model. When an image patch T... i,j When assigned to this path, it will be processed by a dedicated set of high-performance computing cores. The processing executes the complete super-resolution operation function F. full And call all neural network model parameters Φ full (Including complete weights and biases). Its mathematical expression is:

[0068] T′ i,j =F full (T i,j ,Φ full );

[0069] In the formula, T i,j The input image patch; T′ i,j The output is the super-resolution result; Φ full For neural network model parameters; F full This is a super-resolution operation function. This path offers high computational accuracy and reconstruction quality, but also incurs the greatest computational overhead and data transfer volume.

[0070] The low-complexity computation path is configured to perform computationally inexpensive operations. In one embodiment, the low-complexity computation path executes a simplified super-resolution neural network model, such as a model F that has undergone network pruning or weight quantization (e.g., INT8 quantization). med .

[0071] In another embodiment, the path directly executes a conventional, non-neural network image interpolation algorithm F. interp For example, bicubic interpolation. Both of these configurations can generate super-resolution results with a much lower computational cost than the computation path, making them suitable for processing image regions with limited texture detail.

[0072] Because the calculation path executes F full The computational complexity of the operation is much higher than that of the operation performed by the low-complexity computation path, resulting in a significant difference in processing latency. This will cause the super-resolution operation results of each image patch to be processed and output in a different order than their original input. This non-sequential processing completion time is the asynchronous super-resolution operation described in this invention. These asynchronously output super-resolution operation results, along with their original coordinate indices (i,j), will be sent to the next step S400 for reception.

[0073] Reference Figures 1-3In step S300, after the image patch is assigned to different computing paths to initiate asynchronous super-resolution operations, its super-resolution results will be generated at different times according to the computing delay of each path. To handle this temporal uncertainty, this embodiment sets up a result buffer unit. The result buffer unit is a dedicated on-chip storage area used to receive and temporarily store all super-resolution results output by the computing paths and low-complexity computing paths. When any computing path completes the processing of the image patch, it writes the generated super-resolution result, along with the original coordinate index assigned to the image patch in step S100, as a data packet into the result buffer unit.

[0074] To ensure that subsequent image reconstruction steps are initiated only after all data blocks are ready, this embodiment also includes an ordered management mechanism. The core of this mechanism is the creation and maintenance of a completion status table. This completion status table is a two-dimensional array whose size is identical to the grid layout of the image blocks in step S100. At the beginning of processing a new image frame, all entries in this completion status table are initialized to an "incomplete" state, such as a logical value of "0".

[0075] A control logic unit continuously monitors the write activity of the result buffer unit. Whenever a new super-resolution result data packet is stored in the result buffer unit, the control logic unit immediately extracts its corresponding original coordinate index [i,j] from the data packet. Subsequently, the control logic unit uses this index [i,j] as an address to access the completion status table and updates the status of the corresponding entry in the table from "incomplete" (logical "0") to "complete" (logical "1").

[0076] After each update of the completion status table, the control logic unit performs a check to determine whether all image blocks have completed the super-resolution operation. This check is implemented through hardware logic, whose input is all the status bits in the completion status table. The output state of the hardware logic will change only if and only if the status of all entries in the completion status table is "complete".

[0077] Once the hardware logic confirms that all entries have been updated to the "complete" state, it immediately generates a reconstruction ready signal. This signal is transmitted to the hardware module responsible for executing step S500. This signal acts as a trigger, precisely notifying subsequent processing stages that all necessary super-resolution operation results have been received and temporarily stored in the result buffer unit, allowing for the safe initiation of the final high-resolution image spatial location reconstruction and smoothing process. This avoids image reconstruction errors or processing pauses caused by incomplete data.

[0078] Reference Figures 1-3The system creates a frame buffer in memory to store the final high-resolution image. The size of the frame buffer is determined by the size of the original low-resolution image and the super-resolution ratio. The memory address controller calculates the precise write address in the final high-resolution frame buffer based on the original coordinate index [i,j] of each image block. Subsequently, the controller retrieves the corresponding super-resolution result data block from the result buffer unit according to the original coordinate index and writes the entire data block into the corresponding location in the frame buffer. This process is repeated until all super-resolution results are filled into the frame buffer, forming a complete preliminary high-resolution image, which may have visual discontinuities at block boundaries.

[0079] The second stage is boundary smoothing. This stage is specifically designed to address the seams between adjacent blocks resulting from two different processing modes: computational paths and low-complexity computational paths. The process begins by identifying boundary regions. Boundary regions are defined as the boundary between the super-resolution result obtained from the computational path and the super-resolution result obtained from the adjacent low-resolution computational path. The system accurately identifies all such heterogeneous boundaries by querying the routing decision history of each image block in step S300.

[0080] For the identified boundary region, the system performs a weighted fusion calculation on the pixels within it. This boundary region has a preset width, for example, N pixels, with some pixels located on one side of the computation path result block and others on the other side of the low-complexity computation path result block. For any pixel within this region, its final pixel value P... final The calculation is performed using the following formula:

[0081] P final =α·P A +(1-α)·P B ;

[0082] In the formula, P final P represents the final pixel value after pixel fusion within the boundary region. A P is the pixel value at this pixel location derived from the super-resolution operation result originating from the computation path; B α is the pixel value at this pixel location, derived from the super-resolution operation result of the low-complexity computation path; α is a weighting coefficient, the value of which is determined based on the relative position of the spatial location within the boundary region.

[0083] The value of the weight coefficient α is dynamically determined according to the relative position of the pixel within the boundary region, and its value range is between 0 and 1. In a specific implementation, the value of α is designed to smoothly transition from 0 to 1 from the side of the low-complexity calculation path to the side of the calculation path. For example, within a boundary region with a width of N, a normalized coordinate d {0 ≤ d < N} is defined, where d = 0 represents the side closest to the result block of the low-complexity path, and d = N - 1 represents the side closest to the result block of the calculation path. Then the weight coefficient α can be determined as:

[0084] α = d / (N - 1);

[0085] In the formula, α is the weight coefficient; d represents a normalized coordinate within the boundary region; N represents the width of the boundary region, with the unit of pixel.

[0086] In this way, on the side of the boundary region closest to the result of the low-complexity path, α approaches 0, and the fused pixel value is mainly determined by P B ; in the center of the boundary region, α approaches 0.5, and the fused pixel value is approximately equally contributed by P A and P B ; while on the side closest to the result of the calculation path, α approaches 1, and the fused pixel value is mainly determined by P A . Thus, the visual discontinuity between the processing results of different calculation paths is effectively eliminated, generating a final smooth and high-quality high-resolution image.

Claims

1. A method for improving the superdivision operation performance of an AI computing chip, characterized in that, The method comprises the following steps: S1, collecting low-resolution image data and performing block processing on the low-resolution image data to obtain image blocks; S2, performing data complexity analysis on the image blocks to quantify the complexity information of the image blocks, and generating an entropy map according to the complexity information obtained by the analysis; S3, according to the complexity information of the image blocks in the entropy map, the image blocks are adaptively assigned to a detailed calculation path or a low-complexity calculation path to start asynchronous super-resolution operation; S4, receiving the asynchronous output of the super-resolution operation result from the calculation path and the low-complexity calculation path; S5, recombining the received super-resolution operation result according to the original coordinate index, and performing smoothing processing on the super-resolution operation result boundary of the calculation path and the low-complexity calculation path to generate a high-resolution image.

2. The method for improving the superdivision operation performance of an AI computing chip according to claim 1, wherein, In step S1, the block processing on the low-resolution image data comprises: The low-resolution image data is logically divided into image blocks with fixed size and no overlap to adapt to the on-chip cache capacity of the AI computing chip.

3. The method of claim 1, wherein, In step S2, the data complexity analysis on the image blocks comprises: Calculating the pixel value variance of all pixels in the image block; The pixel value variance obtained by calculation is used as the quantized complexity information, which is used to represent the texture detail richness of the image block.

4. The method for improving the superdivision operation performance of an AI computing chip according to claim 3, wherein, The pixel value variance is determined by the following formula: where E i,j is the variance of pixel values of the image block indexed [i,j]; W and H are the width and height of the image block, respectively; p(x,y) is the pixel value at coordinate (x,y) within the image block; μ i,j is the average pixel value of the image block.

5. The method for improving the superdivision operation performance of an AI computing chip according to claim 1, wherein, In step S3, the asynchronous super-resolution operation comprises: Comparing the complexity information of the image blocks with at least one preset complexity threshold; According to the comparison result, the target routing path of the image block is determined as the calculation path or the low-complexity calculation path.

6. The method for improving the superdivision operation performance of an AI computing chip according to claim 5, wherein, The technical features of the calculation path and the low-complexity calculation path are different: The calculation path is configured to execute a complete, unsimplified super-resolution neural network model; The low-complexity calculation path is configured to execute a simplified super-resolution neural network model or a traditional image interpolation algorithm.

7. The method of claim 1, wherein, In step S4, the receiving of the asynchronous output of the super-resolution operation result comprises: Setting a result buffer unit for receiving and temporarily storing the super-resolution operation result; When the super-resolution operation result is output from the calculation path or the low-complexity calculation path, the super-resolution operation result is stored in the result buffer unit together with the corresponding original coordinate index to realize the ordered management of the asynchronous super-resolution operation result.

8. The method for improving the superdivision operation performance of an AI computing chip according to claim 7, wherein, The ordered management specifically comprises: Building and maintaining a completion state table corresponding to the spatial layout of the image blocks, which is used to record whether the super-resolution operation of the image blocks is completed; When the super-resolution operation result is stored in the result buffer unit, according to the corresponding original coordinate index, the state of the corresponding item in the completion state table is updated to the completion state; After the state of all items in the completion state table is updated to the completion state, a reconstruction ready signal is generated, which is used to trigger the subsequent spatial position recombination and smoothing processing.

9. The method for improving the superdivision operation performance of an AI computing chip according to claim 1, wherein, In step S5, the recombination of the spatial positions according to the original coordinate indexes specifically comprises: creating a frame buffer for storing the final high-resolution image; traversing the two-dimensional spatial coordinates of the high-resolution image; retrieving the super-resolution operation results corresponding to the original coordinate indexes from the result buffer unit according to the traversed two-dimensional spatial coordinates, and filling the retrieved super-resolution operation results to the corresponding positions of the frame buffer.

10. The method for improving the superdivision operation performance of an AI computing chip according to claim 1, wherein, In step S5, the boundary smoothing processing of the super-resolution operation results of the calculation paths specifically comprises: determining a boundary region between the super-resolution operation results processed by the calculation path and the super-resolution operation results processed by the low-complexity calculation path; and performing a weighted fusion calculation on the pixels in the boundary region to eliminate the visual discontinuity between the processing results of different calculation paths, the weighted fusion calculation being realized by the following formula: P final = a - P A + (1 - a) - P B ; In the formula, P final is the final pixel value after pixel fusion in the boundary region; P A is the pixel value of the super-resolution operation result from the calculation path at the pixel position; P B is the pixel value of the super-resolution operation result from the low-complexity calculation path at the pixel position; and α is a weight coefficient, the value of which is determined according to the relative position of the spatial position in the boundary region.

Images