System and method for manufacturing wafer

Abstract

A method of manufacturing a wafer includes the steps of: enhancing, by a processor, at least one defective portion of a target wafer image; performing an image processing operation on the at least one defective portion by the processor; adjusting the size of the target wafer image through the processor; comparing, by the processor, a target tensor based on the target wafer image with a plurality of historical tensors of a plurality of historical wafer images to generate a plurality of similarities; and selecting, by the processor, a plurality of historical wafer images of the historical wafer images according to the similarity between the target tensor and the historical tensor to adjust at least parameters of a machine for manufacturing at least one wafer. According to the method for manufacturing the wafer, the wafer with fewer defect parts and higher quality is manufactured.

Description

Technical Field

[0001] This invention relates to a system and method, and more particularly to the manufacture of a wafer. Background Technology

[0002] Searching for wafers with similar defects from a large number of wafers is neither feasible nor of high quality. Relying on experience in identifying suspicious workstation sections, manually comparing wafers for similar defects is extremely time-consuming. Traditional pixel-matching algorithms are not very accurate. Therefore, designing a comparison method to address these problems is an important issue in this field. Summary of the Invention

[0003] A method for manufacturing a wafer includes the following steps: enhancing at least one defective portion of a target wafer image using a processor; performing an image processing operation on the at least one defective portion using a processor; adjusting the size of the target wafer image using a processor; comparing a target tensor based on the target wafer image with multiple historical tensors of multiple historical wafer images using a processor to generate multiple similarities; and selecting multiple historical wafer images of historical wafer images using a processor based on the similarity between the target tensor and the historical tensors to adjust at least parameters of an equipment used to manufacture at least one wafer.

[0004] In some embodiments, the method further includes: removing a plurality of noises from the target wafer image using a processor.

[0005] In some embodiments, the method further includes: a plurality of historical wafer images of historical wafer images by a processor based on a plurality of conditions associated with a plurality of historical wafers.

[0006] In some embodiments, comparing a target tensor with historical tensors by a processor includes calculating each of a plurality of distances between each of the target tensor and historical tensors to generate a similarity.

[0007] In some embodiments, comparing a target tensor with a historical tensor by a processor includes computing each of a plurality of inner product spaces between each of the target tensor and the historical tensor to generate a similarity.

[0008] In some embodiments, the method further includes: sorting historical wafer images according to similarity by a processor.

[0009] In some embodiments, the method further includes: aggregating at least one manufacturing factor corresponding to at least one defective portion by a processor to generate a report related to the at least one manufacturing factor.

[0010] In some embodiments, the method further includes: generating a target tensor based on a target wafer image using a processor.

[0011] A method for manufacturing a wafer includes the following steps: collecting multiple historical wafer images of a machine via a processor, wherein each historical wafer image corresponds to at least one defective portion; segmenting the historical wafer images into multiple historical target wafer images and multiple historical training wafer images via the processor; generating multiple historical target tensors and multiple historical training tensors via the processor; training a neural network via the processor based on the historical target wafer images and historical training wafer images; wherein each of the historical target tensors and each of the historical training tensors has at least one defective tensor, the at least one defective tensor corresponding to at least one defective portion enhanced by the processor; executing the neural network via the processor to generate multiple historical similarities; wherein the historical similarities are related to the relationship between the historical target tensors and the historical training tensors; and selecting multiple historical wafer images of the historical wafer images via the processor based on the historical similarities for display on a user interface of an input / output device.

[0012] In some embodiments, the method further includes: performing image processing operations via a processor to remove multiple noises from historical target wafer images and historical training wafer images.

[0013] In some embodiments, the method further includes: normalizing the historical target tensor and the historical training tensor by a processor so that the historical target tensor and the historical training tensor are between 0 and 1.

[0014] In some embodiments, the neural network is executed by a processor, which includes comparing historical target tensors with historical training tensors to generate historical similarity.

[0015] A wafer manufacturing system includes a machine and a server. The machine is used to manufacture at least one wafer. The server is coupled to the machine and includes a processor. The processor is used to: collect a target wafer image having at least one defective portion from the machine; perform image processing operations on the at least one defective portion of the target wafer image; execute a neural network to compare a target tensor based on the target wafer image with multiple historical tensors based on multiple historical wafer images to generate multiple similarities; and select multiple historical wafer images based on the target tensor and the historical tensors of the historical wafer images, wherein each of the historical wafer images corresponds to at least one manufacturing factor.

[0016] In some embodiments, the processor is further used to adjust the size of the target wafer image.

[0017] In some embodiments, the processor is further configured to execute a neural network to generate a target tensor based on a target wafer image.

[0018] In some embodiments, the system further includes input / output devices. The input / output devices are used to display a user interface associated with multiple historical wafer images based on similarity.

[0019] In some embodiments, the processor is further configured to sort historical wafer images according to similarity.

[0020] In some embodiments, the processor is further configured to generate reports relating to at least one manufacturing factor.

[0021] In some embodiments, the processor is further configured to adjust at least some parameters of the machine to manufacture at least one wafer or to adjust multiple manufacturing conditions for manufacturing at least one wafer.

[0022] In some embodiments, the historical wafer image corresponds to at least one of a plurality of other machines. Attached Figure Description

[0023] To make the above and other objects, features, advantages and embodiments of the present invention more apparent and understandable, the accompanying drawings are described below: Figure 1 This is a system block diagram illustrated according to an embodiment of the present invention.

[0024] Figure 2A This is a flowchart illustrating a method for training a neural network according to an embodiment of the present invention.

[0025] Figure 2B This is a flowchart illustrating a method for adjusting machine parameters by generating tensors and similarities through a processor, according to an embodiment of the present invention, using an execution neural network.

[0026] Figure 3 This is a user interface provided by an input / output device according to an embodiment of the present invention.

[0027] Figure 4 This is a block diagram of a system according to an embodiment of the present invention. Detailed Implementation

[0028] The spirit of the invention will be discussed in the following figures and detailed description, and those skilled in the art will be able to change and modify the disclosed contents of the invention without departing from the spirit and scope of the invention.

[0029] It should be understood that, within this document and the following patent scope, when an element is considered "connected" or "coupled" to another element, it can mean directly connected or coupled to the other element, where there may be other components. Conversely, when an element is considered "directly connected" or "directly coupled" to another element, there will be no other elements in between. Furthermore, "electrically connected" or "connected" can be used to indicate that two or more elements operate or function together.

[0030] It should be understood that the terms “comprising,” “including,” “having,” “having,” etc., used in this document are open-ended and mean “including but not limited to.”

[0031] It should be understood that the term “AND / OR” as used in this article includes any one or more related items and all combinations thereof.

[0032] Please see Figure 1 . Figure 1 This is a block diagram of a system 100 according to an embodiment of the present invention. System 100 includes a machine 110, a server 120 including a memory 121 and a processor 122, and an input / output device 130 (hereinafter referred to as "I / O device 130" for simplicity). The machine 110 is coupled to the server 120. The memory 121 is coupled to the processor 122. The input / output device 130 is coupled to the server 120.

[0033] The machine 110 can be equipment used to manufacture wafers. For example, by depositing thin films on the wafer or performing other manufacturing processes on the wafer.

[0034] Server 120 may be a processing device. For example, a computer may provide data storage, processing, and control capabilities to machine 110, enabling it to operate, monitor process parameters, and collect and analyze data.

[0035] The memory 121 may be one or more static random access memory (SRAM) devices, one or more dynamic random access memory (DRAM) devices, one or more flash memory devices, one or more random access memory (RAM) devices, one or more erasable programmable read-only memory (EPROM) devices, one or more electrically erasable programmable read-only memory (EEPROM) devices, or one or more similar devices.

[0036] The processor 122 may be one or more central processing units (CPUs), one or more graphics processing units (GPUs), one or more digital signal processors (DSPs), one or more microprocessors (MPUs), one or more micro control units (MCUs), or one or more similar devices.

[0037] In some embodiments, at least one historical wafer image and its data are stored in memory 121 for use by processor 122 to train and execute a neural network or to select at least one historical wafer image. For example, the data of the at least one historical wafer image includes tensors, time, yield, wafer type, product type, and testing method, and processor 122 selects the historical wafer image from memory 121 to display it via I / O device 130. The historical wafer corresponding to the historical wafer image was manufactured by machine 110 at a previous period, for example, three months ago.

[0038] In some embodiments, the execution of the program via server 120 is implemented by processor 122.

[0039] In some embodiments, the historical wafer image corresponds to at least one of machine 110 and other machines. For example, the other machines are machines different from machine 110 and are used to manufacture wafers.

[0040] I / O device 130 may be a personal computer, a laptop computer, and a mobile device (such as a mobile phone or tablet), or a similar electronic device having a display, a touch display panel, or a similar display device.

[0041] In some embodiments, server 120 is used to collect images of a target wafer having at least one defective portion of machine 110, and to perform image processing operations on the target wafer and execute a trained neural network to calculate the similarity between the target wafer image and historical wafer images, in order to summarize at least one manufacturing factor corresponding to the at least one defective portion, so as to adjust at least one parameter of the machine to manufacture the wafer. The manufacturing factor may be at least one of temperature, pressure, or other manufacturing factors related to wafer manufacturing. For example, server 120 performs image processing operations to enhance the defective portion of the target wafer and executes a neural network to calculate the similarity between the target wafer image and historical wafer images, summarizing that in order to manufacture a higher-quality wafer with fewer defects than before, the temperature needs to be reduced from 610°C to 600°C.

[0042] In some embodiments, processor 122 generates a report related to at least one manufacturing factor.

[0043] For example, the report shows the changes in defective parts and yield associated with temperature changes (e.g., from 610°C to 600°C).

[0044] Please see Figure 1 and Figure 2A . Figure 2A This is a flowchart illustrating a method 200A for training a neural network according to an embodiment of the present invention. In some embodiments, method 200A may be executed in server 120.

[0045] In step S211, processor 122 collects at least one historical wafer image from machine 110.

[0046] In some embodiments, the machine 110 captures images of the wafers manufactured by the machine 110 to obtain historical wafer images.

[0047] In other embodiments, server 120 obtains wafer parameters to generate historical images, rather than having the wafer photographed by machine 100. For example, the wafer parameters are a temperature of 610°C, a pressure of 100 Pa, and a thickness of 0.66 Å, so server 120 generates historical wafer images based on these parameters.

[0048] In step S212, the processor 122 segments the historical wafer images into historical target wafer images and historical training wafer images. For example, there are 11,000 historical wafer images, of which 1,100 are historical target wafer images and 9,900 are historical training wafer images.

[0049] In step S213, the processor 122 performs image processing operations on the historical target wafer image and the historical training wafer image.

[0050] For example, processor 122 removes noise from the historical target wafer image and the historical training wafer image using one of the following methods: a median filter, a smoothing method, or a similar noise removal method. For example, the noise could be white grains in the historical target wafer image and the historical training wafer image, where the white grains are independent of the wafer. Therefore, processor 122 removes the white grains from the historical target wafer image and the historical training wafer image.

[0051] For example, processor 122 enhances at least one defective portion of the historical target wafer image and the historical training wafer image. For example, processor 122 magnifies the defective portion based on color. Taking a defined black portion as the defective portion as an example, processor 122 magnifies the black portion of the historical target wafer image and the historical training wafer image to prevent the defective portion from disappearing when the historical target wafer image and the historical training wafer image are adjusted.

[0052] In step S214, processor 122 generates historical target tensor and historical training tensor.

[0053] In some embodiments, the processor 122 executes at least one of an auto-encoder model, a k-means clustering model, or a similar model to generate tensors corresponding to historical images.

[0054] For example, processor 122 executes an autoencoder model based on historical target wafer images and historical training wafer images to generate historical target tensors and historical training tensors. Taking three historical target wafer images and three historical training wafer images as an example, the processor 122 generates historical target tensors (e.g., [[1, 2 , 3]、[4, 5, 6]、[7, 8, 9]]、[[1,1, 2]、[3, 3, 4]、[5, 6, 6]]、[[4, 1, 7]、[6, 3, 9]、[0, 1, 5]]) and historical training tensors (e.g., [[1, 2 , 3]、[4, 5, 6]、[7, 8, 9]]、[[1, 2, 3]、[4, 5, 6]、[7, 8, 0]]、[[0, 9, 9]、[2, 3, 3]、[1, 4, 9]]).

[0055] In step S215, the processor 122 normalizes the historical target tensor and the historical training tensor by scaling the tensor to a range of 0 to 1 or a similar method. In some embodiments, the range can be any numerical interval.

[0056] For example, after the processor 122 converts the historical target wafer image and the historical training wafer image into tensors, the processor 122 executes the program code stored in the memory 121 to scale the historical target tensor (by scaling, the historical target tensor is converted into [[0.1, 0.2, 0.3], [0.4, 0.5, 0.6], [0.7, 0.8, 0.9]], [[0.1, 0.1, 0.2], [0.3, 0.3, 0.4], [0.5, 0.6, 0.6]], [[0.4, 0.1, 0.7], [0.6, 0.3, 0.9], [0, 0.1, 0.5]]) and the historical training tensor (by scaling, the historical training tensor is converted into [[0.1, 0.2, 0.3], [0.4, 0.5]]) and the historical training tensor (by scaling, the historical training tensor is converted into [[0.1, 0.2, 0.3], [0.4, 0.5]]) and the historical training tensor. [0.5,0.6], [0.7, 0.8, 0.9], [[0.1, 0.2, 0.3], [0.4, 0.5, 0.6], [0.7, 0.8, 0], [[0,0.9, 0.9], [0.2, 0.3, 0.3], [0.1, 0.4, 0.9]]).

[0057] In step S216, the processor 122 trains a neural network based on a training dataset, which includes multiple historical target wafer images and historical training wafer images. Other historical target wafer images and historical training wafer images are used as a test dataset to evaluate the performance of the trained neural network.

[0058] For example, there are 1100 historical wafer images and 9900 historical wafer images. The training dataset includes 1000 historical target wafer images and 9000 historical training wafer images. The test dataset includes 100 historical target wafer images and 900 historical training wafer images.

[0059] In some embodiments, processor 122 pairs historical target wafer images with historical training wafer images in a training dataset to form multiple pairs, wherein these pairs are used to train a neural network to generate similarity between historical target wafer images and historical training wafer images. In some embodiments, each pair includes historical training wafer images that are similar to the historical target wafer images in this pair, and also includes historical training wafer images that are not similar to the historical target wafer images in this pair.

[0060] For example, the processor 122 forms 1,000 pairs, and each pair includes one historical target wafer image and nine historical training wafer images, of which five historical training wafer images are similar to the historical target wafer image in the pair, and four are not similar to the historical target wafer image in the pair.

[0061] Specifically, due to steps S21 and S215, the processor 122 trains the neural network based on the historical target tensor of the corresponding historical target wafer image and the historical training tensor of the corresponding historical training wafer image.

[0062] In some embodiments, the processor 122 executes at least one of a supervised learning model, an unsupervised learning model, a self-supervised learning model, or a transfer learning model to generate similarity between the historical target tensor and the historical training tensor in each pair. Specifically, historical training wafer images similar to the historical target wafer images have high similarity, and historical training wafer images dissimilar to the historical target wafer images have low similarity.

[0063] In some embodiments, to test a trained neural network, processor 122 executes the trained neural network to generate similarity scores between historical target wafer images and historical training wafer images from a test dataset. Processor 122 then evaluates the performance of the trained neural network by generating a score for each pair of similarities by comparing the similarity scores to correct results (e.g., a list recording whether historical training wafer images are similar to historical target wafer images).

[0064] In some embodiments, the processor 122 determines whether a historical training wafer image is similar to a historical target wafer image by judging whether the similarity is greater than a certain similarity. For example, if the similarity between the historical training wafer image and the historical target wafer image is greater than 70%, the processor 122 determines that the historical training wafer image and the historical target wafer image are similar. Alternatively, if the similarity between the historical training wafer image and the historical target wafer image is less than 70%, the processor 122 determines that the historical training wafer image and the historical target wafer image are not similar.

[0065] For example, in a test dataset, there are 100 pairs, and each pair includes one historical target wafer image and nine historical training wafer images. In this pair, five historical training wafer images are similar to the historical target wafer image, and four historical training wafer images are dissimilar to the historical target wafer image. In some embodiments, in steps S214 and S215, the historical target wafer images and historical training wafer images in the test dataset have been converted into quantities and normalized. The processor 122 executes a trained neural network to generate similarity scores between the historical target tensor and the historical training tensor for each pair (e.g., the similarity scores for one pair are 81%, 90%, 84%, 86%, 97%, 19%, 17%, 7%, and 5%). Five similarity scores are greater than 70%, and four are less than 70%, indicating that the processor 122 determines that five historical training wafer images are similar to the historical target wafer image in this pair, and four historical training wafer images are dissimilar to the historical target wafer image in this pair. Therefore, the processor 122 produces a score of 100 for the trained neural network executed for this pair.

[0066] For another example, processor 122 executes a trained neural network to generate similarity scores between historical target tensors and historical training tensors for each pair (e.g., similarity scores for one pair are 65%, 55%, 84%, 86%, 97%, 19%, 17%, 7%, and 5%). Three similarity scores are greater than 70%, and six are less than 70%, meaning processor 122 determines that three historical training wafer images in this pair are similar to the historical target wafer image, and six historical training wafer images in this pair are dissimilar to the historical target wafer image. Because five historical training wafer images in this pair are similar to the historical target wafer image, and four historical training wafer images in this pair are dissimilar to the historical target wafer image, two out of the nine results judged by the processor 122 are incorrect. Therefore, the score generated by the trained neural network executed by processor 122 for this pair is 77.77 (e.g., seven correct results divided by nine results).

[0067] In some embodiments, the processor 122 averages the scores of the trained neural networks executed in each pair to evaluate the performance of the trained neural networks. Step S216 stops when the average score reaches the ideal score. For example, if the ideal score is 85, the processor 122 will execute step S216 again if the average score is less than 85. When the average score is greater than the ideal score, the processor 122 stops step S216.

[0068] For example, the test dataset contains 100 pairs, and the average score of the trained neural network executed on these 100 pairs is 91.23. Therefore, processor 122 stops step S216.

[0069] In step S217, the processor 122 executes a neural network to compare the historical target tensor with the historical training tensor to generate historical similarity.

[0070] Taking the historical target tensor [[0.1, 0.2, 0.3], [0.4, 0.5, 0.6], [0.7, 0.8, 0.9]] as an example, the historical training tensor [[0.1, 0.2, 0.3], [0.4, 0.5, 0.6], [0.7, 0.8, 0.9]] has 9 values ​​equal to the corresponding values ​​in the historical target tensor. Therefore, the processor 122 executes the neural network to generate a corresponding historical similarity of 100%. The historical training tensor [[0.1, 0.2, 0.3], [0.4, 0.5, 0.6], [0.7, 0.8, 0]] has 8 values ​​equal to the corresponding values ​​in the historical target tensor. Therefore, the processor 122 executes the neural network to generate a corresponding historical similarity of 88.89%. The historical training tensor [[0, 0.9, 0.9], [0.2, 0.3, 0.3], [0.1, 0.4, 0.9]] has one value that is equal to the value at the corresponding position in the historical target tensor, so the processor 122 executes the neural network to generate the corresponding historical similarity of 11.11%.

[0071] In step S218, the processor 122 selects multiple historical wafer images based on historical similarity to display on the user interface 300 of the I / O device 130.

[0072] For example, processor 122 selects historical wafer images with a similarity greater than 60%. Therefore, among the three historical training tensors mentioned above, processor 122 selects two historical wafer images corresponding to the historical training tensors [[0.1, 0.2, 0.3], [0.4, 0.5, 0.6], [0.7, 0.8, 0.9]] and [[0.1, 0.2, 0.3], [0.4, 0.5, 0.6], [0.7, 0.8, 0]], because the historical similarity of the corresponding historical training tensors is 100% and 88.89%. I / O device 130 displays the two historical wafer images on user interface 300.

[0073] In some embodiments, the steps for training the neural network do not include at least one of steps S213, S216, or S218.

[0074] Please see Figure 1 and Figure 2B . Figure 2B This is a flowchart illustrating a method 200B for adjusting the parameters of machine 110 by generating tensors and similarities via processor 122 using an execution neural network according to an embodiment of the present invention. In some embodiments, method 200B may be executed in server 120.

[0075] In step S221, the processor 122 enhances the defective portions of the target wafer image, wherein the server 120 acquires the target wafer image from the machine 110, or the server 120 generates the target image based on the parameters of the target wafer from the machine 110. For example, the parameters of the target wafer are a temperature of 610°C, a pressure of 100 PA, and a thickness of 0.66 Å, so the server 120 generates the target wafer image based on the parameters.

[0076] In step S222, the processor 122 performs image processing operations on the target wafer.

[0077] For example, processor 122 removes noise from the target wafer image using one of the following methods: median filtering, smoothing, or similar noise removal. For example, the noise could be white grains in the target wafer image, where the white grains are unrelated to the target wafer. Therefore, processor 122 removes the white grains from the target wafer image.

[0078] For example, processor 122 enhances at least one defective portion of the target wafer image. For example, processor 122 magnifies the defective portion based on color. Taking a defined black portion as the defective portion as an example, processor 122 magnifies the black portion of the target wafer image to prevent the defective portion from disappearing when the target wafer image is adjusted.

[0079] In step S223, the processor 122 adjusts the size of the target wafer image.

[0080] For example, processor 122 adjusts the size of the target wafer image. For example, processor 122 adjusts the size of the target wafer image from a first size (e.g., 12x12 cm) to a second size (e.g., 1x2 cm).

[0081] In step S224, the processor 122 generates a target tensor based on the target wafer image.

[0082] For example, processor 122 executes an autoencoder model to generate a target wafer image with target tensors [[1, 2, 3], [4, 5, 6], [7, 8, 9]].

[0083] Please see Figure 1 , Figure 2B ,as well as Figure 3 . Figure 3 This is a user interface 300 provided by an I / O device 130 according to an embodiment of the present invention.

[0084] In some embodiments, the user interface 300 includes a target wafer image area 310, a filter setting area 320, a source selection area 330, a customization setting area 340, a search button 350, and a similar wafer image area 360.

[0085] In some embodiments, the user interface 300 does not include at least one of the filter setting area 320, the source selection area 330, or the customization setting area 340.

[0086] In step S225, the processor 122 selects multiple historical wafer images based on conditions associated with the historical wafers.

[0087] In some embodiments, the filter setting area 320 has at least one block for receiving user-input conditions, such as time, similarity, yield, product type, or other conditions related to historical wafers.

[0088] For example, in the filter setting area 320, the I / O device 130 receives the user-input time condition "3 months ago". When the I / O device 130 detects that the search button 350 has been activated, the I / O device 130 sends a control signal to the server 120. The processor 122 selects a historical wafer image from the memory 121, where the corresponding historical wafer was manufactured by the machine 110 3 months ago.

[0089] For example, in the filter setting area 320, the I / O device 130 receives the similarity condition "60%" input by the user. When the I / O device 130 detects that the search button 350 has been activated, the I / O device 130 sends a control signal to the server 120. The processor 122 selects a historical wafer image from the memory 121, wherein the similarity of the historical wafer image is greater than 60%.

[0090] In some embodiments, the source selection area 330 has at least one block for receiving conditions input by the user, such as wafer type, wafer yield testing method, or other wafer type-related conditions.

[0091] For example, in the source selection area 330, the I / O device 130 receives the user-input condition "chip probe" for the method of testing yield. When the I / O device 130 detects that the search button 350 has been activated, the I / O device 130 sends a control signal to the server 120. The processor 122 selects a historical wafer image from the memory 121, where the historical wafer corresponding to the historical wafer image was tested by the machine 110 using chip probe.

[0092] In some embodiments, the customization setting area 340 has at least one block for receiving further conditions input by the user, such as details about the test wafer yield or other further conditions based on the conditions received by the filter setting area 320 or the source selection area 330.

[0093] For example, in the customization settings area 340, the I / O device 130 receives the user-input condition for the type of wafer yield test, "cantilever probe card". When the I / O device 130 detects that the search button 350 is activated, the I / O device 130 sends a control signal to the server 120. The processor 122 selects a historical wafer image from the memory 121, where the historical wafer corresponding to the historical wafer image was tested by the chip tester 110 using a cantilever probe card.

[0094] In some embodiments, the filter setting area 320, the source selection area 330, and the customization setting area 340 receive conditions entered by the user in the form of check boxes, lists, input boxes, or other receiving conditions.

[0095] For example, the filter setting area 320 receives the time condition "3 months ago" via an input box. The source selection area 330 receives the test yield method condition "chip test" via a checkbox. The customization setting area 340 receives the wafer yield type condition "cantilever probe card" via a list.

[0096] In some embodiments, conditions in the filter setting area 320, the source selection area 330, and the customization setting area 340 can be combined to enable the processor 122 to select a plurality of historical wafer images corresponding to those conditions.

[0097] For example, in the context of the filter setting area 320 receiving the time condition "3 months ago" and the source selection area 330 receiving the test yield method condition "chip test", the processor 122 selects a historical wafer image from the memory 121, wherein the historical wafer corresponding to the historical wafer image was manufactured by the machine 110 3 months ago and tested by the machine 110 using chip test.

[0098] In step S226, processor 122 executes a neural network to compare the target tensor with historical tensors to generate a similarity.

[0099] For example, processor 122 executes the trained neural network mentioned in method 200A to compare the target tensor [[1, 2, 3], [4, 5, 6], [7, 8, 9]] with the historical tensor [[0.1, 0.2, 0.3], [0.4, 0.5, 0.6], [0.7, 0.8, 0.9]], [[0.1, 0.2, 0.3], [0.4, 0.5, 0.6], [0.7, 0.8, 0]], and [[0, 0.9, 0.9], [0.2, 0.3, 0.3], [0.1, 0.4, 0.9]] to produce similarities of 100%, 88.89%, and 11.11%, respectively.

[0100] In step S227, the processor 122 selects multiple historical wafer images based on similarity.

[0101] For example, processor 122 selects historical wafer images with a similarity greater than 60%. Therefore, among the three historical training tensors mentioned above, processor 122 selects two historical wafer images corresponding to the historical tensors [[0.1, 0.2, 0.3], [0.4, 0.5, 0.6], [0.7, 0.8, 0.9]] and [[0.1, 0.2, 0.3], [0.4, 0.5, 0.6], [0.7, 0.8, 0]], because the historical similarity of the corresponding historical training tensors is 100% and 88.89%.

[0102] In some embodiments, the I / O device 130 displays historical wafer images selected by the processor 122 in the similar wafer image area 360 of the user interface 300.

[0103] In some embodiments, historical wafer images displayed in the similar wafer image area 360 are sorted according to their similarity. For example, a historical wafer image with 100% similarity is displayed on the left side of the similar wafer image area 360, a historical wafer image with 88.89% similarity is displayed in the middle of the similar wafer image area 360, and a historical wafer image with 61% similarity is displayed on the right side of the similar wafer image area 360.

[0104] In step S228, the processor 122 adjusts the parameters of the machine 110 or the manufacturing conditions (receipt) for manufacturing the wafer, and the machine 110 manufactures the wafer.

[0105] For example, processor 122 adjusts the temperature from 610°C to 600°C based on a manufacturing factor to manufacture a higher-quality wafer with fewer defects than before. The manufacturing factor is calculated by processor 122 by comparing the similarity between a target wafer image and historical wafer images. The manufacturing factor can be at least one of temperature, pressure, or other manufacturing factors related to wafer manufacturing. For example, processor 122 executes a neural network to calculate the similarity between the target wafer image and historical wafer images to determine that the temperature needs to be reduced from 610°C to 600°C to manufacture a higher-quality wafer with fewer defects than before.

[0106] For example, processor 122 adjusts the wafer cleaning step to after the annealing step based on the manufacturing factor.

[0107] In some embodiments, processor 122 generates a report related to at least one manufacturing factor.

[0108] For example, the report shows the changes in defective parts and yield associated with temperature changes (e.g., from 610°C to 600°C).

[0109] In some embodiments, the steps of method 200B do not include at least one of steps S225 or S228.

[0110] In some embodiments, processor 122 calculates each distance between the target tensor and each of the historical tensors to generate a similarity score.

[0111] In some embodiments, the processor 122 computes the inner product space between each of the target tensor and each of the historical tensors to generate similarity.

[0112] Figure 4 This is a block diagram illustrating a system 100 according to an embodiment of the present invention. Figure 1 Compared to system 100, Figure 4 The I / O device 130 is included in the machine base 110.

[0113] While the invention has been described in considerable detail with reference to certain embodiments thereof, other embodiments are possible. Therefore, the spirit and scope of the appended claims should not be limited to the physical description contained herein.

[0114] Those skilled in the art to which this invention pertains can make various modifications and alterations without departing from the principles and spirit of this invention. Therefore, this invention is intended to cover various modifications and variations thereof, provided that such modifications and variations fall within the scope of the following claims.

[0115] [Symbol Explanation] 100: System 110: Machine 120: Server 121: Memory 122: Processor 130: Input / Output Device 200A: Method S211: Steps S212: Steps S213: Steps S214: Steps S215: Steps S216: Steps S217: Steps S218: Steps 200B: Method S221: Steps S222: Steps S223: Steps S224: Steps S225: Steps S226: Steps S227: Steps S228: Steps 300: User Interface 310: Target wafer imaging area 320: Filter settings area 330: Source Selection Area 340: Customization Settings Area 350: Search button 360: Similar wafer image area.

Claims

1. A method of manufacturing a wafer, characterized by, comprising: enhancing, by a processor, at least one defect portion of a target wafer image; performing, by the processor, an image processing operation on the at least one defect portion; adjusting, by the processor, a size of the target wafer image; comparing, by the processor, a target tensor based on the target wafer image with a plurality of historical tensors of a plurality of historical wafer images to generate a plurality of similarities; and selecting, by the processor, a plurality of historical wafer images of the plurality of historical wafer images according to the plurality of similarities between the target tensor and the plurality of historical tensors to adjust at least one parameter of a machine used to manufacture at least one wafer. further comprising:

2. The method of claim 1, wherein, removing, by the processor, a plurality of noises of the target wafer image. further comprising:

3. The method of claim 1, wherein, selecting, by the processor, the plurality of historical wafer images of the plurality of historical wafer images according to a plurality of conditions related to a plurality of historical wafers. wherein comparing, by the processor, the target tensor with the plurality of historical tensors comprises calculating each of a plurality of distances between the target tensor and each of the plurality of historical tensors to generate the plurality of similarities.

4. The method of claim 1, wherein, wherein comparing, by the processor, the target tensor with the plurality of historical tensors comprises calculating each of a plurality of inner product spaces between the target tensor and each of the plurality of historical tensors to generate the plurality of similarities.

5. The method of claim 1, wherein, further comprising:

6. The method of claim 1, wherein, ranking, by the processor, the plurality of historical wafer images according to the plurality of similarities. further comprising:

7. The method of claim 1, wherein, summarizing, by the processor, at least one manufacturing factor corresponding to the at least one defect portion to generate a report related to the at least one manufacturing factor. further comprising:

8. The method of claim 1, wherein, generating, by the processor, the target tensor according to the target wafer image. comprising:

9. A method of manufacturing a wafer, characterized by, collecting, by a processor, a plurality of historical wafer images of a machine, wherein each of the plurality of historical wafer images corresponds to at least one defect portion; segmenting, by the processor, the plurality of historical wafer images into a plurality of historical target wafer images and a plurality of historical training wafer images; generating, by the processor, a plurality of historical target tensors and a plurality of historical training tensors; training, by the processor, a neural network according to the plurality of historical target wafer images and the plurality of historical training wafer images; wherein each of the plurality of historical target tensors and each of the plurality of historical training tensors has at least one defect tensor corresponding to the at least one defect portion enhanced by the processor; performing, by the processor, the neural network to generate a plurality of historical similarities; wherein the plurality of historical similarities are related to a relationship between the plurality of historical target tensors and the plurality of historical training tensors; and selecting, by the processor, a plurality of historical wafer images of the plurality of historical wafer images according to the plurality of historical similarities to display on a user interface of an input / output device. further comprising:

10. The method of claim 9, wherein, performing, by the processor, an image processing operation to remove a plurality of noises of the plurality of historical target wafer images and the plurality of historical training wafer images. further comprising:

11. The method of claim 9, wherein, ​ normalizing, by the processor, the plurality of historical target tensors and the plurality of historical training tensors such that the plurality of historical target tensors and the plurality of historical training tensors are between 0 and 1.

12. The method of claim 9, wherein, wherein performing, by the processor, the neural network comprises comparing the plurality of historical target tensors and the plurality of historical training tensors to generate the plurality of historical similarities.

13. A system for manufacturing a wafer, the system comprising: comprising: a machine tool for manufacturing at least one wafer; and a server coupled to the machine tool, comprising: a processor configured to: collect, from the machine tool, a target wafer image having at least one defective portion; perform an image processing operation on the at least one defective portion of the target wafer image; perform a neural network to compare a target tensor based on the target wafer image with a plurality of historical tensors based on a plurality of historical wafer images to generate a plurality of similarities; and select, based on the target tensor and the plurality of historical tensors of the plurality of historical wafer images, a plurality of historical wafer images of the plurality of historical wafer images, wherein each of the plurality of historical wafer images corresponds to at least one manufacturing factor.

14. The system of claim 13, wherein, wherein the processor is further configured to resize the target wafer image.

15. The system of claim 13, wherein, wherein the processor is further configured to perform the neural network to generate the target tensor based on the target wafer image.

16. The system of claim 13, wherein, further comprising: an input / output device configured to display, based on the plurality of similarities, a user interface related to the plurality of historical wafer images of the plurality of historical wafer images.

17. The system of claim 13, wherein, wherein the processor is further configured to rank the plurality of historical wafer images based on the plurality of similarities.

18. The system of claim 13, wherein, wherein the processor is further configured to generate a report related to the at least one manufacturing factor.

19. The system of claim 13, wherein, wherein the processor is further configured to adjust at least one parameter of the machine tool to manufacture the at least one wafer or to adjust a plurality of manufacturing conditions to manufacture the at least one wafer.

20. The system of claim 13, wherein, wherein the plurality of historical wafer images correspond to at least one of the machine tool and a plurality of other machine tools.

Images