Storage device

Abstract

Embodiments provide a storage device capable of storing data with high precision. According to one embodiment, a memory device includes a first memory cell, a first wiring, a second wiring, a first switch, a third wiring, a second switch, a fourth wiring, a first transistor, a third switch, and a sense amplifier circuit. The first memory cell includes a first magnetoresistive effect element and a first switching element connected to the first magnetoresistive effect element. The first wiring is connected to a first end of the first memory cell. The second wiring is connected to a second end of the first memory cell. The first switch has a third end and a fourth end connected to the second wiring. The third wiring is connected with the fourth end. The second switch has a fifth end and a sixth end connected to the third wiring. The fourth wiring is connected with the sixth end. The first transistor has a gate connected to the third wiring, and a seventh end connected to the fourth wiring. The third switch is connected between the seventh end and a first node receiving the first voltage. The sense amplifier circuit is connected to the fourth wiring.

Description

Technical Field

[0001] The implementation generally relates to a storage device. Background Technology

[0002] Storage devices that use magnetoresistive elements are known to exist. Summary of the Invention

[0003] The technical problem to be solved by the present invention is to provide a storage device capable of storing data with high precision.

[0004] A storage device according to one embodiment includes a first storage cell, a first wiring, a second wiring, a first switch, a third wiring, a second switch, a fourth wiring, a first transistor, a third switch, and a sense amplifier circuit. The first storage cell includes a first magnetoresistive element and a first switch element connected to the first magnetoresistive element. The first wiring is connected to a first terminal of the first storage cell. The second wiring is connected to a second terminal of the first storage cell. The first switch has a third terminal and a fourth terminal connected to the second wiring. The third wiring is connected to the fourth terminal. The second switch has a fifth terminal and a sixth terminal connected to the third wiring. The fourth wiring is connected to the sixth terminal. The first transistor has a gate connected to the third wiring and a seventh terminal connected to the fourth wiring. The third switch is connected between the seventh terminal and a first node receiving a first voltage. The sense amplifier circuit is connected to the fourth wiring. Attached Figure Description

[0005] Figure 1 Functional blocks representing the storage device in the first embodiment.

[0006] Figure 2 This represents a functional block representing the core circuitry of the storage device in the first embodiment.

[0007] Figure 3 The components of the GWL selector and GBL selector of the storage device in the first embodiment, and the connections of the components, are shown.

[0008] Figure 4 Functional blocks representing the sub-core circuitry of the storage device in the first embodiment.

[0009] Figure 5 The components of the WL selector and BL selector of the storage device in the first embodiment, and the connections of the components, are shown.

[0010] Figure 6 This is a perspective view of a portion of the storage cell array of the storage device according to the first embodiment.

[0011] Figure 7A cross section showing an example of the construction of a storage cell in the storage device of the first embodiment.

[0012] Figure 8 Examples illustrating the voltage and current characteristics of the storage cells of the storage device according to the first embodiment.

[0013] Figure 9 This describes the constituent elements of the conversion circuit of the storage device according to the first embodiment, as well as the connections and associated constituent elements.

[0014] Figure 10 Examples of the constituent elements and connections of the readout circuit of the storage device according to the first embodiment are shown.

[0015] Figure 11 This shows the layout of a portion of the storage device according to the first embodiment.

[0016] Figure 12 Several signals and wiring potentials during data readout of the storage device of the first embodiment are shown along time.

[0017] Figure 13 The components of the read amplifier circuit of the storage device in a modified example of the first embodiment and the connections of the components are shown.

[0018] Figure 14 Several signals and wiring potentials during data readout of the storage device of the second embodiment are shown along time.

[0019] Figure 15 Several signals and wiring potentials during data readout of the storage device of the third embodiment are shown along time. Detailed Implementation

[0020] Hereinafter, embodiments will be described with reference to the accompanying drawings. In some embodiments or different embodiments, multiple constituent elements having substantially the same function and structure may sometimes have additional numbers or text appended to the end of the reference numerals in the accompanying drawings to distinguish them from each other.

[0021] In subsequent embodiments of a previously described embodiment, the differences from the previously described embodiment are mainly described. A description of a particular embodiment, unless explicitly or obviously excluded, also applies to the description of other embodiments.

[0022] In this specification and claims, a first element being "connected to" another second element includes cases where the first element is directly, or always, or selectively connected to the second element via an element that is conductive.

[0023] The implementation method is described below using a three-dimensional orthogonal coordinate system. The direction of the x-axis is called the X-direction. The direction opposite to the X-direction is called the -X-direction. The direction of the y-axis is called the Y-direction. The direction opposite to the Y-direction is called the -Y-direction. The direction of the z-axis is called the Z-direction, with "up" referring to the Z-direction. The direction opposite to the Z-direction is called the -Z-direction, with "down" referring to the -Z-direction.

[0024] 1. First Implementation Method

[0025] 1.1. Composition (Structure)

[0026] Figure 1 Functional blocks representing the storage device of the first embodiment. The storage device 1 includes a core circuit 111, an input / output circuit 12, a control circuit 13, a decoding circuit 14, a page buffer 15, and a voltage generation circuit 16.

[0027] The core circuit 11 is a circuit that includes multiple memory cells MC and wiring and circuitry for accessing the memory cells MC.

[0028] Input / output circuit 12 is a circuit for inputting and outputting data and signals. Input / output circuit 12 receives control signals CNT, instructions CMD, address information ADD, and data DAT from an external source of storage device 1, such as a memory controller. Input / output circuit 12 outputs data DAT.

[0029] Control circuit 13 receives instruction CMD and control signal CNT from input / output circuit 12. Based on the control indicated by instruction CMD and control signal CNT, control circuit 13 controls core circuit 11, controlling the reading of data from memory cell MC and the writing of data to memory cell MC. Control circuit 13 also controls voltage generation circuit 16 based on the control indicated by instruction CMD and control signal CNT.

[0030] Decoding circuit 14 is a circuit that decodes address information ADD. Decoding circuit 14 receives address information ADD from input / output circuit 12. Decoding circuit 14 decodes address information ADD and, based on the decoding result, generates a signal for selecting the storage unit MC of the object to be read from or written to. The generated signal is sent to core circuit 11.

[0031] Page buffer 15 is a circuit that temporarily stores data of a certain size. Page buffer 15 receives data DAT written to the memory cell MC from the input / output circuit 12, temporarily stores the data, and transmits the data to the core circuit 11. Page buffer 15 receives data read from the memory cell MC, temporarily stores the read data, and transmits the data DAT to the input / output circuit 12.

[0032] During the writing of data to the memory cell MC, the voltage generation circuit 16 supplies the voltage for data writing to the core circuit 11. During the reading of data from the memory cell MC, the voltage generation circuit 16 supplies the voltage for data reading to the core circuit 11.

[0033] Figure 2 Functional blocks representing the core circuitry of the storage device in the first embodiment. For example... Figure 2 As shown, the core circuit 11 includes multiple sub-core circuits SCC, multiple global word lines GWL, multiple global bit lines GBL, GWL selector GWS, GBL selector GBS, conversion circuit group CCS, wiring FWL, wiring FBL, write circuit 18 and read circuit 19.

[0034] Each sub-core circuit (SCC) is a group of multiple components, including multiple memory cells (MC), multiple selectors, and multiple wirings. Each SCC is connected to one global word line (GWL) and one global bit line (GBL).

[0035] Each global word line (GWL) is connected to multiple sub-core circuits (SCC). Each global bit line (GBL) is connected to multiple sub-core circuits (SCC).

[0036] The GWL selector (GWS) is a circuit that selects one of a plurality of global word lines (GWLs). Each GWL selector (GWS) receives address information ADD or a signal based on address information ADD, and connects one of the global word lines (GWLs) determined by the received address information ADD or the signal based on address information to the wiring FWL.

[0037] The GBL selector (GBS) is a circuit that selects one of a plurality of global bit lines (GBLs). Each GBL selector (GBS) receives address information (ADD) or a signal based on address information (ADD), and connects one of the global bit lines (GBLs) determined by the received address information (ADD) or the signal based on address information to the wiring (FBL).

[0038] A conversion circuit group (CCS) is a group of circuits that convert current into voltage. The CCS is connected between the wiring FBL and the global bit line GBL. The CCS applies a voltage to the wiring FBL based on the magnitude of the current flowing through the global bit line GBL.

[0039] The write circuit 18 is a circuit that controls the writing of data to the memory cell MC. The write circuit 18 receives write data DAT from the input / output circuit 12 and receives the voltage for data writing from the voltage generation circuit 16. Based on the control of the control circuit 13 and the write data DAT, the write circuit 18 supplies the voltage and current for data writing to the wiring FWL and FBL.

[0040] The readout circuit 19 is a circuit that controls the reading of data from the storage cell MC. The readout circuit 19 receives a voltage for data reading from the voltage generation circuit 16. Based on the control of the control circuit 13, the readout circuit 19 uses the voltage for data reading to determine the data stored in the storage cell MC. The determined data is supplied to the input / output circuit 12 as readout data DAT. The readout circuit 19 includes multiple sense amplifier circuits SAC. Each sense amplifier circuit SAC is a circuit that uses a voltage based on the data stored in the storage cell MC to be read out, and outputs the data determined to be stored in the storage cell MC to be read out. Details regarding the sense amplifier circuits SAC will be described later.

[0041] Figure 3 This describes the components and connections of the GWL selector and GBL selector of the storage device in the first embodiment. (Example:) Figure 3 As shown, the GWL selector GWS includes the same number of switches GWSW as the number of sub-core circuits SCC connected to each global word line GBL. Each switch GWSW is connected to a wiring FWL at one end and to a global word line GWL at the other end. Each switch GWSW is a p-type or n-type MOSFET, or a combination of p-type and n-type MOSFETs connected in parallel and receiving complementary signals in their respective gates. The description of the switch GWSW also applies to the switches GWSW, WSW, BSW, SW1, SW2, SW3, SW4, SW5, SW6, SW11, and SW12 described later. Each switch GWSW is turned on or off by the control of the read circuit 19 or write circuit 18 based on address information ADD or a signal based on address information.

[0042] The GBL selector (GBS) contains the same number of switches (GBSW) as the number of sub-core circuits (SCCs) connected to each global word line (GWL). Each GBSW is connected to a wiring FBL at one end and to one global bit line (GBL) at the other end. Each GBSW is turned on or off by the control of the read circuit 19 or write circuit 18 based on address information ADD or a signal based on address information.

[0043] The conversion circuit group CCS contains the same number of conversion circuits CC as the number of sub-core circuits SCC connected to each global word line GWL. Each conversion circuit CC is connected between the wiring FBL and one global bit line GBL. Each conversion circuit CC applies a voltage to the global bit line GBL connected to it based on the magnitude of the current flowing in the wiring FBL to which it is connected.

[0044] Figure 4 Functional blocks representing the sub-core circuitry of the storage device in the first embodiment. For example... Figure 4As shown, each sub-core circuit SCC includes a memory cell array MCA, multiple word lines WL, multiple bit lines BL, WL selector WS, BL selector BS, global word line GWL, and global bit line GBL.

[0045] A memory cell array (MCA) is a collection of multiple memory cells (MCs) arranged in a row. Each memory cell (MC) stores data non-volatilely. Word lines (WL) and bit lines (BL) are also located within the MCA. The following description is based on the example where the word line (WL) is associated with a row and the bit line (BL) is associated with a column. The names WL and BL are simply used to distinguish between the two types of wiring; they can also have opposite names. Each memory cell (MC) is connected to one word line (WL) and one bit line (BL). A memory cell (MC) is determined by selecting one row and one column.

[0046] Each word line (WL) is connected to multiple memory cells (MC). Each bit line (BL) is connected to multiple memory cells (MC). Each memory cell (MC) contains one MTJ element (MTJ) and one switching element (SE). In each memory cell (MC), the MTJ element (MTJ) and the switching element (SE) are connected in series. The switching element (SE) of each memory cell (MC) is connected to one word line (WL). The MTJ element (MTJ) of each memory cell (MC) is connected to one bit line (BL).

[0047] An MTJ element is a device that exhibits the tunneling magnetoresistive effect and includes, for example, a magnetic tunnel junction (MTJ). MTJ elements are also known as magnetoresistive effect devices. An MTJ element is a variable resistance device capable of switching between a low-resistance state and a high-resistance state. An MTJ element can store 1 bit of data using the difference between the two resistance states. In one example, an MTJ element stores "0" data in a low-resistance state and "1" data in a high-resistance state.

[0048] The switching element SE has two terminals and is used to electrically connect or disconnect the two terminals. When the voltage applied between the two terminals along a first direction is less than a certain threshold voltage, the switching element SE is in a high-resistance state, for example, a non-conducting state (off state). When the voltage applied between the two terminals rises above the threshold voltage, the switching element SE becomes a low-resistance state, for example, a conducting state (on state). When the voltage applied between the two terminals of the switching element SE in the low-resistance state decreases and becomes less than the threshold voltage, the switching element SE becomes a high-resistance state. The switching element SE also has the same function in a second direction opposite to the first direction, switching between high-resistance and low-resistance states based on the magnitude of the voltage applied in the first direction. That is, the switching element SE is a bidirectional switching element. By turning the switching element SE on or off, the presence or absence of current supply to the MTJ element MTJ connected to the switching element SE can be controlled, i.e., the selection or non-selection of the MTJ element MTJ.

[0049] Each WL selector (WS) is a circuit that selects one of a plurality of word lines (WL). Each WL selector (WS) receives address information ADD or a signal based on address information ADD, and connects one of the multiple word lines (WL) determined by the received address information ADD or the signal based on address information ADD to a global word line (GWL).

[0050] Each BL selector BS is a circuit that selects one of multiple bit lines BL. Each BL selector BS receives address information ADD or a signal based on address information ADD, and connects one bit line BL, determined by the received address information ADD or the signal based on address information ADD, to a global bit line GBL.

[0051] Figure 5 This describes the constituent elements of the WL selector and BL selector of the storage device in the first embodiment, and the connections between these constituent elements. For example... Figure 5 As shown, the WL selector WS includes the same number of switches WSW as the number of memory cells MC connected to each bit line BL. Each switch WSW is connected to the global word line GWL at one end and to one word line WL at the other end. Each switch WSW is turned on or off by the control of the readout circuit 19 based on the address information ADD or a signal based on the address information ADD.

[0052] The BL selector BS contains the same number of switches BSW as the number of memory cells MC connected to each word line WL. Each switch BSW is connected to the global bit line GBL at one end and to one bit line BL at the other end. Each switch BSW is turned on or off by the readout circuit 19 controlled by a signal based on address information ADD or address information ADD.

[0053] exist Figure 2 , Figure 3 , Figure 4 and Figure 5 In the example, core circuit 11 has two levels. The bottommost first level contains... Figure 4 The diagram shows a group of memory cells MC, word lines WL, bit lines BL, WL selectors WS, and BL selectors BS. The second level includes... Figure 2 The configuration shown is a group of sub-core circuit SCC, global word line GWL, global bit line GBL, GWL selector GWS, and GBL selector GBS.

[0054] The core circuit 11 can also have more than three levels. By turning on the selector switches in each level, a word line WL is connected to the write circuit 18 and the read circuit 19. Similarly, by turning on the selector switches in each level, a bit line BL is connected to the write circuit 18 and the read circuit 19.

[0055] Figure 6 This is a perspective view of a portion of the storage cell array of the storage device according to the first embodiment. Figure 6 As shown, multiple conductors 21 and multiple conductors 22 are provided.

[0056] The conductors 21 have a straight line shape, extend in the X direction, and are arranged in the Y direction. Each conductor 21 functions as at least part of a word line WL.

[0057] Conductor 22 is located further in the Z direction than conductor 21. Conductor 22 has a straight shape, extends in the Y direction, and is arranged in the X direction. Each conductor 22 functions as at least part of a bit line BL.

[0058] A memory cell MC is disposed at the intersection of conductor 21 and conductor 22. The memory cells MC are arranged in a matrix along the xy plane formed by the X and Y directions. Each memory cell MC includes a structure that functions as a switching element SE and a structure that functions as a MTJ element MTJ. The structure that functions as a switching element SE and the structure that functions as a MTJ element MTJ each include one or more layers. For example, the structure that functions as a MTJ element MTJ is located on the upper surface of the structure that functions as a switching element SE. The lower surface of the memory cell MC is in contact with the upper surface of one conductor 21. The upper surface of the memory cell MC is in contact with the lower surface of one conductor 22.

[0059] Figure 7This is a cross-section showing an example of the construction of a storage cell in the storage device of the first embodiment. The switching element SE includes a variable resistive material 32. The variable resistive material 32 is a material that dynamically exhibits variable resistance, for example, having a layered shape. The variable resistive material 32 is a two-terminal switching element, where the first terminal is one of the upper and lower surfaces of the variable resistive material 32, and the second terminal is the other of the upper and lower surfaces. When the voltage applied between the two terminals is less than a certain threshold voltage, the variable resistive material is in a "high resistance" state, for example, a non-conductive state. When the voltage applied between the two terminals rises to above the threshold voltage, the variable resistive material becomes a "low resistance" state, for example, a conductive state. When the voltage between the two terminals of the variable resistive material 32 in the low resistance state decreases to below the threshold voltage, the variable resistive material becomes a high resistance state.

[0060] In one example, the variable resistor material 32 comprises an insulator and dopants introduced into the insulator via ion implantation. The insulator may comprise, for example, an oxide, a material comprising SiO2, or substantially SiO2. The dopants may comprise, in one example, arsenic (As) or germanium (Ge). The description of "substantially constitutes" and similar descriptions mean that the constituent elements that "substantially constitute" are permitted to contain undesirable impurities.

[0061] The switching element SE may also include a lower electrode 31 and an upper electrode 33. Figure 7 This illustrates an example where the variable resistive material 32 is located on the upper surface of the lower electrode 31, and the upper electrode 33 is located on the upper surface of the variable resistive material 32.

[0062] The MTJ element includes a ferromagnetic layer 35, an insulating layer 36, and a ferromagnetic layer 37. For example, ... Figure 7 As shown, insulating layer 36 is located on the upper surface of ferromagnetic layer 35, and ferromagnetic layer 37 is located on the upper surface of insulating layer 36.

[0063] Ferromagnetic layer 35 is a layer of ferromagnetic material. Ferromagnetic layer 35 has an easy magnetization axis along the interface penetrating ferromagnetic layer 35, insulating layer 36, and ferromagnetic layer 37. In one example, the easy magnetization axis has an angle of 45° or more and 90° or less relative to the interface; in another example, it has an easy magnetization axis perpendicular to the interface. The orientation of magnetization of ferromagnetic layer 35 remains unchanged even when data is read from and written to the storage cell MC. Ferromagnetic layer 35 can function as a so-called reference layer RL. Ferromagnetic layer 35 may also comprise multiple layers. Hereinafter, ferromagnetic layer 35 is sometimes referred to as reference layer RL.

[0064] Insulating layer 36 is a layer of insulator. Insulating layer 36 may contain, for example, magnesium oxide (MgO), or be substantially composed of MgO, and functions as a so-called tunnel barrier (TB).

[0065] The ferromagnetic layer 37 is a layer of material exhibiting ferromagnetism. The ferromagnetic layer 37 may contain, for example, cobalt iron boron (CoFeB) or iron boride (FeB), or be substantially composed of CoFeB or FeB. The ferromagnetic layer 37 has an easy magnetization axis along the interface penetrating the ferromagnetic layer 35, the insulating layer 36, and the ferromagnetic layer 37. In one example, the easy magnetization axis has an angle of 45° or more and 90° or less relative to the interface; in another example, it has an easy magnetization axis along a direction orthogonal to the interface. The orientation of the magnetization of the ferromagnetic layer 37 can be varied by writing data to the memory cell MC, and the ferromagnetic layer 37 can function as a so-called memory layer (SL). Hereinafter, the ferromagnetic layer 37 is sometimes referred to as the memory layer SL.

[0066] When the magnetization direction of the storage layer SL is parallel to the magnetization direction of the reference layer RL, the MTJ element has a relatively low resistance. When the magnetization direction of the storage layer SL is antiparallel to the magnetization direction of the reference layer RL, the MTJ element has a higher resistance than when the magnetization direction of the storage layer SL is antiparallel to the magnetization direction of the reference layer RL.

[0067] When a current of magnitude Icp or greater flows from the storage layer SL toward the reference layer RL, the magnetization orientation of the storage layer SL is parallel to that of the reference layer RL. When a current of magnitude Icap or greater flows from the reference layer RL toward the storage layer SL, the magnetization orientation of the storage layer SL is antiparallel to that of the reference layer RL.

[0068] MTJ components can also contain further layers.

[0069] Figure 8 This is an example illustrating the voltage and current characteristics of the storage cells in the storage device of the first embodiment. The horizontal axis of the graph represents the magnitude of the terminal voltage (i.e., the potential difference between the two ends) of the storage cell MC. The vertical axis of the graph represents the magnitude of the current flowing through the storage cell MC on a logarithmic scale. Figure 8 Dashed lines represent virtual characteristics that do not actually occur. Figure 8 This indicates the state of the memory cell MC when it is in a low resistance state and the state when it is in a high resistance state.

[0070] As the voltage increases from 0, the current continues to increase until it reaches the threshold voltage Vth. Before the voltage reaches the threshold voltage Vth, the switching element SE of the memory cell MC is open, i.e., non-conductive.

[0071] If the voltage increases further and reaches the threshold voltage Vth, i.e., point A, the relationship between voltage and current exhibits a discontinuous change, displaying the characteristics shown at points B1 and B2. The current magnitudes at points B1 and B2 are much greater than the current magnitude at point A. This rapid change in current is based on the switching element SE of the memory cell MC being turned on. The current magnitudes at points B1 and B2 depend on the resistance state of the MTJ element MTJ in the memory cell MC.

[0072] If the voltage decreases from the state where the switching element SE is turned on, for example from the state shown by the relationship between voltage and current at point B1 or B2 and points with higher voltages than them, then the current continues to decrease.

[0073] If the voltage decreases further to a certain level, the voltage-current relationship becomes discontinuous. The voltage at which this discontinuity begins depends on the terminal voltage of the MTJ element in the memory cell MC, i.e., whether the MTJ element is in a high-resistance or low-resistance state. When the MTJ element is in a low-resistance state, the voltage-current relationship becomes discontinuous from point C1. When the MTJ element is in a high-resistance state, the voltage-current relationship becomes discontinuous from point C2. The voltage-current relationship exhibits the characteristics shown at points D1 and D2 at points C1 and C2, respectively. The current magnitudes at points D1 and D2 are much smaller than the current magnitudes at points C1 and C2, respectively. This abrupt change in current is due to the opening of the switching element SE in the memory cell MC.

[0074] The terminal voltage at point D1 of the memory cell MC of an MTJ element that includes a low resistance state is called the low holding voltage VhdL. The terminal voltage at point D2 of the memory cell MC of an MTJ element that includes a high resistance state is called the high holding voltage VhdH.

[0075] Figure 9 This describes the components of the conversion circuit of the storage device according to the first embodiment, the connections between the components, and the associated components. Figure 9 This represents an example of Q+1 global bit lines GBL_0 to GBL_Q.

[0076] Each conversion circuit CC includes an n-type MOSFET Tr1 and a switch SW1. Transistor Tr1 and switch SW1 are connected in series between the wiring FBL and the node receiving the ground voltage VSS. The gate of transistor Tr1 is connected to a global bit line GBL. Switch SW1_0 receives signal S1_0. Switch SW1_0 is turned on or off according to signal S1_0. Similarly, for all integers α greater than 1 and less than Q, switch SW1_α receives signal S1_α. Switch SW1_α is turned on or off according to signal S1_α. Signals S1_0 to S1_Q are supplied from the readout control circuit RCC. The readout control circuit RCC is included in the readout circuit 19.

[0077] When switch SW1 receives a high-level or "H" level signal S1, it is in the ON state, maintaining an electrical connection between one end of switch SW1 and the other end. When switch SW1 receives a low-level or "L" level signal S1, it is in the OFF state, maintaining an electrical disconnect between one end of switch SW1 and the other end.

[0078] Let n be an integer greater than or equal to 2. The same applies to the switch SWn and signal Sn described later. That is, for switch SWn, the description of switch SW1 is replaced with the description of switch SWn, and for signal Sn, the description of signal S1 is replaced with the description of signal Sn.

[0079] For all integers where α is greater than or equal to 0 and less than or equal to Q, the readout control circuit RCC maintains the signal S1_α at a high level during data readout when the address information ADD specifies the global bit line GBL_α.

[0080] Figure 10 This illustrates the constituent elements of the readout circuit of the storage device according to the first embodiment, and an example of the connections between these elements. Furthermore, as an example, Figure 10 The diagram also shows a storage unit MC for a data read object and the components associated with that storage unit MC. Hereinafter, the storage unit MC for the data read or data write object is sometimes referred to as the selected storage unit MC_s.

[0081] The switch GBSW used to connect the selected memory cell MC_s to the wiring FBL is called switch GBSW_s. Sometimes the signal received by switch GBSW at the control terminal is called signal SGB, and the signal received by switch GBSW_s at the control terminal is called signal SGB_s.

[0082] The readout circuit 19 also includes switches SW2, SW3, SW4, SW5 and SW6, an n-type MOSFET Tr2, and a readout amplifier circuit SAC.

[0083] Switch SW2 is connected between the node receiving the pre-charge voltage VPRCH and wiring FBL. In one example, the pre-charge voltage VPRCH is supplied from voltage generation circuit 16. The pre-charge voltage VPRCH is higher than the ground voltage VSS.

[0084] Switch SW3 is connected between wiring FBL and the node receiving a certain amount of non-selective voltage VUSEL. In one example, the non-selective voltage VUSEL is supplied from voltage generation circuit 16. The non-selective voltage VUSEL has a height between ground voltage VSS and pre-charge voltage VPRCH. In one example, the non-selective voltage VUSEL has a height of half the pre-charge voltage VPRCH.

[0085] Transistor Tr2 is connected at one end to a node receiving a voltage Vhh at a certain positive height. Voltage Vhh is the internal power supply voltage of storage device 1, and in one example, it is lower than the power supply voltage VDD. In one example, voltage Vhh is supplied from voltage generation circuit 16. Transistor Tr2 receives a voltage Vload at its gate at a certain positive height, and voltage Vload is higher than the ground voltage VSS. In one example, voltage Vload is supplied from voltage generation circuit 16. Transistor Tr2 receives a constant current at its other end based on the magnitude of voltage Vhh and voltage Vload.

[0086] Switch SW4 is connected between the other end of transistor Tr2 and wiring FBL.

[0087] The sense amplifier circuit SAC, based on the supplied voltage, outputs data OUT stored in the selected memory cell MC_s of the data read object. In one example, the sense amplifier circuit SAC includes an operational amplifier OP. The non-inverting input of the operational amplifier OP is connected to wiring FBL. The inverting input of the operational amplifier OP receives a voltage VREF of a certain magnitude. In one example, the voltage VREF has a height between the high holding voltage VhdH and the low holding voltage VhdL.

[0088] Switch SW5 is connected between the wiring FWL and the node receiving the non-selective voltage VUSEL. Switch SW6 is connected between the wiring FWL and the node receiving the ground voltage VSS.

[0089] Read out the RCC output signals S2, S3, S4, S5 and S6 of the control circuit.

[0090] Figure 11 This shows the layout of a portion of the storage device according to the first embodiment. For example... Figure 11 As shown, the storage device 1 includes a substrate 41. The substrate 41 extends along the xy plane. The storage device 1 includes regions 42_1 and 42_2.

[0091] Region 42_1 includes multiple source / drain regions 43_1 and multiple conductors 45_1. The source / drain regions 43_1 have various sizes and shapes. The conductors 45_1 have various sizes and shapes. The source / drain regions 43_1 are irregularly arranged. The portion of each source / drain region 43_1 that overlaps with a conductor 45_1 functions as a transistor TR_1. In one example, transistor TR_1 is a transistor in a sense amplifier circuit SAC.

[0092] Region 42_2 includes multiple source / drain regions 43_2 and multiple conductors 45_2. The source / drain regions 43_2 and conductors 45_2 are arranged regularly. Figure 11 In this example, the source / drain regions 43_2 have the same size or a multiple of the reference size and are arranged in a matrix. The conductors 45_2 are also regularly configured. Figure 11 In the example, conductors 45_2 have the same size in the Y direction and are arranged in the X direction.

[0093] The portions of each source / drain region 43_2 and conductor 45_2 that overlap with the source / drain region 43_2 function as transistors TR_2. In one example, transistor TR_2 is switches GWSW, GBSW, WSW, and BSW. In another example, transistor TR_2 is transistor Tr1 and switch SW1. That is, the switching circuit CC is located in region 42_2.

[0094] Region 42_2 does not include source / drain regions and conductors of the irregular shape, size and / or configuration of Region 42_1.

[0095] 1.2. Actions

[0096] Figure 12 The potentials of several signals and wirings during the data readout period of the storage device of the first embodiment are represented along time. Figure 12 This indicates the selected storage unit MC_s of a data read object. That is, the switches BSW, WSW, and GWSW connected to the selected storage unit MC_s are in [the selected state]. Figure 12 The connection is established during the indicated period. Data reading begins when the selected storage unit MC_s of the selected data read object is selected. Figure 12 The actions during the period shown.

[0097] exist Figure 12 Throughout the entire period shown, the selected storage unit MC_s of the selected data read object is used; therefore, in Figure 12Throughout the entire period shown, signal SB_s is at a high level. Signal SB_s is the signal that turns switch BSW, which is connected to the select bit line BL_s, on or off. Select bit line BL_s is the bit line BL connected to the select memory cell MC_s. The high-level signal SB_s, in... Figure 12 Throughout the period shown, the selection bit line BL_s is connected to one global bit line GBL via the on switch BSW. Hereinafter, the global bit line GBL connected to the selection bit line BL_s via the on switch BSW is sometimes referred to as the selection global bit line GBL_s.

[0098] exist Figure 12 Throughout the period shown, the signal SGB_ns is low. The signal SGB_ns is the signal that turns the switch GBSW_ns, which is connected to the global bit line GBL other than the global bit line GBL_s, on or off. Hereinafter, the global bit line GBL other than the global bit line GBL_s is sometimes referred to as the non-select global bit line GBL_ns. With the low-level signal SGB_ns, the switch GBSW_ns is turned off, thus... Figure 12 During the period shown, the non-selected global bit line GBL_ns is cut off from the wiring FBL.

[0099] exist Figure 12 Throughout the period shown, signal S1_ns is at a low level. Signal S1_ns is the signal S1 supplied to switch SW1 in the conversion circuit CC, which is connected to the non-select global bit line GBL_ns.

[0100] At time t1, signal S1_s is low. Signal S1_s is the signal S1 supplied to switch SW1 in the conversion circuit CC connected to the global bit line GBL_s. The low-level signal S1_s disconnects switch SW1 in the conversion circuit CC connected to the global bit line GBL_s.

[0101] At time t1, signals S2, S4, and S6 are at a low level, while signals S3 and S5 are at a high level. Therefore, switches SW2, SW4, and SW6 are open, and switches SW3 and SW5 are closed.

[0102] At time t1, signal SGB_s is low. Signal SGB_s is the signal that turns switch GBSW_s on or off, connected to the global bit line GBL of the on switch BSW. With the low-level signal SGB_s, switch GBSW_s is off.

[0103] With switch SW2 open and switch SW3 closed, wiring FBL receives the non-selection voltage VUSEL. Therefore, the potential of the select bit line BL_s (selection bit line potential) VBL has the non-selection potential VUSEL. The non-selection potential VUSEL is a potential of magnitude obtained by the wiring receiving the non-selection voltage VUSEL, and in one example, has substantially the same height as the non-selection voltage VUSEL.

[0104] With switch SW6 open and switch SW5 closed, wiring FWL receives the non-selection voltage VUSEL. As a result, the potential (selection word line potential) VWL of the word line (selection word line) WL connected to the selected memory cell MC_s has the non-selection potential VUSEL.

[0105] At time t2, the signal SGB_s is set to high. This selects the global bit line GBL_s to be connected to the wiring FBL.

[0106] At time t2, signal S2 is set to high and signal S3 is set to low. This turns switch SW2 on and switch SW3 off. Therefore, from time t2, the selected bit line potential VBL rises to the precharge potential VPRCH. The precharge potential VPRCH is the potential of the wiring when a precharge voltage VPRCH is applied; in one example, it has a height substantially the same as the precharge voltage VPRCH.

[0107] At time t3, signal S2 is set to low. Consequently, switch SW2 is opened, and wiring FBL, the global selection bit line GBL_s, and the selection bit line BL_s are electrically floated. After time t3, the selection bit line potential VBL remains at the precharge potential VPRCH.

[0108] At time t3, signal SGB_s is set to low. This causes switch GBSW_s to open, disconnecting global bit line GBL_s from wiring FBL.

[0109] At time t4, signal S5 is set to low and signal S6 is set to high. As a result, switch SW5 is turned off and switch SW6 is turned on. Consequently, the select word line potential VWL drops towards the ground potential VSS. The ground potential VSS is the potential that the wiring receives from the ground voltage VSS, and in one example, it has a height substantially the same as the ground voltage VSS.

[0110] At time t5, the difference between the select word line potential VWL and the select bit line potential VBL reaches the threshold voltage Vth. Therefore, the switching element SE of the select memory cell MC_s is turned on. Consequently, the select word line WL is electrically connected to the select bit line BL_s via the turned-on switching element SE in the select memory cell MC_s. Thus, cell current flows from the select bit line BL_s towards the select word line WL.

[0111] Because the selection bit line BL_s is electrically floating, the selection bit line potential VBL decreases due to the cell current flow. At this time, the decrease in the selection bit line potential VBL varies depending on the state of the MTJ element MTJ of the selected memory cell MC_s. The selection bit line potential VBL when the MTJ element MTJ of the selected memory cell MC_s is in a high-resistance state decreases more slowly than the selection bit line potential VBL when the MTJ element MTJ of the selected memory cell MC_s is in a low-resistance state.

[0112] At time t6, the selection bit line potential VBL becomes the height of the resistance state of the MTJ element MTJ based on the selection memory cell MC_s. That is, due to the decrease in the selection bit line potential VBL, the difference between the selection bit line potential VBL and the selection bit line potential VBL decreases. Therefore, when the terminal voltage of the selection memory cell MC_s reaches a certain height, the switching element SE of the selection memory cell MC_s is turned off. As a result, the decrease in the selection bit line potential VBL stops, and the selection bit line potential VBL reaches a certain height.

[0113] The actions from time t4 to time t6 select the bit line potential VBL, and thus select the global bit line GBL_s to have a potential based on the state of the selected memory cell MC_s. Hereinafter, the actions from time t4 to time t6 are sometimes referred to as signal output actions.

[0114] At time t7, signals S4 and S1_s are set to high level. This turns on switches SW1 and SW4, applying a constant current to wiring FBL. At time t7, the global bit line GBL_s has a potential corresponding to the state of the selected memory cell MC_s, thereby applying a voltage to the gate of transistor Tr1 based on the state of the selected memory cell MC_s. Therefore, the potential of wiring FBL has a potential based on the state of the selected memory cell MC_s. In this way, the cell current based on the magnitude of the state of the selected memory cell MC_s is converted into a potential (voltage).

[0115] Next, the data already stored in the selected memory cell MC_s is determined from the output of the readout amplifier circuit SAC based on the potential of the wiring FBL.

[0116] At time t8, signals S4 and S1_s are set to low. The actions between time t7 and time t8 are sometimes referred to as readout (sensing) actions.

[0117] The signal S1_s can also be high only during the signal output and readout operations, that is, after time t4 and low until time t4.

[0118] 1.3. Advantages (Effects)

[0119] According to the first embodiment, as described below, a storage device with high operating margin and high accuracy in storing data can be provided.

[0120] As an example for reference, consider a configuration where the input of the switching circuit CC, i.e., the gate of transistor Tr1, is connected to wiring FBL, and the output of the switching circuit CC, i.e., the drain of transistor Tr1, is connected to the sense amplifier circuit SAC. In this case, during signal output and sense operation, switch GBSW remains on. (From reference...) Figure 3 As described above, the wiring FBL connects multiple elements via multiple global bit lines (GBLs), resulting in a large parasitic capacitance in the wiring FBL. Due to this large parasitic capacitance, a large cell current flows through the switching element SE of the selected memory cell MC_s. This can cause read interference. Read interference may lead to the accidental writing of unwanted data to the selected memory cell MC_s, potentially damaging the selected memory cell MC_s.

[0121] To suppress readout interference, a signal output operation can be performed with the select bit line BL_s disconnected from either the global select bit line GBL_s or the wiring FBL. Then, after the signal output operation generates a potential Vout in the select bit line BL_s based on the state of the selected memory cell MC_s, the select bit line BL_s is connected to the global select bit line GBL_s and the wiring FBL. This allows charge sharing, transferring the charge accumulated in the select bit line BL_s to the wiring FBL. In this state, a readout operation is performed. In this case, because the capacitance of the select bit line BL_s is small, the charge accumulated in the select bit line BL_s with potential Vout is small. Therefore, cell current is suppressed, and readout interference is suppressed. On the other hand, because the small amount of charge accumulated in the select bit line BL_s is shared, the potential of the wiring FBL after charge sharing is smaller than the potential Vout. Therefore, the current input to the conversion circuit CC is small, resulting in a small margin for sensing operation.

[0122] According to the first embodiment, the input of the conversion circuit CC is connected to the global bit line GBL, and the output of the conversion circuit CC is connected to the wiring FBL. Then, signal output and readout operations are performed during the period when the global bit line GBL_s is disconnected from the wiring FBL. Since the global bit line GBL_s is disconnected from the wiring FBL, during the signal output operation, the selection bit line BL_s and the global bit line GBL_s have a potential Vout based on the state of the selection memory cell MC_s. On the other hand, the charge accumulated in the selection bit line BL_s and the global bit line GBL_s is small. Therefore, the cell current when the switching element SE of the selection memory cell MC_s is turned on is small. On the other hand, since the selection bit line BL_s and the global bit line GBL_s have a potential Vout based on the state of the selection memory cell MC_s, the output of the conversion circuit CC is large. Therefore, high-precision data storage and a high operational margin can be achieved.

[0123] 1.4. Variations

[0124] The SAC (Sound Amplifier) ​​circuit can also have... Figure 13 The constituent elements and their connections are shown. Figure 13 The components of the read amplifier circuit of the storage device in a modified example of the first embodiment and the connections of the components are shown.

[0125] like Figure 13 As shown, the readout amplifier circuit SAC includes switches SW11 and SW12, capacitors CP1 and CP2, and operational amplifier OP.

[0126] Switch SW11 is connected between wiring FBL and node SAMP. In one example, signal S11 is supplied from the readout control circuit RCC.

[0127] Capacitor CP1 is connected between node SAMP and the node receiving ground voltage VSS.

[0128] Switch SW12 is connected between wiring FBL and node EVAL. In one example, signal S12 is supplied from the readout control circuit RCC.

[0129] Capacitor CP2 is connected between node EVAL and the node receiving the ground voltage VSS.

[0130] The operational amplifier OP is connected to the node SAMP at its inverting input and to the node EVAL at its non-inverting input.

[0131] The data reading process is as follows. First, with switch SW11 on, refer to... Figure 12The above actions are performed. As a result, the potential based on the state of the selected memory cell MC_s appears at node SAMP. Then, switch SW11 is opened, thereby storing the potential based on the state of the selected memory cell MC_s at node SAMP. No reference is performed. Figure 12 The described action involves the readout amplifier circuit SAC judging the data after time t7.

[0132] A predetermined, fixed reference data is written to the selected memory cell MC_s. The reference data can be either "0" or "1". The following description is based on an example with data "0".

[0133] With switch SW12 on, refer to Figure 12 The above actions are performed. As a result, a potential based on the state of the selected memory cell MC_s appears in node EVAL. This potential is based on the reference data for the selected memory cell MC_s. Then, switch SW12 is opened, thereby storing the potential based on the state of the selected memory cell MC_s in node EVAL. No reference is used. Figure 12 The described action involves the readout amplifier circuit SAC judging the data after time t7.

[0134] By enabling the operational amplifier OP, data OUT is output with values ​​based on the potentials of node SAMP and node EVAL. Data OUT has a value based on the data already stored in the selected memory cell MC_s at the start of data readout. If memory cell MC_s stores "0" data at the start of data readout, the data stored in memory cell MC_s at the start of data readout is the same as the written reference data. Data OUT is output with a value reflecting this situation.

[0135] On the other hand, if the selected storage unit MC_s contains "1" data at the start of data readout, the data stored in the selected storage unit MC_s at the start of data readout may differ from the written reference data. The output will contain data OUT reflecting this situation.

[0136] After outputting the data OUT, the data already stored in the selected storage unit MC_s at the start of the data reading will be written to the selected storage unit MC_s.

[0137] According to a variation, the data in the selected memory cell MC_s is determined by comparing the potential of the selected memory cell MC_s based on its state (the potential of node SAMP) with the potential of the known data written to that selected memory cell MC_s (the potential of node EVAL). Even if the characteristics of the memory cell MC inevitably deviate, the effect of the deviation is suppressed compared to comparing the potential based on the state of the selected memory cell MC_s with a common potential.

[0138] Furthermore, identical components with the same function but in different locations (e.g., switches GBSW connected to different global bit lines GBL) may inevitably have different characteristics. Even when reading data from multiple memory cells storing the same data, the read results may differ due to deviations in the characteristics of the components involved in reading data from memory cell MC. According to a variation, the data in memory cell MC_s is selected by comparing the potential read from the selected memory cell MC_s with the potential based on known reference data written to the selected memory cell MC_s. Therefore, the components involved in reading data from the selected memory cell MC_s are the same as the components involved in reading the written reference data. Thus, deviations in the results when reading the same data from different memory cells MC due to deviations in the characteristics of multiple components can be suppressed.

[0139] 2. Second Implementation Method

[0140] The second implementation differs from the first implementation in terms of the data reading operation.

[0141] Figure 14 The potentials of several signals and wirings during the data readout period of the storage device in the second embodiment are represented along the time axis. Figure 14 Compared with the first embodiment Figure 12 The same state indicates that the storage unit MC of a data read object has been selected. When data reading begins while the storage unit MC of the data read object is selected, the process starts... Figure 14 The actions during the period shown.

[0142] like Figure 14 As shown, at time t4, signal SB_s is set to low. Therefore, at time t4, the select bit line BL_s is disconnected from the select global bit line GBL_s. Thus, signal output occurs while both the select bit line BL_s and the select global bit line GBL_s are disconnected.

[0143] At time t7, signal SB_s is set to high. This connects the select bit line BL_s to the select global bit line GBL_s. Therefore, the read operation is performed while the select bit line BL_s and the select global bit line GBL_s are connected.

[0144] According to the second embodiment, during the signal output operation, the selection bit line BL_s is cut off from the selection global bit line GBL_s. Therefore, during the signal output operation, the parasitic capacitance of the wiring connected to the selection memory cell MC_s (i.e., the selection bit line BL_s) is smaller than in the first embodiment. Consequently, the cell current is smaller.

[0145] 3. Third Implementation Method

[0146] The third implementation method is added to the first implementation method and implemented accordingly.

[0147] Figure 15 The potentials of several signals and wirings during the data readout period of the storage device in the third embodiment are represented along the time axis. Figure 15 Compared with the first embodiment Figure 12 The same indicates that the selected storage unit MC_s of a data read object is selected. When data reading begins while the selected storage unit MC_s of the data read object is selected, the process starts... Figure 15 The actions during the period shown.

[0148] like Figure 15 As shown, at time t7, signal SB_s is set low. Consequently, the selection bit line BL_s is disconnected from the global selection bit line GBL_s. The disconnection of the selection bit line BL_s from the global selection bit line GBL_s continues until... Figure 15 Until the end of the indicated period.

[0149] According to the third embodiment, as described below, data can be read with high accuracy. Even when the switching element SE is off, a small leakage current can flow in the switching element SE. Therefore, during data readout, the selection bit line potential VBL may be available at the moment when the switching element SE of the selection memory cell MC_s is off ( Figure 15 The reading decreases after time t5. This may lead to a decrease in data read accuracy and / or a decrease in data read margin. According to the third embodiment, after the signal output operation, the selection bit line BL_s is cut off from the selection global bit line GBL_s. Therefore, the reduction of charge in the wiring FBL used to determine data after the signal output operation due to leakage via the switching element SE can be suppressed. This helps to suppress the decrease in data read accuracy and / or read margin. For example, even if the amount of charge accumulated in the wiring connected to the selection memory cell MC_s is small, the decrease in data read accuracy and / or read margin can be suppressed by the signal output operation.

[0150] While several embodiments of the invention have been described, these embodiments are provided by way of example and are not intended to limit the scope of the invention. These embodiments can be implemented in various other ways, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their variations are included within the scope or spirit of the invention, and within the scope of the invention as set forth in the claims and its equivalents.

[0151] Explanation of reference numerals in the attached figures

[0152] 1… Storage device, 11… Core circuit, 12… Input / output circuit, 13… Control circuit, 14… Decoding circuit, 15… Page buffer, 16… Voltage generation circuit, MC… Storage cell, FWL… Wiring, FBL… Wiring, CCS… Conversion circuit group, 18… Write circuit, 19… Read circuit.

Claims

1. A memory device comprising: a first memory cell including a first magnetoresistive effect element and a first switching element connected to the first magnetoresistive effect element; a first wiring connected to a first terminal of the first memory cell; a second wiring connected to a second terminal of the first memory cell; a first switch having a third terminal connected to the second wiring and a fourth terminal; a third wiring connected to the fourth terminal; a second switch having a fifth terminal connected to the third wiring and a sixth terminal; a fourth wiring connected to the sixth terminal; a first transistor having a gate connected to the third wiring and a seventh terminal connected to the fourth wiring; a third switch connected between the seventh terminal and a first node receiving a first voltage; and a sense amplifier circuit connected to the fourth wiring.

2. The memory device according to claim 1, comprising: a first region including a plurality of first source / drain regions different in shape and size and a plurality of first gate electrodes different in shape and size; and a second region in which groups of a plurality of second source / drain regions arranged in a first direction are repeatedly provided in a second direction, and in which a second gate electrode extending in the second direction is repeatedly provided in the first direction, the sense amplifier circuit includes at least a portion of one of the plurality of first source / drain regions and one of the plurality of first gate electrodes, and the first transistor includes at least a portion of one of the plurality of second source / drain regions and the second gate electrode.

3. The memory device according to claim 1, wherein a period in which data is read from the first memory cell includes a first period, and in the first period, the first switch and the third switch are maintained to be on, and the second switch is maintained to be off.

4. The memory device according to claim 3, comprising: a second memory cell including a second magnetoresistive effect element and a second switching element connected to the second magnetoresistive effect element; a fifth wiring connected to an eighth terminal of the second memory cell; a sixth wiring connected to a ninth terminal of the second memory cell; a fourth switch having a tenth terminal connected to the sixth wiring and an eleventh terminal; a seventh wiring connected to the eleventh terminal; a fifth switch having a twelfth terminal connected to the seventh wiring and a thirteenth terminal connected to the fourth wiring; a second transistor having a gate connected to the seventh wiring and a fourteenth terminal connected to the fourth wiring; and a sixth switch connected between the fourteenth terminal and a second node receiving the first voltage, wherein in the period of reading, the fourth switch, the fifth switch, and the sixth switch are maintained to be off.

5. The memory device according to claim 4, wherein in a second period before the first period, the fourth wiring is electrically floated after a second voltage is applied thereto, and in the period in which the fourth wiring is electrically floated, the first wiring is applied with a third voltage lower than the second voltage, and in the first period, the first wiring is applied with a fourth voltage lower than the third voltage. ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ 6. The memory device according to claim 3, the readout period further includes a third period following the first period, in the third period, the third switch is maintained to be on, and the first switch and the second switch are maintained to be off.

7. The memory device according to claim 6, in a second period before the first period, the fourth wiring is electrically floated after being applied with a second voltage, in the period during which the fourth wiring is electrically floated, the first wiring is applied with a third voltage lower than the second voltage, in the first period, the first wiring is applied with a fourth voltage lower than the third voltage.

8. The memory device according to claim 1, the period during which data is read out from the first memory cell includes a first period and a third period following the first period, in the first period, the third switch is maintained to be on, and the first switch and the second switch are maintained to be off, in the third period, the first switch is maintained to be on, and the second switch is maintained to be off.

9. The memory device according to claim 8, in a second period before the first period, the fourth wiring is electrically floated after being applied with a second voltage, in the period during which the fourth wiring is electrically floated, the first wiring is applied with a third voltage lower than the second voltage, in the first period, the first wiring is applied with a fourth voltage lower than the third voltage.

10. The memory device according to any one of claims 1 to 9, the sense amplifier circuit includes: a seventh switch connected between the fourth wiring and an eighth wiring; a first capacitor having one end connected to the eighth wiring; an eighth switch connected between the fourth wiring and a ninth wiring; a second capacitor having one end connected to the ninth wiring; and an operational amplifier having a first input connected to the eighth wiring and a second input connected to the ninth wiring. ​

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