Magnetic storage device

Abstract

The invention provides a magnetic storage device capable of improving operation performance. According to one embodiment, a magnetic memory device includes a memory cell (MC), a constant current source (CS), switches (S1, S2, and S3), a peak detection circuit (51), and a sense amplifier (SA). The memory cell includes a variable resistance element (VR) and a selector element (SE). The constant current source (CS) supplies a current (Ipc) to the memory cell. The switch (S1) is connected between the memory cell and the constant current source (CS). A switch (S2) is connected between a ground voltage node and the memory cell. The peak detection circuit (51) includes a comparator (CP) and a diode (D1), a voltage (Vm) charged to the memory cell is input to a first input terminal of the comparator via the diode, and the voltage (Vm) is input to a second input terminal of the comparator. A sense amplifier (SA) compares the voltage (Vm) with a reference voltage (Vref). A switch (S3) is connected between the memory cell and the sense amplifier (SA).

Description

Technical Field

[0001] Embodiments of the present invention relate to magnetic storage devices. Background Technology

[0002] There are known magnetic storage devices (MRAM: Magnetoresistive Random Access Memory) that use magnetoresistive elements as storage elements. Summary of the Invention

[0003] Provide magnetic storage devices that can improve motion performance.

[0004] The magnetic storage device of this embodiment includes a storage cell, a current source, a first switch, a second switch, a detection circuit, a sensing amplifier, and a third switch. The storage cell includes a variable resistor element and a selector element. The current source supplies a first current to the storage cell. The first switch is connected between the storage cell and the current source. The second switch is connected between a ground voltage node supplied with a ground voltage and the storage cell. The detection circuit includes a comparator and a diode; a first voltage charged to the storage cell is input to the first input terminal of the comparator via the diode, and the first voltage is also input to the second input terminal of the comparator. The sensing amplifier compares the first voltage charged to the storage cell with the second voltage. The third switch is connected between the storage cell and the sensing amplifier. Attached Figure Description

[0005] Figure 1 This is a block diagram showing the configuration of a storage system including the magnetic storage device of the first embodiment.

[0006] Figure 2 This is a circuit diagram showing the configuration of the memory cell array included in the magnetic storage device of the first embodiment.

[0007] Figure 3 This is a perspective view showing the structure of the memory cell array included in the magnetic storage device of the first embodiment.

[0008] Figure 4 This is a cross-sectional view of the storage cells within the storage cell array of the first embodiment.

[0009] Figure 5 This is a circuit diagram showing the configuration of the readout circuit of the magnetic storage device according to the first embodiment.

[0010] Figure 6 This is a diagram showing the current-voltage characteristics of the selector element in the first embodiment, illustrating its snapback feature.

[0011] Figure 7This is a circuit diagram showing an example of the configuration of the delay circuit in the first embodiment.

[0012] Figure 8 This is a graph showing the voltage changes of the storage cell voltage and the diode voltage during the readout operation of the first embodiment.

[0013] Figure 9 This is a flowchart illustrating the readout operation of the first embodiment.

[0014] Figure 10 This is a diagram showing the state of the switch, the flow of current, and the voltage changes during the readout operation of the first embodiment.

[0015] Figure 11 This is a diagram showing the state of the switch, the flow of current, and the voltage changes during the readout operation of the first embodiment.

[0016] Figure 12 This is a diagram showing the state of the switch, the flow of current, and the voltage changes during the readout operation of the first embodiment.

[0017] Figure 13 This is a diagram showing the state of the switch, the flow of current, and the voltage changes during the readout operation of the first embodiment.

[0018] Figure 14 This is a circuit diagram showing the configuration of the readout circuit in the second embodiment.

[0019] Figure 15 This is a circuit diagram showing the configuration of the readout circuit of a modified example of the second embodiment.

[0020] Figure 16 This is a graph showing the voltage changes of the storage cell voltage and the diode voltage during the readout operation of a modified example of the second embodiment.

[0021] Explanation of reference numerals in the attached figures

[0022] 1…Magnetic storage device, 2…Storage controller, 11…Storage cell array, 12…Input / output circuit, 13…Control circuit, 14…Row selection circuit, 15…Column selection circuit, 16…Write circuit, 17…Read circuit, 20…Conductive layer, 21…Conductive layer, 30…Lower electrode, 31…Selector material layer, 32…Upper electrode, 40…Ferromagnetic layer, 41…Nonmagnetic layer, 42…Ferromagnetic layer, 51…Peak detection circuit, 52…Delay circuit, C1…Capacitor element, D1…Diode, MC…Storage cell, R1…Resistor element, S1…Precharge switch, S2…Sink switch, S3…Sense amplifier switch, SE…Selector element, VR…Variable resistor element. Detailed Implementation

[0023] Hereinafter, embodiments will be described with reference to the accompanying drawings. In the following description, constituent elements having the same function and structure will be labeled with common reference numerals. Furthermore, the embodiments shown below illustrate apparatus and methods for embodying the technical concept of these embodiments, and do not specify the material, shape, structure, and arrangement of the constituent parts as described below.

[0024] 1. First Implementation Method

[0025] First, an example of a storage system including the magnetic storage device of the first embodiment will be described. Figure 1 This is a block diagram showing the configuration of a storage system MS including the magnetic storage device of the first embodiment.

[0026] like Figure 1 As shown, the storage system MS includes a magnetic storage device 1 and a storage controller 2. The magnetic storage device 1 operates under the control of the storage controller 2. The storage controller 2 can respond to requests (or commands) from external host devices, commanding the magnetic storage device 1 to perform read and write operations, etc.

[0027] 1.1 Composition of Magnetic Storage Devices

[0028] Next, refer to Figure 1 The configuration of the magnetic storage device 1 in the first embodiment will be described.

[0029] Magnetic storage device 1 is a type of resistive variable memory. It is a storage device that uses MTJ (Magnetic Tunnel Junction) elements as storage cells. MTJ elements utilize the magnetoresistance effect based on the magnetic tunnel junction. MTJ elements are also known as magnetoresistance effect elements.

[0030] The magnetic storage device 1 includes, for example, a storage cell array 11, an input / output circuit 12, a control circuit 13, a row selection circuit 14, a column selection circuit 15, a write circuit 16, and a read circuit 17.

[0031] The memory cell array 11 includes multiple memory cells (MC), multiple word lines (WL), and multiple bit lines (BL). Figure 1The diagram illustrates a group of memory cells MC, word lines WL, and bit lines BL. Memory cells MC store data in a non-volatile manner. Each memory cell MC is connected between a word line WL and a bit line BL, and is associated with a group of rows and columns. Row addresses are assigned to word lines WL. Column addresses are assigned to bit lines BL. One or more memory cells MC can be determined by selecting one row and one or more columns.

[0032] Input / output circuit 12 is connected to memory controller 2 and is responsible for communication between magnetic storage device 1 and memory controller 2. Input / output circuit 12 transmits the control signal CNT and command CMD received from memory controller 2 to control circuit 13. Input / output circuit 12 also transmits the row address and column address contained in the address signal ADD received from memory controller 2 to row selection circuit 14 and column selection circuit 15, respectively. Input / output circuit 12 transmits the data DAT (write data) received from memory controller 2 to write circuit 16. Input / output circuit 12 transmits the data DAT (read data) received from read circuit 17 to memory controller 2.

[0033] The control circuit 13 controls the overall operation of the magnetic storage device 1. For example, the control circuit 13 performs read operations, write operations, etc., based on the control signal CNT and the command CMD. For example, during the write operation, the control circuit 13 supplies the voltage used for writing data and the control signal to the write circuit 16. In addition, during the read operation, the control circuit 13 supplies the voltage used for reading data and the control signal to the read circuit 17.

[0034] Row selection circuit 14 is connected to multiple word lines WL. Row selection circuit 14 selects one word line WL determined by the row address. The selected word line WL is electrically connected, for example, to a driver circuit (not shown).

[0035] Column selection circuit 15 is connected to multiple bit lines BL. Column selection circuit 15 selects one or more bit lines BL determined by the column address. The selected bit line BL is electrically connected, for example, to a drive circuit (not shown in the figure).

[0036] The write circuit 16 supplies the voltage used for writing data to the column selection circuit 15 based on the control of the control circuit 13 and the data DAT (write data) received from the input / output circuit 12. The desired data is written to the memory cell MC while the current based on the write data flows through the memory cell MC.

[0037] The readout circuit 17 includes a sense amplifier. Based on the control of the control circuit 13, the readout circuit 17 supplies the voltage used for data readout to the row selection circuit 14 and the column selection circuit 15. The sense amplifier determines the data stored in the memory cell MC based on the voltage or current of the selected memory cell MC and the word line WL. Furthermore, the readout circuit 17 transmits the data DAT (readout data) corresponding to the determination result to the input / output circuit 12. Details regarding the readout circuit 17 will be described later.

[0038] 1.1.1 Circuit configuration of memory cell array

[0039] Reference Figure 2 An example of the circuit configuration of the storage cell array 11 included in the magnetic storage device 1 of the first embodiment will be described. Figure 2 This is a circuit diagram showing the configuration of the memory cell array 11 of the magnetic storage device 1. Figure 2 The WL0 and WL1 words from the WL series, and the BL0 and BL1 bits from the BL series are extracted and shown.

[0040] like Figure 2 As shown, one memory cell MC is connected between WL0 and BL0, between WL0 and BL1, between WL1 and BL0, and between WL1 and BL1. Multiple memory cells MC are arranged, for example, in a matrix within the memory cell array 11.

[0041] Each memory cell (MC) includes a variable resistor element (VR) and a selector element (SE). The variable resistor element (VR) and the selector element (SE) are connected in series between their respective bit lines (BL) and word lines (WL). For example, one end of the variable resistor element (VR) is connected to the bit line (BL). The other end of the variable resistor element (VR) is connected to one end of the selector element (SE). The other end of the selector element (SE) is connected to the word line (WL). Alternatively, the connection relationship between the variable resistor element (VR) and the selector element (SE) between the bit line (BL) and the word line (WL) can be reversed. That is, one end of the variable resistor element (VR) is connected to the word line (WL), and the other end of the variable resistor element (VR) is connected to one end of the selector element (SE). The other end of the selector element (SE) can also be connected to the bit line (BL).

[0042] The variable resistor element VR corresponds to an MTJ element (i.e., a magnetoresistive element). The variable resistor element VR can store data non-volatilely based on its resistance value. For example, the storage cell MC of the variable resistor element VR in a high-resistance state stores data "1". The storage cell MC of the variable resistor element VR in a low-resistance state stores data "0". The allocation of data associated with the resistance value of the variable resistor element VR can also be otherwise configured. The resistance state of the variable resistor element VR can change according to the current flowing through the variable resistor element VR.

[0043] The selector element SE is, for example, a bidirectional diode with a quick-return characteristic. The selector element SE functions as a selector that controls the current supply to the associated variable resistor element VR.

[0044] Specifically, regarding the selector element SE included in a memory cell MC, it is in a cutoff state (or non-conducting state) when the voltage applied to the memory cell MC is lower than the threshold voltage of the selector element SE, and in a connected state (or conducting state) when the voltage rises above the threshold voltage of the selector element SE. In the cutoff state, the selector element SE functions as an insulator with high resistance. When the selector element SE is in the cutoff state, the current flow between the word line WL and the bit line BL connected to the memory cell MC is suppressed. In the connected state, the selector element SE functions as a conductor with low resistance. When the selector element SE is in the connected state, current flows between the word line WL and the bit line BL connected to the memory cell MC. That is, the selector element SE can switch whether current flows based on the magnitude of the voltage applied to the memory cell MC, regardless of the direction of current flow. The quick-return characteristic of the selector element SE will be described later. Furthermore, other components such as transistors can also be used as the selector element SE.

[0045] 1.1.2 Construction of Storage Cell Array

[0046] Reference Figure 3 An example of the structure of the storage cell array 11 provided in the magnetic storage device 1 of the first embodiment will be described. Figure 3 This is a perspective view showing the structure of the memory cell array 11 included in the magnetic storage device 1. In the following description, an XYZ orthogonal coordinate system is used. The X direction corresponds to the extension direction of the word line WL. The Y direction corresponds to the extension direction of the bit line BL. The Z direction corresponds to the vertical direction perpendicular to the surface of the semiconductor substrate used to form the magnetic storage device 1. The term "down" and its derivatives and related terms indicate the position of a smaller coordinate on the Z-axis. The term "up" and its derivatives and related terms indicate the position of a larger coordinate on the Z-axis. Hatching is appropriately added to the perspective view. The hatching added to the perspective view is not necessarily related to the raw materials or characteristics of the constituent elements to which the hatching is added. Illustrations of structures such as interlayer insulating films are omitted in the perspective view and cross-sectional view.

[0047] like Figure 3 As shown, the memory cell array 11 includes multiple conductive layers 20, multiple conductive layers 21, and multiple memory cells MC.

[0048] Multiple conductive layers 20 each have a portion extending in the X direction. The multiple conductive layers 20 are arranged in the Y direction and separated from each other. Each conductive layer 20 is used as a word line WL.

[0049] Each of the multiple conductive layers 21 has a portion extending in the Y direction. The multiple conductive layers 21 are arranged in the X direction and separated from each other. Each conductive layer 21 is used as a bit line BL.

[0050] A wiring layer comprising multiple conductive layers 21 is disposed above a wiring layer comprising multiple conductive layers 20. A memory cell MC is disposed at each intersection of the multiple conductive layers 20 and the multiple conductive layers 21. In other words, each memory cell MC is disposed between an associated word line WL and bit line BL. Each memory cell MC has a columnar structure. In this example, a selector element SE is disposed above the conductive layer 20. A variable resistor element VR is disposed above the selector element SE. The conductive layer 21 is disposed above the variable resistor element VR.

[0051] Furthermore, while the example of the variable resistor element VR being positioned above the selector element SE has been illustrated, it is not a limitation. Depending on the circuit configuration of the memory cell array 11, the variable resistor element VR may also be positioned below the selector element SE. Additionally, other components or conductive layers may be inserted between the memory cell MC and the conductive layer 20. Similarly, other components or conductive layers may be inserted between the memory cell MC and the conductive layer 21. Conductor layers 20 and 21 may each be referred to as "wiring".

[0052] 1.1.3 Cross-sectional structure of the storage cell

[0053] Reference Figure 4 An example of a storage cell MC included in the storage cell array 11 of the magnetic storage device 1 of the first embodiment will be described. Figure 4 This is a cross-sectional view of the storage cells MC included in the storage cell array 11.

[0054] like Figure 4 As shown, the memory cell MC has, for example, the following structure: a lower electrode 30, a selector material layer 31, an upper electrode 32, a ferromagnetic layer 40, a non-magnetic layer 41, and a ferromagnetic layer 42 are sequentially stacked from the conductor layer 20 upwards (Z direction).

[0055] That is, the lower electrode 30 is disposed above the conductive layer 20 (in the Z direction). The selector material layer 31 is disposed above the lower electrode 30. The upper electrode 32 is disposed above the selector material layer 31. The ferromagnetic layer 40 is disposed above the upper electrode 32. The non-magnetic layer 41 is disposed above the ferromagnetic layer 40. The ferromagnetic layer 42 is disposed above the non-magnetic layer 41. The conductive layer 21 is disposed above the ferromagnetic layer 42.

[0056] In other words, the non-magnetic layer 41 is disposed between the ferromagnetic layer 40 and the ferromagnetic layer 42. The ferromagnetic layer 40 is disposed between the non-magnetic layer 41 and the upper electrode 32. The upper electrode 32 is disposed between the ferromagnetic layer 40 and the selector material layer 31. The selector material layer 31 is disposed between the upper electrode 32 and the lower electrode 30. The lower electrode 30 is disposed between the selector material layer 31 and the conductive layer 20. Furthermore, the ferromagnetic layer 42 is disposed between the non-magnetic layer 41 and the conductive layer 21.

[0057] The combination of the lower electrode 30, the selector material layer 31, and the upper electrode 32 corresponds to the selector element SE. The combination of the ferromagnetic layer 40, the non-magnetic layer 41, and the ferromagnetic layer 42 corresponds to the variable resistor element VR.

[0058] Ferromagnetic layers 40 and 42 are each composed of a ferromagnetic material and have a magnetization direction perpendicular to the film surface. In the magnetic storage device 1, for example, the magnetization direction of ferromagnetic layer 40 is fixed, while the magnetization direction of ferromagnetic layer 42 is variable. In this case, ferromagnetic layer 40 functions as a reference layer of the MTJ element, and ferromagnetic layer 42 functions as a storage layer of the MTJ element. The non-magnetic layer 41 is composed of an insulator such as MgO and functions as a tunnel barrier layer. Ferromagnetic layers 40 and 42, together with non-magnetic layer 41, form a magnetic tunnel junction. Such a variable resistance element VR functions as a vertically magnetized MTJ element utilizing the TMR (tunneling magnetoresistive) effect.

[0059] Ferromagnetic layer 40, for example, contains at least one element selected from iron (Fe), cobalt (Co), and nickel (Ni). Nonmagnetic layer 41, for example, contains an oxide of at least one element or compound selected from magnesium (Mg), aluminum (Al), zinc (Zn), titanium (Ti), and LSM (lanthanum-strontium-manganese). Ferromagnetic layer 42, for example, contains at least one element selected from iron (Fe), cobalt (Co), and nickel (Ni).

[0060] The variable resistor element VR can achieve either a low-resistance state or a high-resistance state depending on the relative magnetization directions of the ferromagnetic layers 40 and 42. Furthermore, the variable resistor element VR stores data based on the magnetization direction of the ferromagnetic layer 42 (storage layer). For example, the variable resistor element VR in a state where the magnetization directions of the reference layer and the storage layer are antiparallel (AP state) becomes a high-resistance state (data "1"). On the other hand, the variable resistor element VR in a state where the magnetization directions of the reference layer and the storage layer are parallel (P state) becomes a low-resistance state (data "0").

[0061] In this example, the variable resistor element VR is in the AP state when a write current flows from the ferromagnetic layer 40 to the ferromagnetic layer 42, and in the P state when a write current flows from the ferromagnetic layer 42 to the ferromagnetic layer 40. This writing method, which injects spin torque into the memory layer and reference layer by allowing the write current to flow through the variable resistor element VR to control the magnetization direction of the memory layer, is called spin injection writing. The variable resistor element VR is configured such that when a current large enough to reverse the magnetization direction of the ferromagnetic layer 42 flows through the variable resistor element VR, the magnetization direction of the ferromagnetic layer 40 does not change.

[0062] Furthermore, in this specification, "variable magnetization direction" means that the magnetization direction changes due to the write current. "Fixed magnetization direction" means that the magnetization direction does not change due to the write current. In the variable resistor element VR, the configuration of the storage layer and the reference layer can also be interchanged. Additionally, the variable resistor element VR can also have other layers. For example, the variable resistor element VR can also have a shift cancel layer to suppress the influence of the leakage magnetic field of the reference layer, a SAF (Synthetic Anti-Ferromagnetic) structure, etc. Hereinafter, the storage cell MC of the variable resistor element VR including the AP state will be referred to as the AP state storage cell MC, and the storage cell MC of the variable resistor element VR including the P state will be referred to as the P state storage cell MC.

[0063] 1.1.4 Circuit configuration of the readout circuit

[0064] Reference Figure 5 An example of the circuit configuration of the readout circuit 17 provided in the magnetic storage device 1 of the first embodiment will be described. Figure 5 This is a circuit diagram showing the configuration of the read circuit 17 of the magnetic storage device 1. Figure 5 The image shows the readout circuit 17, the pair of bit lines BL and word lines WL included in the memory cell array 11, and the memory cell MC.

[0065] like Figure 5As shown, the readout circuit 17 includes a constant current source CS, a power supply VH, a peak detection circuit 51, a delay circuit 52, a sensing amplifier SA, a pre-charge switch S1, a snub switch S2, and a sensing amplifier switch S3. The peak detection circuit 51 includes a comparator CP and a diode D1.

[0066] The constant current source CS is connected to the word line WL via the pre-charge switch S1. A power supply VH is connected to the constant current source CS.

[0067] Word line WL is connected to the first input terminal of sense amplifier SA via sense amplifier switch S3. A reference voltage Vref is supplied to the second input terminal of sense amplifier SA. Sense amplifier SA compares the voltage Vm input to the first input terminal, the voltage of memory cell MC (or selector element SE), and word line WL with the reference voltage Vref, and outputs signal SO based on the comparison result.

[0068] The word line WL is connected to the positive input terminal (or non-inverting input terminal) of the comparator CP via diode D1. Furthermore, the word line WL is connected to the negative input terminal (or inverting input terminal) of the comparator CP.

[0069] The output terminal of comparator CP is connected to the input terminal of delay circuit 52. The output terminal of delay circuit 52 is connected to the control terminal of absorb switch S2 and the control terminal of sense amplifier switch S3. The control terminal of absorb switch S2 is used to control absorb switch S2 to either a connected state (or closed state, on state) or a disconnected state (or off state, off state). The control terminal of sense amplifier switch S3 is used to control sense amplifier switch S3 to either a connected state or a disconnected state.

[0070] Bit line BL is connected to the ground voltage VSS node via absorption switch S2. Ground voltage VSS is supplied to the ground voltage VSS node.

[0071] The memory cell MC is connected between the word line WL and the bit line BL. The memory cell MC includes a selector element SE and a variable resistor element VR connected in series. Specifically, one end of the selector element SE is connected to the word line WL, and the other end of the selector element SE is connected to one end of the variable resistor element VR. Furthermore, the other end of the variable resistor element VR is connected to the bit line BL.

[0072] A constant current source CS supplies a pre-charge current Ipc to the memory cell MC (or selector element SE) and word line WL via a pre-charge switch S1, charging the memory cell MC (or selector element SE) and word line WL. The pre-charge current Ipc is constant, and with the supply of the pre-charge current Ipc, the voltage Vm of the memory cell MC (or selector element SE) and word line WL gradually increases. The voltage Vm of the memory cell MC (or selector element SE) and word line WL is the voltage between the terminals connected to the word line WL and the bit line BL of the memory cell MC, i.e., the voltage between the word line WL and the bit line BL of the memory cell MC. Hereinafter, the voltage Vm of the memory cell MC (or selector element SE) and word line WL is referred to as the voltage Vm of the memory cell MC and word line WL, or simply the voltage Vm of the memory cell MC.

[0073] When supplying a pre-charge current Ipc to the memory cell MC, the peak detection circuit 51 detects the peak voltage Vm of the memory cell MC. The peak voltage Vm of the memory cell MC is equivalent to the threshold voltage Vth of the selector element SE of the memory cell MC.

[0074] The memory cell MC is charged by a pre-charge current Ipc supplied from the constant current source CS, causing the voltage Vm of the memory cell MC to rise to the threshold voltage Vth. Then, the selector element SE switches to the ON (or ON) state. Consequently, the cell current Im begins to flow from the memory cell MC through the snub switch S2 to the ground voltage VSS node. Afterwards, the voltage Vm of the memory cell MC decreases due to the quiescent characteristic of the selector element SE, and further decreases due to the cell current Im. Therefore, the threshold voltage Vth becomes the peak voltage of the voltage Vm of the memory cell MC.

[0075] As described above, the peak detection circuit 51 includes a comparator CP and a diode D1. The voltage Vm of the memory cell MC is input to the positive input terminal of the comparator CP via diode D1. The voltage between the cathode of diode D1 and the positive input terminal of the comparator CP is set as voltage Vd. The voltage Vm of the memory cell MC is input to the negative input terminal of the comparator CP without passing through the diode.

[0076] The following is for reference Figure 6 The quick-return characteristics of the selector element SE of the memory cell MC are explained. Figure 6 This is a graph showing the current-voltage characteristics of the selector element SE, illustrating its quick-return behavior. The horizontal axis represents the voltage Vse applied to the selector element SE. The vertical axis represents the current Ise flowing through the selector element SE.

[0077] As the voltage Vse applied to the selector element SE rises from 0, a small current flows through the selector element SE and gradually increases. The selector element SE becomes off when the voltage Vse reaches the threshold voltage Vth of the selector element SE.

[0078] As the voltage Vse rises further, reaching the threshold voltage Vth at point A, the selector element SE switches to the ON state. Consequently, the voltage Vse drops sharply to point B and then rises again. The current Ise increases sharply from point B.

[0079] The phenomenon where the voltage Vse applied to the selector element SE drops sharply when it reaches the threshold voltage Vth of the selector element SE is called a quiescent characteristic. In this embodiment, this quiescent characteristic is utilized to detect when the voltage Vm of the memory cell MC reaches the threshold voltage Vth, based on the principle that "when the voltage Vm of the memory cell MC reaches the threshold voltage Vth, the voltage Vm immediately falls below the diode voltage Vd".

[0080] The comparator CP of the peak detection circuit 51 compares the voltage Vm of the memory cell MC with the voltage Vd. Based on the comparison result, it determines whether the voltage Vm of the memory cell MC has reached the peak voltage, that is, whether the voltage Vm of the memory cell MC has reached the threshold voltage Vth of the selector element SE. The comparator CP outputs a signal O1 based on the determination result.

[0081] When the voltage Vm of the memory cell MC reaches the threshold voltage Vth, the selector element SE switches to the ON state. As a result, the voltage Vm of the memory cell MC, i.e., the charge that has been deposited on the memory cell MC, begins to discharge. That is, the cell current Im begins to flow from the memory cell MC through the absorption switch S2 to the ground voltage VSS node.

[0082] For example, when the voltage Vd of diode D1 is lower than the voltage Vm of memory cell MC, comparator CP outputs a low-level voltage (hereinafter referred to as "L") as a signal O1 indicating that the voltage Vm of memory cell MC has not reached the threshold voltage Vth. On the other hand, when the voltage Vm of memory cell MC reaches the threshold voltage Vth and then drops due to the quick-return characteristic of selector element SE, causing voltage Vd to become higher than voltage Vm, comparator CP outputs a high-level voltage (hereinafter referred to as "H") higher than "L" as a signal O1 indicating that the voltage Vm of memory cell MC has reached the threshold voltage Vth. Furthermore, peak detection circuit 51 is configured, for example, per word line WL.

[0083] The delay circuit 52 delays the signal O1 output from the comparator CP by a predetermined delay time and outputs the signal O2. Figure 7This is a circuit diagram showing an example of the configuration of the delay circuit 52. For example, as shown... Figure 7 As shown in (a), the delay circuit 52 has a configuration of an even number of inverters IV connected in series. Additionally, as... Figure 7 As shown in (b), it has a configuration including two inverters IV, a resistor R1 connected between these inverters, and a capacitor C1.

[0084] The delay time of the delay circuit 52 is set to be shorter than the time from when the voltage Vm of the memory cell MC is detected to reach the threshold voltage Vth, that is, from when the cell current Im starts flowing until the voltage Vm of the memory cell MC drops to the holding voltage Vh. Furthermore, the holding voltage Vh is the voltage maintained by the memory cell MC after the cell current Im flows through the memory cell MC and after the cell current Im (or discharge current) stops flowing.

[0085] The sensing amplifier SA is configured to compare the voltage Vm of the storage cell MC with the reference voltage Vref when reading the data stored in the storage cell MC, and determine the data stored in the storage cell MC based on the comparison result.

[0086] The reference voltage Vref is a voltage used as a threshold when determining whether a data value is "0" or "1". For example, when the voltage Vm of the memory cell MC is above Vref, the sense amplifier SA outputs the voltage corresponding to data "1" as signal SO. On the other hand, when the voltage Vm of the memory cell MC is below Vref, it outputs the voltage corresponding to data "0" as signal SO. Furthermore, the sense amplifier SA is configured, for example, per word line WL.

[0087] The precharge switch S1 is switched based on the control of the control circuit 13 to either supply a precharge current Ipc to the memory cell MC or stop supplying the precharge current Ipc. The precharge switch S1 is connected between the word line WL (or the memory cell MC) and the constant current source CS. Based on the control of the control circuit 13, the precharge switch S1 sets the relationship between the word line WL and the constant current source CS to either a connected state (or a closed state, on state) or a disconnected state (or an open state, off state).

[0088] For example, when the precharge switch S1 is set to the connected state, a precharge current Ipc is supplied from the constant current source CS to the memory cell MC and the word line WL. On the other hand, when the precharge switch S1 is set to the disconnected state, the supply of the precharge current Ipc from the constant current source CS to the memory cell MC and the word line WL is stopped. The precharge switch S1 may include, for example, an n-type MOS field-effect transistor.

[0089] The snub switch S2 controls the cell current Im flowing from the memory cell MC to the ground voltage VSS node based on the signal O2 output from the delay circuit 52. That is, the snub switch S2 is a switch that toggles between releasing charge from the memory cell MC and stopping charge release. The snub switch S2 is connected between the bit line BL (or the memory cell MC) and the ground voltage VSS node. Based on the signal O2 from the delay circuit 52, the snub switch S2 sets the connection between the bit line BL and the ground voltage VSS node to either a connected state or a disconnected state. For example, when the snub switch S2 is set to the connected state, the cell current Im flows from the memory cell MC to the ground voltage VSS node, and the charge charged to the memory cell MC is released. On the other hand, when the snub switch S2 is set to the disconnected state, the cell current Im does not flow from the memory cell MC to the ground voltage VSS node, and the release of charge charged to the memory cell MC is stopped. The snub switch S2 may include, for example, an n-type MOS field-effect transistor.

[0090] The sense amplifier switch S3 is set to an off state when data is read from the memory cell MC based on the signal O2 output from the delay circuit 52. Conversely, it is set to an on state when no data is read from the memory cell MC. The sense amplifier switch S3 is connected between the word line WL (or the memory cell MC) and the sense amplifier SA. The sense amplifier switch S3 sets the connection between the word line WL and the sense amplifier SA to either an on or off state based on the signal O2 from the delay circuit 52. The sense amplifier switch S3 may include, for example, an n-type MOS field-effect transistor.

[0091] Furthermore, the input-output relationship of the positive and negative input terminals of comparator CP, the number of inverter stages included in delay circuit 52, and the polarity of the voltages used to set the pre-charge switch S1, absorption switch S2, and sense amplifier switch S3 to either connected or disconnected states can be arbitrarily set as long as the configuration is valid. For example, when the input-output relationship of the positive and negative input terminals of comparator CP is reversed, the number of inverter stages in delay circuit 52 is set to an odd number.

[0092] 1.2 Read operation of magnetic storage device

[0093] Reference Figure 8 The readout operation of the magnetic storage device 1 in the first embodiment will be described. Figure 8 This is a graph showing the voltage changes of the storage cell MC and the diode D1 during the read operation of the magnetic storage device 1. Figure 8 In the diagram, the horizontal axis represents time, and the vertical axis represents voltage.

[0094] The voltage Vm of the memory cell MC is the voltage charged (or held) in the memory cell MC (or selector element SE) and the word line WL. In other words, the voltage Vm of the memory cell MC is obtained by subtracting the voltage of the bit line BL from the voltage of the word line WL. The read operation is controlled by the control circuit 13 and the read circuit 17.

[0095] First, a pre-charge current Ipc is supplied to the memory cell MC through a constant current source CS. As a result, the voltage Vm of the memory cell MC rises. When the voltage Vm of the memory cell MC rises to the threshold voltage Vth of the selector element SE at time t1, the selector element SE becomes on, and the cell current Im begins to flow in the memory cell MC.

[0096] Here, when the selector element SE is turned on, due to the quick-return characteristic of the selector element SE, the voltage Vm that has risen to the threshold voltage Vth drops sharply. On the other hand, through the reverse current protection function of the diode, the voltage Vd of the diode D1 maintains the peak voltage before the voltage Vm drops, i.e., the threshold voltage Vth.

[0097] At time t2, the peak detection circuit 51 detects that the voltage Vm of the memory cell MC is lower than the voltage Vd of the diode D1, that is, it detects that the voltage Vm of the memory cell MC has reached the threshold voltage Vth of the selector element SE. Corresponding to "the voltage Vm has reached the threshold voltage Vth", the control circuit 13 sets the precharge switch S1 to the off state. Thus, the supply of precharge current Ipc is stopped, preventing excessive precharge current Ipc from being supplied to the memory cell MC.

[0098] Then, after a predetermined delay time Dt has elapsed since the detected voltage Vm reached the threshold voltage Vth, the control circuit 13 reads out the storage cell MC at time t3.

[0099] The above-mentioned processes—supplying the pre-charge current Ipc, detecting when the voltage Vm of the storage cell MC reaches the threshold voltage Vth, stopping the supply of the pre-charge current Ipc, and reading out the storage cell MC—are performed for each storage cell.

[0100] also, Figure 8 The voltage of the memory cell MC at time t4 shown is the aforementioned holding voltage Vh. The holding voltage Vh is the voltage at which, after the voltage Vm of the memory cell MC reaches the threshold voltage Vth and the cell current Im begins to flow, the absorption switch S2 is kept connected until the cell current Im, i.e., the discharge current, no longer flows. The control circuit 13 can also wait until the voltage Vm of the memory cell MC becomes the holding voltage Vh, and then read the memory cell MC that has the holding voltage Vh.

[0101] The following is for reference Figures 9 to 13 The readout operation of the magnetic storage device 1 according to the first embodiment will be described in detail. Figure 9 This is a flowchart illustrating the read operation of the magnetic storage device 1. Figures 10 to 13 It is a graph showing the state of the switch and the flow of current during the readout operation, as well as the voltage changes of voltage Vm and voltage Vd.

[0102] First, the readout circuit 17 supplies a pre-charge current Ipc(S1) to the memory cell MC through a constant current source CS.

[0103] Specifically, such as Figure 10 As shown in (a), at time t0, the readout circuit 17 sets the precharge switch S1, the absorption switch S2, and the sense amplifier switch S3 to the connected state. Consequently, a precharge current Ipc is supplied from the constant current source CS to the memory cell MC, charging the memory cell MC (or the selector element SE) and the word line WL. Figure 10 As shown in (b), the voltage Vm of the memory cell MC and the voltage Vd of the diode D1 rise similarly. Furthermore, at this point in time, the voltage Vm of the memory cell MC does not reach the threshold voltage Vth of the selector element SE.

[0104] Next, the voltage Vm of the memory cell MC rises due to the supply of the pre-charge current Ipc, as... Figure 11 As shown in (b), at time t1, the voltage Vm of the memory cell MC reaches the threshold voltage Vth of the selector element SE. When the voltage Vm of the memory cell MC reaches the threshold voltage Vth, the selector element SE switches to the ON state, as shown in (b). Figure 11 As shown in (a), the cell current Im begins to flow in the storage cell MC.

[0105] Next, the peak detection circuit 51 detects that the voltage Vm of the memory cell MC has reached the threshold voltage Vth of the selector element SE (S2).

[0106] Specifically, the voltage Vm of the memory cell MC is input to the positive input terminal of the comparator CP via diode D1. That is, the voltage Vm of the memory cell MC is input to the anode of diode D1, and the voltage Vd output from the cathode of diode D1 is input to the positive input terminal of the comparator CP. On the other hand, the voltage Vm of the memory cell MC is input to the negative input terminal of the comparator CP.

[0107] When the voltage Vm of the storage cell MC reaches the threshold voltage Vth of the selector element SE, the selector element SE switches to the ON state. Therefore, as... Figure 12As shown in (b), after time t1, the voltage Vm drops sharply due to the quiescent characteristic of the selector element SE. On the other hand, the voltage Vd on the cathode side of diode D1 (or the voltage at the positive input terminal of comparator CP) remains at the threshold voltage Vth due to the reverse current protection function of diode D1.

[0108] At time t2, comparator CP compares the voltage Vd input to the positive input terminal with the voltage Vm input to the negative input terminal. Since voltage Vd is higher than voltage Vm, comparator CP outputs "H" as signal O1. The "H" in signal O1 indicates that the voltage Vm of memory cell MC has reached the threshold voltage Vth.

[0109] Next, when the peak detection circuit 51 detects that the voltage Vm of the storage cell MC has reached the threshold voltage Vth, the readout circuit 17 stops supplying the pre-charge current Ipc to the storage cell MC according to the command from the control circuit 13 corresponding to the detection (S3).

[0110] Specifically, the signal O1 output from the comparator CP of the peak detection circuit 51 is sent to the control circuit 13. Upon receiving "H" as signal O1, the control circuit 13 sends a signal to the readout circuit 17 to switch the pre-charge switch S1 to the off state. The readout circuit 17 then, based on the signal from the control circuit 13, such as... Figure 12 As shown in (a), the precharge switch S1 is set to the off state. The absorption switch S2 and the sensing amplifier switch S3 remain connected.

[0111] Therefore, the supply of pre-charge current Ipc from the constant current source CS to the memory cell MC is stopped. However, the cell current Im continues to flow from the memory cell MC and the word line WL through the snub switch S2 to the ground voltage node. The voltage Vm of the memory cell MC is lower than the threshold voltage Vth due to the quiescent characteristic, and further decreases due to the flow of cell current Im.

[0112] Next, after a predetermined delay time Dt has elapsed since the voltage Vm of the memory cell MC was detected to have reached the threshold voltage Vth, the readout circuit 17 stops the cell current Im flowing from the memory cell MC and the word line WL (S4).

[0113] Specifically, the signal O1 output from comparator CP is input to delay circuit 52. Delay circuit 52 delays the received signal O1 by a predetermined delay time Dt, and outputs signal O2 to the control terminals of absorption switch S2 and sense amplifier switch S3. Figure 13As shown in (a), the absorption switch S2 changes from the connected state to the disconnected state when it receives "H" as signal O2. Similarly, the sensing amplifier switch S3 changes from the connected state to the disconnected state when it receives "H" as signal O2. Thus, as Figure 13 As shown in (a) and (b), at time t3, the cell current Im from the memory cell MC and the word line WL stops. Furthermore, the voltage Vm of the memory cell MC at this time is maintained by the sense amplifier SA.

[0114] Next, the readout circuit 17 performs the readout of the memory cell MC (S5).

[0115] Specifically, the sensing amplifier SA compares the voltage Vm of the storage cell MC at time t3 with the reference voltage Vref, and determines the data stored in the storage cell MC based on the comparison result.

[0116] 1.3 Effects of the first embodiment

[0117] According to the magnetic storage device 1 of the first embodiment, it is possible to reduce discharge defects and read interference defects during the read operation, thereby improving the operation performance.

[0118] The effects of the implementation method will be explained below.

[0119] For example, in the read operation of a memory cell in a magnetic storage device, the memory cell is charged to a pre-charge voltage Vpc, and then discharged at the pre-charge voltage Vpc. The resistance value of the variable resistor is then read based on the voltage of the memory cell after discharge, or the voltage of the memory cell during discharge. Furthermore, the data is determined based on the read resistance value.

[0120] Therefore, the pre-charge voltage Vpc applied to each memory cell needs to be greater than or equal to the threshold voltage Vth of the selector element in each memory cell. Otherwise, a discharge defect will occur where the pre-charge voltage Vpc applied to the memory cell does not discharge.

[0121] However, the threshold voltage Vth of the selector element in a memory cell varies for each selector element. Therefore, in order to set the precharge voltage Vpc to be higher than the threshold voltage Vth of all selector elements in the memory cells, the precharge voltage Vpc needs to be set to a voltage that is higher than the average threshold voltage.

[0122] On the other hand, if the precharge voltage Vpc is set too high above the threshold voltage Vth of the selector element, the discharge current, i.e., the cell current, increases, which can sometimes cause read interference problems. That is, if a voltage higher than the originally required precharge voltage Vpc is applied to the memory cell, read interference problems may occur. As described above, a trade-off between discharge problems and read interference problems arises during the read operation.

[0123] In contrast, in the first embodiment, a constant current source CS and a peak detection circuit 51 are provided. The constant current source CS supplies a pre-charge current Ipc to the memory cell MC. The peak detection circuit 51 detects whether the voltage Vm of the memory cell MC has reached the threshold voltage Vth of the selector element SE. In other words, it detects whether the voltage Vm charged to the memory cell MC (or the selector element SE) and the word line WL has risen to the threshold voltage Vth of the selector element SE.

[0124] Therefore, the peak detection circuit 51 detects the timing when the voltage Vm of the memory cell MC reaches the threshold voltage Vth of the selector element SE (hereinafter referred to as the threshold arrival timing). Based on the threshold arrival timing, the control circuit 13 switches the precharge switch S1 to the off state, stopping the supply of precharge current Ipc. This prevents the supply of excessive precharge current Ipc to the memory cell MC. Furthermore, it prevents the voltage Vm of the memory cell MC from charging to a voltage higher than the threshold voltage Vth.

[0125] In the first embodiment, the voltage Vm charged to the storage cell MC can be set to the threshold voltage Vth of the selector element SE of the storage cell MC. In other words, the pre-charge voltage Vpc (i.e., voltage Vm) can be set to the threshold voltage Vth of the selector element SE for each selector element in a manner that matches the deviation of the threshold voltage Vth of the selector element SE of each storage cell MC.

[0126] Therefore, it is not necessary to set the pre-charge voltage Vpc to a voltage that is higher than the average threshold voltage, which can reduce the occurrence of poor discharge where the discharge current (cell current) does not flow in the memory cell MC.

[0127] Furthermore, since it is possible to prevent the application of a voltage higher than the originally required pre-charge voltage Vpc to the memory cell MC, it is possible to suppress the increase in cell current flowing in the variable resistive element (e.g., MTJ element) VR of the memory cell MC, thereby reducing the occurrence of read interference problems.

[0128] Furthermore, in the first embodiment, as described above, the cumulative current to the variable resistor element VR can be reduced, thus reducing the current load on the variable resistor element VR during readout operations and extending the lifespan of the variable resistor element VR until fatigue.

[0129] Furthermore, in the first embodiment, during the read operation, the discharge current (cell current) is stopped midway through the discharge after the memory cell MC (and word line WL) is charged to the pre-charge voltage Vpc, and the read operation is performed. Therefore, compared with the case where the read operation is performed after the voltage of the memory cell MC reaches the holding voltage Vh without stopping the discharge current, the time required for the read operation can be shortened.

[0130] As described above, the magnetic storage device 1 according to the first embodiment can improve operational performance.

[0131] 2. Second Implementation Method

[0132] Next, the magnetic storage device according to the second embodiment will be described. In the second embodiment, the signal O1 output from the peak detection circuit 51 is input to the control terminal of the precharge switch S1 to control the opening and closing state of the precharge switch S1. The configuration of the storage system, the circuit configuration of the storage cell array, and the structure of the storage cell array in the second embodiment are the same as those in the first embodiment described above. In the second embodiment, the differences from the first embodiment will be mainly explained.

[0133] 2.1 Composition of Magnetic Storage Devices

[0134] 2.1.1 Circuit configuration of the readout circuit

[0135] Reference Figure 14 An example of the circuit configuration of the readout circuit 17 provided in the magnetic storage device 1 of the second embodiment will be described. Figure 14 This is a circuit diagram showing the configuration of the readout circuit 17 in the second embodiment.

[0136] like Figure 5 As shown, in the readout circuit 17 of the second embodiment, the output terminal of the comparator CP of the peak detection circuit 51 is connected to the control terminal of the precharge switch S1. That is, the signal O1 output from the comparator CP is input to the control terminal of the precharge switch S1. Other configurations are the same as those of the readout circuit 17 in the first embodiment.

[0137] 2.2 Read operation of magnetic storage device

[0138] Next, refer to Figure 9 The readout operation of the magnetic storage device 1 in the second embodiment will be described.

[0139] First, the readout circuit 17 supplies a pre-charge current Ipc to the memory cell MC via a constant current source CS (S1). Due to the supply of the pre-charge current Ipc, the voltage Vm of the memory cell MC rises, eventually reaching the threshold voltage Vth of the selector element SE. The readout circuit 17 detects that the voltage Vm of the memory cell MC has reached the threshold voltage Vth of the selector element SE (S2). This is the same as in the first embodiment described above.

[0140] Next, when the peak detection circuit 51 detects that the voltage Vm of the memory cell MC has reached the threshold voltage Vth, the readout circuit 17 stops supplying the pre-charge current Ipc to the memory cell MC in response to the detection (S3).

[0141] Specifically, the signal O1 output from the comparator CP of the peak detection circuit 51 is input to the control terminal of the precharge switch S1. When the precharge switch S1 receives "H" as signal O1, it changes from the connected state to the disconnected state. The absorption switch S2 and the sensing amplifier switch S3 remain connected.

[0142] Therefore, the supply of pre-charge current Ipc to the memory cell MC stops, and the cell current Im flows from the memory cell MC and word line WL to the ground voltage node via the absorption switch S2. The voltage Vm of the memory cell MC is lower than the threshold voltage Vth due to the quiescent characteristic, and further decreases due to the flow of cell current Im.

[0143] Next, similar to the first embodiment, after a predetermined delay time Dt elapsed since the voltage Vm of the memory cell MC was detected to have reached the threshold voltage Vth, the readout circuit 17 stops the cell current flowing from the memory cell MC and the word line WL (S4). Then, the readout circuit 17 performs the readout of the memory cell MC (S5).

[0144] 2.3 Variation Example

[0145] Next, a modified example of the magnetic storage device according to the second embodiment will be described. In the modified example, the peak detection circuit 51 has a configuration that takes into account the forward voltage drop (forward voltage drop) of the diode D1.

[0146] 2.3.1 Circuit configuration of the readout circuit

[0147] Reference Figure 15 as well as Figure 16 An example of the circuit configuration of the readout circuit 17 provided in the magnetic storage device 1 of the modified embodiment 2 will be described. Figure 15 This is a circuit diagram showing the configuration of the readout circuit 17 in a modified example. Figure 16This is a graph showing the voltage Vm of the storage cell MC and the voltage changes of the diodes D1 Vk and Vd during the readout operation of the magnetic storage device 1 in the modified example.

[0148] Here, in diode D1, a voltage drop is generated as a forward voltage decrease, which is assumed to produce a voltage drop Vf. To compensate for this voltage drop Vf, in the peak detection circuit 51 of the modified example, as follows... Figure 15 As shown, a constant voltage source VF is positioned between the cathode of diode D1 and the positive input terminal of comparator CP. The constant voltage source VF generates a voltage equivalent to the voltage drop Vf in diode D1. Let Vk be the voltage between the cathode of diode D1 and the constant voltage source VF, and let Vd be the voltage between the constant voltage source VF and the positive input terminal of comparator CP.

[0149] The voltage Vm of the memory cell MC is input to the anode of diode D1. Diode D1 causes the voltage Vm to decrease to voltage Vf, and a voltage Vk is output from the cathode of diode D1. The voltage Vk output from diode D1 is then boosted by a constant voltage source VF to voltage Vf, and this voltage Vd is input to the positive input terminal of comparator CP. Thus, as... Figure 16 As shown, the voltage Vd input to the positive input terminal of the comparator CP becomes the same level as the voltage Vm until the voltage Vm of the storage cell MC reaches the threshold voltage Vth.

[0150] The other circuit configurations and readout operations are the same as in the second embodiment described above.

[0151] 2.4 Effects of the second embodiment

[0152] The magnetic storage device 1 according to the second embodiment, like the one in the first embodiment, can reduce poor discharge and poor read interference during the read operation, and can improve the operation performance.

[0153] In the second embodiment, in addition to the effects of the first embodiment described above, the following effects can also be obtained.

[0154] In the configuration of the second embodiment, the signal O1 output from the comparator CP of the peak detection circuit 51 is input to the control terminal of the pre-charge switch S1. Furthermore, the signal O1 is used to switch the pre-charge switch S1 between its connected and disconnected states. Therefore, in the second embodiment, the circuit for controlling the pre-charge switch S1 can be simplified compared to the first embodiment.

[0155] Furthermore, in the modified example, since the forward voltage drop of diode D1 can be compensated, a more suitable circuit configuration for installation can be provided.

[0156] 3. Other

[0157] In this specification, "connection" means electrical connection, excluding the possibility of connection via other components. The non-magnetic layer 41 may also be referred to as an "oxide layer". The elements contained in the layers of the MTJ element can be determined, for example, by using electron energy loss spectroscopy (EELS) performed with a scanning transmission electron microscope (STEM).

[0158] Several embodiments of the present invention have been described, but these embodiments are provided as examples and are not intended to limit the scope of the invention. These embodiments can be implemented in a wide variety of other ways, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their variations are included within the scope and spirit of the invention, as well as within the scope of the invention as described in the claims and its equivalents.

Claims

1. A magnetic storage device comprising: a storage unit including a variable resistance element and a selector element; a current source that supplies a first current to the storage unit; a first switch connected between the storage unit and the current source; a second switch connected between a ground voltage node supplied with a ground voltage and the storage unit; a detection circuit including a comparator and a diode, a first voltage charged to the storage unit being input to a first input terminal of the comparator via the diode, the first voltage being input to a second input terminal of the comparator; a sense amplifier that compares the first voltage charged to the storage unit with a second voltage; and a third switch connected between the storage unit and the sense amplifier.

2. The magnetic storage device according to claim 1, wherein the detection circuit outputs a first signal when the voltage input to the first input terminal is higher than the first voltage input to the second input terminal.

3. The magnetic storage device according to claim 2, wherein the selector element transitions to an on state when the first voltage rises to a threshold voltage, and wherein the first voltage drops to a voltage lower than the threshold voltage after rising to the threshold voltage.

4. The magnetic storage device according to claim 3, wherein the detection circuit detects that the first voltage drops to a voltage lower than the threshold voltage after rising to the threshold voltage, and outputs the first signal.

5. The magnetic storage device according to claim 2, wherein the first switch is cut off between the storage unit and the current source when the first signal is output from the detection circuit.

6. The magnetic storage device according to claim 2, wherein an output terminal of the detection circuit is electrically connected to the first switch, and wherein the first switch cuts off between the storage unit and the current source according to the first signal when the first signal is output from the detection circuit.

7. The magnetic storage device according to claim 1, further comprising a delay circuit electrically connected to an output terminal of the detection circuit, wherein an output terminal of the delay circuit is electrically connected to the second switch and the third switch, wherein the detection circuit outputs a first signal when the voltage input to the first input terminal is higher than the first voltage input to the second input terminal, and wherein the delay circuit outputs a second signal to the second switch and the third switch by delaying the first signal by a first delay time.

8. The magnetic storage device according to claim 1, further comprising: a first wiring connected to one end of the storage unit; and a second wiring connected to the other end of the storage unit, wherein the first voltage is a voltage between the first wiring and the second wiring.

9. The magnetic storage device according to claim 1, further comprising: a first wiring connected to one end of the storage unit; and a second wiring connected to the other end of the storage unit, wherein the first wiring has one end to which the selector element is connected, wherein the first current is supplied to the first wiring from the current source, and wherein the first voltage is a voltage held by the first wiring. ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ 10. The magnetic memory device according to claim 1, the variable resistance element includes an MTJ element, i.e., a magnetic tunnel junction element.

11. A magnetic memory device comprising: a memory cell including a variable resistance element and a selector element; a current source that supplies a first current to the memory cell; a first switch connected between the memory cell and the current source; a second switch connected between a ground voltage node supplied with a ground voltage and the memory cell; a detection circuit that outputs a first signal when a second current flows from the memory cell to the second switch; a sense amplifier that compares a first voltage charged to the memory cell with a second voltage; a third switch connected between the memory cell and the sense amplifier.

12. The magnetic memory device according to claim 11, the second current flows when the selector element is set to an on state.

13. The magnetic memory device according to claim 11, the selector element has a threshold voltage, the second current flows when the first voltage of the memory cell rises to the threshold voltage.

14. The magnetic memory device according to claim 11, the selector element is turned to an on state when the first voltage rises to a threshold voltage, the first voltage falls to a voltage lower than the threshold voltage after rising to the threshold voltage.

15. The magnetic memory device according to claim 14, the detection circuit detects that the first voltage falls to a voltage lower than the threshold voltage after rising to the threshold voltage, and outputs the first signal.

16. The magnetic memory device according to claim 11, the detection circuit includes a comparator and a diode, the first voltage is input to a first input terminal of the comparator via the diode, and the first voltage is input to a second input terminal of the comparator.

17. The magnetic memory device according to claim 11, the memory cell and the current source are cut off by the first switch when the first signal is output from the detection circuit.

18. The magnetic memory device according to claim 11, an output terminal of the detection circuit is electrically connected to the first switch, the memory cell and the current source are cut off by the first switch according to the first signal when the first signal is output from the detection circuit.

19. The magnetic memory device according to claim 11, further comprising a delay circuit electrically connected to an output terminal of the detection circuit, an output terminal of the delay circuit is electrically connected to the second switch and the third switch, the detection circuit outputs the first signal to the delay circuit, the delay circuit outputs a second signal to the second switch and the third switch by delaying the first signal by a first delay time.

20. The magnetic memory device according to claim 11, further comprising: a first wiring connected to one end of the memory cell; and a second wiring connected to the other end of the memory cell, the first voltage is a voltage between the first wiring and the second wiring. ​

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