Storage device

Abstract

In a memory device, a second conductor is positioned closer to a first direction than a first conductor. The third conductor extends in the first direction, intersects the first conductor and the second conductor, and has a first end and a second end, the first end being located closer to the first direction than the second end. The first memory cell is connected to the first conductor and the third conductor. The second memory cell is connected to the second conductor and the third conductor. The first switch is connected with the first end of the third conductor. The second switch is connected with the second end of the third conductor. In a case where data is read out from the memory cell, the first switch is maintained on and the second switch is maintained off. In a case where data is read out from the second memory cell, the second switch is maintained on and the first switch is maintained off.

Description

Technical Field

[0001] The implementation methods generally involve storage devices. Background Technology

[0002] A storage device is known to use a component with dynamically variable resistance to store data. The requirement is that the storage device can write data within a short time. Summary of the Invention

[0003] It provides a storage device that suppresses malfunctions.

[0004] A storage device according to one embodiment includes a first conductor, a second conductor, a third conductor, a first storage cell, a second storage cell, a first switch, and a second switch. The second conductor is located further in a first direction than the first conductor. The third conductor extends along the first direction, intersecting with the first and second conductors, and has a first end and a second end, the first end being located further in the first direction than the second end. The first storage cell is connected to the first and third conductors. The second storage cell is connected to the second and third conductors. The first switch is connected to the first end of the third conductor. The second switch is connected to the second end of the third conductor. When data is read from the first storage cell, the first switch is kept on, and the second switch is kept off. When data is read from the second storage cell, the second switch is kept on, and the first switch is kept off. Attached Figure Description

[0005] Figure 1 This is a function block representing the storage device in the first embodiment.

[0006] Figure 2 This is a circuit diagram of the storage cell array of the storage device according to the first embodiment.

[0007] Figure 3 This is a perspective view of a portion of the storage cell array of the storage device according to the first embodiment.

[0008] Figure 4 A cross-section showing a construction example of the storage cell of the storage device according to the first embodiment.

[0009] Figure 5 Functional blocks and constituent elements representing a portion of the storage device in the first embodiment.

[0010] Figure 6 This shows the layout and circuit configuration of a portion of the storage device according to the first embodiment.

[0011] Figure 7The components of the row selection circuit of the storage device according to the first embodiment are shown.

[0012] Figure 8 The components of the column selection circuit of the storage device in the first embodiment are shown.

[0013] Figure 9 Examples illustrating the classification of storage units in the storage device of the first embodiment.

[0014] Figure 10 This is a circuit diagram of the readout circuit of the storage device according to the first embodiment.

[0015] Figure 11 An example representing a state during the operation of the storage device in the first embodiment.

[0016] Figure 12 An example representing a state during the operation of the storage device in the first embodiment.

[0017] Figure 13 Examples illustrating the classification of storage units in the storage device of the second embodiment.

[0018] Figure 14 An example representing a state during the operation of the storage device in the second embodiment.

[0019] Figure 15 An example representing a state during the operation of the storage device in the second embodiment.

[0020] Figure 16 An example representing a state during the operation of the storage device in the second embodiment.

[0021] Figure 17 Functional blocks and constituent elements representing a portion of the storage device in the third embodiment.

[0022] Figure 18 The components of the column selection circuit of the storage device in the third embodiment are shown.

[0023] Figure 19 An example representing a state during the operation of the storage device in the third embodiment.

[0024] Figure 20 Examples illustrating the classification of storage units in the storage device of the third embodiment.

[0025] Figure 21 An example representing a state during the operation of the storage device in the fourth embodiment.

[0026] Figure 22 An example representing a state during the operation of the storage device in the fourth embodiment.

[0027] Figure 23 An example representing a state during the operation of the storage device in the fourth embodiment. Detailed Implementation

[0028] The embodiments are described below with reference to the accompanying drawings. To distinguish between multiple components having substantially the same function and structure in a particular embodiment or different embodiments, numbers or words are sometimes added to the end of the reference numerals in the drawings. In subsequent embodiments of a previously described embodiment, the differences from the previously described embodiment are mainly described. All descriptions of a particular embodiment, unless expressly stated or clearly excluded, also apply to the description of another embodiment.

[0029] In this specification and claims, the term "connected to" or "linked" to other second elements includes the first element being directly connected to the second element, or being connected to the second element always or selectively via an element that is conductive.

[0030] The implementation method is described below using an XYZ orthogonal coordinate system. Sometimes the positive direction of the vertical axis of the graph is called the top, and the negative direction is called the bottom. Sometimes the positive direction of the horizontal axis of the graph is called the right side, and the negative direction is called the left side. That is, in a top view representing the XY plane (XY plane view (hereinafter the same)), the top refers to the +Y direction, the bottom refers to the -Y direction, the right side refers to the +X direction, and the left side refers to the -X direction.

[0031] 1. First Implementation Method

[0032] 1.1. Composition (Structure)

[0033] Figure 1 This is a functional block representing the storage device of the first embodiment. Storage device 1 is a device for storing data. Storage device 1 uses a stack of magnetic bodies exhibiting variable resistance to store data. For example... Figure 1 As shown, the storage device 1 includes a storage cell array 11, an input / output circuit 12, a control circuit 13, a row selection circuit 14, a column selection circuit 15, a write circuit 16, a read circuit 17, and a voltage generation circuit 18.

[0034] The storage cell array 11 is a collection of multiple storage cells MC arranged in a row. Each storage cell MC can store data non-volatilely. Multiple word lines WL and multiple bit lines BL are located in the storage cell array 11. Each storage cell MC is connected to one word line WL and one bit line BL. The word line WL is associated with a row (low). The bit line BL is associated with a column (column). A storage cell MC is determined by selecting a row and selecting a column.

[0035] Input / output circuit 12 is a circuit for inputting and outputting data and signals. Input / output circuit 12 receives control signals CNT, instructions CMD, address information ADD, and data DAT from an external source of storage device 1, such as a memory controller. Input / output circuit 12 outputs data DAT. Data DAT is called "written data" when data is written to storage device 1. Data DAT is called "read data" when data is read from storage device 1.

[0036] The voltage generation circuit 18 is a circuit that generates voltages of various magnitudes based on the voltage received from the external storage device 1. The voltage generation circuit 18 outputs a voltage of a certain magnitude for data reading. The voltage generation circuit 18 also outputs a voltage of a certain magnitude for data writing.

[0037] The write circuit 16 controls the writing of data to the storage unit MC. The write circuit 16 receives write data DAT from the input / output circuit 12 and receives the voltage for data writing from the voltage generation circuit 18. Based on the control of the control circuit 13 and the write data DAT, the write circuit 16 outputs the voltage and current for data writing.

[0038] The readout circuit 17 is a circuit that controls the reading of data from the storage unit MC. The readout circuit 17 receives the voltage for data reading from the voltage generation circuit 18. Based on the control of the control circuit 13, the readout circuit 17 uses the voltage used for data reading to determine the data to be stored in the storage unit MC. The determined data, as readout data DAT, is transferred to the input / output circuit 12. The readout circuit 17 includes a sense amplifier.

[0039] Row selection circuit 14 is a circuit that selects the row of memory cell MC. Row selection circuit 14 receives address information ADD from input / output circuit 12. Row selection circuit 14 receives voltage for data writing from write circuit 16. Row selection circuit 14 receives voltage for data reading from read circuit 17. During data writing, row selection circuit 14 transfers the voltage for data writing, causing one or more word lines WL associated with the row determined by the received address information ADD to be selected. During data reading, row selection circuit 14 transfers the voltage for data reading, causing one or more word lines WL associated with the row determined by the received address information ADD to be selected.

[0040] Column selection circuit 15 is a circuit for selecting columns of memory cell MC. Column selection circuit 15 receives address information ADD from input / output circuit 12. Column selection circuit 15 receives voltage for data writing from write circuit 16. Column selection circuit 15 receives voltage for data reading from read circuit 17. During data writing, column selection circuit 15 transfers the voltage for data writing, causing one or more bit lines BL associated with the column determined by the received address information ADD to be selected. During data reading, column selection circuit 15 transfers the voltage for data reading, causing one or more bit lines BL associated with the column determined by the received address information ADD to be selected.

[0041] Control circuit 13 is a circuit that controls the operation of storage device 1. Control circuit 13 receives control signal CNT and instruction CMD from input / output circuit 12. Based on the control signal CNT and instruction CMD, control circuit 13 controls write circuit 16 and read circuit 17. Specifically, control circuit 13 controls write circuit 16 to supply voltage received from voltage generation circuit 18 to row selection circuit 14 and column selection circuit 15 during data writing to storage cell MC. Control circuit 13 controls read circuit 17 to supply voltage received from voltage generation circuit 18 to row selection circuit 14 and column selection circuit 15 during data reading from storage cell MC.

[0042] Figure 2 This is a circuit diagram of the storage cell array of the storage device according to the first embodiment. (Example) Figure 2 As shown, the M+1 (M is a positive integer) root word line WL (WL_0, WL_1, ..., WL_M) and the N+1 (N is a positive integer) root bit line BL (BL_0, BL_1, ..., BL_N) are located in the memory cell array 11.

[0043] Each memory cell (MC) is connected to a word line (WL) and a bit line (BL). Each memory cell (MC) contains an MTJ element (MTJ) and a switching element (SE). In each memory cell (MC), the MTJ element (MTJ) and the switching element (SE) are connected in series. The switching element (SE) of each memory cell (MC) is connected to a word line (WL). The MTJ element (MTJ) of each memory cell (MC) is connected to a bit line (BL).

[0044] MTJ devices exhibit the tunneling magnetoresistive effect, such as those containing a magnetic tunnel junction (MTJ). MTJ devices are also known as magnetoresistive effect devices. MTJ devices are variable resistance devices capable of switching between low-resistance and high-resistance states. MTJ devices utilize the difference between these two resistance states to store 1 bit of data. For example, an MTJ device stores "0" data in a low-resistance state and "1" data in a high-resistance state.

[0045] A switching element SE is a component that electrically connects or disconnects its two ends. The switching element SE has two terminals. When the voltage applied between the two terminals is less than a first threshold, the switching element SE is in a high-resistance state, for example, a non-conductive state (open state). If the voltage applied between the two terminals rises and exceeds the first threshold, the switching element SE becomes a low-resistance state, for example, a conductive state (closed state). If the voltage applied between the two terminals of the low-resistance switching element SE decreases and falls below a second threshold, the switching element SE becomes a high-resistance state. The switching element SE also has the same function as described above—switching between high-resistance and low-resistance states based on the magnitude of the voltage applied in the first direction—for a second direction opposite to the first direction. That is, the switching element SE is a bidirectional switching element. By controlling the on or off state of the switching element SE, the supply of current to the MTJ element MTJ connected to the switching element SE can be controlled, i.e., the selection or non-selection of the MTJ element MTJ can be controlled.

[0046] Figure 3 This is a perspective view of a portion of the storage cell array of the storage device according to the first embodiment. Figure 3 As shown, there are multiple conductors 21 and multiple conductors 22.

[0047] Conductors 21 have a straight line shape and extend along the x-axis. Conductors 21 are arranged along the y-axis. The y-axis is orthogonal to the x-axis. Each conductor 21 functions as a word line WL.

[0048] Conductor 22 is positioned above conductor 21 on the z-axis. The z-axis is orthogonal to the x-axis and y-axis. Conductors 22 have a straight line shape, extending along the y-axis and arranged along the x-axis. Each conductor 22 functions as a bit line BL.

[0049] A memory cell MC is provided at the intersection of conductor 21 and conductor 22. Each memory cell MC includes a structure that functions as a switching element (SE) and a structure that functions as an intermediate switching element (MTJ). The structures that function as the switching element (SE) and the structures that function as the MTJ each include one or more layers. In one example, the structure that functions as the MTJ is located on the upper surface of the structure that functions as the switching element (SE). The lower surface of the memory cell MC is in contact with the upper surface of a conductor 21. The upper surface of the memory cell MC is in contact with the lower surface of a conductor 22.

[0050] Figure 4 A cross-section showing a construction example of the storage cell of the storage device according to the first embodiment. For example... Figure 4 As shown, the switching element SE includes a variable resistive material 32. The variable resistive material 32 is a material exhibiting dynamically variable resistance, for example, having a layered shape. The variable resistive material 32 is a two-terminal switching element, with the first terminal of the two terminals being one of the upper and lower surfaces of the variable resistive material 32, and the second terminal of the two terminals being the other of the upper and lower surfaces of the variable resistive material 32. When the voltage applied between the two terminals is less than a certain first threshold (threshold voltage Vth), the variable resistive material is in a "high resistance" state, for example, a non-conductive state. If the voltage applied between the two terminals rises and becomes above the first threshold, the variable resistive material becomes in a "low resistance" state, for example, a conductive state. If the voltage applied between the two terminals of the variable resistive material 32 in the low resistance state decreases and becomes below a second threshold, the variable resistive material becomes in a high resistance state. The variable resistive material 32 includes an insulator and a dopant introduced into the insulator by ion implantation. The insulator, for example, includes an oxide and contains SiO2 or a material substantially composed of SiO2. The dopant, for example, includes arsenic (As) and germanium (Ge). Furthermore, in this embodiment, the variable resistor material 32 composed of the above-described components has been described, but it is not limited to these components. The expression "substantially become (or constitute)" and similar expressions mean that the constituent element that "substantially becomes" is allowed to contain undesirable impurities.

[0051] The switching element SE may also include a lower electrode 31 and an upper electrode 33. Figure 4 This illustrates an example where the variable resistive material 32 is located on the upper surface of the lower electrode 31, and the upper electrode 33 is located on the upper surface of the variable resistive material 32.

[0052] The MTJ component includes a strongly magnetic layer 35, an insulating layer 36, and a strongly magnetic layer 37. For example, ... Figure 4 As shown, the insulating layer 36 is located on the upper surface of the strongly magnetic layer 35, and the strongly magnetic layer 37 is located on the upper surface of the insulating layer 36.

[0053] The strong magnetic layer 35 is a layer of material exhibiting strong magnetism. The strong magnetic layer 35 has an easy magnetization axis along the interface extending through the strong magnetic layer 35, the insulating layer 36, and the strong magnetic layer 37. For example, it has an easy magnetization axis at an angle greater than 45° and less than 90° relative to the interface, or it has an easy magnetization axis perpendicular to the interface. The orientation of the magnetization of the strong magnetic layer 35 is designed to remain unchanged even when data is read from and written to the memory cell MC. The strong magnetic layer 35 can function as a so-called reference layer. The strong magnetic layer 35 may also comprise multiple layers. Hereinafter, the strong magnetic layer 35 is sometimes referred to as the reference layer 35.

[0054] The insulating layer 36 is a layer of insulation. The insulating layer 36 may contain, for example, magnesium oxide (MgO) or be substantially composed of MgO, and functions as a so-called tunnel barrier.

[0055] The strong magnetic layer 37 is a layer of material exhibiting strong magnetism. The strong magnetic layer 37 may contain, for example, cobalt iron boron (CoFeB) or iron boride (FeB), or be substantially composed of CoFeB or FeB. The strong magnetic layer 37 has an easy magnetization axis along the interface penetrating the strong magnetic layer 35, the insulating layer 36, and the strong magnetic layer 37. For example, it may have an easy magnetization axis at an angle of 45° or more and 90° or less relative to the interface, or it may have an easy magnetization axis perpendicular to the interface. The orientation of the magnetization of the strong magnetic layer 37 can vary depending on the data written to the memory cell MC, and the strong magnetic layer 37 can function as a so-called memory layer. Hereinafter, the strong magnetic layer 37 is sometimes referred to as memory layer 37.

[0056] If the magnetization orientation of the storage layer 37 is parallel to the magnetization orientation of the reference layer 35, the MTJ element has a relatively low resistance. If the magnetization orientation of the storage layer 37 is antiparallel to the magnetization orientation of the reference layer 35, the MTJ element has a higher resistance than when the magnetization orientation of the storage layer 37 is parallel to the magnetization orientation of the reference layer 35. Hereinafter, the state in which the magnetization orientation of the strong magnetic layer 37 of a certain MTJ element is parallel to the magnetization orientation of the reference layer 35 is sometimes referred to as the MTJ element being in a "parallel state" or "P state". The state in which the magnetization orientation of the strong magnetic layer 37 of a certain MTJ element is antiparallel to the magnetization orientation of the reference layer 35 is sometimes referred to as the MTJ element being in an "antiparallel state" or "AP state".

[0057] If a current of magnitude Icp greater than or equal to a certain magnitude flows from storage layer 37 toward reference layer 35, then the magnetization orientation of storage layer 37 becomes parallel to the magnetization orientation of reference layer 35.

[0058] If a current of magnitude Icap greater than or equal to a certain magnitude flows from the reference layer 35 toward the storage layer 37, then the magnetization orientation of the storage layer 37 becomes antiparallel to the magnetization orientation of the reference layer 35.

[0059] MTJ components may also contain other layers.

[0060] Figure 5 Functional blocks and constituent elements representing a portion of the storage device in the first embodiment. For example... Figure 5 As shown, the readout circuit 17 is connected to the global word line GWL and the global bit line GBL.

[0061] The global word line GWL is connected to the row selection circuit 14. The row selection circuit 14 connects the global word line GWL to a word line WL selected by the address information ADD.

[0062] The global bit line GBL is connected to column select circuit 15. Column select circuit 15 connects the global bit line GBL to a bit line BL selected by address information ADD.

[0063] Figure 6 This shows the layout and circuit configuration of a portion of the storage device according to the first embodiment. Figure 6 The layout of conductors 21 and 22, and switches SX, SYL and SYU (described later) is shown, along with the circuit configuration of other constituent elements. Figure 6 This represents an example of eight conductors 21 and eight conductors 22, i.e., an example where M = N = 7. Figure 6 The following diagrams and descriptions are based on this example.

[0064] like Figure 6 As shown, for all cases where α is greater than or equal to 0 and less than M, the conductor 21_α, which functions as the word line WL_α, is located more in the Y direction if it has a larger α value. For all cases where β is greater than or equal to 0 and less than N, the conductor 22_β, which functions as the bit line BL_β, is located more in the X direction if it has a larger β value.

[0065] The row selection circuit 14 includes M+1 switches SX, or, based on the current example, 8 switches SX_0 to SX_7. Switches SX_0 to SX_7 are located further in the -X direction than conductor 21. For all cases where α is 0 or higher and 7 or lower, one end of switch SX_α is connected to the -X direction side of conductor 21_α via wiring (conductor). The other end of each of switches SX_0 to SX_7 is connected to the global word line GWL via wiring. Examples of each switch SX include an n-type MOSFET (Metal-Oxide Semiconductor Field Effect Transistor), a p-type MOSFET, and p-type and n-type MOSFETs connected in parallel.

[0066] The column selection circuit 15 includes N+1 switches SYL, or, based on the current example, eight switches SYL_0 to SYL_7. Switches SYL_0 to SYL_7 are located further in the -Y direction than conductor 21. For all cases where β is above 0 and below 7, one end of switch SYL_β is connected to the -Y direction side of conductor 22_β via wiring (conductor). The other end of each of switches SYL_0 to SYL_7 is connected to the global bit line GBL via wiring. Examples of switches SYL include n-type MOSFETs, p-type MOSFETs, and p-type and n-type MOSFETs connected in parallel.

[0067] The column selection circuit 15 includes N+1 switches SYU, that is, based on the current example, it includes 8 switches SYU_0 to SYU_7. Switches SYU_0 to SYU_7 are located further in the Y direction than conductor 21. For all cases where β is 0 or higher and 7 or lower, one end of switch SYU_β is connected to the Y-direction side of conductor 22_β via wiring (conductor). The other end of each of switches SYU_0 to SYU_7 is connected to the global bit line GBL via wiring. Examples of each switch SYU include n-type MOSFETs, p-type MOSFETs, and p-type and n-type MOSFETs connected in parallel.

[0068] Figure 7 The components of the row selection circuit of the storage device in the first embodiment are shown. For example... Figure 7As shown, switches SX_0 to SX_7 receive signals CX_0 to CX_7 respectively at the control terminal (or gate electrode). Switches SX_0 to SX_7 remain on or off based on signals CX_0 to CX_7. During the period when signals CX_0 to CX_7 have an assertion level logic (or the asserted logic level), switches SX_0 to SX_7 remain on. The assertion level logic for n-type MOSFETs is high. The assertion level logic for p-type MOSFETs is low.

[0069] Signals CX_0 to CX_7 are supplied by the decoder (decoder circuit) 141 in the row selection circuit 14. Decoder 141 receives address information ADD and decodes it. Decoder 141 outputs signals CX_0 to CX_7 with logic levels based on the decoding result.

[0070] Figure 8 The components of the column selection circuit of the storage device in the first embodiment are shown. For example... Figure 8 As shown, switches SYL_0 to SYL_7 receive signals CYL_0 to CYL_7 respectively at the control terminal (or, gate electrode). Switches SYL_0 to SYL_7 remain on or off based on signals CYL_0 to CYL_7. During the period when signals CYL_0 to CYL_7 have assertion level logic, switches SYL_0 to SYL_7 are respectively turned on.

[0071] Switches SYU_0 to SYU_7 receive signals CYU_0 to CYU_7 respectively at the control terminal (or gate electrode). Switches SYU_0 to SYU_7 remain on or off based on signals CYU_0 to CYU_7. During the period when signals CYU_0 to CYU_7 have assertion-level logic, switches SYU_0 to SYU_7 are respectively turned on.

[0072] Signals CYL_0 to CYL_7 and CYU_0 to CYU_7 are supplied by the decoder (decoder circuit) 151 in the column select circuit 15. The decoder 151 receives address information ADD and decodes the address information ADD. The decoder 151 outputs signals CYL_0 to CYL_7 and CYU_0 to CYU_7 with logic levels based on the decoding result.

[0073] Figure 9This section illustrates an example of classifying the storage cells of the storage device according to the first embodiment. The storage cells MC are classified into two groups. For example, when M / 2 conductors 21 are arranged in the positive direction and M / 2 conductors 21 are arranged in the negative direction, with the center of the conductor 22 on the y-axis as the starting point, for all cases where α is 0 or more and less than (M+1) / 2, the storage cell MC connected to conductor 21_α belongs to group G1. In other words, for all cases where β is 0 or more and less than N, if the distance from a storage cell MC to the switch SYL_β via a current path including a portion of conductor 22_β is shorter than the distance from the storage cell MC to the switch SYU_β via a current path including a portion of conductor 22_β, the storage cell MC belongs to group G1. Based on the current example, the storage cell MC connected to any one of conductors 21_0, 21_1, 21_2, and 21_3 belongs to group G1. That is, conductors 21_0, 21_1, 21_2, and 21_3 are closer to the end (lower end) on the -Y direction side than the end (upper end) on the Y direction side of conductor 22.

[0074] For all cases where α is (M+1) / 2 or greater and M is less than or equal to α, the memory cell MC connected to conductor 21_α belongs to group G2. In other words, for all cases where β is 0 or greater and N is less than or equal to β, if the distance of the current path from a memory cell MC to the switch SYU_β via a current path including a portion of conductor 22_β is shorter than the distance of the current path from the memory cell MC to the switch SYL_β via a current path including a portion of conductor 22_β, then the memory cell MC belongs to group G2. Based on the current example, the memory cell MC connected to any one of conductors 21_4, 21_5, 21_6, and 21_7 belongs to group G2. That is, conductors 21_4, 21_5, 21_6, and 21_7 are closer to the upper end of conductor 22 than the lower end of conductor 22.

[0075] Figure 10 This is a circuit diagram of the readout circuit of the storage device according to the first embodiment. Figure 10 The text represents the state of a specific memory cell (MC) being selected. That is, as shown in the reference... Figure 1 As explained, let's assume that a word line WL is selected by row selection circuit 14, and a bit line BL is selected by column selection circuit 15. A memory cell MC connected to both the selected word line WL and the selected bit line BL becomes selected, and data is read from the selected memory cell MC. Furthermore, Figure 10 The word line WL, bit line BL, and memory cell MC shown are selected.

[0076] like Figure 10 As shown, the readout circuit 17 is connected to the global word line GWL and the global bit line GBL. The readout circuit 17 includes a sense amplifier circuit SAC, switches SW3, SW4, SW5, and SW6, and a readout control circuit RCC. Examples of switches SW3, SW4, SW5, and SW6 include n-type MOSFETs, p-type MOSFETs, and p-type and n-type MOSFETs connected in parallel.

[0077] Switch SW3 is connected between the node receiving a precharge voltage VPRCH and the global word line GWL. The node receiving the precharge voltage VPRCH functions as the node supplying the precharge voltage VPRCH. In one example, the precharge voltage VPRCH is supplied from voltage generation circuit 18. The precharge voltage VPRCH is higher than the ground voltage VSS. Switch SW3 is turned on during the period of S3 when receiving the assertion level logic signal.

[0078] Switch SW4 is connected between the global word line GWL and a node that receives a certain magnitude of the non-selection voltage VUSEL. The node receiving the non-selection voltage VUSEL functions as the node supplying the non-selection voltage VUSEL. In one example, the non-selection voltage VUSEL is supplied from the voltage generation circuit 18. The non-selection voltage VUSEL has a magnitude between the ground voltage VSS and the pre-charge voltage VPRCH, the potential difference between the pre-charge voltage VPRCH and the non-selection voltage VUSEL, and the potential difference between the non-selection voltage VUSEL and the ground voltage VSS, which are smaller than a first threshold value of the switching element SE. In one example, the non-selection voltage VUSEL has half the magnitude of the pre-charge voltage VPRCH. Switch SW4 is turned on during the period when the assertion level logic signal S4 is received.

[0079] The sense amplifier circuit (SAC) outputs data determined to be stored in the selected memory cell (MC) of the data read-out object based on the voltage on the global word line (GWL). In one example, the sense amplifier circuit (SAC) includes an operational amplifier (OP). The non-inverting input of the operational amplifier (OP) is connected to the global word line (GWL). The inverting input of the operational amplifier (OP) receives a reference voltage (VREF). In one example, the reference voltage (VREF) has a potential between the magnitude of the high holding voltage (VhdH) and the magnitude of the low holding voltage (VhdL). The high holding voltage (VhdH) is the terminal voltage of the memory cell (MC) containing the MTJ element (MTJ) in a high-resistance state. The low holding voltage (VhdL) is the terminal voltage of the memory cell (MC) containing the MTJ element (MTJ) in a low-resistance state.

[0080] Switch SW5 is connected between the global bit line GBL and the node that accepts the non-selective voltage VUSEL. Switch SW5 is turned on during the period when signal S5, which receives assertion-level logic, is received.

[0081] Switch SW6 is connected between the global bit line GBL and the node that receives the ground voltage VSS. Switch SW6 is turned on during the period when the signal S6 of the assertion level logic is received.

[0082] Read out the RCC output signals S4 to S6 of the control circuit.

[0083] 1.2. Actions

[0084] Figure 11 An example illustrating a state during operation of the storage device in the first embodiment. Figure 11 The diagram illustrates the state during data reading from memory cell MC belonging to group G1. For example, it shows the state during data reading from memory cell MC_3_0. Memory cell MC_p_q is the memory cell MC connected to word line WL_p and bit line BL_q. Hereinafter, the memory cell MC to which data is read is sometimes referred to as the selected memory cell MC. The word line WL and bit line BL connected to the selected memory cell MC are sometimes referred to as the selected word line WL and selected bit line BL, respectively. Word lines WL other than the selected word line WL are sometimes referred to as the non-selected word line WL. Bit lines BL other than the selected bit line BL are sometimes referred to as the non-selected bit line BL.

[0085] The switch SX connected to the select word line WL (conductor 21 functioning as the select word line WL) is kept on, and the switch SX connected to the non-select word line WL (conductor 21 functioning as the non-select word line WL) is kept off. Figure 11 In the example, switch SX_3 is kept on, and all switches SX except for switch SX_3 are kept off.

[0086] When the storage unit MC of the data read object belongs to group G1, switch SYU, one of the switches SYL and SYU connected to the select bit line BL (conductor 22 functioning as the select bit line BL), is kept on, and switch SYL is kept off. Switches SYL and SYU, connected to the non-select bit line BL (conductor 22 functioning as the non-select bit line BL), are kept off. Figure 11 In the example, switch SYU_0 is kept on, while all switches SYU except for switch SYU_0 and all switches SYL are kept off.

[0087] Figure 12 An example illustrating a state during operation of the storage device in the first embodiment. Figure 12 The table shows the state during the period when data is read from storage cell MC belonging to group G2. For example, the table shows the state during the period when data is read from storage cell MC_7_7.

[0088] The switch SX connected to the select word line WL is kept on, and the switch SX connected to the non-select word line WL is kept off. Figure 12 In the example, switch SX_7 is kept on, and all switches SX except for switch SX_7 are kept off.

[0089] When the storage unit MC of the data read object belongs to group G2, switch SYL, which is connected to the select bit line BL, is kept on, and switch SYU is kept off. Switches SYL and SYU, which are connected to the non-select bit line BL, are kept off. Figure 12 In the example, switch SYL_7 is kept on, while all switches SYL except for switch SYL_7 and all switches SYU are kept off.

[0090] Selecting the storage unit MC for reference Figure 11 as well as Figure 12 Data readout is performed while connected to the global word line GWL and the global bit line GBL according to the rules described above. The readout operation can be performed in any manner. Hereinafter, an example of the readout operation is described. That is, firstly, a voltage VUSEL is applied to the global word line GWL and the global bit line GBL. This is done by keeping switches SW3 and SW6 open and switches SW4 and SW5 closed.

[0091] During the application of the non-selection voltage VUSEL to the global bit line GBL, a pre-charge voltage VPRCH is applied to the global word line GWL. This is done by keeping switch SW4 open and switch SW3 on. Then, by keeping switch SW3 open, the global word line GWL is kept electrically floated.

[0092] During the period when the global word line GWL is electrically floating, a ground voltage VSS is applied to the global bit line GBL. This is done by keeping switch SW5 open and switch SW6 closed. As a result, the potential difference between the select word line WL and the select bit line BL reaches the threshold voltage Vth of the switching element SE of the select memory cell MC. Consequently, the switching element SE of the select memory cell MC turns on. As a result, cell current flows from the select word line WL to the select bit line BL via the select memory cell MC, and the potential of the select word line WL decreases. When the MTJ element MTJ of the select memory cell MC is in a low resistance state due to the decrease in the potential of the select word line WL, the terminal voltage of the select memory cell MC becomes a low holding voltage VhdL. On the other hand, when the MTJ element MTJ of the select memory cell MC is in a high resistance state, the terminal voltage of the select memory cell MC becomes a high holding voltage VhdH, and the switching element SE of the select memory cell MC turns off. Therefore, the global word line GWL has a potential based on the magnitude of the resistance state of the MTJ element MTJ of the select memory cell MC. The data stored in the selected memory cell MC is identified by using this potential through the readout circuit 17.

[0093] 1.3. Advantages (Effects)

[0094] The storage device according to the first embodiment, as described below, can suppress data write errors and damage to the storage unit MC.

[0095] Consider the case where only switches SYL_0 to SYL_7 are used, without the group containing switches SYU_0 to SYU_7. In this case, the length of the current path containing the memory cell MC varies significantly depending on its location. Specifically, the current path is longer when the memory cell MC is located further from both row selection circuit 14 and column selection circuit 15 (e.g., memory cell MC_7_7), resulting in higher resistance. Conversely, the current path is shorter when the memory cell MC is located closer to both row selection circuit 14 and column selection circuit 15 (e.g., memory cell MC_0_0), resulting in lower resistance. The difference between the longest and shortest current paths is significant. In this case, even with different current paths, the charge charged by the pre-charge voltage VPRCH is the same. During data reading from the memory cell MC contained in the shorter current path, the charge discharges with lower parasitic resistance, resulting in a larger peak cell current flow. Depending on the magnitude of the peak cell current, the resistance state of the MTJ element in the memory cell MC within the shorter current path may change, potentially causing data write errors or read interference. Depending on the magnitude of the cell current, it may even damage the memory cell MC.

[0096] According to the first embodiment, switches SYU and SYL are connected to one end and the other end of each conductor 22 (bit line BL), respectively. During data readout, one of the switches SYU and SYL connected to the selected bit line BL that is farther from the selected memory cell MC is kept on, and the other switch is kept off. That is, even if each conductor 21 can be connected to the global bit line GBL via the closer one of the switches SYU and SYL, it will be connected to the global bit line GBL via the farther one. Therefore, even if a shorter current path can be formed, it will not be used. This helps to suppress the difference between the length of the longest current path used (e.g., in the case of selected memory cell MC_7_7) and the length of the shortest current path used (e.g., in the case of selected memory cell MC_3_0). Since the difference between the longest and shortest current paths is small, the difference between the resistance of the longest current path and the resistance of the shortest current path is small. Thus, even with the same precharge voltage VPRCH, the difference in the peak value of the cell current based on the difference in current paths can be suppressed. Therefore, data miswriting or read interference to the storage unit MC and damage to the storage unit are suppressed.

[0097] 2. Second Implementation Method

[0098] The second embodiment differs from the first embodiment in the classification of storage units (MCs).

[0099] 2.1. Composition

[0100] Figure 13 Here is an example of the classification of storage cells in the storage device of the second embodiment. Storage cells MC are classified into three groups. For all cases where β is P or more and N or less, the MC connected to conductor 22_β belongs to group GB1. In other words, storage cells MC located at a position farther from switch SX belong to group GB1. An example of P is the smallest integer greater than (N+1) / 2. Another example of P is the smallest integer greater than (N+1)×2 / 3. Based on the current example, P is 6, and the following description is based on this example. Based on the current example, the storage cell MC connected to either conductor 22_6 or conductor 22_7 belongs to group GB1.

[0101] For all cases where β is 0 or greater and less than P, and α is 0 or greater and less than (M+1) / 2, the memory cell MC connected to conductors 22_β and 21_α belongs to group GB2. In other words, for all cases where the memory cell MC is located close to switch SX and β is 0 or greater and less than P, if the distance of the current path from a memory cell MC to switch SYL_β via a current path including a portion of conductor 22_β (bit line BL_β) is shorter than the distance of the current path from the memory cell MC to switch SYU_β via a current path including a portion of conductor 22_β, then the memory cell MC belongs to group GB2. Based on the current example, the memory cell MC connected to any one of conductors 22_0, 22_1, 22_2, 22_3, 22_4, and 22_5, and connected to any one of conductors 21_0, 21_1, 21_2, and 21_3, belongs to group GB2.

[0102] For all cases where β is 0 or more and less than P, and α is (M+1) / 2 or more and less than M, the memory cell MC connected to conductors 22_β and 21_α belongs to group GB3. In other words, for all cases where the memory cell MC is located close to switch SX and β is 0 or more and less than P, if the distance of the current path from a memory cell MC to switch SYU_β via a current path including a portion of conductor 22_β (bit line BL_β) is shorter than the distance of the current path from the memory cell MC to switch SYL_β via a current path including a portion of conductor 22_β, then the memory cell MC belongs to group GB3. Based on the current example, the memory cell MC connected to any one of conductors 22_0, 22_1, 22_2, 22_3, 22_4, and 22_5, and connected to any one of conductors 21_4, 21_5, 21_6, and 21_7, belongs to group GB3.

[0103] 2.2. Actions

[0104] Figure 14 An example illustrating a state during operation of the storage device in the second embodiment. Figure 14 The table shows the state during the period when data is read from storage cell MC belonging to group GB1. For example, the table shows the state during the period when data is read from storage cell MC_3_7.

[0105] The switch SX connected to the select word line WL is kept on, and the switch SX connected to the non-select word line WL is kept off. Figure 14 In the example, switch SX_3 is kept on, and all switches SX except for switch SX_3 are kept off.

[0106] When the storage unit MC of the data read object belongs to group GB1, both switches SYL and SYU connected to the select bit line BL are kept on. Switches SYL and SYU connected to the non-select bit line BL are kept off. Figure 14 In the example, switches SYL_7 and SYU_7 are kept on, while all switches SYL except SYL_7 and all switches SYU except SYU_7 are kept off.

[0107] Figure 15 An example illustrating a state during operation of the storage device in the second embodiment. Figure 15 The table shows the state during the period when data is read from storage cell MC belonging to group GB2. For example, it shows the state during the period when data is read from storage cell MC_3_0.

[0108] The switch SX connected to the select word line WL is kept on, and the switch SX connected to the non-select word line WL is kept off. Figure 15 In the example, switch SX_3 is kept on, and all switches SX except for switch SX_3 are kept off.

[0109] When the storage unit MC of the data read object belongs to group GB2, the switch SYL connected to the select bit line BL and the switch SYU in SYU are kept on, while the switch SYL is kept off. The switches SYL and SYU connected to the non-select bit line BL are kept off. Figure 15 In the example, switch SYU_0 is kept on, while all switches SYU except for switch SYU_0 and all switches SYL are kept off.

[0110] Figure 16 An example illustrating a state during operation of the storage device in the second embodiment. Figure 16 The table shows the state during the period when data is read from storage unit MC belonging to group GB3. For example, it shows the state during the period when data is read from storage unit MC_7_5.

[0111] The switch SX connected to the select word line WL is kept on, and the switch SX connected to the non-select word line WL is kept off. Figure 16 In the example, switch SX_7 is kept on, and all switches SX except for switch SX_7 are kept off.

[0112] When the storage unit MC of the data read object belongs to group GB3, switch SYL, which is connected to the select bit line BL, is kept on, and switch SYU is kept off. Switches SYL and SYU, which are connected to the non-select bit line BL, are kept off. Figure 16 In the example, switch SYL_5 is kept on, while all switches SYL except for switch SYL_5 and all switches SYU are kept off.

[0113] The read operation of the storage unit MC in the selected state is the same as in the first embodiment.

[0114] 2.3. Advantages

[0115] The resistance of the memory cell MC located further away from the switch SX is relatively high due to the resistance generated by the conductor 21. According to the second embodiment, similar to the first embodiment, switches SYU and SYL are connected to one end and the other end of each conductor 21, respectively. Furthermore, during data reading from the selected memory cell MC connected to the portion of the conductor 21 that is further away from the switch SX, both switches SYU and SYL connected to the conductor 22 of the selected memory cell MC are kept on. Therefore, the resistance between the switch SX connected to the selected memory cell MC via the conductor 21 and the switches SYU and SYL connected to the selected memory cell MC via the conductor 22 is lower than when only one of the switches SYU and SYL is used. Therefore, when the resistance of the conductor 21 is high due to its distance from the switch SX, the resistance of the conductor 22 can be prevented from becoming excessively high, thus suppressing the peak value of the cell current. As a result, the deviation of the cell current caused by the deviation of the resistance of the current path is suppressed.

[0116] Furthermore, according to the second embodiment, similar to the first embodiment, during the reading of data from the selection memory cell MC connected to a portion of the conductor 21 not far from the switch SX, one of the switches SYU and SYL connected to the selection bit line BL that is farther from the selection memory cell MC is turned on, while the other switch remains off. Therefore, when reading data from the selection memory cell MC connected to a portion of the conductor 21 not far from the switch SX, the same advantages as in the first embodiment can be obtained. Thus, according to the second embodiment, the deviation of the cell current caused by the position of the memory cell MC is smaller than the deviation in the first embodiment.

[0117] 3. Third Implementation Method

[0118] The third implementation method relates to the data writing operation. The third implementation method can be implemented additionally to the first or second implementation method.

[0119] Figure 17 Functional blocks and constituent elements representing a portion of the storage device in the third embodiment. For example... Figure 17 As shown, the write circuit 16 is connected to the global word line GWL and the global bit line GBL.

[0120] Figure 18 The components of the column selection circuit of the storage device in the second embodiment are shown. For example... Figure 18 As shown, decoder 151 also receives instruction CMD. Based on the decoding result of address information ADD and instruction CMD, decoder 151 outputs signals CYL_0 to CYL_7 and CYU_0 to CYU_7 with logic levels based on the decoding result.

[0121] Figure 19 An example illustrating a state during operation of the storage device in the third embodiment. Figure 19 As an example, the state during the writing of data to the memory cell MC_3_4 is shown. Similar to the first and second embodiments, the switch SX connected to the select word line WL is kept on, and the switch SX connected to the non-select word line WL is kept off.

[0122] During the writing of data to the selection memory cell MC of the data writing target, the column selection circuit 15 keeps both switches SYL and SYU connected to the selection bit line BL closed. That is, when the decoder 151 of the column selection circuit 15 receives the instruction CMD indicating data writing, it keeps both switches SYL and SYU connected to the selection bit line BL closed. Figure 19 In the example shown, during data writing, switches SYL_4 and SYU_4 are kept on. During data writing, the two switches SYL and SYU connected to each non-select bit line BL are kept off. While switches SYU and SYL are kept on or off as described above, the write circuit 16 applies voltage or current to the global word line GWL and the global bit line GBL to cause cell current to flow in the select memory cell MC based on the data written to it.

[0123] According to the third embodiment, similar to the first and second embodiments, switches SYU and SYL are connected to one end and the other end of each conductor 22, respectively. Furthermore, during data writing, both switches SYU and SYL connected to the conductor 22 connected to the selected memory cell MC are kept on. Therefore, the resistance between switch SX connected to the selected memory cell MC via conductor 21 and switches SYU and SYL connected to the selected memory cell MC via conductor 22 is lower than in the case where only one of switches SYU and SYL is used. Therefore, the resistance of the current path is suppressed, allowing a larger cell current to flow in such a current path. Thus, the decrease in cell current or the increase in write time caused by the resistance of the current path is suppressed.

[0124] 4. Fourth Implementation Method

[0125] The fourth embodiment differs from the first and second embodiments in the classification of storage units (MCs).

[0126] 4.1. Composition

[0127] Figure 20 This section illustrates an example of the classification of storage cells in the storage device according to the fourth embodiment. Storage cells MC are classified into three groups. As an example, R conductors 21 are arranged in the positive direction and R conductors 22 in the negative direction, with the center of the conductor 22 on the y-axis as the starting point; the following description is based on this example. For all cases where α is (M+1) / 2-R or more and (M+1) / 2+R-1 or less, the MC connected to conductor 21_α belongs to group GC1. In other words, for all cases where β is 0 or more and N or less, if the distance from a storage cell MC to the switch SYL_β via a current path including a portion of conductor 22_β, and the distance from the storage cell MC to the switch SYU_β via a current path including a portion of conductor 22_β, are both a certain or greater, then the storage cell MC belongs to group GC1. Based on the existing example, if R is 1, the storage cell MC connected to either conductor 21_3 or conductor 21_4 belongs to group GC1.

[0128] For all cases where α is 0 or greater and less than (M+1) / 2-R, the memory cell MC connected to conductor 21_α belongs to group GC2. In other words, for all cases where β is 0 or greater and less than N, if the distance of the current path from a memory cell MC to the switch SYL_β via a current path including a portion of conductor 22_β is shorter than the distance of the current path from a memory cell MC located on the same conductor 22_β and belonging to group GC1 to the switch SYL_β via a current path including a portion of conductor 22_β, then the memory cell MC belongs to group GC2. Based on the existing example, the memory cell MC connected to any of conductors 21_0, 21_1, and 21_2 belongs to group GC2.

[0129] For all cases where α is greater than (M+1) / 2+R-1 and less than M, the memory cell MC connected to conductor 21_α belongs to group GC3. In other words, for all cases where β is greater than 0 and less than N, if the distance of the current path from a memory cell MC to the switch SYU_β via a current path including a part of conductor 22_β is shorter than the distance of the current path from a memory cell MC located on the same conductor 22_β and belonging to group GC1 to the switch SYU_β via a current path including a part of conductor 22_β, then the memory cell MC belongs to group GC3.

[0130] Based on the current example, the memory cell MC connected to any of the conductors 21_5, 21_6, and 21_7 belongs to group GC3.

[0131] 4.2. Actions

[0132] Figure 21 An example representing a state during the operation of the storage device in the fourth embodiment. Figure 21 This indicates the state during the period when data is read from storage unit MC belonging to group GC1. For example, it indicates the state during the period when data is read from storage unit MC_4_2.

[0133] The switch SX connected to the select word line WL is kept on, and the switch SX connected to the non-select word line WL is kept off. Figure 21 In the example, switch SX_4 is kept on, and all switches in switch SX except for switch SX_4 are kept off.

[0134] When the storage unit MC of the data read object belongs to group GC1, both switches SYL and SYU connected to the select bit line BL are kept on. Switches SYL and SYU connected to the non-select bit line BL are kept off. Figure 21In the example, switches SYL_2 and SYU_2 are kept on, and all switches in switch SYL except switch SYL_2 and all switches in switch SYU except switch SYU_2 are kept off.

[0135] Figure 22 An example representing a state during the operation of the storage device in the fourth embodiment. Figure 22 This indicates the state during the period when data is read from storage unit MC belonging to group GC2. For example, it indicates the state during the period when data is read from storage unit MC_1_6.

[0136] The switch SX connected to the select word line WL is kept on, and the switch SX connected to the non-select word line WL is kept off. Figure 22 In the example, switch SX_1 is kept on, and all switches in switch SX except for switch SX_1 are kept off.

[0137] When the storage unit MC of the data read object belongs to group GC2, switch SYU of the switches SYL and SYU connected to the select bit line BL is kept on, and switch SYL is kept off. Switches SYL and SYU connected to the non-select bit line BL are kept off. Figure 22 In the example, switch SYU_6 is kept on, and all switches in switch SYU except for switch SYU_6, as well as all switches SYL, are kept off.

[0138] Figure 23 An example representing a state during the operation of the storage device in the fourth embodiment. Figure 23 This indicates the state during the period when data is read from storage unit MC belonging to group GC3. For example, it indicates the state during the period when data is read from storage unit MC_5_4.

[0139] The switch SX connected to the select word line WL is kept on, and the switch SX connected to the non-select word line WL is kept off. Figure 23 In the example, switch SX_5 is kept on, and all switches in switch SX except for switch SX_5 are kept off.

[0140] When the storage unit MC of the data read object belongs to group GC3, switch SYL, which is connected to the select bit line BL, remains on, and switch SYU remains off. Switches SYL and SYU, which are connected to the non-select bit line BL, remain off. Figure 23 In the example, switch SYL_4 is kept on, and all switches in switch SYL except switch SYL_4 and all switches SYU are kept off.

[0141] According to the fourth embodiment, similarly to the first embodiment, switches SYU and SYL are connected to one end and the other end of each conductor 22 (bit line BL), respectively. During data readout, the switch SYU or SYL connected to the selection bit line BL that is farther from the selection memory cell MC is kept on, while the other is kept off. Therefore, the same advantages as the first embodiment can be obtained. Furthermore, during data readout from the selection memory cell MC connected to the portion of the conductor 21 that is farther from both switches SYU and SYL, both switches SYU and SYL connected to the selection bit line BL are kept on. Therefore, the resistance of the current path during data readout from the selection memory cell MC that is farther from both switches SX and SY is small.

[0142] 5. Variations

[0143] The description up to this point is based on the example where the boundary between group G1 and group G2, or the boundary between group GB2 and group GB3, is located at the center of conductor 22, i.e., based on the example where the number of memory cells MC arranged along the y-axis in group G1 or group GB2 is equal to the number of memory cells MC arranged along the y-axis in group G2 or group GB3. Alternatively, the number of memory cells MC arranged along the y-axis in group G1 or group GB2 may differ from the number of memory cells MC arranged along the y-axis in group G2 or group GB3.

[0144] The description up to this point is based on an example where the number of memory cells MC arranged along the y-axis in group GC2 is equal to the number of memory cells MC arranged along the y-axis in group GC3. Alternatively, the number of memory cells MC arranged along the y-axis in group GC2 may differ from the number of memory cells MC arranged along the y-axis in group GC3. The description up to this point is based on an example of a fourth embodiment that is grounded in the first embodiment. Alternatively, the fourth embodiment may be combined with the second embodiment.

[0145] The first, second, third, and fourth embodiments are based on the example where switch SX is connected only to one end of conductor 21, and switches SYL and SYU are connected to both ends of conductor 22, respectively. Alternatively, switch SY (e.g., equivalent to switch SYL) can be connected only to one end of conductor 22 (e.g., the end on the -Y direction side), and switches SXL and SXR can be connected to both ends of conductor 21, respectively. In this case, in the first embodiment, group G1 includes a memory cell MC closer to switch SXL, and group G2 includes a memory cell MC closer to switch SXR. In the second embodiment, group GB1 includes a memory cell MC farther from switch SY, group GB2 includes a memory cell MC close to both switch SY and switch SXL, and group GB3 includes a memory cell MC close to both switch SY and switch SXR. In the fourth embodiment, group GC1 includes a storage cell MC that is spaced apart from both switches SXL and SXR by a certain distance; group GC2 includes a storage cell MC that is closer to switch SXL than the storage cell MC in group GC1; and group GC3 includes a storage cell MC that is closer to switch SXR than the storage cell MC in group GC1. Regarding operation, it is applicable to replace the descriptions of switches SYL and SYU described in the first and second embodiments with those of switches SXL and SXR, and to replace the description of switch SX with that of switch SY.

[0146] While several embodiments of the invention have been described, these embodiments are provided as examples and are not intended to limit the scope of the invention. These embodiments can be implemented in various other ways, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their variations are included within the scope and spirit of the invention, as well as within the scope of the claims and their equivalents.

[0147] Explanation of reference numerals in the attached figures

[0148] 1… Storage device,

[0149] 11… Storage cell array,

[0150] 12…Input / output circuit,

[0151] 13…control circuit,

[0152] 14… row selection circuit,

[0153] 15… column selection circuit,

[0154] 16…Write into the circuit,

[0155] 17…Readout circuit,

[0156] 18…Voltage generation circuit,

[0157] MC… storage unit,

[0158] WL…word line,

[0159] BL…bitline,

[0160] 21… conductors,

[0161] 22… conductors,

[0162] 32… Variable resistance material,

[0163] 31…lower electrode,

[0164] 33… Upper electrode,

[0165] 35…strong magnetic layer,

[0166] 36…Insulation layer,

[0167] 37…strong magnetic layer,

[0168] GWL…Global Word Line

[0169] GBL…Global Bitline

[0170] SX… switch,

[0171] SYL… switch,

[0172] SYU… switch.

Claims

1. A memory device comprising: a first conductive body; a second conductive body located closer to a first direction than the first conductive body; a third conductive body extending along the first direction, intersecting the first conductive body and the second conductive body, and having a first end and a second end, the first end being located closer to the first direction than the second end; a first memory cell connected to the first conductive body and the third conductive body; a second memory cell connected to the second conductive body and the third conductive body; a first switch connected to the first end of the third conductive body; and a second switch connected to the second end of the third conductive body, wherein in a case where data is read out from the first memory cell, the first switch is maintained on and the second switch is maintained off, and in a case where data is read out from the second memory cell, the second switch is maintained on and the first switch is maintained off.

2. The memory device according to claim 1, wherein the first conductive body and the second conductive body extend along a second direction, the first conductive body has a third end on one side in the second direction, the second conductive body has a fourth end on one side in the second direction, the memory device further comprises a third switch connected to the third end of the first conductive body and a fourth switch connected to the fourth end of the second conductive body, in a case where data is read out from the first memory cell, the third switch is maintained on, and in a case where data is read out from the second memory cell, the fourth switch is maintained on.

3. The memory device according to claim 2, further comprising a first wiring, the first switch is connected between the first end of the third conductive body and the first wiring, and the second switch is connected between the second end of the third conductive body and the first wiring.

4. The memory device according to claim 3, further comprising a second wiring, the third switch is connected between the third end of the first conductive body and the second wiring, the fourth switch is connected between the fourth end of the second conductive body and the second wiring, one of the first wiring and the second wiring is connected to a node of a first voltage and a sense amplifier circuit, and the other of the first wiring and the second wiring is connected to a node of a second voltage lower than the first voltage.

5. The memory device according to claim 1, wherein the first conductive body is located closer to the second end than the first end of the third conductive body, and the second conductive body is located closer to the first end than the second end of the third conductive body.

6. The memory device according to claim 5, further comprising a memory cell array including a plurality of memory cells including the first memory cell and the second memory cell, the first switch is located closer to the first direction than the memory cell array, and the second switch is located closer to a direction opposite to the first direction than the memory cell array.

7. The memory device according to claim 4, wherein ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ Further comprising a memory cell array including a plurality of memory cells including the first memory cell and the second memory cell, The first switch is located closer to the first direction than the memory cell array, The second switch is located closer to a direction opposite to the first direction than the memory cell array.

8. The memory device according to claim 2, wherein The first conductor is located closer to the second end than the first end of the third conductor, The second conductor is located closer to the first end than the second end of the third conductor.

9. The memory device according to claim 8, wherein Further comprising a memory cell array including a plurality of memory cells including the first memory cell and the second memory cell, The first switch is located closer to the first direction than the memory cell array, The second switch is located closer to a direction opposite to the first direction than the memory cell array.

10. The memory device according to claim 1, wherein Further comprising a memory cell array including a plurality of memory cells including the first memory cell and the second memory cell, The first switch is located closer to the first direction than the memory cell array, The second switch is located closer to a direction opposite to the first direction than the memory cell array.

11. The memory device according to claim 1, comprising: A fourth conductor extending in the first direction, located closer to a direction opposite to the second direction than the third conductor, intersecting the first conductor and the second conductor, and having a fifth end and a sixth end, the fifth end being located closer to the first direction than the sixth end; A third memory cell connected to one of the first conductor and the second conductor and the fourth conductor; A fifth switch connected to the fifth end of the fourth conductor; and A sixth switch connected to the sixth end of the fourth conductor, In a case where data is read out from the third memory cell, the fifth switch and the sixth switch are maintained on.

12. The memory device according to claim 11, wherein The first conductor and the second conductor extend in the second direction, The first conductor has a third end on one side in the second direction, The second conductor has a fourth end on one side in the second direction, The memory device further comprises a third switch connected to the third end of the first conductor and a fourth switch connected to the fourth end of the second conductor, In a case where data is read out from the first memory cell, the third switch is maintained on, In a case where data is read out from the second memory cell, the fourth switch is maintained on.

13. The memory device according to claim 12, wherein Further comprising a first wiring, The first switch is connected between the first end of the third conductor and the first wiring, The second switch is connected between the second end of the third conductor and the first wiring, ​ The fifth switch is connected between the fifth terminal of the fourth conductor and the first wiring, The sixth switch is connected between the sixth terminal of the fourth conductor and the first wiring.

14. The memory device according to claim 13, wherein a second wiring is further provided, The third switch is connected between the third terminal of the first conductor and the second wiring, The fourth switch is connected between the fourth terminal of the second conductor and the second wiring, One of the first wiring and the second wiring is connected to a node of a first voltage and a sense amplifier circuit, The other of the first wiring and the second wiring is connected to a node of a second voltage lower than the first voltage.

15. The memory device according to claim 11, wherein The first conductor is located closer to the second terminal than the first terminal of the third conductor, The second conductor is located closer to the first terminal than the second terminal of the third conductor.

16. The memory device according to claim 12, wherein The first conductor is located closer to the second terminal than the first terminal of the third conductor, The second conductor is located closer to the first terminal than the second terminal of the third conductor.

17. The memory device according to claim 1, wherein Each of the first memory cell and the second memory cell includes a first strong magnetic layer, a second strong magnetic layer, and an insulating layer between the first strong magnetic layer and the second strong magnetic layer.

18. A memory device comprising: a first conductor; a second conductor intersecting the first conductor, extending in a first direction, and having a first terminal and a second terminal, the first terminal being located closer to the first direction than the second terminal; a memory cell connected to the first conductor and the second conductor; a first switch connected to the first terminal of the second conductor; and a second switch connected to the second terminal of the second conductor, The first switch and the second switch are maintained on when data is written to the memory cell.

19. The memory device according to claim 18, wherein The first conductor extends in a second direction, The first conductor has a third terminal on a side of the second direction, The memory device further comprises a third switch connected to the third terminal of the first conductor, The third switch is maintained on when data is written to the memory cell. a fifth conductor located closer to the first direction than the first conductor and closer to a direction opposite to the first direction than the second conductor, intersecting the third conductor; and 20. The memory device of claim 1, wherein, a fourth memory cell connected to the fifth conductor and the third conductor, The first switch and the second switch are maintained on when data is read from the fourth memory cell.

21. The memory device according to claim 20, wherein The first conductor is located closer to the second terminal than the first terminal of the third conductor, ​ ​ ​ the second electrically conductive body is located closer to the first end than the second end of the third electrically conductive body, the fifth electrically conductive body is located further from the second end of the third electrically conductive body than the first electrically conductive body, and is located further from the first end of the third electrically conductive body than the second electrically conductive body.

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