Semiconductor device, operation method and system thereof, and computer readable storage medium

Abstract

The invention provides a semiconductor device, an operation method and system thereof and a computer readable storage medium, the semiconductor device comprises a storage array and a peripheral circuit coupled with the storage array, and the peripheral circuit is configured to apply a first verification voltage to a word line coupled with a target storage unit in a verification stage of a first programming loop; applying a first voltage to a word line coupled to a target storage unit in a stage of performing operation by using the semiconductor device; the absolute value of the difference between the first voltage and the first verification voltage is smaller than a first preset value.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductor technology, and in particular to a semiconductor device and its operating method, system, and computer-readable storage medium. Background Technology

[0002] In the classic von Neumann computing architecture, memory and processor are separate, with data transfer between them via a data bus. When executing commands, the processor first reads data from memory, processes it, and then writes the updated data back to memory. This frequent data movement incurs significant power consumption and time overhead. Furthermore, due to limited memory bandwidth, the processor's processing speed is constrained by the memory access speed, greatly impacting computational performance. With the rise of big data and artificial intelligence applications, the processing of massive amounts of data has made the bottlenecks of the von Neumann computing architecture increasingly prominent. Summary of the Invention

[0003] In view of the above, embodiments of the present disclosure provide a semiconductor device and its operating method, system, and computer-readable storage medium.

[0004] In a first aspect, embodiments of this disclosure provide a semiconductor device, the semiconductor device including a memory array and peripheral circuitry coupled to the memory array, the peripheral circuitry being configured to: apply a first verification voltage to a word line coupled to a target memory cell during a verification phase of a first programming cycle; and apply a first voltage to the word line coupled to the target memory cell during an operation phase using the semiconductor device; wherein the absolute value of the difference between the first voltage and the first verification voltage is less than a first preset value.

[0005] In one alternative implementation, the first preset value is less than or equal to 0.1V.

[0006] In one alternative implementation, the first verification voltage is equal to the first voltage.

[0007] In one optional implementation, the peripheral circuit is configured to: apply a first programming voltage to the word line coupled to the target memory cell during the programming phase of the first programming cycle; and apply a second programming voltage to the word line coupled to the target memory cell during the programming phase of the second programming cycle following the first programming cycle; wherein the difference between the second programming voltage and the first programming voltage is less than a second preset value.

[0008] In one alternative implementation, the second preset value is less than or equal to 0.1V.

[0009] In one alternative implementation, the first programming voltage is less than or equal to the second programming voltage.

[0010] In one alternative implementation, the target memory cell is configured to store one bit of data, and the peripheral circuitry is configured to apply a second verification voltage to the word line coupled to the target memory cell during the verification phase of a second programming cycle following the first programming cycle, wherein the first verification voltage is equal to the second verification voltage.

[0011] In an optional implementation, during the verification phase of the first programming loop, the peripheral circuit is configured to: precharge the sensing node coupled to the target memory cell to a target voltage; based on the target state of the target memory cell being a first memory state, at a first moment after the sensing node begins to discharge through the memory cell string to which the target memory cell belongs, sense the current of the bit line coupled to the target memory cell; based on the target state of the target memory cell being a second memory state, at a second moment after the sensing node begins to discharge through the memory cell string to which the target memory cell belongs, sense the current of the bit line coupled to the target memory cell; the threshold voltage corresponding to the target memory cell being in the first memory state is less than the threshold voltage corresponding to the target memory cell being in the second memory state; and the time interval between the moment when the sensing node begins to discharge through the memory cell string to which the target memory cell belongs and the first moment is less than the time interval between the moment when the sensing node begins to discharge through the memory cell string to which the target memory cell belongs and the second moment.

[0012] In one alternative implementation, during the computation phase using the semiconductor device, the peripheral circuitry is configured to: precharge a sensing node coupled to the target memory cell to a target voltage; sense the current in the bit line coupled to the target memory cell; and obtain a computation result based on the current in the bit line coupled to the target memory cell.

[0013] In one alternative implementation, the peripheral circuit is configured to apply a second voltage to the word line coupled to the target memory cell during a computation phase using the semiconductor device; the second voltage is less than the first voltage, and the second voltage causes multiple memory cells coupled to the word line coupled to the target memory cell to be in a turned-off state.

[0014] In one alternative implementation, the peripheral circuit is configured to apply corresponding on-state voltages to the top select line, the bottom select line, and word lines other than the word lines coupled to the target memory cell during the computation phase using the semiconductor device.

[0015] In one optional implementation, the peripheral circuitry includes: an analog-to-digital converter (ADC), a column decoder, control logic, a digital-to-analog converter (DAC), and a voltage generator; the ADC is coupled to the column decoder and the control logic; and the DAC is coupled to the voltage generator and the control logic.

[0016] In one alternative implementation, the semiconductor device includes a three-dimensional NAND-type memory.

[0017] In one optional embodiment, the semiconductor device includes a first semiconductor structure and a second semiconductor structure; the memory array is located in the first semiconductor structure, the peripheral circuit is located in the second semiconductor structure, and the first semiconductor structure and the second semiconductor structure are stacked along the thickness direction of the semiconductor device.

[0018] Secondly, embodiments of this disclosure provide a system, including:

[0019] At least one semiconductor device described in any of the above embodiments;

[0020] A controller, coupled to the at least one semiconductor device and configured to send input data to the semiconductor device and receive the computation results from the semiconductor device.

[0021] Thirdly, embodiments of this disclosure provide an operation method for a semiconductor device, the operation method comprising: applying a first verification voltage to a word line coupled to a target memory cell during a verification phase of a first programming cycle; applying a first voltage to the word line coupled to the target memory cell during an operation phase using the semiconductor device; wherein the absolute value of the difference between the first voltage and the first verification voltage is less than a first preset value.

[0022] In one alternative implementation, the first preset value is less than or equal to 0.1V.

[0023] In one alternative implementation, the first verification voltage is equal to the first voltage.

[0024] In an optional implementation, the operation method further includes: applying a first programming voltage to the word line coupled to the target memory cell during the programming phase of the first programming cycle; applying a second programming voltage to the word line coupled to the target memory cell during the programming phase of the second programming cycle following the first programming cycle; wherein the difference between the second programming voltage and the first programming voltage is less than a second preset value.

[0025] In one alternative implementation, the second preset value is less than or equal to 0.1V.

[0026] In one alternative implementation, the first programming voltage is less than or equal to the second programming voltage.

[0027] In one alternative implementation, the target storage cell is configured to store one bit of data, and the operation method further includes: applying a second verification voltage to a word line coupled to the target storage cell during a verification phase of a second programming cycle following the first programming cycle, wherein the first verification voltage is equal to the second verification voltage.

[0028] In an optional implementation, during the verification phase of the first programming loop, the operation method further includes: pre-charging the sensing node coupled to the target memory cell to a target voltage; based on the target state of the target memory cell being a first memory state, sensing the current of the bit line coupled to the target memory cell at a first moment after the sensing node begins to discharge through the memory cell string to which the target memory cell belongs; based on the target state of the target memory cell being a second memory state, sensing the current of the bit line coupled to the target memory cell at a second moment after the sensing node begins to discharge through the memory cell string to which the target memory cell belongs; wherein the threshold voltage corresponding to the target memory cell being in the first memory state is less than the threshold voltage corresponding to the target memory cell being in the second memory state; and the time interval between the moment when the sensing node begins to discharge through the memory cell string to which the target memory cell belongs and the first moment is less than the time interval between the moment when the sensing node begins to discharge through the memory cell string to which the target memory cell belongs and the second moment.

[0029] In one optional implementation, during the computation phase using the semiconductor device, the operation method further includes: pre-charging a sensing node coupled to the target memory cell to a target voltage; sensing the current of a bit line coupled to the target memory cell; and obtaining a computation result based on the current of the bit line coupled to the target memory cell.

[0030] In an optional implementation, the operation method further includes: during the computation phase using the semiconductor device, applying a second voltage to the word line coupled to the target memory cell; the second voltage is less than the first voltage, and the second voltage causes multiple memory cells coupled to the word line coupled to the target memory cell to be in a turned-off state.

[0031] In an optional implementation, the operation method further includes: during the computation phase using the semiconductor device, applying corresponding on-state voltages to the top select line, the bottom select line, and word lines other than the word lines coupled to the target memory cell.

[0032] Fourthly, embodiments of this disclosure provide a computer-readable storage medium storing a computer program, which, when executed by a processor, performs the operation method described in any of the above embodiments.

[0033] In this embodiment of the present disclosure, the absolute value of the difference between the first verification voltage applied during the verification phase after programming the word line coupled to the target memory cell and the first voltage applied to the word line coupled to the target memory cell is less than a first preset value. That is, the difference between the first verification voltage and the first voltage is small. During the programming of the memory cell, the first verification voltage is applied to perform the verification operation on the memory cell, so that the current distribution under the first verification voltage is narrow. In the operation phase, the first voltage applied to the word line coupled to the target memory cell is close to the first verification voltage, thereby narrowing the current distribution during the operation process and improving the accuracy of memory operation. Attached Figure Description

[0034] Figure 1 This is a schematic diagram of the structure of a three-dimensional NAND type memory provided in an embodiment of the present disclosure.

[0035] Figure 2 This is a schematic diagram showing the distribution of storage cells in a three-dimensional NAND type memory according to an embodiment of the present disclosure.

[0036] Figure 3 This is a schematic diagram of an exemplary semiconductor device including peripheral circuitry, provided as an embodiment of the present disclosure.

[0037] Figure 4 This is a cross-sectional schematic diagram of a storage array including a string of storage cells, provided for an embodiment of the present disclosure.

[0038] Figure 5 A schematic diagram of a semiconductor device including peripheral circuitry and a memory array provided for an embodiment of this disclosure. Figure 1 .

[0039] Figure 6 A schematic diagram of a semiconductor device including peripheral circuitry and a memory array provided for an embodiment of this disclosure. Figure 2 .

[0040] Figure 7 This is a schematic diagram of input voltage being input to a memory block via a word line, according to an embodiment of this disclosure.

[0041] Figure 8 This is a schematic diagram of an embodiment of the present disclosure showing an input voltage input to a memory block via a top selection line.

[0042] Figure 9 This is a schematic diagram illustrating the input voltage to the memory block via the bottom selection line, as provided in one embodiment of this disclosure.

[0043] Figure 10 This is a schematic diagram of the threshold voltage distribution of a memory cell coupled to a target word line, provided as an embodiment of the present disclosure.

[0044] Figure 11 A schematic diagram of voltage application provided in an embodiment of this disclosure. Figure 1 .

[0045] Figure 12 This is a schematic diagram illustrating the relationship between the current in a string of memory cells and the voltage applied to the word line coupled to the target memory cell, according to an embodiment of this disclosure.

[0046] Figure 13 A schematic diagram of voltage application provided in an embodiment of this disclosure. Figure 2 .

[0047] Figure 14 This is a schematic diagram illustrating the relationship between the sensing node voltage and discharge time according to an embodiment of the present disclosure.

[0048] Figure 15 This is a schematic diagram of a plurality of memory cell strings coupled to a bit line, provided as an embodiment of the present disclosure.

[0049] Figure 16 This is a schematic flowchart illustrating an operation method of a semiconductor device provided in an embodiment of this disclosure.

[0050] Figure 17 This is a schematic diagram of an exemplary system with a memory system provided in an embodiment of the present disclosure.

[0051] Figure 18 This is a schematic diagram of an exemplary system having a memory device provided according to an embodiment of the present disclosure.

[0052] Figure 19 This is a schematic diagram of an exemplary memory card with a memory system provided according to an embodiment of the present disclosure.

[0053] Figure 20 This is a schematic diagram of an exemplary solid-state drive with a memory system provided in an embodiment of the present disclosure.

[0054] Figure 21 This is a schematic diagram of a computer-readable storage medium provided according to an embodiment of the present disclosure. Detailed Implementation

[0055] Exemplary embodiments of the present disclosure will now be described in more detail with reference to the accompanying drawings. While exemplary embodiments of the present disclosure are shown in the drawings, it should be understood that the present disclosure may be implemented in various forms and should not be limited to the specific embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the disclosure to those skilled in the art.

[0056] In the following description, numerous specific details are set forth in order to provide a more thorough understanding of this disclosure. However, it will be apparent to those skilled in the art that this disclosure may be practiced without one or more of these details. In other instances, to avoid confusion with this disclosure, certain technical features well-known in the art have not been described; that is, not all features of actual embodiments are described herein, nor are well-known functions and structures described in detail.

[0057] In the accompanying drawings, the same reference numerals denote the same elements throughout.

[0058] It should be understood that spatial relation terms such as “below,” “under,” “below,” “below,” “above,” “above,” etc., are used herein for convenience of description to describe the relationship between one element or feature shown in the figure and other elements or features. It should be understood that, in addition to the orientation shown in the figure, spatial relation terms are intended to also include different orientations of the device in use and operation. For example, if the device in the figure is flipped, then the element or feature described as “below” or “below” other elements or features will be oriented “above” other elements or features. Therefore, the exemplary terms “below” and “under” can include both upper and lower orientations. The device may be otherwise oriented (rotated 90 degrees or otherwise) and the spatial descriptive terms used herein will be interpreted accordingly.

[0059] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit this disclosure. When used herein, the singular forms “a,” “an,” and “the” are also intended to include the plural forms unless the context clearly indicates otherwise. It should also be understood that the terms “comprise” and / or “comprising,” when used in this specification, identify the presence of the stated features, integers, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups. When used herein, the term “and / or” includes any and all combinations of the associated listed items.

[0060] In the classic von Neumann computing architecture, memory and processor are separate, with data transfer between them via a data bus. When executing commands, the processor first reads data from memory, processes it, and then writes the updated data back to memory. This frequent data movement incurs significant power consumption and time overhead. Furthermore, due to limited memory bandwidth, processor speed is constrained by memory access speed, severely impacting computational performance. With the rise of big data and artificial intelligence applications, the processing of massive amounts of data has made the bottlenecks of the von Neumann computing architecture increasingly prominent. To address these bottlenecks, in-memory computing chip architecture has emerged. Its basic idea is to embed computing functions within memory and directly utilize memory for logical calculations, thereby reducing the amount and distance of data transfer between memory and processor, lowering power consumption while improving computational performance. This promises to build high-performance, high-bandwidth, and high-energy-efficiency computing systems.

[0061] In-memory computing (IMC) chips possess both storage and computational capabilities due to their inherent physical characteristics. Storage capability refers to the ability of different memory devices to store numerical values ​​by changing their conductivity, while computational capability refers to the ability to perform vector-matrix multiplication within a given time by constructing an array of memory devices and applying Ohm's law and Kirchhoff's laws. IMC chips include, but are not limited to, Static Random Access Memory (SRAM), NAND flash memory, and Dynamic Random Access Memory (DRAM). Among these, NAND flash memory, being a non-volatile memory with a large capacity, has become a widely studied area of ​​interest in IMC chips. The following section will provide a detailed introduction to NAND flash memory.

[0062] Figure 1 An exemplary schematic diagram of a three-dimensional NAND flash memory is provided. Figure 2 An exemplary schematic diagram of the cell layout of a three-dimensional NAND flash memory is provided. The three-dimensional NAND flash memory includes a memory array and peripheral circuitry coupled to the memory array. For example... Figure 1 As shown, a storage array can include multiple storage planes, such as Plane0, Plane1, Plane2, and Plane3, a total of four storage planes. Each storage plane includes multiple storage blocks. Figure 2As shown, the storage array of a three-dimensional NAND flash memory consists of several rows of parallel, staggered rows of memory cells parallel to the gate isolation structure. Every four rows of memory cells are separated by a gate isolation structure and a select gate isolation structure. Each row of memory cells includes multiple strings of memory cells, and each string of memory cells includes multiple memory cells arranged along the Z-direction. The select gate isolation structure can be a top select gate isolation structure, which divides the top select gate into multiple top select lines. Alternatively, it can be a bottom select gate isolation structure, which divides the bottom select gate into multiple bottom select lines. The gate isolation structure can include a first gate isolation structure and a second gate isolation structure. The first gate isolation structure divides the storage array into multiple storage blocks, and multiple second gate isolation structures can divide the storage blocks into multiple finger regions. A select gate isolation structure positioned in the middle of each finger region can divide the finger region into two parts, thus dividing the finger region into two storage chips. Figure 2 The storage block shown contains 6 storage pieces. In practical applications, the number of storage pieces in a storage block is not limited to this. Figure 2 Only one storage block of the memory is shown as an example, but the memory includes multiple such blocks. Figure 2 The memory blocks shown are separated by a first gate isolation structure, and multiple memory blocks can be arranged along the Y direction.

[0063] It should be noted that, Figure 2 The number of cell rows between the gate isolation structure and the selected gate isolation structure given is merely an example and is not intended to limit the number of cell rows contained in a single memory region of the three-dimensional NAND memory in this disclosure. In practical applications, the number of cell rows contained in a single memory region can be adjusted according to actual conditions, such as 2, 4, 8, 16, etc.

[0064] Figure 3This is a schematic diagram of an exemplary semiconductor device including peripheral circuitry, provided for embodiments of the present disclosure. The semiconductor device 300 may include a memory array 301 and peripheral circuitry 302 coupled to the memory array 301. Taking a three-dimensional NAND-type memory array as an example, the memory cells 306 are NAND memory cells, provided in the form of an array of memory cell strings 308, each memory cell string 308 extending vertically above a substrate (not shown). In some embodiments, each memory cell string 308 includes a plurality of memory cells 306 coupled in series and stacked vertically. Each memory cell 306 may hold a continuous analog value, such as voltage or charge, depending on the number of electrons trapped in the region of the memory cell 306. Each memory cell 306 may be a floating-gate type memory cell including a floating-gate transistor, or a charge-trapping type memory cell including a charge-trapping transistor.

[0065] In some implementations, each memory cell 306 is a single-level cell (SLC) having two possible memory states and thus capable of storing one bit of data. For example, a first memory state "0" may correspond to a first voltage range, and a second memory state "1" may correspond to a second voltage range. In some implementations, each memory cell 306 is a multi-level cell capable of storing more than a single bit of data in four or more memory states, such as a multi-level cell (MLC) storing two bits per cell, a triple-level cell (TLC) storing three bits per cell, or a quad-level cell (QLC) storing four bits per cell.

[0066] like Figure 3As shown, each memory cell string 308 may include a bottom select gate (BSG) 310 at its source terminal and a top select gate (TSG) 312 at its drain terminal. The bottom select gate 310 and top select gate 312 can be configured to activate the selected memory cell string 308 during read and program operations. In some embodiments, the sources of memory cell strings 308 within the same memory block 304 can be coupled via a common source line (CSL) 314. In other words, all memory cell strings 308 within the same memory block 304 have a common source (ACS). According to some embodiments, the top select gate 312 of each memory cell string 308 is coupled to a corresponding bit line 316, and data can be read from or written to the bit line 316 via an output bus (not shown). In some implementations, each memory cell string 308 is configured to be selected or deselected by applying a selection voltage (e.g., a voltage higher than the threshold voltage of the top select transistor 312) or a deselection voltage (e.g., 0V) to the corresponding top select transistor 312 via one or more top select lines (TSL) 313 and / or by applying a selection voltage (e.g., a voltage higher than the threshold voltage of the bottom select transistor 310) or a deselection voltage (e.g., 0V) to the corresponding bottom select transistor 310 via one or more bottom select lines (BSL) 315.

[0067] like Figure 3 As shown, the memory cell string 308 can be organized into multiple memory blocks 304, each of which can have a common source line 314. In some embodiments, each memory block 304 is the basic data unit for an erase operation, i.e., all memory cells 306 on the same memory block 304 are erased simultaneously. To erase memory cells 306 in a selected memory block, an erase voltage bias can be used to couple the common source line 314 to the selected memory block and the unselected memory blocks on the same plane as the selected memory block. It should be understood that in some examples, the erase operation can be performed at the half-block level, at the quarter-block level, or at a level with any suitable number of memory blocks or any suitable fraction of memory blocks. Memory cells 306 of adjacent memory cell strings 308 can be coupled via word lines 318, which select which row of memory cells 306 is affected by read and program operations.

[0068] Figure 4 A schematic cross-sectional view of an exemplary memory array including a string of memory cells 308, according to some aspects of this disclosure, is shown. Figure 4 As shown, the stacked structure 410 includes a plurality of gate layers 411 and a plurality of insulating layers 412 stacked alternately in sequence, and a string of memory cells 308 perpendicularly penetrating the gate layers 411 and the insulating layers 412. The gate layers 411 and the insulating layers 412 can be stacked alternately, with adjacent gate layers 411 separated by an insulating layer 412. The number of memory cells included in the memory array is mainly related to the number of pairs of gate layers 411 and insulating layers 412 in the stacked structure 410.

[0069] The constituent materials of the gate layer 411 may include conductive materials. Conductive materials include, but are not limited to, tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), polysilicon, doped silicon, silicide, or any combination thereof. In some embodiments, each gate layer 411 includes a metal layer, such as a tungsten layer. In some embodiments, each gate layer 411 includes a doped polysilicon layer. Each gate layer 411 may include a control gate surrounding a memory cell. The gate layer 411 at the top of the stack 410 may extend laterally as a top select line, the gate layer 411 at the bottom of the stack 410 may extend laterally as a bottom select line, and the gate layer 411 extending laterally between the top select line and the bottom select line may serve as a word line layer.

[0070] In some embodiments, the stacked structure 410 may be disposed on the semiconductor layer 401. The semiconductor layer 401 may include silicon (e.g., single-crystal silicon), silicon-germanium (SiGe), gallium arsenide (GaAs), germanium (Ge), silicon-on-insulator (SOI), germanium-on-insulator (GOI), or any other suitable material. In other embodiments, the semiconductor device may not include a semiconductor layer.

[0071] In some embodiments, the memory cell string 308 includes a channel structure extending vertically through the stacked structure 410. In some embodiments, the channel structure includes channel holes filled with one or more semiconductor materials (e.g., as a semiconductor channel) and one or more dielectric materials (e.g., as a memory film). In some embodiments, the semiconductor channel includes silicon, for example, polycrystalline silicon. In some embodiments, the memory film is a composite dielectric layer including a tunneling layer, a storage layer (also referred to as a "charge trap / storage layer"), and a barrier layer. The channel structure may have a cylindrical shape (e.g., a pillar shape). According to some embodiments, the semiconductor channel, tunneling layer, storage layer, and barrier layer are arranged radially from the center of the pillar toward the outer surface of the pillar in this order. The tunneling layer may include silicon oxide, silicon oxynitride, or any combination thereof. The storage layer may include silicon nitride, silicon oxynitride, or any combination thereof. The barrier layer may include silicon oxide, silicon oxynitride, a high-k dielectric, or any combination thereof. In one example, the memory film may include a composite layer of silicon oxide / silicon oxynitride / silicon oxide (ONO).

[0072] Return to reference Figure 3 The peripheral circuitry 302 can be coupled to the memory array 301 via bit line 316, word line 318, source line 314, BSL315, and TSL313. The peripheral circuitry 302 can include any suitable analog, digital, and mixed-signal circuitry to facilitate the operation of the memory array 301 by applying voltage and / or current signals to each target memory cell 306 via bit line 316, word line 318, source line 314, BSL315, and TSL313, and by sensing voltage and / or current signals from each target memory cell 306. The peripheral circuitry 302 can include various types of peripheral circuitry formed using metal-oxide-semiconductor (MODS) technology.

[0073] Figure 5 A schematic diagram of a semiconductor device including peripheral circuitry and a memory array provided for embodiments of this disclosure. Figure 1 Combined with reference Figure 3 and Figure 5 The peripheral circuitry 302 may include control logic 512, a digital-to-analog converter (DAC) circuit 501 coupled to the control logic 512 and the memory array 301, and an analog-to-digital converter (ADC) circuit 502 coupled to the memory array 301 and the control logic 512. During the computation phase using semiconductor devices, the DAC circuit 501 can convert digital signals into voltage signals required by the memory array 301 in the in-memory computing chip. The ADC circuit 502 can convert the current signals output by the memory array 301 into digital signals. The control logic 512 can be coupled to the peripheral circuitry and configured to control the operation of the peripheral circuitry. The control logic 512 can also be used to receive input data sent by the controller and send the computation results to the controller.

[0074] Figure 5 Schematic diagram of the composition of the semiconductor device provided in the embodiments of this disclosure Figure 3 ,remove Figure 5 In addition to the circuit structure shown, peripheral circuitry 302 may also include a page buffer / sensor amplifier 504, a column decoder / bit line driver 506, a row decoder / word line driver 508, a voltage generator 510, a register 514, an interface 516, and a data bus 518. It should be understood that in some examples, additional components may be included. Figure 5 as well as Figure 6 Additional peripheral circuitry not shown.

[0075] Page buffer / sensor amplifier 504 can be configured to read data from and program (write) data to memory array 301 according to control signals from control logic 512. In one example, page buffer / sensor amplifier 504 can store a page of programming data (write data) to be programmed into a page of memory array 301. In another example, page buffer / sensor amplifier 504 can perform a programming verification operation to ensure that data has been correctly programmed into memory cell 306 coupled to selected word line 318. In yet another example, page buffer / sensor amplifier 504 can also sense a low-power signal from bit line 316 representing a data bit stored in memory cell 306 and amplify the corresponding signal to a recognizable logic level during a read operation. Column decoder / bit line driver 506 can be configured to be controlled by control logic 512 and select one or more memory cell strings 308 by applying a bit line voltage generated from voltage generator 510.

[0076] The row decoder / word line driver 508 can be configured to be controlled by control logic 512 and to select / deselect memory blocks 304 of memory array 301 and select / deselect word lines 318 of memory blocks 304. The row decoder / word line driver 508 can also be configured to drive word lines 318 using word line voltages generated from voltage generator 510. In some embodiments, the row decoder / word line driver 508 can also select / deselect and drive BSL 315 and TSL 313. As described in detail below, the row decoder / word line driver 508 is configured to perform programming operations on memory cells 306 coupled to one or more selected word lines 318. The voltage generator 510 can be configured to be controlled by control logic 512 and to generate word line voltages (e.g., read voltage, programming voltage, pass voltage, local voltage, verification voltage, etc., input voltage), bit line voltages, and source line voltages to be supplied to memory array 301.

[0077] Register 514 can be coupled to control logic 512 and includes a status register, a command register, and an address register for storing status information, command opcodes (OP codes), and command addresses for controlling the operation of each peripheral circuit. Interface 516 can be coupled to control logic 512 and acts as a control buffer to buffer control commands received from the host device and relay them to control logic 512, as well as to buffer status information received from control logic 512 and relay it to the host device. Interface 516 can also be coupled to column decoder / bit line driver 506 via data bus 518 and acts as a data I / O interface and data buffer to buffer data and relay it to or from memory array 301.

[0078] In some embodiments, such as Figure 6 As shown, the analog-to-digital converter (ADC) 501 can be specifically connected to the control logic 512 and the voltage generator 510, while the analog-to-digital converter (ADC) 502 can be specifically connected to the control logic 512 and the column decoder / BL driver 506. During the computation phase using the three-dimensional NAND memory, the control logic 512 receives input data from the controller. The ADC 501 converts the input data into voltage signals that need to be applied to the word lines or bit lines. The voltage generator 510 generates the corresponding voltages that need to be applied to the word lines or bit lines. The row decoder / word line driver 508 is configured to drive the selected word line using the word line voltage generated by the voltage generator 510, or the column decoder / bit line driver 506 is configured to drive the selected bit line using the bit line voltage generated by the voltage generator 510. The analog computation result is transmitted to the ADC 502 through the page buffer and the column decoder. The ADC 502 converts the analog computation result into a digital computation result and transmits the final digital computation result to the control logic 512.

[0079] In some embodiments, for in-memory computing chips, it is necessary to implement the product operation or multiplication and summation operation of input data and weight matrix. The input data can be an input vector or input matrix composed of multiple elements, and the weight matrix can include multiple weights. Each element in the input data needs to be multiplied and summed with the multiple weights in the weight matrix to obtain the corresponding element in the output data.

[0080] To achieve the aforementioned computational functions, the memory array 301 in the semiconductor device 300 can be configured to store a weight matrix. Specifically, the weights in the weight matrix can be written into the memory array 301 according to a certain mapping rule, and each memory cell 306 in the memory array 301 can be configured to store one weight. During the computation phase, the semiconductor device 300 can receive input data from the controller. The input data can be an input vector or an input matrix composed of multiple elements. Each element in the input data can be converted into an input voltage by the digital-to-analog converter circuit 501 and input to the memory array 301 via the bit line 316 or the word line 318.

[0081] In some specific examples, Figure 7 This is a schematic diagram showing the input voltage being input to the memory block via the word line. (Example) Figure 7 As shown, the memory cells coupled to the target word line WLn can be configured as memory weights. Specifically, the memory state corresponding to the threshold voltage of a memory cell can correspond to a weight. The sensing nodes coupled to the bit lines can be pre-charged to the target voltage. An input voltage V is applied to the target word line WLn. in And apply a turn-on voltage V to the non-target word line coupled to the same memory block. pass This ensures that all memory cells coupled to non-target word lines are in a conducting state, and applies corresponding on-state voltages to the top select line and bottom select line in the memory block. In this case, the following checks are performed: whether each memory cell string generates a current greater than a preset value, and whether the threshold voltage of the memory cell coupled to the target word line WLn is greater than the input voltage V. in Related to, when the input voltage V in When the voltage exceeds the threshold voltage of the memory cell, the memory cell string to which that memory cell belongs is turned on, and the sensing node discharges through the memory cell string, generating a current greater than a preset value. When the input voltage V... in When the voltage is less than the threshold voltage of the memory cell, the memory cell string to which that memory cell belongs is turned off, and no significant current is generated. In this case, the current on each bit line can be detected at the end coupled to the sensing circuit. Taking bit line BL0 as an example, the current I0 on it corresponds to the input voltage V. in The corresponding input data and weights w are respectively 00 w 10 w 20 The result of multiplying and accumulating the products is that the current I1 on bit line BL1 corresponds to the input voltage V. in The corresponding input data and weights w are respectively 01 w 11 w 21 The result of multiplying and accumulating the products is that the current I2 on bit line BL2 corresponds to the input voltage V. in The corresponding input data and weights w are respectively02 w 12 w 22 Multiply and then sum the results.

[0082] In other specific examples, Figure 8 This is a schematic diagram showing the input voltage being input to the memory block via the top select line. (See diagram below.) Figure 8 As shown, the memory cells coupled to the target word line WLn can be configured as a storage weight matrix. Specifically, the memory state corresponding to the threshold voltage of the memory cell can correspond to a weight. The sensing nodes coupled to the bit lines can be pre-charged to the target voltage. A read voltage is applied to the target word line WLn. Taking a single-level cell as an example, the read voltage can be located between the first threshold voltage range corresponding to the first memory state and the second threshold voltage range corresponding to the second memory state. An on-state voltage V is applied to the non-target word lines coupled to the same memory block. pass This ensures that all memory cells coupled to non-target word lines are in a conducting state, and applies a corresponding conduction voltage to the bottom select line of the memory block. Input voltage V is then applied to the top select lines TSL0, TSL1, and TSL2 of the memory block. in0 V in1 V in2 In this case, it depends on whether each string of memory cells in the memory block generates a current greater than a preset value, whether the threshold voltage of the memory cell coupled to the target word line WLn is greater than the read voltage, and the input voltage applied to the top select line coupled to the string of memory cells. When the input voltage V applied to the top select line... in When the top select transistor coupled to the top select line is in the ON state, and the read voltage is greater than the threshold voltage of the memory cell, the memory cell string to which the memory cell belongs is turned on. The sensing node discharges through the memory cell string, and the memory cell string generates a current greater than a preset value. When the input voltage V applied to the top select line... in This ensures that the top select transistor coupled to the top select line is in the off state, and / or that the read voltage is less than the threshold voltage of the memory cell, thus turning off the memory cell string to which the memory cell belongs, without generating a significant current. The calculation result can be obtained by sensing the current on the bit line coupled to the target memory block and based on the current on the bit line coupled to the target memory cell. For example, sensing the current I0 on bit line BL0 can yield the result related to the input voltage V. in0 Corresponding elements and weights w 00 The product of the input voltage V in1 Corresponding elements and weights w 10 The product of the input voltage V in2 Corresponding elements and weights w 20 The sum of the product of these three.

[0083] In some specific examples, such as Figure 9 As shown, the input voltage can also be applied to the memory block via the bottom select line, and a corresponding on-state voltage can be applied to the top select lines of the memory block. Input voltages V can also be applied to the bottom select lines BSL0, BSL1, and BSL2 of the memory block, respectively. in0 V in1 V in2 . Figure 9 The calculation method shown is the same as Figure 8 Similar examples are shown, so I will not repeat them here.

[0084] In some embodiments, before performing calculations using semiconductor devices, memory cells need to be programmed to store weight matrices in the memory array. Programming semiconductor devices primarily employs Incremental Step Pulse Programming (ISPP). In ISPP programming, the entire programming process can include multiple programming loops, such as a first programming loop, a second programming loop, and so on up to the Nth programming loop. In some specific embodiments, each programming loop can include multiple stages; for example, a programming loop can include a pre-charge stage, a programming stage, and a verification stage. In the verification stage, programming verification operations are performed. Specifically, a verification voltage can be applied to the word lines coupled to the memory cell to be verified, and corresponding on-state voltages can be applied to the word lines coupled to other memory cells. In the programming stage, a corresponding programming voltage is applied to the target word line. The application of the programming voltage can involve first applying a programming start voltage, then gradually increasing it by a step voltage. Furthermore, in the programming stage, a programmable disable voltage can be applied to the bit lines coupled to memory cells already programmed to the target state among the multiple memory cells coupled to the target word line.

[0085] Figure 10 This is a graph showing the distribution of threshold voltages in memory cells after programming them using the ISPP programming method. (Example:) Figure 10 As shown, a memory cell can be a single-level cell. Memory cells within a memory block have a first memory state (erase state E) and a second memory state (programmable state P). The upper limit of the threshold voltage for the first memory state is -aV, and the lower limit of the threshold voltage for the second memory state is aV. For example... Figure 11 As shown, during the programming process using the ISPP programming method, the programming voltage Vpgm applied in the operation phase of each programming cycle is the programming voltage applied in the previous programming cycle plus a step voltage Δispp. In the verification phase, verification voltages of -aV and aV can be applied to the target word line respectively, and a voltage of 0V is applied to the target word line in the operation phase. Figure 12 This diagram illustrates the relationship between the current in the memory cell string and the voltage applied to the word line coupled to the target memory cell. From... Figure 12 As can be seen, when a 0V voltage is applied to the word line coupled to the target memory cell during the computation phase, the current distribution in the memory cell string is relatively wide, which affects the accuracy of the computation. How to narrow the current distribution during the computation process and improve the accuracy of the computation has become an urgent problem to be solved.

[0086] The present disclosure provides the following implementation methods.

[0087] This disclosure provides a semiconductor device, see reference. Figure 1 , Figure 3 and Figure 6 The semiconductor device includes a memory array 301 and peripheral circuitry 302 coupled to the memory array 301. The peripheral circuitry is configured to: apply a first verification voltage to a word line coupled to a target memory cell during the verification phase of a first programming cycle; and apply a first voltage to a word line coupled to the target memory cell during an operation phase using the semiconductor device; wherein the absolute value of the difference between the first voltage and the first verification voltage is less than a first preset value.

[0088] In this embodiment of the present disclosure, the absolute value of the difference between the first verification voltage applied during the verification phase after programming the word line coupled to the target memory cell and the first voltage applied to the word line coupled to the target memory cell is less than a first preset value. That is, the difference between the first verification voltage and the first voltage is small. During the programming of the memory cell, the first verification voltage is applied to perform the verification operation on the memory cell, so that the current distribution under the first verification voltage is narrow. In the operation phase, the first voltage applied to the word line coupled to the target memory cell is close to the first verification voltage, thereby narrowing the current distribution during the operation process and improving the accuracy of memory operation.

[0089] In this embodiment of the disclosure, the first voltage can be as follows: Figure 7 The input voltage Vin applied to the target word line WLn, as shown, is a first voltage located between the threshold voltage range of the first memory state of a single-level cell and the threshold voltage range of the second memory state. The first voltage can also be as follows: Figure 8 as well as Figure 9 The first voltage, Vrd, applied to the target word line WLn, is located between the threshold voltage range of the first memory state of the single-level cell and the threshold voltage range of the second memory state.

[0090] In some embodiments, the first preset value is less than or equal to 0.1V.

[0091] It should be noted that the range of the first preset value mentioned above is only an example and is not intended to limit the value of the first preset value in the embodiments of this disclosure. In some specific examples, the first preset value can be specifically set according to the current distribution.

[0092] In some embodiments, the first verification voltage is equal to the first voltage.

[0093] like Figure 13 As shown, the first verification voltage applied to the word line (TargetedWL) coupled to the target memory cell during the verification phase of the first programming cycle is equal to the first voltage applied to the word line (TargetedWL) coupled to the target memory cell during the operation phase; for example, both can be 0V. It should be noted that the specific values ​​of the first voltage and the first verification voltage in the above embodiments are merely examples and are not intended to limit the specific values ​​of the first voltage and the first verification voltage in the embodiments of this disclosure.

[0094] In this embodiment of the disclosure, when the first verification voltage is equal to the first voltage, that is, when the first verification voltage is consistent with the first voltage, the current distribution in the operation phase can be further narrowed.

[0095] In some embodiments, the peripheral circuit is configured to: apply a first programming voltage to the word line coupled to the target memory cell during the programming phase of the first programming cycle; and apply a second programming voltage to the word line coupled to the target memory cell during the programming phase of the second programming cycle following the first programming cycle; wherein the difference between the second programming voltage and the first programming voltage is less than a second preset value.

[0096] In some embodiments, the second preset value is less than or equal to 0.1V.

[0097] It should be noted that the range of the second preset value mentioned above is only an example and is not intended to limit the value of the second preset value in the embodiments of this disclosure. In some specific examples, the second preset value can be specifically set according to the current distribution.

[0098] In some embodiments, the first programming voltage is less than or equal to the second programming voltage.

[0099] like Figure 13 As shown, the first programming voltage applied to the word line (TargetedWL) coupled to the target memory cell during the programming phase of the first programming cycle is equal to the second programming voltage applied to the word line (TargetedWL) coupled to the target memory cell during the programming phase of the second programming cycle, both being Vpgm.

[0100] In this embodiment of the disclosure, during the programming of the memory cell, the step voltage can be minimized. That is, the difference in programming voltage applied to the programming stage of two adjacent programming cycles in multiple programming cycles is small, and the step voltage can even be made to be 0 so that the programming voltage applied to the programming stage of two adjacent programming cycles is equal. This allows for further narrowing of the current distribution and further improvement of the accuracy of memory calculation.

[0101] In some embodiments, the target storage unit is configured to store one bit of data, such as Figure 13 As shown, the peripheral circuit is configured to apply a second verification voltage to the word line (Targeted WL) coupled to the target memory cell during the verification phase of the second programming cycle following the first programming cycle. The first verification voltage is equal to the second verification voltage. For example, both the first verification voltage and the second verification voltage can be 0V.

[0102] In this embodiment of the disclosure, the verification voltage of the word line coupled to the target memory cell can be kept consistent during the verification phase of multiple programming loops, which allows for further narrowing of the final current distribution and improvement of computational accuracy.

[0103] It should be noted that in this embodiment of the disclosure, only two programming loops are used as an example for description, but they are not intended to limit the number of programming loops in the programming process in this embodiment of the disclosure. The first programming loop and the second programming loop can be any two programming loops in the programming process.

[0104] In some embodiments, during the verification phase of the first programming loop, the peripheral circuit is configured to: precharge the sensing node coupled to the target memory cell to a target voltage; based on the target state of the target memory cell being a first memory state, at a first moment after the sensing node begins to discharge through the memory cell string to which the target memory cell belongs, sense the current of the bit line coupled to the target memory cell; based on the target state of the target memory cell being a second memory state, at a second moment after the sensing node begins to discharge through the memory cell string to which the target memory cell belongs, sense the current of the bit line coupled to the target memory cell; the threshold voltage corresponding to the target memory cell being in the first memory state is less than the threshold voltage corresponding to the target memory cell being in the second memory state; and the time interval between the moment when the sensing node begins to discharge through the memory cell string to which the target memory cell belongs and the first moment is less than the time interval between the moment when the sensing node begins to discharge through the memory cell string to which the target memory cell belongs and the second moment.

[0105] In this embodiment, the first memory state can be an erase state E, and the second memory state can be a programmable state P. During the verification phase, the sensing node coupled to the target memory cell can be pre-charged to the target voltage. After applying the verification voltage to the word line coupled to the memory cell, as... Figure 14 As shown, the discharge speed of the sensing node varies. When the threshold voltage of the target memory cell is lower than the verification voltage, the sensing node can quickly discharge through the memory cell string to which the target memory cell belongs. The lower the threshold voltage of the target memory cell, the faster the sensing node discharges. For example... Figure 14 The discharge rates of nodes ③ and ④ are relatively fast, with node ④ discharging faster than node ③. When the threshold voltage of the target memory cell is greater than the verification voltage, the discharge rate of the sensing node is relatively slow, for example... Figure 14 The discharge rates of ① and ② are relatively slow, with the discharge rate of ① being slower than that of ②. In this embodiment, when a verification voltage between the threshold voltage range of the first memory state and the threshold voltage range of the second memory state is applied to the word line coupled to the target memory cell, the sensing node coupled to the memory cell in the erase state E discharges rapidly through the memory cell string to which the target memory cell belongs, while the sensing node coupled to the memory cell in the programming state P does not discharge or discharges very slowly through the memory cell string to which the target memory cell belongs. For memory cells in different memory states, the time interval between the moment of the current on the sensing bit line and the moment when the sensing node begins to discharge through the memory cell string to which the target memory cell belongs is different, which improves the verification accuracy.

[0106] In some embodiments, during the computation phase using the semiconductor device, the peripheral circuitry is configured to: precharge a sensing node coupled to the target memory cell to a target voltage; sense the current in a bit line coupled to the target memory cell; and obtain a computation result based on the current in the bit line coupled to the target memory cell.

[0107] As mentioned above... Figure 7 , Figure 8 as well as Figure 9 As described in this embodiment of the present disclosure, during the computation phase, the sensing node coupled to the target memory cell is pre-charged to the target voltage, the current of the bit line coupled to the target memory cell is sensed, and then the current is converted into the computation result by an analog-to-digital converter.

[0108] In some embodiments, the peripheral circuit is configured to: apply a second voltage to the word line coupled to the target memory cell during a computation phase using the semiconductor device; the second voltage is less than the first voltage, and the second voltage causes multiple memory cells coupled to the word line coupled to the target memory cell to be in a turned-off state.

[0109] In such Figure 7In the operation method shown where the input voltage is input to the memory block via the word line, the first voltage can be a voltage between the threshold voltage range of the first memory state and the threshold voltage range of the second memory state, and the second voltage can be a voltage less than the threshold voltage range of the first memory state.

[0110] In some embodiments, the peripheral circuitry is configured to apply corresponding on-state voltages to the top select line, the bottom select line, and word lines other than the word lines coupled to the target memory cell during the computation phase using the semiconductor device.

[0111] In such Figure 7 In the illustrated storage method, corresponding on-state voltages can be applied to each word line except for the top select line, bottom select line, and the word line coupled to the target memory cell, so that all memory cells coupled to the word lines except for the upper select transistor, lower select transistor, and the word line coupled to the target memory cell are in a conducting state. The on-state voltages applied to the word lines except for the top select line, bottom select line, and the word line coupled to the target memory cell can be the same or different; the on-state voltages applied to different top select lines can be the same or different; the on-state voltages applied to different bottom select lines can be the same or different; and the on-state voltages applied to different word lines other than the word line coupled to the target memory cell can be the same or different.

[0112] In such Figure 8 In the memory computing method shown, the peripheral circuitry can be configured to apply a corresponding input voltage to the top select line, a corresponding turn-on voltage to the bottom select line, and corresponding turn-on voltages to the word lines other than the word line coupled to the target memory cell during the computation phase using semiconductor devices. The input voltage applied to the top select line can either turn on the upper select transistor coupled to the top select line or turn it off.

[0113] In such Figure 9 In the memory computing method shown, the peripheral circuit can be configured to apply a corresponding input voltage to the bottom select line, a corresponding turn-on voltage to the top select line, and corresponding turn-on voltages to the word lines other than the word line coupled to the target memory cell during the computation phase using semiconductor devices. The input voltage applied to the bottom select line can either turn on the upper select transistor coupled to the bottom select line or turn off the upper select transistor coupled to the bottom select line.

[0114] The following is based on Figure 8 Taking the storage and calculation method shown as an example, combined with Figure 15 Further explanation is needed.

[0115] Combined with reference Figure 8 and Figure 15 Taking a memory block comprising a string of eight memory cells coupled to bit line BL0 as an example, four memory cells coupled to the target word line WLn are in the first memory state (erase state E), and the other four memory cells are in the second memory state (programming state P). Input data can be input from the eight top select lines TSL0 to TSL7. Specifically, the input data can be an input vector comprising eight elements, which can include five logic "1"s and three logic "0"s. The digital-to-analog converter circuit can convert each element of the input vector into a corresponding voltage signal, and the voltage signal is converted into an input voltage to be applied to the top select line by a voltage generator. The input voltage is then transmitted to the top select word line by a driver coupled to the top select line. Specifically, the eight input voltages can be applied to the eight top select lines simultaneously. Among them, the input voltage corresponding to "1" includes V in0 V in1 V in4 V in5 and V in6 This allows the top selection transistors TSG0, TSG1, TSG4, TSG5, and TSG6, respectively coupled to the top selection lines TSL0, TSL1, TSL4, TSL5, and TSL6, to be turned on. The input voltages corresponding to "0" include V. in2 V in3 V in7 This allows the top selection transistors TSG2, TSG3, and TSG7, which are coupled to the top selection lines TSL2, TSL3, and TSL7 respectively, to be turned off. During the computation phase using the semiconductor device, the peripheral circuitry is configured to apply a corresponding first on-state voltage V to the non-target word lines (WL0~WLn-1 and WLn+1~WL_end). pass1 This ensures that all memory cells coupled to non-target word lines are turned on; a corresponding second on-state voltage V is applied to the bottom select line BSL coupled to the memory block. pass2This ensures that all bottom select transistors coupled to the bottom select line BSL are turned on. The current I0 on the bit line BL0 is the sum of the output currents of the eight memory cell strings coupled to the bit line BL0. The input voltage on the top select line coupled to memory cell strings Str0, Str4, and Str5 causes the top select transistors TSG0, TSG4, and TSG5 to be turned on. The memory cells in memory cell strings Str0, Str4, and Str5 coupled to the target word line WLn have a first memory state (erase state E). Therefore, memory cell strings Str0, Str4, and Str5 are turned on and can generate current. The current I0 on the bit line BL0 is approximately equal to the sum of the output currents of memory cell strings Str0, Str4, and Str5, and the multiple of current I0 relative to the current generated by any one of the memory cell strings Str0, Str4, and Str5 is approximately 3. If the weight value stored in the memory cell in the first memory state is equivalent to "1", and the weight value stored in the memory cell in the second memory state is equivalent to "0", then the operation performed by the eight memory cell strings coupled to the bit line BL0 can be equivalent to: 1*1+1*0+0*1+0*0+1*1+1*1+1*0+0*0=3.

[0116] In some embodiments, the peripheral circuitry includes: an analog-to-digital converter circuit, a column decoder, control logic, a digital-to-analog converter circuit, and a voltage generator; the analog-to-digital converter circuit is coupled to the column decoder and the control logic; the digital-to-analog converter circuit is coupled to the voltage generator and the control logic.

[0117] In some embodiments, the semiconductor device in the above embodiments includes a three-dimensional NAND type memory.

[0118] In some embodiments, the semiconductor device in the above embodiments includes a first semiconductor structure and a second semiconductor structure, the memory array is located in the first semiconductor structure, the peripheral circuit is located in the second semiconductor structure, and the first semiconductor structure and the second semiconductor structure are stacked along the thickness direction of the semiconductor device.

[0119] In some embodiments, the semiconductor device includes a first semiconductor structure, a bonding layer, and a second semiconductor structure stacked along the thickness direction of the semiconductor device; the memory array is located in the first semiconductor structure, the peripheral circuit is located in the second semiconductor structure, and the peripheral circuit and the memory array are coupled through the bonding structure in the bonding layer.

[0120] In the embodiments of this disclosure, the first semiconductor structure and the second semiconductor structure of the semiconductor device can be formed by bonding two wafers. For example, the first semiconductor structure can be formed on one wafer, and the second semiconductor structure can be formed on another wafer, and then the two wafers can be bonded together. The first semiconductor structure and the second semiconductor structure are stacked along the thickness direction of the semiconductor device. In other embodiments, the first semiconductor structure and the second semiconductor structure of the semiconductor device can also be formed on the same wafer, but the first semiconductor structure and the second semiconductor structure are stacked along the thickness direction of the semiconductor device. This stacked architecture of the first semiconductor structure and the second semiconductor structure along the thickness direction of the semiconductor device can save more area of ​​the semiconductor device.

[0121] In some embodiments, such as Figure 1 As shown, a memory array may include multiple memory surfaces, each including multiple memory blocks. Peripheral circuitry can be configured to: simultaneously apply a corresponding first voltage to target word lines coupled to each of the multiple memory blocks; simultaneously apply a corresponding input voltage to multiple top select lines coupled to each of the multiple memory blocks, or simultaneously apply a corresponding input voltage to multiple bottom select lines coupled to each of the multiple memory blocks, or simultaneously apply a corresponding on-state voltage to both the multiple top select lines and bottom select lines coupled to each of the multiple memory blocks; and simultaneously sense current on bit lines coupled to the multiple memory blocks. Thus, multiple memory blocks in a semiconductor device can perform operations in parallel, thereby improving the computing power of the semiconductor device.

[0122] In this embodiment of the disclosure, the peripheral circuit can also be configured to perform logical operations based on the operation results corresponding to multiple storage surfaces. That is, the peripheral circuit can also perform logical operations again on the operation results corresponding to different storage surfaces. For example, the peripheral circuit can be configured to add the operation results output simultaneously by at least two storage surfaces.

[0123] Based on a concept similar to the aforementioned semiconductor device, this disclosure also provides a method for operating a semiconductor device. Figure 16 This is a schematic flowchart illustrating the operation method of the semiconductor device provided in the embodiments of this disclosure, such as... Figure 16 As shown, the operation method of a semiconductor device includes the following steps.

[0124] Step S10: During the verification phase of the first programming cycle, a first verification voltage is applied to the word line coupled to the target memory cell.

[0125] Step S20: During the computation phase using the semiconductor device, a first voltage is applied to the word line coupled to the target memory cell; the absolute value of the difference between the first voltage and the first verification voltage is less than a first preset value.

[0126] The first preset value is less than or equal to 0.1V.

[0127] In some embodiments, the first verification voltage is equal to the first voltage.

[0128] In some embodiments, the operation method further includes: applying a first programming voltage to a word line coupled to the target memory cell during the programming phase of the first programming cycle; applying a second programming voltage to the word line coupled to the target memory cell during the programming phase of a second programming cycle following the first programming cycle; wherein the difference between the second programming voltage and the first programming voltage is less than a second preset value.

[0129] In some embodiments, the second preset value is less than or equal to 0.1V.

[0130] In some embodiments, the first programming voltage is less than or equal to the second programming voltage.

[0131] In some embodiments, the target storage cell is configured to store one bit of data, and the operation method further includes: applying a second verification voltage to a word line coupled to the target storage cell during a verification phase of a second programming cycle following the first programming cycle, wherein the first verification voltage is equal to the second verification voltage.

[0132] In some embodiments, during the verification phase of the first programming loop, the operation method further includes: pre-charging the sensing node coupled to the target memory cell to a target voltage; based on the target state of the target memory cell being a first memory state, sensing the current of the bit line coupled to the target memory cell at a first moment after the sensing node begins to discharge through the memory cell string to which the target memory cell belongs; based on the target state of the target memory cell being a second memory state, sensing the current of the bit line coupled to the target memory cell at a second moment after the sensing node begins to discharge through the memory cell string to which the target memory cell belongs; the threshold voltage corresponding to the target memory cell being in the first memory state is less than the threshold voltage corresponding to the target memory cell being in the second memory state; and the time interval between the moment when the sensing node begins to discharge through the memory cell string to which the target memory cell belongs and the first moment is less than the time interval between the moment when the sensing node begins to discharge through the memory cell string to which the target memory cell belongs and the second moment.

[0133] In some embodiments, during the computation phase using the semiconductor device, the operation method further includes: pre-charging a sensing node coupled to the target memory cell to a target voltage; sensing the current of a bit line coupled to the target memory cell; and obtaining a computation result based on the current of the bit line coupled to the target memory cell.

[0134] In some embodiments, the operation method further includes: during a computation phase using the semiconductor device, applying a second voltage to a word line coupled to the target memory cell; the second voltage is less than the first voltage, and the second voltage causes multiple memory cells coupled to the word line coupled to the target memory cell to be in a turned-off state.

[0135] In some embodiments, the operation method further includes: during the computation phase using the semiconductor device, applying corresponding on-state voltages to the top select line, the bottom select line, and word lines other than the word lines coupled to the target memory cell.

[0136] Based on a concept similar to the semiconductor devices described above, this disclosure also provides a system comprising: at least one semiconductor device as described in any of the above embodiments and a controller coupled to the semiconductor device.

[0137] In some embodiments, the controller is configured to send input vectors or input matrices to the semiconductor device and receive the computation results from the semiconductor device.

[0138] In some embodiments, the system described above may be as follows: Figure 17 The memory system 102 shown includes a memory controller 106 and a memory device 104 coupled to the memory controller 106. In the above embodiment, the controller may be the memory controller 106 and the semiconductor device may be the memory device 104.

[0139] In other embodiments, the system described in the above embodiments can be as follows: Figure 18 The system 100 shown includes a host 108 and a memory device 104 coupled to the host 108. The controller in the above embodiment may be the CPU in the host 108.

[0140] According to some implementation methods, such as Figure 17 As shown, memory controller 106 is coupled to memory device 104 and host 108, and is configured to control the operation of memory device 104, such as read, erase, program, and compute operations. Memory controller 106 can manage data stored in memory device 104 and communicate with host 108.

[0141] In such Figure 19In one example shown, the system can be integrated into a memory card 202. The semiconductor device in the system can be the memory 104 within the memory card 202, and the controller in the system can be the memory controller 106 within the memory card 202. The memory card 202 can be a compact flash memory card, a smart media card (SMC), a memory stick (MS), a multi-media card (MMC), such as RS-MMC, MMCmicro, eMMC, etc., a secure digital card, such as a Mini SD card, Micro SD card, SDHC card, etc., or a general-purpose flash memory card. The memory card 202 may also include a memory card connector 204 that couples the memory card 202 to a host computer. Figure 20 In another example shown, the system can be integrated into a solid-state drive (SSD) 206. The semiconductor device in the system can be the memory device 104 within the SSD 206, and the controller in the system can be the memory controller 106 within the SSD 206. The SSD 206 may also include a solid-state drive connector 208 that couples the SSD 206 to a host device. In some embodiments, the storage capacity and / or operating speed of the SSD 206 is greater than the storage capacity and / or operating speed of the memory card 202.

[0142] In other embodiments, the system can be integrated into the terminal device, and the controller can be the central processing unit (CPU) of the terminal device. Here, the terminal device can be, but is not limited to, any terminal device or portable terminal device such as mobile phone, smart TV, smart speaker, wearable device, tablet computer, desktop computer, all-in-one computer, handheld computer, laptop computer, server, ultra-mobile personal computer (UMPC), netbook, personal digital assistant (PDA), laptop computer, mobile computer, augmented reality (AR) device, virtual reality (VR) device, artificial intelligence (AI) device, etc.

[0143] Based on a concept similar to the operation method of the aforementioned semiconductor devices, this disclosure also provides a computer-readable storage medium. Figure 21This disclosure provides a schematic diagram of a computer-readable storage medium according to an embodiment. The computer-readable storage medium 601 stores a computer program, which, when executed by the processor 602, can implement the operation method of the semiconductor device in any of the above embodiments.

[0144] In some specific embodiments, the computer-readable storage medium 601 may be a magnetic random access memory (FRAM), a read-only memory (ROM), a programmable read-only memory (PROM), an erasable programmable read-only memory (EPROM), an electrically erasable programmable read-only memory (EEPROM), a flash memory, a magnetic surface memory, an optical disc, or a compact disc read-only memory (CD-ROM), etc.; or it may be a device that includes one or any combination of the above-mentioned memory devices.

[0145] The features disclosed in the several device embodiments provided in this disclosure can be arbitrarily combined without conflict to obtain new device embodiments.

[0146] The methods disclosed in the several method embodiments provided in this disclosure can be arbitrarily combined without conflict to obtain new method embodiments.

[0147] The above description is merely a specific embodiment of this disclosure, but the scope of protection of this disclosure is not limited thereto. Any changes or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this disclosure should be included within the scope of protection of this disclosure.

Claims

1. A semiconductor device, characterized by, The semiconductor device includes a memory array and a peripheral circuit coupled with the memory array, the peripheral circuit is configured to: In a verify phase of the first programming cycle, a first verify voltage is applied to a word line coupled with the target memory cell; In an operation phase using the semiconductor device, a first voltage is applied to the word line coupled with the target memory cell; An absolute value of a difference between the first voltage and the first verify voltage is less than a first preset value.

2. The semiconductor device according to claim 1, wherein The first preset value is less than or equal to 0.1V.

3. The semiconductor device of claim 1, wherein The first verify voltage is equal to the first voltage.

4. The semiconductor device of claim 1, wherein The peripheral circuit is configured to: In a program phase of the first programming cycle, a first program voltage is applied to the word line coupled with the target memory cell; In a program phase of a second programming cycle after the first programming cycle, a second program voltage is applied to the word line coupled with the target memory cell; A difference between the second program voltage and the first program voltage is less than a second preset value.

5. The semiconductor device according to claim 4, wherein The second preset value is less than or equal to 0.1V.

6. The semiconductor device of claim 4, wherein The first program voltage is less than or equal to the second program voltage.

7. The semiconductor device of claim 1, wherein The target memory cell is configured to store one bit of data, and the peripheral circuit is configured to: In a verify phase of a second programming cycle after the first programming cycle, a second verify voltage is applied to the word line coupled with the target memory cell, and the first verify voltage is equal to the second verify voltage.

8. The semiconductor device of claim 1, wherein In the verify phase of the first programming cycle, the peripheral circuit is configured to: Pre-charge a sensing node coupled with the target memory cell to a target voltage; Based on a target state of the target memory cell being a first memory state, sense a current of a bit line coupled with the target memory cell at a first time after the sensing node starts discharging through a memory cell string to which the target memory cell belongs; Based on the target state of the target memory cell being a second memory state, sense the current of the bit line coupled with the target memory cell at a second time after the sensing node starts discharging through the memory cell string to which the target memory cell belongs; A threshold voltage corresponding to the first memory state of the target memory cell is less than a threshold voltage corresponding to the second memory state of the target memory cell; and a time interval between a time when the sensing node starts discharging through the memory cell string to which the target memory cell belongs and the first time is less than a time interval between the time when the sensing node starts discharging through the memory cell string to which the target memory cell belongs and the second time.

9. The semiconductor device of claim 1, wherein, In the operation phase using the semiconductor device, the peripheral circuit is configured to: Pre-charge the sensing node coupled with the target memory cell to the target voltage; Sense the current of the bit line coupled with the target memory cell; Obtain an operation result based on the current of the bit line coupled with the target memory cell.

10. The semiconductor device of claim 1, wherein The peripheral circuit is configured to: In the operation phase using the semiconductor device, a second voltage is applied to the word line coupled with the target memory cell; the second voltage is less than the first voltage, and the second voltage causes a plurality of memory cells coupled with the word line coupled with the target memory cell to be in an off state.

11. The semiconductor device of claim 1, wherein The peripheral circuit is configured to: In an operation stage using the semiconductor device, a corresponding turn-on voltage is applied to a word line other than the word line coupled to the top selection line, the bottom selection line, and the target memory cell.

12. The semiconductor device of claim 1, wherein The peripheral circuit includes an analog-to-digital conversion circuit, a column decoder, control logic, a digital-to-analog conversion circuit, and a voltage generator; the analog-to-digital conversion circuit is coupled to the column decoder and the control logic; the digital-to-analog conversion circuit is coupled to the voltage generator and the control logic.

13. The semiconductor device of claim 1, wherein The semiconductor device includes a three-dimensional NAND type memory.

14. The semiconductor device of claim 1, wherein The semiconductor device includes a first semiconductor structure and a second semiconductor structure; the memory array is located in the first semiconductor structure, and the peripheral circuit is located in the second semiconductor structure; the first semiconductor structure and the second semiconductor structure are stacked along the thickness direction of the semiconductor device.

15. A system, comprising: Comprising: at least one semiconductor device as claimed in any one of claims 1 to 14; a controller coupled to the at least one semiconductor device and configured to send input data to the semiconductor device and accept the operation result of the semiconductor device.

16. A method of operating a semiconductor device, characterized by, The operation method comprises: In the verification stage of the first programming cycle, a first verification voltage is applied to the word line coupled to the target memory cell; In the operation stage using the semiconductor device, a first voltage is applied to the word line coupled to the target memory cell; the absolute value of the difference between the first voltage and the first verification voltage is less than a first preset value.

17. The method of operation of claim 16, wherein, The first preset value is less than or equal to 0.1V.

18. The method of claim 16, wherein, The first verification voltage is equal to the first voltage.

19. The method of claim 16, wherein, The operation method further comprises: In the programming stage of the first programming cycle, a first programming voltage is applied to the word line coupled to the target memory cell; In the programming stage of the second programming cycle after the first programming cycle, a second programming voltage is applied to the word line coupled to the target memory cell; the difference between the second programming voltage and the first programming voltage is less than a second preset value.

20. The method of claim 19, wherein, The second preset value is less than or equal to 0.1V.

21. The method of claim 19, wherein, The first programming voltage is less than or equal to the second programming voltage.

22. The method of claim 16, wherein, The target memory cell is configured to store one bit of data, and the operation method further comprises: In the verification stage of the second programming cycle after the first programming cycle, a second verification voltage is applied to the word line coupled to the target memory cell, and the first verification voltage is equal to the second verification voltage.

23. The method of claim 16, wherein, In the verification stage of the first programming cycle, the operation method further comprises: Pre-charge the sensing node coupled to the target memory cell to a target voltage; Based on the target state of the target memory cell being a first memory state, at a first time when the sensing node starts discharging through the memory cell string to which the target memory cell belongs, sense the current of the bit line coupled to the target memory cell. the target memory cell is in the first memory state, sensing a current of a bit line coupled with the target memory cell at a second time point after the sensing node starts discharging through a memory cell string to which the target memory cell belongs; the threshold voltage corresponding to the first memory state of the target memory cell is less than the threshold voltage corresponding to the second memory state of the target memory cell; and a time interval between the time point at which the sensing node starts discharging through the memory cell string to which the target memory cell belongs and the first time point is less than a time interval between the time point at which the sensing node starts discharging through the memory cell string to which the target memory cell belongs and the second time point.

24. The method of claim 16, wherein, In the operation stage using the semiconductor device, the operation method further includes: pre-charging a sensing node coupled with the target memory cell to a target voltage; sensing a current of a bit line coupled with the target memory cell; obtaining an operation result based on the current of the bit line coupled with the target memory cell.

25. The method of claim 16, wherein, The operation method further includes: In the operation stage using the semiconductor device, applying a second voltage to a word line coupled with the target memory cell; the second voltage is less than the first voltage, and the second voltage causes all memory cells coupled with the word line to be in an off state.

26. The method of claim 16, wherein, The operation method further includes: In the operation stage using the semiconductor device, applying a corresponding turn-on voltage to a top selection line, a bottom selection line, and a word line other than the word line coupled with the target memory cell, respectively.

27. A computer readable storage medium, having stored thereon a computer program, the computer program being executed by a processor to perform the operation method of any one of claims 16 to 26.

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