Storage unit, programming method thereof and computer readable storage medium
By adjusting the voltage and time increments to adapt to changes in the number of cells to be programmed in the FLASH memory, the problems of low programming efficiency and high power consumption caused by multiple pressure applications are solved, achieving a more efficient and low-power programming effect.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-09-09
- Publication Date
- 2026-03-10
AI Technical Summary
In FLASH memory, the parameter differences among multiple storage cells make it impossible to complete programming with a single pressure application, resulting in low programming efficiency and increased power consumption.
By determining the number of memory cells to be programmed, the voltage and time increments are adjusted accordingly to gradually optimize the programming voltage and time, thus adapting to the programming requirements of different memory cells.
It improves programming efficiency, reduces power consumption, and ensures a high programming success rate.
Smart Images
Figure CN121641129A_ABST
Abstract
Description
TECHNICAL FIELD
[0001] The present application relates to the technical field of storage, in particular to a storage unit, a programming method thereof and a computer readable storage medium. BACKGROUND
[0002] FLASH memory is a kind of non-volatile memory, which is widely used in various medical electronics, automotive electronics and daily consumer electronics. How to store information faster without increasing power consumption is a topic that FLASH memory needs to research and break through forever.
[0003] When programming the storage unit in the FLASH memory, multiple storage units are often applied with voltage at the same time. However, since the parameters of different storage units are different, the programming of all storage units cannot be completed by applying voltage once, and multiple voltage applications are needed, which brings problems to the programming efficiency of FLASH memory. SUMMARY
[0004] To solve the above problems, the present application provides a storage unit, a programming method thereof and a computer readable storage medium, which can reduce the power consumption of programming and improve the efficiency of programming.
[0005] One technical solution provided by the present application is to provide a programming method of a storage unit, which comprises: determining the number of storage units to be programmed; determining the corresponding voltage increment and / or time increment according to the number of storage units to be programmed; wherein the voltage increment is positively correlated with the number of storage units to be programmed, and the time increment is positively correlated with the number of storage units to be programmed; determining the updated programming voltage according to the sum of the current programming voltage and the voltage increment, and / or determining the updated programming time according to the reference time and the time increment; and programming the storage units to be programmed using the updated programming voltage and programming time.
[0006] In an embodiment, the number of storage units to be programmed is determined by: obtaining the data to be programmed; and comparing the storage data of multiple storage units in the storage array to be programmed with the data to be programmed to determine the number of storage units with different data as the number of storage units to be programmed.
[0007] In an embodiment, comparing the storage data of multiple storage units in the storage array to be programmed with the data to be programmed to determine the number of storage units with different data as the number of storage units to be programmed comprises: sequentially comparing the storage data of multiple storage units in the storage array to be programmed with the data to be programmed; in response to the comparison result indicating that the data is different, counting and taking the count value as the number of storage units to be programmed.
[0008] In one embodiment, sequentially comparing the stored data of multiple storage cells in the storage array to be programmed with the data to be programmed includes: sequentially comparing the stored data of multiple storage cells in the storage array to be programmed with the data to be programmed, and caching the comparison results; in response to the comparison results indicating that the data is different, counting is performed, and the count value is used as the number of storage cells to be programmed, including: reading the cached comparison results, in response to the comparison results indicating that the data is different, counting is performed, and the count value is used as the number of storage cells to be programmed.
[0009] In one embodiment, the method for programming a memory cell further includes: pre-establishing a first functional relationship between a voltage increment and the number of memory cells to be programmed; pre-establishing a second functional relationship between a time increment and the number of memory cells to be programmed; and determining the corresponding voltage increment and time increment based on the number of memory cells to be programmed, including: substituting the number of memory cells to be programmed into the first functional relationship to obtain the voltage increment, and substituting the number of memory cells to be programmed into the second functional relationship to obtain the time increment.
[0010] In one embodiment, after the step of programming the memory cells to be programmed using the updated programming voltage and programming time, the step of determining the number of memory cells to be programmed is performed again.
[0011] In one embodiment, determining the updated programming voltage based on the sum of the current programming voltage and the voltage increment includes: determining the programming voltage based on a reference voltage and the voltage increment during the first programming; and determining the updated programming voltage based on the sum of the previous programming voltage and the voltage increment during the second and subsequent programming.
[0012] Another technical solution provided by this application is: a storage device comprising: a storage array including storage cells distributed in an array; a programming unit connected to the storage array; and a control unit connected to the programming unit, the control unit being configured to control the programming unit using the programming method of the storage cells as described above, so as to program the storage cells.
[0013] In one embodiment, the storage device further includes: a cache unit connected to a control unit, the control unit being configured to sequentially compare stored data of a plurality of storage units in the storage array to be programmed with data to be programmed, and cache the comparison results to the cache unit; and a counting unit connected to the cache unit, the counting unit being configured to read the comparison results from the cache unit, and to count in response to the comparison results indicating that the data are different, the control unit being configured to use the count value as the number of storage units to be programmed.
[0014] Another technical solution provided by this application is: to provide a computer-readable storage medium that stores program data, which, when executed by a processor, is used to implement the programming method of the storage unit as described above.
[0015] The programming method for memory cells provided in this application includes: determining the number of memory cells to be programmed; determining the corresponding voltage increment and / or time increment based on the number of memory cells to be programmed; wherein the voltage increment is positively correlated with the number of memory cells to be programmed, and the time increment is positively correlated with the number of memory cells to be programmed; determining the updated programming voltage based on the sum of the current programming voltage and the voltage increment, and / or determining the updated programming time based on the reference time and the time increment; and performing programming operations on the memory cells to be programmed using the updated programming voltage and programming time. Through the above method, since both the voltage increment and the time increment are positively correlated with the number of memory cells to be programmed, as the number of programming attempts increases, the number of memory cells to be programmed will inevitably decrease, so the voltage increment and time increment will also decrease. Therefore, the programming voltage increases while the programming time decreases. Compared to related technologies where the voltage increment and time increment remain constant during multiple programming attempts, the programming voltage increases while the increase rate decreases, which can ensure improved programming success rate while reducing power consumption. The shorter programming time also reduces power consumption and improves programming efficiency. Attached Figure Description
[0016] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort. Wherein:
[0017] Figure 1 This is a schematic diagram of the architecture of a storage unit in one embodiment;
[0018] Figure 2 This is a schematic diagram illustrating the relationship between programming time and programming voltage in the relevant embodiments;
[0019] Figure 3 This is a flowchart illustrating an embodiment of the programming method for the storage unit provided in this application;
[0020] Figure 4 This is a schematic diagram illustrating the change in the number of memory cells to be programmed in one embodiment;
[0021] Figure 5 This is a schematic diagram illustrating the relationship between programming time and programming voltage in one embodiment;
[0022] Figure 6This is a flowchart illustrating another embodiment of the programming method for the storage unit provided in this application;
[0023] Figure 7 This is a flowchart illustrating step 62 in one embodiment;
[0024] Figure 8 This is a schematic diagram illustrating the effects of a buffer and a counter in one embodiment;
[0025] Figure 9 This is a schematic diagram of the structure of an embodiment of the storage device provided in this application;
[0026] Figure 10 This is a schematic diagram of an embodiment of the computer-readable storage medium provided in this application. Detailed Implementation
[0027] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. It is understood that the specific embodiments described herein are only for explaining this application and not for limiting it. Furthermore, it should be noted that, for ease of description, only the parts related to this application are shown in the accompanying drawings, not all structures. All other embodiments obtained by those skilled in the art based on the embodiments of this application without creative effort are within the scope of protection of this application.
[0028] The terms "first," "second," etc., used in this application are used to distinguish different objects, not to describe a specific order. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover non-exclusive inclusion. For example, a process, method, system, product, or apparatus that includes a series of steps or units is not limited to the listed steps or units, but may optionally include steps or units not listed, or may optionally include other steps or units inherent to these processes, methods, products, or apparatuses.
[0029] In this document, the term "embodiment" means that a particular feature, structure, or characteristic described in connection with an embodiment may be included in at least one embodiment of this application. The appearance of this phrase in various places throughout the specification does not necessarily refer to the same embodiment, nor is it a separate or alternative embodiment mutually exclusive with other embodiments. It will be explicitly and implicitly understood by those skilled in the art that the embodiments described herein can be combined with other embodiments.
[0030] See Figure 1 , Figure 1This is a schematic diagram of a memory cell architecture in one embodiment. This embodiment uses NAND FLASH as an example. NAND FLASH includes many data blocks, each data block consisting of many memory cells used for reading and writing data. These memory cells are arranged in an array. A specific memory cell within the array is typically selected via a word line (WL0~WLn) and a pair of bit lines (BL / BL#). The word line is typically coupled to one or more control gates of each memory cell in a row, and the bit line pair is typically coupled to the storage point of each memory cell in a column to a sense amplifier. Read, write, and erase operations on the memory cell can be achieved by controlling the high and low voltages of the word line and bit line.
[0031] Furthermore, SGD and SGS correspond to two switching transistors. By controlling these two switching transistors, the memory cells in the middle section can be selected, namely the memory cells corresponding to WL0, WL1...WLn. WL0, WL1...WLn can be called data word lines. After selection, read, write, and erase operations can be performed.
[0032] Understandably, the data stored in a memory cell is determined by the number of electrons in that cell. Therefore, applying a voltage pulse to the corresponding memory cell changes the number of electrons, thus storing information. Furthermore, the change in the number of electrons in a memory cell needs to reach a certain threshold for the information represented by the cell to change. On the other hand, even two memory cells with the same design and manufacturing process will have different changes in the number of electrons under the same voltage pulse. Therefore, in one embodiment, multiple voltage pulses need to be applied to ensure that the number of electrons in all memory cells reaches the threshold.
[0033] like Figure 2 As shown, Figure 2 This is a schematic diagram illustrating the relationship between programming time and programming voltage in a related embodiment. During multiple programming operations, the selected memory cell is subjected to voltage pulses of different magnitudes (programming voltage) and durations (programming time) during each programming operation. As each programming operation proceeds, the memory cell is subjected to voltage pulses of progressively increasing magnitude. Between two adjacent programming operations, the voltage increase and duration of the pulses are the same. For example, the voltage difference V2-V1 between the second and first pulses, and the voltage difference V3-V2 between the third and second pulses, are the same, i.e., V3-V2 = V2-V1. Similarly, the time difference T2-T1 between the second and first pulses, and the time difference T3-T2 between the third and second pulses, are the same, i.e., T3-T2 = T2-T1.
[0034] Specifically, the first pulse is applied. If all the electrons in all the memory cells reach the threshold number (the voltage reaches the threshold voltage), the programming ends. If the electrons in any memory cell do not reach the threshold number, the second pulse is applied. If all the electrons in all the memory cells reach the threshold number, the programming ends. If the electrons in any memory cell do not reach the threshold number, the third pulse is applied, and so on, until all the electrons in all the memory cells reach the threshold number, at which point the programming operation is complete.
[0035] Understandably, using the above method, the voltage increment and time increment of each pulse are the same. As the number of programming iterations increases, the total programming time also increases accordingly, which will lead to increased power consumption and reduced programming efficiency.
[0036] See Figure 3 , Figure 3 This is a flowchart illustrating an embodiment of the programming method for a storage unit provided in this application. The method includes:
[0037] Step 31: Determine the number of memory cells to be programmed.
[0038] Understandably, to improve programming efficiency, it's necessary to determine the number of memory units to be programmed before starting programming. Since the data stored in a particular memory unit might be the same as the data to be written, in this case, there's no need to program that memory unit again.
[0039] Understandably, the number of storage units corresponding to a word line is generally counted in bytes (8 bits). Typically, an integer number of storage units (bytes) can be programmed at a time. For example, 8 storage units (8 bits) can be programmed at a time, or 16 storage units (16 bits) can be programmed at a time.
[0040] In one embodiment, taking the programming operation of 8 storage units at a time as an example (i.e., 8 bits of data), the data to be written is also 8 bits. In this case, the 8 bits of data in the 8 storage units are compared with the 8 bits to be written to determine the number of storage units to be programmed. For example, if the 8 bits to be written are 11111111, and the data stored in the 8 storage units is 11001100, then 4 bits of data are different from the data to be written, and the number of storage units to be programmed is 4.
[0041] In another embodiment, taking the programming operation on 16 memory cells at a time as an example (i.e., 16 bits of data), the data to be written is also 16 bits. In this case, the 16 bits of data in the 16 memory cells are compared with the 16 bits to be written to determine the number of memory cells to be programmed. For example, if the 16 bits to be written are 1111111111111111, and the data stored in 8 memory cells is 1100110011000000, then 10 bits of data are different from the data to be written, and the number of memory cells to be programmed is 10.
[0042] Understandably, in the above embodiments, when the number of electrons stored in the storage unit is less than a quantity threshold (or the voltage is less than a voltage threshold), it represents data "1"; when the number of electrons stored in the storage unit is greater than a quantity threshold (or the voltage is greater than a voltage threshold), it represents data "0". Therefore, the programming process in this embodiment mainly refers to the process of writing "0". In other embodiments, when the number of electrons stored in the storage unit is less than a quantity threshold (or the voltage is less than a voltage threshold), it represents data "0"; when the number of electrons stored in the storage unit is greater than a quantity threshold (or the voltage is greater than a voltage threshold), it represents data "1". Therefore, in other embodiments, the above programming method can also be applied to the process of writing "1".
[0043] Step 32: Determine the corresponding voltage increment and / or time increment based on the number of memory cells to be programmed; wherein the voltage increment is positively correlated with the number of memory cells to be programmed, and the time increment is positively correlated with the number of memory cells to be programmed.
[0044] Understandably, the voltage increment is positively correlated with the number of memory cells to be programmed, and the time increment is also positively correlated with the number of memory cells to be programmed. That is, the more memory cells to be programmed, the larger the voltage increment and the time increment, and the fewer memory cells to be programmed, the smaller the voltage increment and the time increment.
[0045] Optionally, in one embodiment, a first functional relationship between the voltage increment and the number of memory cells to be programmed is established in advance; a second functional relationship between the time increment and the number of memory cells to be programmed is established in advance; step 32 may include: substituting the number of memory cells to be programmed into the first functional relationship to obtain the voltage increment, and substituting the number of memory cells to be programmed into the second functional relationship to obtain the time increment.
[0046] Specifically, the first function is:
[0047] Δv=f1(m)
[0048] Where Δv is the voltage increment and m is the number of memory cells to be programmed.
[0049] Specifically, the second function is:
[0050] Δt=f2(m)
[0051] Where Δt is the time increment and m is the number of memory units to be programmed.
[0052] Understandably, the functional relationships f1 and f2 described above are positively correlated mapping relationships.
[0053] It is worth noting that the first and second functions mentioned above vary depending on the manufacturing process, size, or material of the storage unit. During production, storage units of the same batch or model can be tested to determine the functional relationships f1 and f2.
[0054] In one embodiment, the correspondence between voltage increment Δv, time increment Δt, and the number of memory cells to be programmed m can be established in advance as shown in Table 1 below.
[0055] Table 1:
[0056] Number of storage cells to be programmed m Voltage increment Δv Time increment Δt 1 Δv1 Δt1 2 Δv2 Δt2 3 Δv3 Δt3 …… …… ……
[0057] Among them, Δv1<Δv2<Δv3, Δt1<Δt2<Δt3.
[0058] Then, after multiple programming tests, the voltage increment Δv and time increment Δt were gradually adjusted. The adjustment principle was to ensure that each programming operation enabled as many memory cells as possible to complete the programming operation (the number of electrons reached the data threshold / the voltage reached the voltage threshold), and to minimize the voltage increment Δv and time increment Δt as much as possible.
[0059] Furthermore, after adjusting the voltage increment Δv and time increment Δt, a fitting function is constructed, such as a linear function or a quadratic function (satisfying the function increment when m>1). There are no restrictions here. Then, the adjusted voltage increment Δv and time increment Δt are substituted into the fitting function to perform fitting, and the final first function Δv=f1(m) and second function Δt=f2(m) are obtained.
[0060] Step 33: Determine the updated programming voltage based on the sum of the current programming voltage and the voltage increment, and / or determine the updated programming time based on the reference time and the time increment.
[0061] Regarding the programming voltage, in one embodiment, during the first programming, the programming voltage is determined based on the reference voltage and the voltage increment, i.e., the programming voltage is the sum of the reference time and the voltage increment; during the second and subsequent programming, the updated programming voltage is determined based on the sum of the previous programming voltage and the voltage increment.
[0062] For example, assuming the reference voltage is v0, then the programming voltage corresponding to the first programming is v0 + Δv1, the programming voltage corresponding to the second programming is v0 + Δv1 + Δv2, the programming voltage corresponding to the third programming is v0 + Δv1 + Δv2 + Δv3, and so on. It can be seen that as the number of programming iterations increases, the programming voltage also increases, but the magnitude of each increase (voltage increment) becomes smaller. Here, Δv1 is the voltage increment corresponding to the first programming, Δv2 is the voltage increment corresponding to the second programming, and Δv3 is the voltage increment corresponding to the third programming.
[0063] Regarding the programming voltage, in another embodiment, during the first programming, a reference voltage is used as the programming voltage, i.e., the programming voltage is used as the reference time; during the second and subsequent programming, the updated programming voltage is determined based on the sum of the previous programming voltage and the voltage increment.
[0064] For example, assuming the reference voltage is v0, then the programming voltage corresponding to the first programming is v0, the programming voltage corresponding to the second programming is v0 + Δv2, the programming voltage corresponding to the third programming is v0 + Δv3, and so on. Here, Δv2 is the voltage increment corresponding to the second programming, and Δv3 is the voltage increment corresponding to the third programming.
[0065] In one embodiment, programming time is the sum of base time and time increment.
[0066] For example, assuming the base time is t0, then the programming time for the first programming iteration is t0 + Δt1, the programming time for the second iteration is t0 + Δt2, the programming time for the third iteration is t0 + Δt3, and so on. It can be seen that the programming time gradually decreases with each iteration. Here, Δt1 is the time increment for the first programming iteration, Δt2 is the time increment for the second programming iteration, and Δt3 is the time increment for the third programming iteration.
[0067] In another embodiment, programming time is a time increment.
[0068] For example, the programming time corresponding to the first programming session is Δt1, the programming time corresponding to the second programming session is Δt2, the programming time corresponding to the third programming session is Δt3, and so on. Here, Δt1 is the time increment corresponding to the first programming session, Δt2 is the time increment corresponding to the second programming session, and Δt3 is the time increment corresponding to the third programming session.
[0069] Optionally, the reference voltage v0 and the reference time t0 here can be set according to experience. For example, if the threshold voltage of a batch of memory cells is Vth, then the reference voltage v0 here can be set according to the threshold voltage Vth. For example, v0 = Vth. In other embodiments, it can also be set to v0 < Vth. For example, v0 = Vth / 2. The reference time t0 can be set according to the time required for a normal single programming. In other embodiments, it can also be set to be less than the time required for a normal single programming. For example, half of the time required for a normal single programming.
[0070] Step 34: Program the memory cell to be programmed using the updated programming voltage and programming time.
[0071] That is, program the memory cell to be programmed using the obtained programming voltage and programming time above, so as to Figure 1 For the NAND FLASH shown, that is, input a high-level signal to a word line WL where the memory cell to be programmed is located, with a duration of the above programming time, and then input the above programming voltage through a bit line BL.
[0072] It can be understood that since multiple programming operations are required, the above steps 31 - step 34 are executed multiple times.
[0073] In one embodiment, specifically,
[0074] First programming: Programming voltage: v0 + Δv1; Programming time: t0 + Δt1;
[0075] Second programming: Programming voltage: v0 + Δv1 + Δv2; Programming time: t0 + Δt2;
[0076] Third programming: Programming voltage: v0 + Δv1 + Δv2 + Δv3; Programming time: t0 + Δt3;
[0077] ……
[0078] Among them, the voltage increment Δv1 and the time increment Δt1 are determined based on the number m of memory cells to be programmed before the first programming. After the first programming, the number m of memory cells to be programmed is updated, and the voltage increment Δv2 and the time increment Δt2 are determined again, so as to perform the second programming. After the second programming, the number m of memory cells to be programmed is updated, and the voltage increment Δv3 and the time increment Δt3 are determined again, so as to perform the third programming...
[0079] The following is illustrated with a specific application scenario. For example, Figure 4 and Figure 5 , Figure 4 is a schematic diagram of the change in the number of memory cells to be programmed in one embodiment.Figure 5 This is a schematic diagram illustrating the relationship between programming time and programming voltage in one embodiment.
[0080] Initially, the number of memory cells to be programmed, m, is 10. Based on the value 10, the voltage increment for the first programming operation is Δv1, and the time increment is Δt1. That is, the programming voltage for the first programming operation is v0 + Δv1, and the programming time is t0 + Δt1. Here, v0 is the reference voltage, and t0 is the reference time. After the first programming, the change in the number of electrons in 4 memory cells needs to reach the threshold, completing the information rewriting. The remaining 6 memory cells need to continue the programming operation. Therefore, after the first programming, the number of memory cells to be programmed, m, is 6. Then, based on the value 6, the voltage increment for the second programming operation is Δv2, and the time increment is Δt2. That is, the programming voltage for the second programming operation is v + Δv1 + Δv2, and the programming time is t + Δt2. And so on, the programming voltage and programming time for the nth programming operation can be obtained.
[0081] It is worth noting that the above Figure 5 The voltage pulses between two adjacent pulses are not continuous, and the number of memory cells to be programmed, m, needs to be redefined between two adjacent programming operations.
[0082] Understandably, as the number of memory cells to be programmed, m, decreases, the voltage increment Δv1 and the time increment Δt1 also gradually decrease, i.e., Δv1>Δv2>..., Δt1>Δt2>... Therefore, the overall programming voltage gradually increases, while the programming time gradually decreases.
[0083] The memory cell programming method provided in this embodiment includes: determining the number of memory cells to be programmed; determining the corresponding voltage increment and / or time increment based on the number of memory cells to be programmed; wherein the voltage increment is positively correlated with the number of memory cells to be programmed, and the time increment is positively correlated with the number of memory cells to be programmed; determining the updated programming voltage based on the sum of the current programming voltage and the voltage increment, and / or determining the updated programming time based on the reference time and the time increment; and performing programming operations on the memory cells to be programmed using the updated programming voltage and programming time. Through the above method, since both the voltage increment and the time increment are positively correlated with the number of memory cells to be programmed, as the number of programming attempts increases, the number of memory cells to be programmed will inevitably decrease, so the voltage increment and time increment will also decrease. Therefore, the programming voltage increases while the programming time decreases. Compared to related technologies where the voltage increment and time increment remain constant during multiple programming attempts, the programming voltage increases while the increase rate decreases, which can ensure improved programming success rate while reducing power consumption. The shorter programming time also reduces power consumption and improves programming efficiency.
[0084] See Figure 6 , Figure 6 This is a flowchart illustrating another embodiment of the programming method for the storage unit provided in this application, the method comprising:
[0085] Step 61: Obtain the data to be programmed.
[0086] The data to be programmed is the data that needs to be written to a certain storage array. Understandably, such as... Figure 1 As shown, taking NAND FLASH as an example, one word line (WL) is equivalent to one page. Generally, one page of storage units can be programmed at the same time. Therefore, the data to be programmed here can be the data to be written to one page of storage space corresponding to one word line (WL).
[0087] Step 62: Compare the stored data of multiple storage cells in the storage array to be programmed with the data to be programmed, and determine the number of storage cells whose data is different according to the comparison results as the number of storage cells to be programmed.
[0088] The comparison method here can be to compare them one by one in sequence.
[0089] like Figure 7 As shown, Figure 7 This is a flowchart illustrating step 62 in one embodiment. Step 62 may specifically include:
[0090] Step 621: Sequentially compare the stored data of multiple storage cells in the storage array to be programmed with the data to be programmed.
[0091] Specifically, the stored data of multiple storage cells in the storage array to be programmed are compared with the data to be programmed in sequence, and the comparison results are cached.
[0092] Step 622: In response to the comparison result indicating that the data is different, count the data and use the count value as the number of memory units to be programmed.
[0093] Specifically, the comparison result in the cache is read, and in response to the comparison result indicating that the data is different, a count is performed, and the count value is used as the number of storage units to be programmed.
[0094] In one embodiment, the above operations can be accomplished by setting a cache and a counter. The stored data of multiple storage cells in the storage array to be programmed are sequentially compared with the data to be programmed, and the comparison results are cached in the cache; the comparison results in the cache are read, and in response to the comparison results indicating that the data is different, the counter is incremented by 1, and the final count value of the counter is used as the number of storage cells to be programmed.
[0095] like Figure 8 As shown,Figure 8 This is a schematic diagram illustrating the effect of the cache and counter in one embodiment. In this embodiment, the cache size is 1 bit, meaning that only 1 bit of the comparison result from one storage unit can be stored at a time. Therefore, the number of comparisons and caching operations can be performed as many times as there are storage units.
[0096] Optionally, if the cache result is high, it indicates that the current memory cell is consistent with the target value of the data to be programmed, and no further programming operation is needed. If the cache result is low, it indicates that the current memory cell is inconsistent with the target value of the data to be programmed, and a programming operation is needed; simultaneously, the counter is incremented by 1. After reading all caches, the result represented by the counter is the number of memory cells that need to be programmed in this programming operation.
[0097] Step 63: Determine the corresponding voltage increment and / or time increment based on the number of memory cells to be programmed; wherein the voltage increment is positively correlated with the number of memory cells to be programmed, and the time increment is positively correlated with the number of memory cells to be programmed.
[0098] Understandably, the voltage increment is positively correlated with the number of memory cells to be programmed, and the time increment is also positively correlated with the number of memory cells to be programmed. That is, the more memory cells to be programmed, the larger the voltage increment and the time increment, and the fewer memory cells to be programmed, the smaller the voltage increment and the time increment.
[0099] Optionally, in one embodiment, a first functional relationship between the voltage increment and the number of memory cells to be programmed is established in advance; a second functional relationship between the time increment and the number of memory cells to be programmed is established in advance; step 32 may include: substituting the number of memory cells to be programmed into the first functional relationship to obtain the voltage increment, and substituting the number of memory cells to be programmed into the second functional relationship to obtain the time increment.
[0100] Specifically, the first function is:
[0101] Δv=f1(m)
[0102] Where Δv is the voltage increment and m is the number of memory cells to be programmed.
[0103] Specifically, the second function is:
[0104] Δt=f2(m)
[0105] Where Δt is the time increment and m is the number of memory units to be programmed.
[0106] Understandably, the functional relationships f1 and f2 described above are positively correlated mapping relationships.
[0107] Step 64: Determine the updated programming voltage based on the sum of the current programming voltage and the voltage increment, and / or determine the updated programming time based on the reference time and the time increment.
[0108] Regarding the programming voltage, in one embodiment, during the first programming, the programming voltage is determined based on the reference voltage and the voltage increment, i.e., the programming voltage is the sum of the reference time and the voltage increment; during the second and subsequent programming, the updated programming voltage is determined based on the sum of the previous programming voltage and the voltage increment.
[0109] For example, assuming the reference voltage is v0, then the programming voltage corresponding to the first programming is v0 + Δv1, the programming voltage corresponding to the second programming is v0 + Δv1 + Δv2, the programming voltage corresponding to the third programming is v0 + Δv1 + Δv2 + Δv3, and so on. It can be seen that as the number of programming iterations increases, the programming voltage also increases, but the magnitude of each increase (voltage increment) becomes smaller. Here, Δv1 is the voltage increment corresponding to the first programming, Δv2 is the voltage increment corresponding to the second programming, and Δv3 is the voltage increment corresponding to the third programming.
[0110] In one embodiment, programming time is the sum of base time and time increment.
[0111] For example, assuming the base time is t0, then the programming time for the first programming iteration is t0 + Δt1, the programming time for the second iteration is t0 + Δt2, the programming time for the third iteration is t0 + Δt3, and so on. It can be seen that the programming time gradually decreases with each iteration. Here, Δt1 is the time increment for the first programming iteration, Δt2 is the time increment for the second programming iteration, and Δt3 is the time increment for the third programming iteration.
[0112] Step 65: Program the memory cell to be programmed using the updated programming voltage and programming time.
[0113] Understandably, since multiple programming operations are required, steps 61-65 above are executed multiple times.
[0114] See Figure 9 , Figure 9 This is a schematic diagram of an embodiment of the storage device provided in this application. The storage device 900 includes a storage array 10, a programming unit 20, and a control unit 30.
[0115] The storage array 10 includes storage cells arranged in an array. Taking NAND FLASH as an example, it can be referred to as follows: Figure 1The architecture shown; programming unit 20 is connected to storage array 10; control unit 30 is connected to programming unit 20, and control unit 30 is configured as follows:
[0116] Determine the number of memory cells to be programmed; determine the corresponding voltage increment and / or time increment based on the number of memory cells to be programmed; wherein the voltage increment is positively correlated with the number of memory cells to be programmed, and the time increment is positively correlated with the number of memory cells to be programmed; determine the updated programming voltage based on the sum of the current programming voltage and the voltage increment, and / or determine the updated programming time based on the reference time and the time increment; use the updated programming voltage and programming time to perform programming operations on the memory cells to be programmed.
[0117] Optionally, in one embodiment, the storage device 900 further includes a cache unit 40 and a counting unit 50. The cache unit 40 is connected to the control unit 30, and the counting unit 50 is connected to both the cache unit 40 and the control unit 30. The control unit 30 is configured to sequentially compare the stored data of multiple storage units in the storage array 10 to be programmed with the data to be programmed, and cache the comparison results in the cache unit 40. The counting unit 50 is configured to read the comparison results from the cache unit, and count in response to the comparison results indicating that the data is different. The control unit 30 is configured to use the count value as the number of storage units to be programmed.
[0118] See Figure 10 , Figure 10 This is a schematic diagram of an embodiment of the computer-readable storage medium 1000 provided in this application. The computer-readable storage medium 100 stores program data 100, which, when executed by a processor, is used to implement:
[0119] Determine the number of memory cells to be programmed; determine the corresponding voltage increment and / or time increment based on the number of memory cells to be programmed; wherein the voltage increment is positively correlated with the number of memory cells to be programmed, and the time increment is positively correlated with the number of memory cells to be programmed; determine the updated programming voltage based on the sum of the current programming voltage and the voltage increment, and / or determine the updated programming time based on the reference time and the time increment; use the updated programming voltage and programming time to perform programming operations on the memory cells to be programmed.
[0120] Optionally, in one embodiment, when the program data 100 is executed by the processor, it is used to: acquire data to be programmed; and compare the stored data of a plurality of storage cells in the storage array to be programmed with the data to be programmed, so as to determine the number of storage cells whose data are different as a result of the comparison as the number of storage cells to be programmed.
[0121] In this process, the stored data of multiple storage cells in the storage array to be programmed are compared with the data to be programmed in sequence; in response to the comparison result indicating that the data is different, a count is performed, and the count value is used as the number of storage cells to be programmed.
[0122] Specifically, the stored data of multiple storage cells in the storage array to be programmed are compared with the data to be programmed in sequence, and the comparison results are cached; the cached comparison results are read, and in response to the comparison results indicating that the data is different, a count is performed, and the count value is used as the number of storage cells to be programmed.
[0123] Optionally, in one embodiment, when the program data 100 is executed by the processor, it is used to: pre-establish a first functional relationship between the voltage increment and the number of memory cells to be programmed; pre-establish a second functional relationship between the time increment and the number of memory cells to be programmed; substitute the number of memory cells to be programmed into the first functional relationship to obtain the voltage increment, and substitute the number of memory cells to be programmed into the second functional relationship to obtain the time increment.
[0124] In the several embodiments provided in this application, it should be understood that the disclosed methods and devices can be implemented in other ways. For example, the device embodiments described above are merely illustrative. For instance, the division of modules or units is only a logical functional division, and in actual implementation, there may be other division methods. For example, multiple units or components may be combined or integrated into another system, or some features may be ignored or not executed.
[0125] The units described as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the units can be selected to achieve the purpose of this embodiment, depending on actual needs.
[0126] Furthermore, the functional units in the various embodiments of this application can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit. The integrated unit can be implemented in hardware or as a software functional unit.
[0127] The above description is merely an embodiment of this application and does not limit the patent scope of this application. Any equivalent structural or procedural transformations made using the content of this application's specification and drawings, or direct or indirect applications in other related technical fields, are similarly included within the patent protection scope of this application.
Claims
1. A method of programming a memory cell, comprising: The programming method of the storage unit comprises: determining the number of storage units to be programmed; determining the corresponding voltage increment and / or time increment according to the number of storage units to be programmed; wherein the voltage increment is positively correlated with the number of storage units to be programmed, and the time increment is positively correlated with the number of storage units to be programmed; determining the updated programming voltage according to the sum of the current programming voltage and the voltage increment, and / or determining the updated programming time according to the reference time and the time increment; performing programming operation on the storage units to be programmed by using the updated programming voltage and the programming time.
2. The programming method of a memory cell according to claim 1, wherein, The step of determining the number of storage units to be programmed comprises: obtaining the data to be programmed; and comparing the storage data of a plurality of storage units in the storage array to be programmed with the data to be programmed to determine the number of storage units with different data as the number of storage units to be programmed.
3. The programming method of a memory cell according to claim 2, wherein, The step of comparing the storage data of a plurality of storage units in the storage array to be programmed with the data to be programmed to determine the number of storage units with different data as the number of storage units to be programmed comprises: sequentially comparing the storage data of a plurality of storage units in the storage array to be programmed with the data to be programmed; in response to the comparison result indicating different data, counting and taking the count value as the number of storage units to be programmed.
4. The programming method of a memory cell according to claim 3, wherein, The step of sequentially comparing the storage data of a plurality of storage units in the storage array to be programmed with the data to be programmed comprises: sequentially comparing the storage data of a plurality of storage units in the storage array to be programmed with the data to be programmed and buffering the comparison result; The step of counting in response to the comparison result indicating different data and taking the count value as the number of storage units to be programmed comprises: reading the buffered comparison result, counting in response to the comparison result indicating different data, and taking the count value as the number of storage units to be programmed.
5. The programming method of a memory cell according to claim 1, wherein, The programming method of the storage unit further comprises: pre-establishing a first functional relationship between the voltage increment and the number of storage units to be programmed; pre-establishing a second functional relationship between the time increment and the number of storage units to be programmed; The step of determining the corresponding voltage increment and / or time increment according to the number of storage units to be programmed comprises: substituting the number of storage units to be programmed into the first functional relationship to obtain the voltage increment, and / or substituting the number of storage units to be programmed into the second functional relationship to obtain the time increment.
6. The programming method of a memory cell according to claim 1, wherein, After the step of performing programming operation on the storage units to be programmed by using the updated programming voltage and the programming time, the step of determining the number of storage units to be programmed is performed again.
7. The programming method of a memory cell according to claim 6, wherein, The step of determining the updated programming voltage according to the sum of the current programming voltage and the voltage increment comprises: in the first programming, determining the programming voltage according to the reference voltage and the voltage increment; in the second and subsequent programming, determining the updated programming voltage according to the sum of the programming voltage of the previous time and the voltage increment.
8. A memory device, comprising: The storage device comprises: a storage array comprising array-distributed storage cells; a programming unit connected to the storage array; a control unit connected to the programming unit, the control unit configured to control the programming unit to program the storage cells using the programming method of any one of claims 1-7.
9. The memory device of claim 8, wherein, The storage device further comprises: a cache unit connected to the control unit, the control unit configured to sequentially compare the storage data of a plurality of storage cells in the storage array to be programmed with the data to be programmed and cache the comparison results to the cache unit; a counting unit connected to the cache unit, the counting unit configured to read the comparison results of the cache unit and count in response to the comparison results indicating that the data is different, the control unit configured to use the count value as the number of storage cells to be programmed.
10. A computer-readable storage medium, characterized in that, The computer readable storage medium stores program data, which when executed by a processor, implements the programming method of any one of claims 1-7.