Power converter and control circuit applied to power converter

Abstract

The invention provides a power converter and a control circuit applied to the power converter, in the power converter, a first switch and a second switch are connected in series and then connected with the input end of the power converter, and the two ends of the second switch are connected with the output end of the power converter. In the control circuit of the power converter, a first input end and a second input end of an operational amplifier circuit are respectively used for receiving a reference voltage and a ripple voltage of an output end of the power converter. The first output end and the second output end of the operational amplifier circuit are respectively connected with the first input end and the second input end of the voltage-controlled delay circuit, and the third input end of the voltage-controlled delay circuit is used for receiving a clock signal. The first output end and the second output end of the voltage-controlled delay circuit are respectively connected with the first input end and the second input end of the trigger circuit, and the first output end and the second output end of the trigger circuit are respectively connected with the first switch and the second switch. Based on the invention, the delay time of the control circuit can be reduced.

Description

Technical Field

[0001] This application relates to the field of power supply circuit technology, and in particular to a power converter and a control circuit applied to the power converter. Background Technology

[0002] With the rapid development of electronic information technology, power converters are widely used in electronic devices and systems due to their high efficiency and compact design, providing stable voltage to ensure normal operation. Currently, power converters consist of switching and control circuits. In the traditional proportional-integral-derivative (PID) control method, the control circuit mainly controls the duty cycle signal of the switch through a comparator and a resistor-capacitor (RC) compensation circuit, thereby converting the input voltage of the power circuit into the output voltage required by the electronic device or system. However, when the power converter is a high-frequency, high-speed converter, limitations in comparator performance can lead to logic errors and duty cycle constraints, resulting in excessively long delays in the control circuit. Summary of the Invention

[0003] This application provides a power converter and a control circuit applied to the power converter, which can reduce the delay time of the control circuit and improve the transient response speed of the control circuit, and has strong applicability.

[0004] In a first aspect, embodiments of this application provide a power converter, which includes an input terminal, a first switch, a second switch, an output terminal, and a control circuit. The input terminal of the power converter is connected to a power source. The first switch and the second switch are connected in series to the input terminal of the power converter. The two ends of the second switch are connected (e.g., directly or indirectly) to the output terminal of the power converter. The output terminal of the power converter is connected to a load. The control circuit includes an operational amplifier circuit, a voltage-controlled delay circuit, and a trigger circuit. The first input terminal of the operational amplifier circuit receives a reference voltage, and the second input terminal receives the ripple voltage at the output terminal of the power converter. The first output terminal of the operational amplifier circuit is connected to the first input terminal of the voltage-controlled delay circuit, the second output terminal of the operational amplifier circuit is connected to the second input terminal of the voltage-controlled delay circuit, and the third input terminal of the voltage-controlled delay circuit receives a clock signal. The first output terminal of the voltage-controlled delay circuit is connected to the first input terminal of the trigger circuit, the second output terminal of the voltage-controlled delay circuit is connected to the second input terminal of the trigger circuit, the first output terminal of the trigger circuit is connected to the first switch, and the second output terminal of the trigger circuit is connected to the second switch. By implementing the embodiments of this application, a voltage-controlled delay circuit can replace a comparator for signal delay, thereby avoiding problems such as logic errors and limited duty cycle caused by using a comparator for signal delay. This reduces the delay time of the control circuit and improves its transient response speed. Furthermore, it avoids the need for complex RC compensation circuits in the control circuit, simplifying its structure and achieving a smaller circuit area. This further simplifies the structure of the power converter and achieves a smaller circuit area, making it highly adaptable.

[0005] In one possible implementation, the operational amplifier circuit includes a first operational amplifier and a second operational amplifier. The non-inverting input of the first operational amplifier and the inverting input of the second operational amplifier are connected to the first input of the operational amplifier circuit to receive a reference voltage. The inverting input of the first operational amplifier and the non-inverting input of the second operational amplifier are connected to the second input of the operational amplifier circuit to receive the ripple voltage at the output of the power converter. The output of the first operational amplifier is connected to the first output of the operational amplifier circuit, and the output of the second operational amplifier is connected to the second output of the operational amplifier circuit. The first operational amplifier outputs a first control signal to the voltage-controlled delay circuit based on the reference voltage and the ripple voltage. The second operational amplifier outputs a second control signal to the voltage-controlled delay circuit based on the reference voltage and the ripple voltage. Both the first and second control signals are used to control the delay time of the voltage-controlled delay circuit. By implementing the embodiments of this application, the first and second control signals can be adjusted in real time according to the difference between the reference voltage and the ripple voltage, thereby controlling the delay time of the voltage-controlled delay circuit in real time, providing greater flexibility in delay time control.

[0006] In one possible implementation, the voltage-controlled delay circuit includes a first voltage-controlled delay line and a second voltage-controlled delay line. The first input terminal of the first voltage-controlled delay line is connected to the first input terminal of the voltage-controlled delay circuit to receive a first control signal output by a first operational amplifier. The first input terminal of the second voltage-controlled delay line is connected to the second input terminal of the voltage-controlled delay circuit to receive a second control signal output by a second operational amplifier. The second input terminal of the first voltage-controlled delay line is connected to the third input terminal of the voltage-controlled delay circuit to receive a clock signal. The output terminal of the first voltage-controlled delay line is connected to the second input terminal of the second voltage-controlled delay line and the first output terminal of the voltage-controlled delay circuit, and the output terminal of the second voltage-controlled delay line is connected to the second output terminal of the voltage-controlled delay circuit. The first voltage-controlled delay line is used to delay the clock signal based on the first control signal and output a first delayed signal to the second voltage-controlled delay line and the trigger circuit. The second voltage-controlled delay line is used to delay the first delayed signal based on the second control signal and output a second delayed signal to the trigger circuit. By implementing the embodiments of this application, the comparator can be replaced by the first voltage-controlled delay line and the second voltage-controlled delay line to perform signal delay, thereby avoiding problems such as logic errors and duty cycle limitations caused by using a comparator for signal delay, thus reducing the delay time of the control circuit and improving the transient response speed of the control circuit.

[0007] In one possible implementation, the aforementioned trigger circuit includes a trigger and an inverter. The first input terminal of the trigger is connected to the first input terminal of the trigger circuit to receive a first delay signal output from a first voltage-controlled delay line. The second input terminal of the trigger is connected to the second input terminal of the trigger circuit to receive a second delay signal output from a second voltage-controlled delay line. The output terminal of the trigger is connected to the first output terminal of the trigger circuit and the input terminal of the inverter, and the output terminal of the inverter is connected to the second output terminal of the trigger circuit. The trigger is used to output a duty cycle signal to a first switch based on the first and second delay signals, and then output an inverted duty cycle signal to a second switch via the inverter, so that the difference between the output voltage of the power converter and the voltage of the load is less than a preset threshold. By implementing the embodiments of this application, the first and second switches can be controlled to turn on or off in real time according to the duty cycle signal and the inverted duty cycle signal, thereby quickly adjusting the output voltage of the power converter to meet the voltage requirements of the load.

[0008] In one possible implementation, the delay time between the first delay signal and the clock signal is positively correlated with the absolute value of the difference between the reference voltage and the ripple voltage. By implementing the embodiments of this application, the delay time between the first delay signal and the clock signal can be adjusted in real time based on the absolute value of the difference, resulting in greater flexibility in delay time control.

[0009] In one possible implementation, the delay time between the second delayed signal and the first delayed signal is positively correlated with the absolute value of the difference between the reference voltage and the ripple voltage. By implementing the embodiments of this application, the delay time between the second delayed signal and the first delayed signal can be adjusted in real time based on the absolute value of the difference, resulting in greater flexibility in delay time control.

[0010] In one possible implementation, the control circuit further includes a voltage-controlled oscillator (VCO) circuit, wherein the input terminal of the VCO circuit is connected to the output terminal of the power converter, and the output terminal of the VCO circuit is connected to the third input terminal of the voltage-controlled delay circuit. The VCO circuit is used to output a clock signal to the voltage-controlled delay circuit based on the sampled output voltage of the power converter. By implementing the embodiments of this application, the oscillation frequency of the clock signal can be changed in real time according to the sampled output voltage, thereby outputting a high-precision high-frequency clock signal, which offers greater control flexibility and higher accuracy.

[0011] In one possible implementation, the power converter further includes an inductor connected between the series connection point of the first and second switches and the output terminal of the power converter. The control circuit further includes a current sampling circuit, wherein the input terminal of the current sampling circuit is connected between the series connection point of the first and second switches and the inductor, and the output terminal of the current sampling circuit is connected to the second input terminal of the operational amplifier circuit. The current sampling circuit is used to collect the current flowing through the inductor and output a ripple voltage to the operational amplifier circuit based on the current flowing through the inductor. By implementing the embodiments of this application, the magnitude of the ripple voltage can be detected in real time based on the current flowing through the inductor to meet different voltage requirements of the load.

[0012] Secondly, embodiments of this application provide a control circuit for a power converter. The control circuit includes an operational amplifier circuit, a voltage-controlled delay circuit, and a trigger circuit. The power converter includes an input terminal, a first switch, a second switch, and an output terminal. The first and second switches are connected in series to the input terminal of the power converter, and the two ends of the second switch are connected to the output terminal of the power converter. The first input terminal of the operational amplifier circuit receives a reference voltage, and the second input terminal receives the ripple voltage at the output terminal of the power converter. The first output terminal of the operational amplifier circuit is connected to the first input terminal of the voltage-controlled delay circuit, and the second output terminal is connected to the second input terminal of the voltage-controlled delay circuit. The third input terminal of the voltage-controlled delay circuit receives a clock signal. The first output terminal of the voltage-controlled delay circuit is connected to the first input terminal of the trigger circuit, and the second output terminal of the voltage-controlled delay circuit is connected to the second input terminal of the trigger circuit. The first output terminal of the trigger circuit is connected to the first switch, and the second output terminal is connected to the second switch. By implementing the embodiments of this application, a voltage-controlled delay circuit can replace a comparator for signal delay, thereby avoiding problems such as logic errors and limited duty cycle caused by using a comparator for signal delay. This reduces the delay time of the control circuit and improves its transient response speed. Furthermore, it avoids the need for complex RC compensation circuits in the control circuit, simplifying its structure and achieving a smaller circuit area. This further simplifies the structure of the power converter and achieves a smaller circuit area, making it highly adaptable.

[0013] In one possible implementation, the operational amplifier circuit includes a first operational amplifier and a second operational amplifier. The non-inverting input of the first operational amplifier and the inverting input of the second operational amplifier are connected to the first input of the operational amplifier circuit to receive a reference voltage. The inverting input of the first operational amplifier and the non-inverting input of the second operational amplifier are connected to the second input of the operational amplifier circuit to receive the ripple voltage at the output of the power converter. The output of the first operational amplifier is connected to the first output of the operational amplifier circuit, and the output of the second operational amplifier is connected to the second output of the operational amplifier circuit. The first operational amplifier outputs a first control signal to the voltage-controlled delay circuit based on the reference voltage and the ripple voltage. The second operational amplifier outputs a second control signal to the voltage-controlled delay circuit based on the reference voltage and the ripple voltage. Both the first and second control signals are used to control the delay time of the voltage-controlled delay circuit. By implementing the embodiments of this application, the first and second control signals can be adjusted in real time according to the difference between the reference voltage and the ripple voltage, thereby controlling the delay time of the voltage-controlled delay circuit in real time, providing greater flexibility in delay time control.

[0014] In one possible implementation, the voltage-controlled delay circuit includes a first voltage-controlled delay line and a second voltage-controlled delay line. The first input terminal of the first voltage-controlled delay line is connected to the first input terminal of the voltage-controlled delay circuit to receive a first control signal output by a first operational amplifier. The first input terminal of the second voltage-controlled delay line is connected to the second input terminal of the voltage-controlled delay circuit to receive a second control signal output by a second operational amplifier. The second input terminal of the first voltage-controlled delay line is connected to the third input terminal of the voltage-controlled delay circuit to receive a clock signal. The output terminal of the first voltage-controlled delay line is connected to the second input terminal of the second voltage-controlled delay line and the first output terminal of the voltage-controlled delay circuit, and the output terminal of the second voltage-controlled delay line is connected to the second output terminal of the voltage-controlled delay circuit. The first voltage-controlled delay line is used to delay the clock signal based on the first control signal and output a first delayed signal to the second voltage-controlled delay line and the trigger circuit. The second voltage-controlled delay line is used to delay the first delayed signal based on the second control signal and output a second delayed signal to the trigger circuit. By implementing the embodiments of this application, the comparator can be replaced by the first voltage-controlled delay line and the second voltage-controlled delay line to perform signal delay, thereby avoiding problems such as logic errors and duty cycle limitations caused by using a comparator for signal delay, thus reducing the delay time of the control circuit and improving the transient response speed of the control circuit.

[0015] In one possible implementation, the aforementioned trigger circuit includes a trigger and an inverter. The first input terminal of the trigger is connected to the first input terminal of the trigger circuit to receive a first delay signal output from a first voltage-controlled delay line. The second input terminal of the trigger is connected to the second input terminal of the trigger circuit to receive a second delay signal output from a second voltage-controlled delay line. The output terminal of the trigger is connected to the first output terminal of the trigger circuit and the input terminal of the inverter, and the output terminal of the inverter is connected to the second output terminal of the trigger circuit. The trigger is used to output a duty cycle signal to a first switch based on the first and second delay signals, and then output an inverted duty cycle signal to a second switch via the inverter, so that the difference between the output voltage of the power converter and the voltage of the load is less than a preset threshold. By implementing the embodiments of this application, the first and second switches can be controlled to turn on or off in real time according to the duty cycle signal and the inverted duty cycle signal, thereby quickly adjusting the output voltage of the power converter to meet the voltage requirements of the load.

[0016] In one possible implementation, the delay time between the first delay signal and the clock signal is positively correlated with the absolute value of the difference between the reference voltage and the ripple voltage. By implementing the embodiments of this application, the delay time between the first delay signal and the clock signal can be adjusted in real time based on the absolute value of the difference, resulting in greater flexibility in delay time control.

[0017] In one possible implementation, the delay time between the second delayed signal and the first delayed signal is positively correlated with the absolute value of the difference between the reference voltage and the ripple voltage. By implementing the embodiments of this application, the delay time between the second delayed signal and the first delayed signal can be adjusted in real time based on the absolute value of the difference, resulting in greater flexibility in delay time control.

[0018] In one possible implementation, the control circuit further includes a voltage-controlled oscillator (VCO) circuit, wherein the input terminal of the VCO circuit is connected to the output terminal of the power converter, and the output terminal of the VCO circuit is connected to the third input terminal of the voltage-controlled delay circuit. The VCO circuit is used to output a clock signal to the voltage-controlled delay circuit based on the sampled output voltage of the power converter. By implementing the embodiments of this application, the oscillation frequency of the clock signal can be changed in real time according to the sampled output voltage, thereby outputting a high-precision high-frequency clock signal, which offers greater control flexibility and higher accuracy.

[0019] In one possible implementation, the control circuit further includes a current sampling circuit, and the power converter further includes an inductor. The inductor is connected between the series connection point of the first and second switches and the output terminal of the power converter. The input terminal of the current sampling circuit is connected between the series connection point of the first and second switches and the inductor, and the output terminal of the current sampling circuit is connected to the second input terminal of the operational amplifier circuit. The current sampling circuit is used to collect the current flowing through the inductor and output a ripple voltage to the operational amplifier circuit based on the current flowing through the inductor. By implementing the embodiments of this application, the magnitude of the ripple voltage can be detected in real time according to the current flowing through the inductor to meet different voltage requirements of the load.

[0020] It should be understood that the implementations and beneficial effects of the above-mentioned aspects of this application can be referenced from each other. Attached Figure Description

[0021] Figure 1 This is a circuit diagram of a power converter provided in an embodiment of this application;

[0022] Figure 2 This is another circuit diagram of the power converter provided in the embodiments of this application;

[0023] Figure 3 This is another circuit diagram of the power converter provided in the embodiments of this application;

[0024] Figure 4 This is another circuit diagram of the power converter provided in the embodiments of this application;

[0025] Figure 5 This is a waveform diagram of the clock signal, the first delay signal, the second delay signal, and the duty cycle signal provided in the embodiments of this application;

[0026] Figure 6 This is another circuit diagram of the power converter provided in the embodiments of this application;

[0027] Figure 7A This is a waveform diagram of the output voltage of a power converter when the control circuit adopts the traditional PID control method;

[0028] Figure 7B This is a waveform diagram of the output voltage of the power converter when the control circuit provided in this application adopts a hysteresis control method based on time domain information. Detailed Implementation

[0029] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0030] The implementation of the technical solution of this application will be further described in detail below with reference to the accompanying drawings.

[0031] See Figure 1 , Figure 1 This is a circuit diagram of a power converter provided in an embodiment of this application. Figure 1 As shown, the power converter 2 is used to connect between the power supply 1 and the load 3 to perform voltage conversion. Specifically, it converts the voltage provided by the power supply 1 into the target voltage and supplies power to the load 3, thereby meeting the voltage requirements of the load 3. For example, the power converter 2 can be a high-frequency, high-speed power converter or a low-speed power converter, without limitation.

[0032] The power converter 2 includes an input terminal in, a first switch S1, a second switch S2, an output terminal out, and a control circuit 21. The input terminal in of the power converter 2 is connected to a power supply 1 to receive the voltage provided by the power supply 1. The first switch S1 and the second switch S2 are connected in series to the input terminal in of the power converter 2. The two ends of the second switch S2 are connected (either directly or indirectly) to the output terminal out of the power converter 2. The output terminal out of the power converter 2 is connected to a load 3 to supply power to the load 3 by outputting a target voltage.

[0033] The control circuit 21 includes an operational amplifier circuit 211, a voltage-controlled delay circuit 212, and a trigger circuit 213. The first input terminal of the operational amplifier circuit 211 receives a reference voltage Vref, and the second input terminal receives the ripple voltage Vramp from the output of the power converter 2. This ripple voltage Vramp represents the AC power frequency component in the output voltage of the power converter 2. The first output terminal of the operational amplifier circuit 211 is connected to the first input terminal of the voltage-controlled delay circuit 212, and the second output terminal is connected to the second input terminal of the voltage-controlled delay circuit 212. The third input terminal of the voltage-controlled delay circuit 212 receives a clock signal CLK. The first output terminal of the voltage-controlled delay circuit 212 is connected to the first input terminal of the trigger circuit 213, and the second output terminal is connected to the second input terminal of the trigger circuit 213. The first output terminal of the aforementioned trigger circuit 213 is connected (e.g., directly or indirectly) to the first switch S1, and the second output terminal of the trigger circuit 213 is connected (e.g., directly or indirectly) to the second switch S2.

[0034] By implementing the embodiments of this application, a voltage-controlled delay circuit 212 can be used to replace the comparator for signal delay, thereby avoiding problems such as logic errors and duty cycle limitations caused by using a comparator for signal delay. This reduces the delay time of the control circuit 21 and improves its transient response speed. Furthermore, it avoids the need for complex RC compensation circuits in the control circuit 21, simplifying its structure and achieving a smaller circuit area. This further simplifies the structure of the power converter 2 and achieves a smaller circuit area, making it highly adaptable.

[0035] It is understood that the aforementioned control circuit 21 can be implemented using a fully integrated chip-level approach, meaning that all functional circuits of the control circuit 21 are integrated into a single system-on-a-chip (SoC). This avoids the need for complex RC compensation circuits in the control circuit 21, saving chip area and reducing costs. Optionally, the discrete components in all functional circuits of the control circuit 21 can also be implemented at the board level, meaning that the discrete components in all functional circuits are arranged on a printed circuit board (PCB) according to their circuit connection methods.

[0036] The control circuit 21 described above can be integrated inside the power converter 2. Optionally, the control circuit 21 can also be located outside the power converter 2 and exist independently. This application embodiment does not limit the specific location of the control circuit 21.

[0037] For example, when power converter 2 is a direct current (DC) / DC converter, power supply 1 is a DC power supply and load 3 is a DC load. When power converter 2 is an alternating current (AC) / DC converter, power supply 1 is an AC power supply and load 3 is a DC load. When power converter 2 is an AC / AC converter, power supply 1 is an AC power supply and load 3 is an AC load.

[0038] For example, each of the first switch S1 and the second switch S2 can be any of the following switches: a metal-oxide-semiconductor field-effect transistor (MOSFET), an insulated-gate bipolar transistor (IGBT), a bipolar junction transistor (BJT), a silicon controlled rectifier (SCR), a gate turn-off thyristor (GTO), a MOSFET (MCT), a static inductance transistor (SIT), and a metal-oxide-semiconductor (MOS). These are merely examples, and the embodiments of this application do not limit the specific type of each switch.

[0039] When a current surge in load 3 causes a change in the voltage of load 3 (i.e., a transient event occurs), control circuit 21 controls the output voltage of power converter 2 to increase or decrease by controlling the on / off states of the first switch S1 and the second switch S2, thereby meeting the voltage requirements of load 3. For example, when the current of load 3 decreases, the voltage of load 3 increases, and control circuit 21 controls the output voltage of power converter 2 to increase; conversely, when the current of load 3 increases, the voltage of load 3 decreases, and control circuit 21 controls the output voltage of power converter 2 to decrease.

[0040] The specific implementation process of the control circuit 21 controlling the output voltage of the power converter 2 can be combined with the following... Figures 2 to 6 Provide an example.

[0041] When power converter 2 is a switching inductor type converter, such as a buck converter, one possible circuit structure for power converter 2 is as follows: Figure 2 As shown above, Figure 1 The power converter 2 shown also includes an inductor L and a capacitor C1. The inductor L is connected between the series connection point of the first switch S1 and the second switch S2 and the output terminal out of the power converter 2. The capacitor C1 is connected to the output terminal out of the power converter 2 and is used to filter the target voltage before outputting it to the load 3 to supply power. Figure 1 The control circuit 21 shown also includes a current sampling circuit 214. Exemplarily, the current sampling circuit 214 can be a current sensor or a current sampling resistor; the above is merely an example, and this application embodiment does not limit the circuit structure of the current sampling circuit 214. The input terminal of the current sampling circuit 214 is connected between the series connection point of the first switch S1 and the second switch S2 and the inductor L, and the output terminal of the current sampling circuit 214 is connected to the second input terminal of the operational amplifier circuit 211. The current sampling circuit 214 is used to collect the current I flowing through the inductor L and output a ripple voltage Vramp to the operational amplifier circuit 211 based on the current I flowing through the inductor L. By implementing this application embodiment, the magnitude of the ripple voltage Vramp can be detected in real time according to the current I flowing through the inductor L to meet the different voltage requirements of the load 3.

[0042] like Figure 2 As shown, the control circuit 21 further includes a voltage-controlled oscillator (VCO) circuit 215. Exemplarily, the VCO circuit 215 can be one of an inductor-capacitor (LC) VCO, an RC VCO, and a crystal VCO. The input terminal of the VCO circuit 215 is connected to the output terminal of the power converter 2, and the output terminal of the VCO circuit 215 is connected to the third input terminal of the voltage-controlled delay circuit 212. The VCO circuit 215 is used to output a clock signal CLK to the voltage-controlled delay circuit 212 based on the sampled output voltage Vo of the power converter 2. The sampled output voltage Vo can be directly sampled by the VCO circuit 215, or output to the VCO circuit 215 by an external voltage sampling circuit. By implementing this embodiment, the oscillation frequency of the clock signal CLK can be changed in real time according to the sampled output voltage Vo (i.e., frequency conversion), thereby outputting a high-precision high-frequency clock signal CLK, resulting in greater control flexibility and higher accuracy for the clock signal CLK.

[0043] See Figure 3 , Figure 3 This is another circuit diagram of the power converter provided in an embodiment of this application. For example... Figure 3 As shown above, Figure 2The operational amplifier circuit 211 shown includes a first operational amplifier OPA1 and a second operational amplifier OPA2. Exemplarily, each operational amplifier (OPA) in the first operational amplifier OPA1 and the second operational amplifier OPA2 can be an operational transconductance amplifier (OTA) or a differential amplifier; this is merely an example, and the embodiments of this application do not limit the specific type of each operational amplifier. The non-inverting input terminal of the first operational amplifier OPA1 and the inverting input terminal of the second operational amplifier OPA2 are connected to the first input terminal of the operational amplifier circuit 211 to receive the reference voltage Vref. The inverting input terminal of the first operational amplifier OPA1 and the non-inverting input terminal of the second operational amplifier OPA2 are connected to the second input terminal of the operational amplifier circuit 211 to receive the ripple voltage Vramp at the output terminal of the power converter 2. The output terminal of the first operational amplifier OPA1 is connected to the first output terminal of the operational amplifier circuit 211, and the output terminal of the second operational amplifier OPA2 is connected to the second output terminal of the operational amplifier circuit 211. Optionally, the output of the first operational amplifier OPA1 is also connected to the reference ground via capacitor C2, and the second operational amplifier OPA2 is also connected to the reference ground via capacitor C3.

[0044] The first operational amplifier OPA1 is used to output a first control signal CS1 to the voltage-controlled delay circuit 212 based on the reference voltage Vref and the ripple voltage Vramp. The second operational amplifier OPA2 is used to output a second control signal CS2 to the voltage-controlled delay circuit 212 based on the reference voltage Vref and the ripple voltage Vramp. Both the first control signal CS1 and the second control signal CS2 are used to control the delay time of the voltage-controlled delay circuit 212. For example, when each operational amplifier is a transconductance amplifier, each operational amplifier converts the difference between the reference voltage Vref and the ripple voltage Vramp into a current signal and outputs this current signal as a control signal (such as the first control signal CS1 or the second control signal CS2) to the voltage-controlled delay circuit 212. Optionally, when each operational amplifier is a differential amplifier, each operational amplifier amplifies the difference between the reference voltage Vref and the ripple voltage Vramp to obtain a voltage signal and outputs this voltage signal as a control signal to the voltage-controlled delay circuit 212. By implementing the embodiments of this application, the first control signal CS1 and the second control signal CS2 can be adjusted in real time according to the difference between the reference voltage Vref and the ripple voltage Vramp, thereby controlling the delay time of the voltage-controlled delay circuit 212 in real time, and making the control of the delay time more flexible.

[0045] It is understood that the first operational amplifier OPA1 and the second operational amplifier OPA2 can be two independent devices. Optionally, the first operational amplifier OPA1 and the second operational amplifier OPA2 can also be integrated into a single structure.

[0046] See Figure 4 , Figure 4 This is another circuit diagram of the power converter provided in an embodiment of this application. For example... Figure 4 As shown above, Figure 3 The voltage-controlled delay circuit 212 shown includes a first voltage-controlled delay line VCDL1 and a second voltage-controlled delay line VCDL2. Exemplarily, each of the first and second voltage-controlled delay lines (VCDL1 and VCDL2) can be implemented by multiple inverters connected in series or by multiple capacitors connected in parallel; these are merely examples and not intended to be limiting. The first input terminal of the first voltage-controlled delay line VCDL1 is connected to the first input terminal of the voltage-controlled delay circuit 212 to receive the first control signal CS1 output by the first operational amplifier OPA1. The first input terminal of the second voltage-controlled delay line VCDL2 is connected to the second input terminal of the voltage-controlled delay circuit 212 to receive the second control signal CS2 output by the second operational amplifier OPA2. The second input terminal of the first voltage-controlled delay line VCDL1 is connected to the third input terminal of the voltage-controlled delay circuit 212 to receive the clock signal CLK output by the voltage-controlled oscillator circuit 215. The output terminal of the first voltage-controlled delay line VCDL1 is connected to the second input terminal of the second voltage-controlled delay line VCDL2 and the first output terminal of the voltage-controlled delay circuit 212. The output terminal of the second voltage-controlled delay line VCDL2 is connected to the second output terminal of the voltage-controlled delay circuit 212.

[0047] The first voltage-controlled delay line VCDL1 is used to delay the clock signal CLK based on the first control signal CS1, and outputs a first delay signal SET to the second voltage-controlled delay line VCDL2 and the trigger circuit 213. The delay time between the first delay signal SET and the clock signal CLK is positively correlated with the absolute value of the difference between the reference voltage Vref and the ripple voltage Vramp. The second voltage-controlled delay line VCDL2 is used to delay the first delay signal SET based on the second control signal CS2, and outputs a second delay signal RESET to the trigger circuit 213. The delay time between the second delay signal RESET and the first delay signal SET is also positively correlated with the absolute value of the difference between the reference voltage Vref and the ripple voltage Vramp. For example, the waveforms of the clock signal CLK, the first delay signal SET, and the second delay signal RESET can be as follows: Figure 5As shown, the delay time Td1 between the first delay signal SET and the clock signal CLK is the time interval between the rising edge of the first delay signal SET and the rising edge of the clock signal CLK, and the delay time Td1 is positively correlated with the phase difference between the rising edges of the first delay signal SET and the clock signal CLK. Similarly, the delay time Td2 between the second delay signal RESET and the first delay signal SET is the time interval between the rising edge of the second delay signal RESET and the rising edge of the first delay signal SET, and the delay time Td2 is also positively correlated with the phase difference between the rising edges of the second delay signal RESET and the first delay signal SET.

[0048] By implementing the embodiments of this application, the comparator can be replaced by the first voltage-controlled delay line VCDL1 and the second voltage-controlled delay line VCDL2 for signal delay, thereby avoiding problems such as logic errors and duty cycle limitations caused by using a comparator for signal delay. This reduces the delay time of the control circuit 21 and improves its transient response speed. Furthermore, the delay time between the first delay signal and the clock signal, as well as the delay time between the second delay signal and the first delay signal, can be adjusted in real time based on the absolute value of the difference, providing greater flexibility in delay time control.

[0049] It is understood that the first voltage-controlled delay line VCDL1 and the second voltage-controlled delay line VCDL2 can be two independent devices. Optionally, the first voltage-controlled delay line VCDL1 and the second voltage-controlled delay line VCDL2 can also be integrated into a single structure.

[0050] See Figure 6 , Figure 6 This is another circuit diagram of the power converter provided in an embodiment of this application. For example... Figure 6 As shown above, Figure 5 The illustrated flip-flop circuit 213 includes a flip-flop FF and an inverter NOT. Exemplarily, the flip-flop FF can be a reset set (RS) flip-flop or a JK flip-flop; these are merely examples and not intended to be limiting. The first input terminal of the flip-flop FF is connected to the first input terminal of the flip-flop circuit 213 to receive the first delayed signal SET output by the first voltage-controlled delay line VCDL1. The second input terminal of the flip-flop FF is connected to the second input terminal of the flip-flop circuit 213 to receive the second delayed signal RESET output by the second voltage-controlled delay line VCDL2. Exemplarily, when the flip-flop FF is an RS flip-flop, the first input terminal of the flip-flop FF is the set input S, and the second input terminal of the flip-flop FF is the reset input R. The output terminal of the flip-flop FF is connected to the first output terminal of the flip-flop circuit 213 and the input terminal of the inverter NOT; the output terminal of the inverter NOT is connected to the second output terminal of the flip-flop circuit 213.

[0051] The aforementioned trigger FF is used to output a duty cycle signal Q to the first switch S1 based on the first delay signal SET and the second delay signal RESET. This Q is then inverted via the inverter NOT to output an inverted duty cycle signal to the second switch S2, ensuring that the difference between the output voltage of the power converter 2 and the voltage of the load 3 is less than a preset threshold. The preset threshold is either a pre-set value or a value determined by internal components of the power converter 2. When the duty cycle signal Q is high, the inverted duty cycle signal is low; conversely, when the duty cycle signal Q is low, the inverted duty cycle signal is high. It should be understood that the duty cycle signal Q output by the flip-flop FF can also be amplified by the drive circuit 22 and output to the first switch S1 to control the first switch S1 to turn on or off. The inverted duty cycle signal output by the inverter NOT can also be amplified by the drive circuit 22 and output to the second switch S2 to control the second switch S2 to turn on or off, so that the difference between the output voltage of the power converter 2 and the voltage of the load 3 is less than a preset threshold, that is, the output voltage of the power converter 2 is basically consistent with the voltage of the load 3, thereby ensuring the normal operation of the load 3.

[0052] For example, the waveform of the duty cycle signal Q described above can be as follows: Figure 5 As shown, when the first delay signal SET is high and the second delay signal RESET is low, the duty cycle signal Q is high. When both the first delay signal SET and the second delay signal RESET are high, the duty cycle signal Q is low. When both the first delay signal SET and the second delay signal RESET are high, the duty cycle signal Q remains at the same level as the previous moment, i.e., it remains low.

[0053] By implementing the embodiments of this application, the first switch S1 and the second switch S2 can be turned on or off in real time according to the duty cycle signal and the inverted duty cycle signal, thereby quickly adjusting the output voltage of the power converter 2 to meet the voltage requirements of the load 3.

[0054] It is understandable that the flip-flop (FF) and the inverter (NOT) can be two independent devices. Optionally, the inverter (NOT) can also be integrated inside the flip-flop (FF) to form a single integrated structure.

[0055] It can be understood that the aforementioned control circuit 21 adjusts the upper limit of the hysteresis voltage Vramp in the hysteresis control mode through the first operational amplifier OPA1 and the first voltage-controlled delay line VCDL1, and adjusts the lower limit of the hysteresis voltage Vramp in the hysteresis control mode through the second operational amplifier OPA2 and the second voltage-controlled delay line VCDL2. The hysteresis control mode is a control method designed for loads 3 that require faster transient response; this hysteresis control mode can also be called ripple control. The aforementioned upper and lower hysteresis limits can be adjusted through the gain of the first operational amplifier OPA1 and the gain of the second operational amplifier OPA2. For example, the upper hysteresis limit is negatively correlated with the gain of the first operational amplifier OPA1, and the lower hysteresis limit is negatively correlated with the gain of the second operational amplifier OPA2. Furthermore, the aforementioned control circuit 21 can replace the comparator in the traditional hysteresis control method with a voltage-controlled delay line, converting the control signal obtained from the difference between the reference voltage Vref and the ripple voltage Vramp into a delayed signal containing time-domain information such as phase difference and delay time. This avoids the logic errors and duty cycle limitations caused by using a comparator for signal delay, thereby reducing the delay time of the control circuit 21 and improving its transient response speed. In summary, the control method adopted by the control circuit 21 can be called a time-domain information-based hysteresis control method. This time-domain information-based hysteresis control method is also a nonlinear control method. Therefore, the control circuit 21 can provide closed-loop control capability for the power converter 2, and compared with the traditional PID control method, it significantly improves the system dynamic performance of the power converter 2.

[0056] For example, taking a power converter 2 with an input voltage of 1.8V, an output voltage of 0.9V, and a switching frequency of 50MHz as an example, when the control circuit 21 adopts a traditional PID control method and the load switching speed of the control circuit 21 is 40A / 150ns, the waveform of the output voltage of the power converter 2 can be as follows: Figure 7A As shown, the output voltage of power converter 2 drops by ΔV = 104 MV, and after a recovery time of Δt = 1 μs, control circuit 21 can control the output voltage of power converter 2 to rise until the difference between it and the voltage of load 3 is less than a preset threshold. When control circuit 21 uses the time-domain information-based hysteresis control method provided in this embodiment, and the load shedding speed of control circuit 21 is 40 A / 150 ns, the waveform of the output voltage of power converter 2 can be as follows: Figure 7BAs shown, the output voltage of power converter 2 drops by ΔV = 40MV, and after a recovery time of Δt = 0.9μs, the control circuit 21 can control the output voltage of power converter 2 to rise until the difference between it and the voltage of load 3 is less than a preset threshold. Therefore, compared with the traditional PID control method, the hysteresis control method based on time domain information provided in this embodiment results in a smaller drop in the output voltage of power converter 2, a shorter recovery time, and better system dynamic performance of power converter 2.

[0057] It should be noted that the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance.

[0058] The above description is merely a specific embodiment of this application, but the scope of protection of this application is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this application should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

Claims

1. A power converter, characterized by, The power converter comprises an input end, a first switch, a second switch, an output end and a control circuit; the input end of the power converter is used for connecting a power supply; the first switch and the second switch are connected in series and then connected to the input end of the power converter; two ends of the second switch are connected to the output end of the power converter; and the output end of the power converter is used for connecting a load; The control circuit comprises an operational amplifier circuit, a voltage-controlled delay circuit and a flip-flop circuit; a first input end of the operational amplifier circuit is used for receiving a reference voltage; a second input end of the operational amplifier circuit is used for receiving a ripple voltage of the output end of the power converter; a first output end of the operational amplifier circuit is connected to a first input end of the voltage-controlled delay circuit; a second output end of the operational amplifier circuit is connected to a second input end of the voltage-controlled delay circuit; a third input end of the voltage-controlled delay circuit is used for receiving a clock signal; a first output end of the voltage-controlled delay circuit is connected to a first input end of the flip-flop circuit; a second output end of the voltage-controlled delay circuit is connected to a second input end of the flip-flop circuit; a first output end of the flip-flop circuit is connected to the first switch; and a second output end of the flip-flop circuit is connected to the second switch.

2. The power converter of claim 1, wherein, The operational amplifier circuit comprises a first operational amplifier and a second operational amplifier; a non-inverting input end of the first operational amplifier and an inverting input end of the second operational amplifier are connected to the first input end of the operational amplifier circuit; an inverting input end of the first operational amplifier and a non-inverting input end of the second operational amplifier are connected to the second input end of the operational amplifier circuit; an output end of the first operational amplifier is connected to the first output end of the operational amplifier circuit; and an output end of the second operational amplifier is connected to the second output end of the operational amplifier circuit; The first operational amplifier is used for outputting a first control signal to the voltage-controlled delay circuit based on the reference voltage and the ripple voltage; The second operational amplifier is used for outputting a second control signal to the voltage-controlled delay circuit based on the reference voltage and the ripple voltage.

3. The power converter of claim 2, wherein, The voltage-controlled delay circuit comprises a first voltage-controlled delay line and a second voltage-controlled delay line; a first input end of the first voltage-controlled delay line is connected to the first input end of the voltage-controlled delay circuit; a first input end of the second voltage-controlled delay line is connected to the second input end of the voltage-controlled delay circuit; a second input end of the first voltage-controlled delay line is connected to the third input end of the voltage-controlled delay circuit; an output end of the first voltage-controlled delay line is connected to a second input end of the second voltage-controlled delay line and the first output end of the voltage-controlled delay circuit; and an output end of the second voltage-controlled delay line is connected to the second output end of the voltage-controlled delay circuit; The first voltage-controlled delay line is used for delaying the clock signal based on the first control signal and outputting a first delay signal to the second voltage-controlled delay line and the flip-flop circuit; The second voltage-controlled delay line is used for delaying the first delay signal based on the second control signal and outputting a second delay signal to the flip-flop circuit.

4. The power converter of claim 3, wherein, The trigger circuit comprises a flip-flop and an inverter, wherein a first input end of the flip-flop is connected to the first input end of the trigger circuit, a second input end of the flip-flop is connected to the second input end of the trigger circuit, an output end of the flip-flop is connected to the first output end of the trigger circuit and an input end of the inverter, and an output end of the inverter is connected to the second output end of the trigger circuit. The flip-flop is configured to output a duty cycle signal to the first switch and output an inverted duty cycle signal to the second switch through the inverter based on the first delay signal and the second delay signal, so that a difference between an output voltage of the power converter and a voltage of the load is less than a preset threshold.

5. The power converter of claim 3 or 4, wherein a delay time between the first delay signal and the clock signal is positively correlated with an absolute value of a difference between the reference voltage and the ripple voltage.

6. The power converter of any one of claims 3-5, wherein a delay time between the second delay signal and the first delay signal is positively correlated with an absolute value of a difference between the reference voltage and the ripple voltage.

7. The power converter of any of claims 1-6, wherein, The control circuit further comprises a voltage-controlled oscillation circuit, an input end of the voltage-controlled oscillation circuit is connected to an output end of the power converter, and an output end of the voltage-controlled oscillation circuit is connected to a third input end of the voltage-controlled delay circuit. The voltage-controlled oscillation circuit is configured to output the clock signal to the voltage-controlled delay circuit based on a sampled output voltage of the power converter.

8. The power converter of any of claims 1-7, wherein, The power converter further comprises an inductor, the inductor is connected between a series connection point of the first switch and the second switch and an output end of the power converter. The control circuit further comprises a current sampling circuit, an input end of the current sampling circuit is connected between the series connection point of the first switch and the second switch and the inductor, and an output end of the current sampling circuit is connected to a second input end of the operational amplifier circuit. The current sampling circuit is configured to collect a current flowing through the inductor and output the ripple voltage to the operational amplifier circuit based on the current flowing through the inductor.

9. A control circuit for a power converter, characterized by The control circuit comprises an operational amplifier circuit, a voltage-controlled delay circuit, and a trigger circuit, the power converter comprises an input end, a first switch, a second switch, and an output end, the first switch and the second switch are connected in series and connected to the input end of the power converter, and two ends of the second switch are connected to the output end of the power converter. The first input end of the operational amplifier circuit is used for receiving a reference voltage, the second input end of the operational amplifier circuit is used for receiving a ripple voltage of an output end of the power converter, the first output end of the operational amplifier circuit is connected with the first input end of the voltage-controlled delay circuit, the second output end of the operational amplifier circuit is connected with the second input end of the voltage-controlled delay circuit, the third input end of the voltage-controlled delay circuit is used for receiving a clock signal, the first output end of the voltage-controlled delay circuit is connected with the first input end of the flip-flop circuit, the second output end of the voltage-controlled delay circuit is connected with the second input end of the flip-flop circuit, and the first output end of the flip-flop circuit is used for connecting the first switch, and the second output end of the flip-flop circuit is used for connecting the second switch.

10. The control circuit of claim 9, wherein, The operational amplifier circuit comprises a first operational amplifier and a second operational amplifier, wherein the non-inverting input end of the first operational amplifier and the inverting input end of the second operational amplifier are connected with the first input end of the operational amplifier circuit, the inverting input end of the first operational amplifier and the non-inverting input end of the second operational amplifier are connected with the second input end of the operational amplifier circuit, the output end of the first operational amplifier is connected with the first output end of the operational amplifier circuit, and the output end of the second operational amplifier is connected with the second output end of the operational amplifier circuit. The first operational amplifier is used for outputting a first control signal to the voltage-controlled delay circuit based on the reference voltage and the ripple voltage. The second operational amplifier is used for outputting a second control signal to the voltage-controlled delay circuit based on the reference voltage and the ripple voltage.

11. The control circuit of claim 10, wherein, The voltage-controlled delay circuit comprises a first voltage-controlled delay line and a second voltage-controlled delay line, wherein the first input end of the first voltage-controlled delay line is connected with the first input end of the voltage-controlled delay circuit, the first input end of the second voltage-controlled delay line is connected with the second input end of the voltage-controlled delay circuit, the second input end of the first voltage-controlled delay line is connected with the third input end of the voltage-controlled delay circuit, the output end of the first voltage-controlled delay line is connected with the second input end of the second voltage-controlled delay line and the first output end of the voltage-controlled delay circuit, and the output end of the second voltage-controlled delay line is connected with the second output end of the voltage-controlled delay circuit. The first voltage-controlled delay line is used for delaying the clock signal based on the first control signal and outputting a first delay signal to the second voltage-controlled delay line and the flip-flop circuit. The second voltage-controlled delay line is used for delaying the first delay signal based on the second control signal and outputting a second delay signal to the flip-flop circuit.

12. The control circuit of claim 11, wherein, The flip-flop circuit comprises a flip-flop and an inverter, wherein the first input end of the flip-flop is connected with the first input end of the flip-flop circuit, the second input end of the flip-flop is connected with the second input end of the flip-flop circuit, the output end of the flip-flop is connected with the first output end of the flip-flop circuit and the input end of the inverter, and the output end of the inverter is connected with the second output end of the flip-flop circuit. The trigger is configured to output a duty cycle signal to the first switch and output an inverted duty cycle signal to the second switch through the inverter based on the first delay signal and the second delay signal, so that a difference between an output voltage of the power converter and a voltage of the load is less than a preset threshold. 13.The control circuit of claim 11 or 12, wherein a delay time between the first delay signal and the clock signal is positively related to an absolute value of a difference between the reference voltage and the ripple voltage. 14.The control circuit of any one of claims 11-13, wherein a delay time between the second delay signal and the first delay signal is positively related to an absolute value of a difference between the reference voltage and the ripple voltage.

15. The control circuit according to any one of claims 9-14, characterized by The control circuit further comprises a voltage-controlled oscillation circuit, an input terminal of the voltage-controlled oscillation circuit is connected to an output terminal of the power converter, and an output terminal of the voltage-controlled oscillation circuit is connected to a third input terminal of the voltage-controlled delay circuit. The voltage-controlled oscillation circuit is configured to output the clock signal to the voltage-controlled delay circuit based on a sampled output voltage of the power converter.

16. The control circuit of any of claims 9-15, wherein, The control circuit further comprises a current sampling circuit, and the power converter further comprises an inductor connected between a series connection point of the first switch and the second switch and an output terminal of the power converter, an input terminal of the current sampling circuit is connected between the series connection point of the first switch and the second switch and the inductor, and an output terminal of the current sampling circuit is connected to a second input terminal of the operational amplifier circuit. The current sampling circuit is configured to collect a current flowing through the inductor and output the ripple voltage to the operational amplifier circuit based on the current flowing through the inductor.

Images