Power conversion circuit

Abstract

A power conversion circuit comprises a transformer, a resonant capacitor, an upper bridge transistor, a lower bridge transistor, a current detection circuit, a feedback circuit and a control circuit. The transformer comprises a primary coil connected with the resonant capacitor in series. The upper bridge transistor and the lower bridge transistor are coupled to the primary coil. The current detection circuit detects a resonant current flowing through the resonant capacitor to generate a current detection signal. The feedback circuit generates a feedback signal based on the output voltage of the power conversion circuit. The control circuit integrates a superimposed signal obtained by superimposing the current detection signal on the slope compensation signal to generate a first integrated signal, integrates the feedback signal to generate a second integrated signal, and compares the first integrated signal and the second integrated signal to drive the upper bridge transistor and the lower bridge transistor.

Description

TECHNICAL FIELD

[0001] The present application relates to a resonant power conversion circuit, and more particularly to a resonant power conversion circuit using the integral result of a feedback signal for control. BACKGROUND

[0002] With the development of portable electronic devices, the development trend of power conversion circuits is similar to most power products, which is towards high efficiency, high power density, high reliability and low cost. Because the resonant power conversion circuit (including LLC resonant power conversion circuit, etc.) has the advantages of achieving zero-voltage switching (ZVS) on the primary side and zero-current switching (ZCS) of the secondary side rectifier diode in the full load range, using frequency control to make the duty cycle of the upper and lower bridge transistors 50%, no output inductor, and the secondary side can use lower voltage transistors to reduce cost and improve efficiency, etc., in recent years, it is more and more applied to DC voltage converters. SUMMARY

[0003] The resonant power conversion circuit provided by the present application tracks the integral of the feedback signal by the integral of the current flowing through the resonant capacitor, which is beneficial to more accurate control of input power and output power, and adds a slope compensation signal to eliminate the negative effects caused by the right half plane zero. In addition, the integral of the current of the resonant capacitor can also be replaced by the voltage across the resonant capacitor, which can also accurately control the input power and the output power.

[0004] According to an embodiment of the present application, a power conversion circuit is provided for converting an input voltage to an output voltage. The power conversion circuit includes a transformer, a resonant capacitor, an upper bridge transistor, a lower bridge transistor, a current sensing circuit, a feedback circuit, and a control circuit. The transformer includes a primary winding and a secondary winding, wherein the primary winding is coupled between a switching node and a resonant node. The resonant capacitor is coupled between the resonant node and a ground terminal. The upper bridge transistor provides the input voltage to the switching node based on an upper bridge drive signal. The lower bridge transistor couples the switching node to the ground terminal based on a lower bridge drive signal. The current sensing circuit senses a resonant current flowing through the resonant capacitor and generates a current sensing signal. The feedback circuit generates a feedback signal based on the output voltage. The control circuit generates a superimposed signal by superimposing the current sensing signal with a slope compensation signal, and generates a first integral signal by integrating the superimposed signal. The control circuit further generates a second integral signal by integrating the feedback signal, and generates the upper bridge drive signal and the lower bridge drive signal by comparing the first integral signal and the second integral signal.

[0005] According to an embodiment of the present application, the slope compensation signal is a sawtooth wave.

[0006] According to an embodiment of the present application, the second integral signal is a product of the feedback signal and an on-time. The on-time is any one of a turn-on time of the upper bridge transistor, a turn-on time of the lower bridge transistor, and a switching period. The upper bridge drive signal and the lower bridge drive signal have the switching period.

[0007] According to an embodiment of the present application, when the upper bridge transistor is turned on, the second integral signal is a product of the feedback signal and a turn-on time of a previous turn-on period of the upper bridge transistor. When the lower bridge transistor is turned on, the second integral signal is a product of the feedback signal and a turn-on time of a previous turn-on period of the lower bridge transistor.

[0008] According to an embodiment of the present application, when the upper bridge transistor or the lower bridge transistor is turned on, the second integral signal is a product of the feedback signal and the switching period.

[0009] According to an embodiment of the present application, the control circuit further comprises a superimposition circuit and a first integration circuit. The superimposition circuit superimposes the current detection signal and the slope compensation signal to generate the superimposition signal. The first integration circuit integrates the superimposition signal to generate the first integration signal. When the upper bridge transistor is turned on, the superimposition circuit adds the current detection signal and the slope compensation signal to generate the superimposition signal. When the lower bridge transistor is turned on, the superimposition circuit subtracts the current detection signal from the slope compensation signal to generate the superimposition signal.

[0010] According to an embodiment of the present application, the control circuit further comprises a full-wave rectifier and a comparator. The full-wave rectifier full-wave rectifies the first integration signal to generate a full-wave rectified signal. The comparator compares the full-wave rectified signal and the second integration signal. When the full-wave rectified signal exceeds the second integration signal, the control circuit turns off the upper bridge transistor or turns off the lower bridge transistor.

[0011] According to an embodiment of the present application, when the upper bridge transistor is turned on and the full-wave rectified signal drops to not exceed the second integration signal, the control circuit turns off the upper bridge transistor. When the lower bridge transistor is turned on and the full-wave rectified signal drops to not exceed the second integration signal, the control circuit turns off the lower bridge transistor.

[0012] According to another embodiment of the present application, the control circuit further comprises a first error amplifier, a second error amplifier, a first comparator, and a second comparator. The first error amplifier compares the second integration signal and a reference voltage to generate an upper threshold voltage. The second error amplifier compares the reference voltage and the second integration signal to generate a lower threshold voltage. The first comparator compares the first integration signal and the upper threshold voltage to disable the upper bridge drive signal. The second comparator compares the first integration signal and the lower threshold voltage to disable the lower bridge drive signal. When the upper bridge transistor is turned on and the first integration signal exceeds the upper threshold voltage, the first comparator disables the upper bridge drive signal. When the lower bridge transistor is turned on and the lower threshold voltage exceeds the first integration signal, the second comparator disables the lower bridge drive signal.

[0013] According to an embodiment of the present application, when the upper bridge transistor is turned on and the first integration signal drops to not exceed the upper threshold voltage, the control circuit turns off the upper bridge transistor. When the lower bridge transistor is turned on and the first integration signal rises to exceed the lower threshold voltage, the control circuit turns off the lower bridge transistor.

[0014] According to an embodiment of the present application, the control circuit controls the first integral signal to track the second integral signal, and further controls the power conversion circuit to receive an input power from the output voltage and to generate an output power for the output voltage.

[0015] According to an embodiment of the present application, the on-time of the upper bridge transistor is equal to the on-time of the lower bridge transistor.

[0016] According to an embodiment of the present application, the power conversion circuit further comprises a rectifier circuit. The rectifier circuit is coupled to the secondary winding. The rectifier circuit is used to convert the energy of the secondary winding to the output voltage.

[0017] The present application further provides a power conversion circuit for converting an input voltage to an output voltage. The power conversion circuit comprises a transformer, a resonant capacitor, an upper bridge transistor, a lower bridge transistor, a voltage detection circuit, a feedback circuit, and a control circuit. The transformer comprises a primary winding and a secondary winding, wherein the primary winding is coupled between a switching node and a resonant node. The resonant capacitor is coupled between the resonant node and a ground terminal. The upper bridge transistor is used to provide the input voltage to the switching node based on an upper bridge drive signal. The lower bridge transistor is used to couple the switching node to the ground terminal based on a lower bridge drive signal. The voltage detection circuit is used to detect the voltage across the resonant capacitor and to generate a voltage detection signal. The feedback circuit is used to generate a feedback signal based on the output voltage. The control circuit is used to generate a superimposed signal by superimposing the voltage detection signal with a slope compensation signal, and to generate an integral signal by integrating the feedback signal. The control circuit is further used to generate the upper bridge drive signal and the lower bridge drive signal by comparing the integral signal with the superimposed signal.

[0018] According to an embodiment of the present application, the slope compensation signal is the result of integrating a sawtooth wave with respect to time.

[0019] According to an embodiment of the present application, the slope compensation signal is a parabolic wave.

[0020] According to an embodiment of the present application, the integral signal is the product of the feedback signal and an on-time. The on-time is any one of the on-time of the upper bridge transistor, the on-time of the lower bridge transistor, and a switching period. The upper bridge drive signal and the lower bridge drive signal have the switching period.

[0021] According to an embodiment of the present application, when the upper bridge transistor is turned on, the integral signal is the product of the feedback signal and the on-time of the previous on-period of the upper bridge transistor. When the lower bridge transistor is turned on, the integral signal is the product of the feedback signal and the on-time of the previous on-period of the lower bridge transistor.

[0022] According to an embodiment of the present application, when the upper bridge transistor or the lower bridge transistor is turned on, the integral signal is the product of the feedback signal and the switching period.

[0023] According to an embodiment of the present application, the control circuit further comprises a superimposition circuit. The superimposition circuit superimposes the voltage detection signal and the slope compensation signal to generate the superimposition signal. When the upper bridge transistor is turned on, the superimposition circuit adds the voltage detection signal and the slope compensation signal to generate the superimposition signal. When the lower bridge transistor is turned on, the superimposition circuit subtracts the voltage detection signal and the slope compensation signal to generate the superimposition signal.

[0024] According to an embodiment of the present application, the voltage detection circuit comprises a voltage dividing circuit. The voltage dividing circuit divides the voltage across the resonant capacitor to generate the voltage detection signal.

[0025] According to an embodiment of the present application, the control circuit further comprises a full-wave rectifier and a comparator. The full-wave rectifier full-wave rectifies the superimposition signal to generate a full-wave rectified signal. The comparator compares the full-wave rectified signal and the integral signal. When the full-wave rectified signal exceeds the integral signal, the control circuit turns off the upper bridge transistor or turns off the lower bridge transistor.

[0026] According to an embodiment of the present application, when the upper bridge transistor is turned on and the superimposition signal drops to not exceed the integral signal, the control circuit turns off the upper bridge transistor. When the lower bridge transistor is turned on and the superimposition signal drops to not exceed the integral signal, the control circuit turns off the lower bridge transistor.

[0027] According to another embodiment of the present invention, the control circuit further includes a first error amplifier, a second error amplifier, a first comparator, and a second comparator. The first error amplifier compares the integrated signal with a reference voltage to generate an upper threshold voltage. The second error amplifier compares the reference voltage with the integrated signal to generate a lower threshold voltage. The first comparator compares the superimposed signal with the upper threshold voltage and disables the upper bridge drive signal. The second comparator compares the superimposed signal with the lower threshold voltage and disables the lower bridge drive signal. When the upper bridge transistor is turned on and the superimposed signal exceeds the upper threshold voltage, the first comparator disables the upper bridge drive signal. When the lower bridge transistor is turned on and the lower threshold voltage exceeds the superimposed signal, the second comparator disables the lower bridge drive signal.

[0028] According to one embodiment of the present invention, when the upper bridge transistor is turned on and the superimposed signal drops to below the upper threshold voltage, the control circuit turns off the upper bridge transistor. When the lower bridge transistor is turned on and the superimposed signal rises to above the lower threshold voltage, the control circuit turns off the lower bridge transistor.

[0029] According to one embodiment of the present invention, the conduction time of the upper bridge transistor is equal to the conduction time of the lower bridge transistor. Attached Figure Description

[0030] Figure 1 This is a block diagram showing a power conversion circuit according to an embodiment of the present invention;

[0031] Figure 2 This is a waveform diagram showing the power conversion circuit according to an embodiment of the present invention;

[0032] Figure 3 This is a block diagram showing a power conversion circuit according to another embodiment of the present invention;

[0033] Figure 4 This is a block diagram showing a power conversion circuit according to yet another embodiment of the present invention;

[0034] Figure 5 This is a block diagram showing a power conversion circuit according to yet another embodiment of the present invention; and

[0035] Figure 6 This is a block diagram showing a power conversion circuit according to yet another embodiment of the present invention.

[0036] Symbol explanation:

[0037] 100, 300, 400, 500, 600: Power conversion circuit;

[0038] TM: Transformer;

[0039] LR: Resonant inductor;

[0040] CR: Resonant capacitor;

[0041] 110: Upper-bridge transistor;

[0042] 120: Lower-bridge transistor;

[0043] 130: Current detection circuit;

[0044] 140: Rectifier circuit;

[0045] 150: Feedback circuit;

[0046] 160, 360, 460, 560, 660: Control circuit;

[0047] PS: Primary coil;

[0048] SS: Secondary coil;

[0049] NR: Resonant node;

[0050] SW: Switch node;

[0051] VCR: Resonant voltage;

[0052] HSG: Upper bridge gate drive signal;

[0053] VIN: Input voltage;

[0054] LSG: Lower bridge gate drive signal;

[0055] IR: Resonant current;

[0056] SCS: Current detection signal;

[0057] R1: First resistor;

[0058] C1: First capacitor;

[0059] D1: First rectifier element;

[0060] D2: Second rectifier element;

[0061] COUT: Output capacitor;

[0062] VOUT: Output voltage;

[0063] FB: Feedback signal;

[0064] R2: Second resistor;

[0065] R3: Third resistor;

[0066] DR: Voltage regulator;

[0067] PD: Optical coupling element;

[0068] R4: Fourth resistor;

[0069] VD1: First voltage divider voltage;

[0070] LED: Diode;

[0071] Q: Transistor;

[0072] 161: First superposition circuit;

[0073] 162: First integrating circuit;

[0074] 163: Full-wave rectifier;

[0075] 164: Second integrator circuit;

[0076] CMP1: First comparator;

[0077] LH1: First latch;

[0078] LH2: Second latch;

[0079] SC1: Slope compensation signal;

[0080] SP: Superimposed signal;

[0081] SW1: First switch;

[0082] SW2: Second switch;

[0083] ADD: Adder circuit;

[0084] OTA: Transconductance Amplifier;

[0085] VB: Bias voltage;

[0086] CINT: Integrating capacitor;

[0087] gm: transduction;

[0088] IINT: Integral current;

[0089] INT1: First integration signal;

[0090] FW: Full-wave rectified signal;

[0091] HS: Upper bridge drive signal;

[0092] LS: Lower bridge drive signal;

[0093] INT2: Second integral signal;

[0094] CP1: First comparison signal;

[0095] T1: First time point;

[0096] T2: Second time point;

[0097] T3: Third time point;

[0098] T4: Fourth time point;

[0099] TON1: First conduction time;

[0100] TON2: Second conduction time;

[0101] EA1: First error amplifier;

[0102] EA2: Second error amplifier;

[0103] CMP2: Second comparator;

[0104] CMP3: Third comparator;

[0105] VR: Reference voltage;

[0106] VTHH: Upper limit voltage;

[0107] VTHL: Lower threshold voltage;

[0108] CP2: Second comparison signal;

[0109] CP3: Third comparison signal;

[0110] 430: Voltage detection circuit;

[0111] SVS: Voltage Detection Signal;

[0112] 461: Second superposition circuit;

[0113] SC2: Second slope compensation signal. Detailed Implementation

[0114] The following description illustrates embodiments of the present invention. Its purpose is to demonstrate the general principles of the invention and should not be construed as limiting the invention. The scope of the invention is defined by the claims.

[0115] It is worth noting that the following disclosure provides multiple embodiments or examples for practicing different features of the present invention. The specific examples and arrangements of elements described below are merely for briefly illustrating the spirit of the invention and are not intended to limit the scope of the invention. Furthermore, the same element symbols or words may be repeated in multiple examples in the following description. However, the purpose of repetition is only to provide a simplified and clear explanation and is not intended to limit the relationship between the various embodiments and / or configurations discussed below.

[0116] Furthermore, the description in the following specification of a feature being connected to, coupled to, and / or formed on top of another feature may actually include multiple different embodiments, including features that are in direct contact, or additional features that are formed between features, such that the features are not in direct contact.

[0117] Furthermore, relative terms such as "lower" or "bottom" and "higher" or "top" may be used in the embodiments to describe the relative relationship of one element of the diagram to another element. It is understood that if the arrangement of the diagram is flipped so that it is upside down, the element depicted on the "lower" side will become the element on the "higher" side.

[0118] It is understood that although terms such as "first," "second," and "third" may be used herein to describe various elements, components, regions, layers, and / or portions, these elements, components, regions, layers, and / or portions should not be limited by these terms, and these terms are only used to distinguish different elements, components, regions, layers, and / or portions. Therefore, a first element, component, region, layer, and / or portion discussed below may be referred to as a second element, component, region, layer, and / or portion without departing from the teachings of some embodiments of the present invention.

[0119] Some embodiments of the present invention can be understood in conjunction with the accompanying drawings, which are also considered part of the description of the embodiments of the present invention. It should be understood that the drawings of the embodiments of the present invention are not drawn to scale with actual devices and components. The shape and thickness of the embodiments may be exaggerated in the drawings to clearly show the features of the embodiments of the present invention. Furthermore, the structures and devices in the drawings are illustrated schematically to clearly show the features of the embodiments of the present invention.

[0120] Here, the terms "about," "approximately," and "roughly" generally indicate within 20% of a given value or range, preferably within 10%, and even more preferably within 5%, or within 3%, or within 2%, or within 1%, or within 0.5%. The quantities given here are approximate quantities, meaning that the meaning of "about," "approximately," or "roughly" is implied even without specific mention of them.

[0121] Unless otherwise defined, all terms used herein (including technical and scientific terms) have the same meaning as commonly understood by those skilled in the art to which this disclosure pertains. It is understood that these terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning consistent with the relevant art and the background or context of the invention, and should not be interpreted in an idealized or overly formal manner, unless specifically defined in the embodiments of the invention.

[0122] In some embodiments of the present invention, terms such as "connection" and "interconnection" are used to refer to two structures in direct contact, unless otherwise defined. This can also refer to two structures that are not in direct contact, with another structure disposed between them. Furthermore, these terms can also include cases where both structures are movable or both structures are fixed.

[0123] In a diagram, similar elements and / or features may have the same element symbol. Elements of the same type can be distinguished by adding letters or numbers after the element symbol to differentiate similar elements and / or features.

[0124] Figure 1 This is a block diagram showing a power conversion circuit according to an embodiment of the present invention. Figure 1 As shown, the power conversion circuit 100 includes a transformer TM, a resonant inductor LR, a resonant capacitor CR, an upper bridge transistor 110, a lower bridge transistor 120, a current detection circuit 130, a rectifier circuit 140, a feedback circuit 150, and a control circuit 160.

[0125] The transformer TM includes a primary coil PS and a secondary coil SS, wherein the primary coil PS is coupled to the resonant node NR. A resonant inductor LR is coupled between the switching node SW and the primary coil PS, and a resonant capacitor CR is coupled between the resonant node NR and ground. According to one embodiment of the invention, the resonant inductor LR can be replaced by the leakage inductance of the primary coil PS of the transformer TM. In other words, the primary coil PS can be coupled between the switching node SW and the resonant node NR.

[0126] According to some embodiments of the present invention, the power conversion circuit 100 is a resonant power conversion circuit. According to one embodiment of the present invention, the power conversion circuit 100 may be an LLC resonant power conversion circuit. According to another embodiment of the present invention, the power conversion circuit 100 may also be an asymmetrical half-bridge (AHB) flyback converter.

[0127] The upper bridge gate drive signal HSG drives the upper bridge transistor 110 to turn on and off, providing the input voltage VIN to the switching node SW. The lower bridge gate drive signal LSG drives the lower bridge transistor 120 to turn on and off, coupling the switching node SW to ground. The current detection circuit 130 is coupled to the resonant node NR to detect the resonant current IR flowing through the resonant capacitor CR and generate a current detection signal SCS. The current detection circuit 130 includes a first capacitor C1 and a first resistor R1. The first capacitor C1 is coupled to the resonant node NR, and the first resistor R1 is coupled between the first capacitor C1 and the ground terminal, wherein the current detection signal SCS is generated between the first capacitor C1 and the first resistor R1. In other words, the current detection signal SCS is the voltage across the first resistor R1.

[0128] Rectifier circuit 140 is coupled to the secondary coil SS to convert the energy of the secondary line source SS into an output voltage VOUT. In other words, rectifier circuit 140 converts the current flowing through the secondary coil SS into an output voltage VOUT. Figure 1 As shown, the rectifier circuit 140 includes a first rectifier element D1, a second rectifier element D2, and an output capacitor COUT.

[0129] The first rectifier element D1 and the second rectifier element D2 are used to more efficiently charge the output capacitor COUT with the current flowing through the secondary coil SS, thereby generating the output voltage VOUT. According to other embodiments of the present invention, the first rectifier element D1 and the second rectifier element D2 can be replaced with electronic components with low on-resistance to further improve the conversion efficiency.

[0130] Feedback circuit 150 generates a feedback signal FB based on the output voltage VOUT. For example... Figure 1 As shown, the feedback circuit 150 includes a second resistor R2, a third resistor R3, a voltage regulator DR, an optocoupler PD, and a fourth resistor R4. The second resistor R2 and the third resistor R3 are used to divide the output voltage VOUT to generate a first voltage divider voltage VD1. Based on the first voltage divider voltage VD1, the voltage regulator DR generates current flowing through the diode LED of the optocoupler PD, causing the LED to emit light. This light, through optocoupler, turns on the transistor Q of the optocoupler PD, thereby generating the feedback signal FB.

[0131] The fourth resistor R4 is used to limit the current flowing through the diode LED. According to one embodiment of the invention, the voltage regulator DR can be a TL431. According to one embodiment of the invention, when the output voltage VOUT increases, the feedback signal FB decreases accordingly. According to another embodiment of the invention, when the output voltage VOUT decreases, the feedback signal FB increases accordingly. According to one embodiment of the invention, when the output power of the output voltage VOUT increases, the feedback signal FB increases accordingly. According to another embodiment of the invention, when the output power of the output voltage VOUT decreases, the feedback signal FB decreases accordingly.

[0132] The control circuit 160 generates the upper bridge gate drive signal HSG and the lower bridge gate drive signal LSG based on the current detection signal SCS and the feedback signal FB. For example... Figure 1 As shown, the control circuit 160 includes a first superposition circuit 161, a first integrating circuit 162, a full-wave rectifier 163, a second integrating circuit 164, a first comparator CMP1, a first latch LH1, and a second latch LH2.

[0133] The first superposition circuit 161 is used to superimpose the current detection signal SCS with the first slope compensation signal SC1 to generate the superimposed signal SP. According to some embodiments of the present invention, the first slope compensation signal SC1 is used to eliminate the negative impact of the right half-plane zero. According to one embodiment of the present invention, the first slope compensation signal SC1 is a sawtooth wave. In other words, the first slope compensation signal SC1 is the result of integrating a constant over time. Figure 1 As shown, the first superposition circuit 161 includes a first switch SW1, a second switch SW2, and an adder circuit ADD.

[0134] According to one embodiment of the present invention, when the upper bridge gate drive signal HSG turns on the upper bridge transistor 110, the first switch SW1 is turned on, and the adder circuit ADD adds the current detection signal SCS to the first slope compensation signal SC1 to generate the superimposed signal SP. According to another embodiment of the present invention, when the lower bridge gate drive signal LSG turns on the lower bridge transistor 120, the second switch SW2 is turned on, and the adder circuit ADD subtracts the first slope compensation signal SC1 from the current detection signal SCS to generate the superimposed signal SP.

[0135] The first integrating circuit 162 is used to integrate the superimposed signal SP to generate the first integrated signal INT1. For example... Figure 1As shown, the first integrating circuit 162 includes a transconductance amplifier OTA and an integrating capacitor CINT. The transconductance amplifier OTA is powered by a bias voltage VB and generates an integrating current IINT based on a superimposed signal SP. The integrating current IINT charges the integrating capacitor CINT to generate a first integrating signal INT1. According to an embodiment of the present invention, the transconductance gm generated by the transconductance amplifier OTA is proportional to the input voltage VIN.

[0136] A full-wave rectifier 163 is used to perform full-wave rectification on the first integrated signal INT1 to generate a full-wave rectified signal FW. A second integrating circuit 164 integrates the feedback signal FB based on the upper bridge drive signal HS and the lower bridge drive signal LS to generate a second integrated signal INT2. A first comparator CMP1 compares the full-wave rectified signal FW and the second integrated signal INT2 to generate a first comparison signal CP1.

[0137] According to one embodiment of the present invention, when the full-wave rectified signal FW exceeds the second integral signal INT2, the first comparison signal CP1 is disabled. According to another embodiment of the present invention, when the full-wave rectified signal FW does not exceed the second integral signal INT2, the first comparison signal CP1 is enabled. How the second integrator circuit 164 generates the second integral signal INT2 based on the upper bridge drive signal HS and the lower bridge drive signal LS will be discussed below. Figure 2 The description is detailed in detail.

[0138] The first latch LH1 enables the upper bridge gate drive signal HSG based on the enabled upper bridge drive signal HS, and disables the upper bridge gate drive signal HSG based on the rising edge of the first comparison signal CP1. The second latch LH2 enables the lower bridge gate drive signal LSG based on the enabled lower bridge drive signal LS, and disables the lower bridge gate drive signal LSG based on the rising edge of the first comparison signal CP1.

[0139] According to some embodiments of the present invention, when the upper bridge gate drive signal HSG or the lower bridge gate drive signal LSG is enabled, the upper bridge transistor 110 or the lower bridge transistor 120 is turned on. According to other embodiments of the present invention, when the upper bridge gate drive signal HSG or the lower bridge gate drive signal LSG is disabled, the upper bridge transistor 110 or the lower bridge transistor 120 is turned off.

[0140] Figure 2 This is a waveform diagram showing a power conversion circuit according to an embodiment of the present invention. The following is for... Figure 2 The description of the waveform will be paired with Figure 1The power conversion circuit 100 is described in detail below. Between the first time point T1 and the second time point T2, the lower bridge gate drive signal LSG enables and conducts the lower bridge transistor 120, and the second integrator circuit 164 generates a second integration signal INT2 (i.e., ...) based on the enabled lower bridge drive signal LSG. Figure 2 As shown in INT2(LS)).

[0141] When the full-wave rectified signal FW decreases and does not exceed the second integral signal INT2 at the second time point T2 (i.e., Figure 2 When INT2(LS) is shown, the rising edge of the first comparison signal CP1 disables the lower bridge gate drive signal LSG, thus turning off the lower bridge transistor 120. Specifically, when the first comparison signal CP1 transitions from a disabled state to an enabled state (i.e., the full-wave rectified signal FW drops from exceeding the second integral signal INT2 to not exceeding the second integral signal INT2), the second latch LH2 disables the lower bridge gate drive signal LSG, thus turning off the lower bridge transistor 120. According to an embodiment of the present invention, the first conduction time TON1 is the conduction time of the lower bridge transistor 120.

[0142] Between the second time point T2 and the third time point T3, the upper bridge gate drive signal HSG enables and conducts the upper bridge transistor 110, and the second integrator circuit 164 generates a second integration signal INT2 based on the enabled upper bridge drive signal HSG (i.e., Figure 2 As shown in INT2(HS)). When the full-wave rectified signal FW decreases and does not exceed the second integral signal INT2 at the third time point T3 (i.e., Figure 2 When INT2(HS) is shown, the rising edge of the first comparison signal CP1 disables the upper bridge gate drive signal HSG and turns off the upper bridge transistor 110. In detail, when the first comparison signal CP1 transitions from the disabled state to the enabled state (i.e., the full-wave rectified signal FW drops from exceeding the second integral signal INT2 to not exceeding the second integral signal INT2), the first latch LH1 disables the upper bridge gate drive signal HSG and turns off the upper bridge transistor 110.

[0143] According to one embodiment of the present invention, the second conduction time TON2 is the conduction time of the upper bridge transistor 110. According to some embodiments of the present invention, the first conduction time TON1 may be equal to the second conduction time TON2. According to other embodiments of the present invention, the first conduction time TON1 may not be equal to the second conduction time TON2. According to some embodiments of the present invention, the second integral signal INT2 is the product of the feedback signal FB and the previous conduction time.

[0144] For example, the second integral signal INT2 (i.e., between the second time point T2 and the third time point T3) Figure 2The INT2(HS) shown is the product of the feedback signal FB and the first conduction time TON1 between the first time point T1 and the second time point T2. The second integral signal INT2 (i.e., ...) between the third time point T3 and the fourth time point T4 is the second integral signal INT2. Figure 2 The INT2(LS) shown is the product of the feedback signal FB and the second conduction time TON2 between the second time point T2 and the third time point T3.

[0145] In other words, when the upper-bridge transistor 110 is turned on between the second time point T2 and the third time point T3, the second integral signal INT2 is the product of the feedback signal FB and the conduction time of the lower-bridge transistor 120 between the first time point T1 and the second time point T2 (i.e., the first conduction time TON1). When the lower-bridge transistor 120 is turned on between the third time point T3 and the fourth time point T4, the second integral signal INT2 is the product of the feedback signal FB and the conduction time of the upper-bridge transistor 110 between the second time point T2 and the third time point T3 (i.e., the second conduction time TON2).

[0146] In addition, such as Figure 2 As shown in the embodiment, the second integral signal INT2 (i.e., corresponding to the conduction of the upper bridge transistor 110) is... Figure 2 The INT2(HS) shown increases continuously when the lower-bridge transistor 120 is turned on and reaches its maximum value when the lower-bridge transistor 120 is turned off. Similarly, the second integral signal INT2(i.e., when the lower-bridge transistor 120 is turned on) corresponds to the following: Figure 2 The INT2(LS) shown increases continuously when the upper bridge transistor 110 is turned on and reaches its maximum value when the upper bridge transistor 110 is turned off.

[0147] In this invention Figure 2 In this embodiment, since the first conduction time TON1 is equal to the second conduction time TON2, the second integral signal INT2 is almost a constant (i.e., Figure 2 The INT2(LS) shown is equal to INT2(HS). According to other embodiments of the present invention, when the first conduction time TON1 is different from the second conduction time TON2, the second integral signal INT2 corresponding to the conduction of the upper bridge transistor 110 and the lower bridge transistor 120 is not the same.

[0148] According to other embodiments of the present invention, the second integration signal INT2 can also be the product of the feedback signal FB and the switching period TS, such that the second integration signal INT2 corresponding to the conduction of the upper bridge transistor 110 and the lower bridge transistor 120 is the same. In other words, when the second integration signal INT2 is the product of the feedback signal FB and the switching period TS, the second integration circuit 164 no longer generates the corresponding second integration signal INT2 based on the upper bridge drive signal HS and the lower bridge drive signal LS, and Figure 2 The second integral signal INT2 is a constant.

[0149] In the power conversion circuit 100, the input power PIN of the input voltage VIN is the product of the input voltage VIN and the average current IAV flowing through the upper bridge transistor 110, as shown in Formula 1:

[0150] PIN=VIN×IAV (Formula 1)

[0151] The average current IAV can be replaced by the product of the resonant capacitance CR, the change in resonant voltage VCR ΔVCR, and the switching frequency FS, where the switching frequency FS is the switching frequency of the upper bridge drive signal HS and the lower bridge drive signal LS, and the switching frequency FS is... Figure 1 The reciprocal of the switching period TS. See Formula 2 for details:

[0152] PIN=VIN×CR×ΔVCR×FS (Formula 2)

[0153] According to some embodiments of the present invention, the control change ΔVCR tracking feedback signal FB can be used as an indicator for monitoring the input power PIN. However, in Figure 1 In the embodiment of the power conversion circuit 100, the switching frequency FS changes with the output voltage VOUT. If only the change ΔVCR is controlled, the effect of the switching frequency FS on the input power PIN is ignored. Furthermore, the product of the resonant capacitance CR and the change ΔVCR is equal to the integral of the resonant current IR over time. Therefore, the input power PIN in Equation 2 can be rewritten as Equation 3.

[0154] PIN=VIN×∫(IR)dt×FS (Formula 3)

[0155] exist Figure 1 In this embodiment, the first comparator CMP1 controls the integral of the resonant current IR to track the integral of the feedback signal FB, thereby eliminating the switching frequency FS in Equation 3. Figure 2As shown, the transduction gm of the transconductance amplifier OTA charges the integrating capacitor CINT based on the current detection signal SCS, which can be expressed as the left side of Equation 4. The right side of Equation 4 is the integration of the feedback signal FB by the second integrating circuit 164, and the second integrating signal INT2 can be expressed as the product of the feedback signal FB and the conduction time TON, where the conduction time TON corresponds to the product of the current detection signal FB and the current detection signal SCS. Figure 2 The first conduction time TON1 or the second conduction time TON2. According to other embodiments of the present invention, the conduction time TON may also be... Figure 2 The switching period TS is the reciprocal of the switching frequency FS.

[0156]

[0157] The integral of the current detection signal SCS can be expressed by Equation 5.

[0158]

[0159] Since the current sensing signal SCS is used to represent the resonant current IR, the integral of the resonant current IR can be obtained from the formula...

[0160] Equation 6 represents this.

[0161]

[0162] Substituting Formula 6 into Formula 3, we get Formula 7.

[0163]

[0164] like Figure 1 As shown in the embodiment, the first conduction time TON1 and the second conduction time TON2 are equal, therefore the conduction time TON in Formula 7 is approximately half of the switching period TS. In other words, the product of TON and FS in Formula 7 is approximately 0.5. Therefore, Formula 7 can be rewritten as Formula 8.

[0165]

[0166] According to one embodiment of the present invention, the transconductance gm generated by the transconductance amplifier OTA is proportional to the input voltage VIN. In other words, the transconductance gm can be expressed as the product of a constant k and the input voltage VIN, and the product of the constant k and the input voltage VIN is substituted for gm in Equation 8, and rewritten as Equation 9.

[0167]

[0168] As shown in Formula 9, the input power PIN is only related to the feedback signal FB. In other words, the feedback signal FB serves not only as an indicator of the output power of the power conversion circuit 100, but also as an indicator of the input power PIN of the power conversion circuit 100. In detail, Figure 1 The power conversion circuit 100 uses the first integration signal INT1 and the second integration signal INT2 to drive the upper bridge transistor 110 and the lower bridge transistor 120, which is beneficial to simultaneously control the input power of the input voltage VIN and the output power of the output voltage VOUT.

[0169] According to some embodiments of the present invention, the second integral signal INT2 may be a DC voltage value. According to some embodiments of the present invention, Figure 3 The power conversion circuit 100 uses a control method that integrates the current detection signal SCS and the feedback signal, which is similar to the peak current control mode.

[0170] Figure 3 This is a block diagram showing a power conversion circuit according to another embodiment of the present invention. Figure 1 The power conversion circuit 300 and the control circuit 360 Figure 3 Compared to the control circuit 160, the full-wave rectifier 163 and the first comparator CMP1 of the control circuit 160 are replaced by the first error amplifier EA1, the second error amplifier EA2, the second comparator CMP2 and the third comparator CMP3 of the control circuit 360.

[0171] like Figure 4 As shown, the first error amplifier EA1 generates an upper threshold voltage VTHH based on the difference between the second integral signal INT2 and the reference voltage VR. The second error amplifier EA2 generates a lower threshold voltage VTHL based on the difference between the reference voltage VR and the second integral signal INT2. According to some embodiments of the present invention, the reference voltage VR can be adjusted to adjust the proportion of the conduction time of the upper bridge transistor 110 and the conduction time of the lower bridge transistor 120. The second comparator CMP2 compares the upper threshold voltage VTHH and the first integral signal INT1 to generate a second comparison signal CP2. The third comparator CMP3 compares the first integral signal INT1 and the lower threshold voltage VTHL to generate a third comparison signal CP3.

[0172] According to one embodiment of the present invention, when the upper bridge gate drive signal HSG turns on the upper bridge transistor 110 and the first integration signal INT1 drops to no more than the upper threshold voltage VTHH, the first latch LH1 deactivates the upper bridge gate drive signal HSG and turns off the upper bridge transistor 110. More specifically, when the upper bridge transistor 110 is turned on and the first integration signal INT1 drops from exceeding the upper threshold voltage VTHH to no more than the upper threshold voltage VTHH, the control circuit 360 turns off the upper bridge transistor 110.

[0173] According to another embodiment of the present invention, when the lower bridge gate drive signal LSG turns on the lower bridge transistor 120 and the first integration signal INT1 rises above the lower threshold voltage VTHL, the second latch LH2 disables the lower bridge gate drive signal LSG and turns off the lower bridge transistor 120. More specifically, when the lower bridge transistor 120 is turned on and the first integration signal INT1 rises from not exceeding the lower threshold voltage VTHL to exceeding the lower threshold voltage VTHL, the control circuit 360 turns off the lower bridge transistor 120.

[0174] Figure 4 This is a block diagram showing a power conversion circuit according to another embodiment of the present invention. Figure 1 Power conversion circuit 400 and Figure 4 Compared to the power conversion circuit 100, the current detection circuit 130 of the power conversion circuit 100 is replaced by the voltage detection circuit 430, the first superposition circuit 161 of the control circuit 160 is replaced by the second superposition circuit 461, and the first integration circuit 162 is omitted.

[0175] like Figure 1 As shown, the voltage detection circuit 430 is coupled to the resonant node NR and generates a voltage detection signal SVS based on the resonant voltage VCR. According to one embodiment of the present invention, the voltage detection circuit 430 may include a voltage divider circuit, wherein the voltage divider circuit is used to divide the resonant voltage VCR to generate the voltage detection signal SVS. In other words, the resonant voltage VCR multiplied by the voltage division ratio is the voltage detection signal SVS.

[0176] The second superposition circuit 461 is used to superimpose the second slope compensation signal SC2 onto the voltage detection signal SVS to generate a superimposed signal SP. According to an embodiment of the present invention, the second slope compensation signal SC2 is the integral of the first slope compensation signal SC1. Specifically, the first slope compensation signal SC1 is a sawtooth wave, and the sawtooth wave, after integration with respect to time, generates a parabolic wave. In other words, the second slope compensation signal SC2 is the result of integrating the first slope compensation signal SC1 with respect to time; that is, the second slope compensation signal SC2 is a parabolic wave.

[0177] Since the integrated current signal is equivalent to the voltage signal, the integrated first slope compensation signal SC1 is equal to the second slope compensation signal SC2. Figure 5 The current detection signal SCS plus the first slope compensation signal SC1, then integrated, is equivalent to the voltage detection signal SVS plus the second slope compensation signal SC2. In other words, the full-wave rectified signal FW of the power conversion circuit 400 is equivalent to the full-wave rectified signal FW of the power conversion circuit 100.

[0178] According to one embodiment of the present invention, when the upper bridge transistor 110 is turned on and the full-wave rectified signal FW drops to no more than the second integral signal INT2, the first latch LTH1 disables the upper bridge gate drive signal HSG and turns off the upper bridge transistor 110. According to another embodiment of the present invention, when the lower bridge transistor 120 is turned on and the full-wave rectified signal FW drops to no more than the second integral signal INT2, the second latch LTH2 disables the lower bridge gate drive signal LSG and turns off the lower bridge transistor 120.

[0179] Figure 5 This is a block diagram showing a power conversion circuit according to yet another embodiment of the present invention. Figure 4 The power conversion circuit 500 and the control circuit 560 Figure 5 Compared to the control circuit 460, the full-wave rectifier 163 and the first comparator CMP1 of the control circuit 460 are replaced by the first error amplifier EA1, the second error amplifier EA2, the second comparator CMP2 and the third comparator CMP3 of the power conversion circuit 500.

[0180] like Figure 6 As shown, the first error amplifier EA1 generates an upper threshold voltage VTHH based on the difference between the second integral signal INT2 and the reference voltage VR. The second error amplifier EA2 generates a lower threshold voltage VTHL based on the difference between the reference voltage VR and the second integral signal INT2. According to some embodiments of the present invention, the reference voltage VR can be adjusted to adjust the proportion of the conduction time of the upper bridge transistor 110 and the conduction time of the lower bridge transistor 120. The second comparator CMP2 compares the upper threshold voltage VTHH and the superimposed signal SP to generate a second comparison signal CP2. The third comparator CMP3 compares the superimposed signal SP and the lower threshold voltage VTHL to generate a third comparison signal CP3.

[0181] According to one embodiment of the present invention, when the upper bridge gate drive signal HSG turns on the upper bridge transistor 110 and the superimposed signal SP drops to no more than the upper threshold voltage VTHH, the first latch LH1 disables the upper bridge gate drive signal HSG and turns off the upper bridge transistor 110. More specifically, when the upper bridge transistor 110 is turned on and the superimposed signal SP drops from exceeding the upper threshold voltage VTHH to no more than the upper threshold voltage VTHH, the control circuit 560 turns off the upper bridge transistor 110.

[0182] According to another embodiment of the present invention, when the lower bridge gate drive signal LSG turns on the lower bridge transistor 120 and the superimposed signal SP rises above the lower threshold voltage VTHL, the second latch LH2 disables the lower bridge gate drive signal LSG and turns off the lower bridge transistor 120. More specifically, when the lower bridge transistor 120 is turned on and the first integration signal INT1 rises from not exceeding the lower threshold voltage VTHL to exceeding the lower threshold voltage VTHL, the control circuit 360 turns off the lower bridge transistor 120.

[0183] Figure 6 This is a block diagram showing a power conversion circuit according to yet another embodiment of the present invention. Figure 1 The power conversion circuit 600 and Figure 4 Compared to the power conversion circuit 100, the power conversion circuit 600 is... Figure 1 The second superposition circuit 461 replaced Figure 6 The first superposition circuit 161. (As shown in the example...) Figure 1 As shown, the second superposition circuit 461 is located between the first integrating circuit 162 and the full-wave rectifier 163, and the second superposition circuit 461 is used to superimpose the second slope compensation signal SC2 onto the integral of the current detection signal SCS.

[0184] like Figure 1 As shown, the signal received by the full-wave rectifier 163 of the power conversion circuit 100 is the integral of the current detection signal SCS superimposed with the first slope compensation signal SC1. Since the second slope compensation signal SC2 is the integral of the first slope compensation signal SC1, therefore Figure 6 The signal received by the full-wave rectifier 163 is equivalent to the integral of the current detection signal SCS plus the second slope compensation signal SC2.

[0185] like Figure 6 As shown, the signal received by the full-wave rectifier 163 of the power conversion circuit 600 is also the integral of the current detection signal SCS (i.e., ​The first integral signal INT1 is added to the second slope compensation signal SC2. In other words, the full-wave rectifier 163 of the power conversion circuit 100 and the power conversion circuit 600 receive the same signal, so the full-wave rectified signal FW generated by the power conversion circuit 100 and the power conversion circuit 600 is also the same.

[0186] The resonant power conversion circuit proposed in this invention tracks the integral of the feedback signal by integrating the current flowing through the resonant capacitor, which facilitates more precise control of input and output power. Furthermore, a slope compensation signal is added to eliminate the negative impact caused by the right-half-plane zero. In addition, the integral of the current through the resonant capacitor can also be replaced by the voltage across the resonant capacitor, which similarly enables precise control of input and output power.

[0187] While the embodiments and advantages of the present invention have been disclosed above, it should be understood that anyone skilled in the art can make modifications, substitutions, and refinements without departing from the spirit and scope of the invention. Furthermore, the scope of protection of the present invention is not limited to the processes, machines, manufacturing methods, material compositions, apparatuses, methods, and steps described in the specific embodiments of the specification. Any process, machine, manufacturing method, material composition, apparatus, method, and step that is currently or will be developed in the future can be understood from the disclosure of some embodiments of the present invention, and can be used according to some embodiments of the present invention as long as it can perform substantially the same function or obtain substantially the same results in the embodiments described herein. Therefore, the scope of protection of the present invention includes the above-described processes, machines, manufacturing methods, material compositions, apparatuses, methods, and steps. In addition, each claim constitutes an individual embodiment, and the scope of protection of the present invention also includes combinations of various claim scopes and embodiments.

Claims

1. A power conversion circuit, characterized by, A transformer includes a primary winding and a secondary winding, wherein the primary winding is coupled between a switching node and a resonance node; a resonance capacitor coupled between the resonance node and a ground terminal; a top bridge transistor configured to provide the input voltage to the switching node based on a top bridge drive signal; a bottom bridge transistor configured to couple the switching node to the ground terminal based on a bottom bridge drive signal; a current detection circuit configured to detect a resonance current flowing through the resonance capacitor and generate a current detection signal; a feedback circuit configured to generate a feedback signal based on the output voltage; and a control circuit configured to superimpose a slope compensation signal on the current detection signal to generate a superimposed signal, and integrate the superimposed signal to generate a first integrated signal; wherein the control circuit is further configured to integrate the feedback signal to generate a second integrated signal, and compare the first integrated signal and the second integrated signal to generate the top bridge drive signal and the bottom bridge drive signal. The slope compensation signal is a sawtooth wave.

2. The power conversion circuit of claim 1, wherein, The second integrated signal is a product of the feedback signal and an on-time; 3. The power conversion circuit of claim 1, wherein, wherein the on-time is any one of a turn-on time of the top bridge transistor, a turn-on time of the bottom bridge transistor, and a switching period; wherein the top bridge drive signal and the bottom bridge drive signal have the switching period. The second integrated signal is a product of the feedback signal and a turn-on time of a previous turn-on period of the top bridge transistor when the top bridge transistor is turned on; 4. The power conversion circuit of claim 3, wherein, wherein the second integrated signal is a product of the feedback signal and a turn-on time of a previous turn-on period of the bottom bridge transistor when the bottom bridge transistor is turned on. The second integrated signal is a product of the feedback signal and the switching period when the top bridge transistor or the bottom bridge transistor is turned on.

5. The power conversion circuit of claim 3, wherein, The control circuit further comprises:

6. The power conversion circuit of claim 1, wherein, a superimposition circuit configured to superimpose the slope compensation signal on the current detection signal to generate the superimposed signal; and a first integration circuit configured to integrate the superimposed signal to generate the first integrated signal; wherein the superimposition circuit adds the current detection signal to the slope compensation signal to generate the superimposed signal when the top bridge transistor is turned on; wherein the superimposition circuit subtracts the current detection signal from the slope compensation signal to generate the superimposed signal when the bottom bridge transistor is turned on. The control circuit further comprises:

7. The power conversion circuit of claim 1, wherein, a full-wave rectification device configured to full-wave rectify the first integrated signal to generate a full-wave rectified signal; and a comparator configured to compare the full-wave rectified signal and the second integrated signal; wherein the control circuit turns off the top bridge transistor or turns off the bottom bridge transistor when the full-wave rectified signal exceeds the second integrated signal. The control circuit turns off the top bridge transistor when the top bridge transistor is turned on and the full-wave rectified signal falls to not exceed the second integrated signal.

8. The power conversion circuit of claim 7, wherein, ​ wherein the control circuit turns off the upper bridge transistor when the upper bridge transistor is turned on and the first integral signal falls to not more than the upper threshold voltage.

9. The power conversion circuit of claim 1, wherein, The control circuit further comprises: a first error amplifier comparing the second integral signal with a reference voltage to generate an upper threshold voltage; a second error amplifier comparing the reference voltage with the second integral signal to generate a lower threshold voltage; a first comparator comparing the first integral signal with the upper threshold voltage to disable the upper bridge drive signal; and a second comparator comparing the first integral signal with the lower threshold voltage to disable the lower bridge drive signal; wherein the first comparator disables the upper bridge drive signal when the upper bridge transistor is turned on and the first integral signal exceeds the upper threshold voltage; wherein the second comparator disables the lower bridge drive signal when the lower bridge transistor is turned on and the lower threshold voltage exceeds the first integral signal.

10. The power conversion circuit of claim 9, wherein, The control circuit turns off the upper bridge transistor when the upper bridge transistor is turned on and the first integral signal falls to not more than the upper threshold voltage. The control circuit turns off the lower bridge transistor when the lower bridge transistor is turned on and the first integral signal rises to exceed the lower threshold voltage.

11. The power conversion circuit of claim 1, wherein, The control circuit controls the first integral signal to track the second integral signal, thereby controlling the power conversion circuit to receive an input power from the output voltage and to generate an output power of the output voltage.

12. The power conversion circuit of claim 1, wherein, The turn-on time of the upper bridge transistor is equal to the turn-on time of the lower bridge transistor.

13. The power conversion circuit of claim 1, wherein, Further comprising: a rectifier circuit coupled to the secondary coil; wherein the rectifier circuit is used to convert the energy of the secondary coil to the output voltage.

14. A power conversion circuit, characterized by To convert an input voltage to an output voltage, comprising: a transformer comprising a primary coil and a secondary coil, wherein the primary coil is coupled between a switching node and a resonance node; a resonance capacitor coupled between the resonance node and a ground terminal; an upper bridge transistor providing the input voltage to the switching node based on an upper bridge drive signal; a lower bridge transistor coupling the switching node to the ground terminal based on a lower bridge drive signal; a voltage detection circuit detecting the voltage across the resonance capacitor to generate a voltage detection signal; a feedback circuit generating a feedback signal based on the output voltage; and a control circuit generating an integral signal by integrating the feedback signal, and generating an added signal by adding a slope compensation signal to the voltage detection signal; wherein the control circuit further compares the integral signal and the added signal to generate the upper bridge drive signal and the lower bridge drive signal.

15. The power conversion circuit of claim 14, wherein, The slope compensation signal is the result of integrating a sawtooth wave with respect to time.

16. The power conversion circuit of claim 14, wherein, The slope compensation signal is a parabolic wave.

17. The power conversion circuit of claim 14, wherein, The integral signal is the product of the feedback signal and a turn-on time; wherein the turn-on time is any one of the turn-on time of the upper bridge transistor, the turn-on time of the lower bridge transistor, and a switching period. The upper bridge drive signal and the lower bridge drive signal have the switching period.

18. The power conversion circuit of claim 17, wherein, When the upper bridge transistor is turned on, the integral signal is a product of the feedback signal and an on-time of a previous on-period of the upper bridge transistor; When the lower bridge transistor is turned on, the integral signal is a product of the feedback signal and an on-time of a previous on-period of the lower bridge transistor.

19. The power conversion circuit of claim 17, wherein, When the upper bridge transistor or the lower bridge transistor is turned on, the integral signal is a product of the feedback signal and the switching period.

20. The power conversion circuit of claim 14, wherein, The control circuit further comprises: a superimposition circuit superimposes the voltage detection signal and the slope compensation signal to generate the superimposed signal; When the upper bridge transistor is turned on, the superimposition circuit adds the voltage detection signal and the slope compensation signal to generate the superimposed signal; When the lower bridge transistor is turned on, the superimposition circuit subtracts the voltage detection signal and the slope compensation signal to generate the superimposed signal.

21. The power conversion circuit of claim 14, wherein, The voltage detection circuit comprises: a voltage dividing circuit divides a voltage across the resonant capacitor to generate the voltage detection signal.

22. The power conversion circuit of claim 14, wherein, The control circuit further comprises: a full-wave rectification device full-wave rectifies the superimposed signal to generate a full-wave rectified signal; and a comparator compares the full-wave rectified signal and the integral signal; When the full-wave rectified signal exceeds the integral signal, the control circuit turns off the upper bridge transistor or turns off the lower bridge transistor.

23. The power conversion circuit of claim 22, wherein, When the upper bridge transistor is turned on and the superimposed signal drops to not exceed the integral signal, the control circuit turns off the upper bridge transistor; When the lower bridge transistor is turned on and the superimposed signal rises to exceed the integral signal, the control circuit turns off the lower bridge transistor.

24. The power conversion circuit of claim 14, wherein, The control circuit further comprises: a first error amplifier compares the integral signal and a reference voltage to generate an upper threshold voltage; a second error amplifier compares the reference voltage and the integral signal to generate a lower threshold voltage; a first comparator compares the superimposed signal and the upper threshold voltage to disable the upper bridge drive signal; and a second comparator compares the superimposed signal and the lower threshold voltage to disable the lower bridge drive signal; When the upper bridge transistor is turned on and the superimposed signal exceeds the upper threshold voltage, the first comparator disables the upper bridge drive signal; When the lower bridge transistor is turned on and the lower threshold voltage exceeds the superimposed signal, the second comparator disables the lower bridge drive signal.

25. The power conversion circuit of claim 24, wherein, When the upper bridge transistor is turned on and the superimposed signal drops to not exceed the upper threshold voltage, the control circuit turns off the upper bridge transistor; When the lower bridge transistor is turned on and the superimposed signal rises to exceed the lower threshold voltage, the control circuit turns off the lower bridge transistor.

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