Control circuit of motor

Abstract

The invention provides a control circuit of a motor. The control circuit comprises a sampling circuit and a sampling control circuit. The sampling circuit comprises a signal gating circuit. The signal gating circuit comprises a plurality of phase current acquisition ports and a bus current acquisition port. The plurality of phase current acquisition ports are correspondingly connected with multi-phase coils of the motor and are respectively used for acquiring phase currents of the coils connected with the phase current acquisition ports. The bus current acquisition port is connected with a bus of the motor and is used for acquiring bus current of the motor. And the sampling control circuit is connected with the sampling circuit and is used for controlling the signal gating circuit to sequentially gate the multi-phase current and the bus current in a time-sharing manner and sampling a target signal which is output by the sampling circuit and corresponds to the current gated current. According to the invention, the size and cost of the circuit can be reduced, the complexity of control operation is reduced, and the efficiency and stability of the control circuit are improved.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of motor control, in particular to a motor control circuit. BACKGROUND

[0002] In the inductive FOC control system of the motor, current sampling is a very important part in the feedback link. The current sampling includes phase current sampling and bus current sampling. For motor current sampling, there are usually three methods: single-resistor sampling, double-resistor sampling, and triple-resistor sampling. The cost, algorithm complexity, and final running effect of the above three methods are different.

[0003] Single-resistor sampling adopts bus current collection, which only needs to detect a resistor and an operational amplifier, and saves one to two sampling channels compared with double / triple-resistor sampling technology, which can reduce the cost and size of the motor controller. However, the control algorithm is complex and difficult to process. Especially when the motor is at low speed, the jitter is very obvious and not easy to control.

[0004] Double / triple-resistor sampling has balanced PWM output and sufficient time for sampling, and performs well in the low-speed process of the motor and has little vibration. In addition, it is also superior to the single-resistor scheme in terms of brake control. However, it requires more circuit modules, and the MCU needs to integrate multiple analog IPs, which makes the entire chip area large and the design cost high. Especially for a multi-motor system, as the number of controlled motors increases, the scale of the sampling and amplification circuit also increases exponentially, and the entire control system occupies too many hardware resources. Since the driving analog circuit requires a relatively large current, the expansion of the analog circuit scale leads to high power consumption of the entire circuit, complex peripheral sampling circuit, and increased system cost. SUMMARY

[0005] The present application provides a motor control circuit, which can reduce the size and cost of the circuit, reduce the complexity of control operation, and improve the efficiency and stability of the control circuit.

[0006] The present application provides a motor control circuit, which comprises:

[0007] a sampling circuit and a sampling control circuit;

[0008] The sampling circuit comprises a signal gating circuit, which comprises a plurality of phase current collection ports and a bus current collection port. The plurality of phase current collection ports are connected to the multi-phase coils of the motor respectively for collecting the phase currents of the connected coils. The bus current collection port is connected to the bus of the motor for collecting the bus current of the motor.

[0009] The sampling control circuit is connected with the sampling circuit, and is configured to control the signal gating circuit to sequentially and time-divisionally gate the multiphase phase currents and the bus current, and sample the target signal corresponding to the current currently gated and output by the sampling circuit.

[0010] Optionally, the control circuit further comprises an overcurrent detection circuit and a motor engine control circuit, an input end of the overcurrent detection circuit is connected with the sampling circuit, and an output end of the overcurrent detection circuit is connected with the motor engine control circuit; the overcurrent detection circuit is configured to output a signal representing a comparison result of the bus current and a reference signal according to the bus current and the reference signal; and the motor engine control circuit is connected with the motor, and is configured to judge whether the bus current is overcurrent according to the signal output by the overcurrent detection circuit, and control the motor.

[0011] Optionally, the overcurrent detection circuit comprises a comparison circuit, the comparison circuit comprises a first comparison input end and a second comparison input end, the first comparison input end is connected with the sampling circuit, the second comparison input end is configured to receive the reference signal, and an output end of the comparison circuit is connected with the motor engine control circuit; the comparison circuit is configured to compare the reference signal and a voltage signal corresponding to the bus current, and output a comparison result signal.

[0012] Optionally, the overcurrent detection circuit further comprises a filter circuit, the filter circuit is connected between the output end of the comparison circuit and the motor engine control circuit, and is configured to filter the comparison result signal and output a filtering result signal to the motor engine control circuit; and the motor engine control circuit is configured to judge whether the bus current is overcurrent according to the filtering result signal.

[0013] Optionally, the sampling circuit comprises a signal processing circuit, the signal processing circuit is connected between the signal gating circuit and the sampling control circuit, and is configured to process the signal output by the signal gating circuit and output the target signal; the first comparison input end is connected with an output end of the signal processing circuit, and the comparison circuit is configured to compare the reference signal and the target signal.

[0014] The filter circuit is configured to filter and shape the comparison result signal and count when the bus current is gated, and suspend filtering and shaping and counting when the phase current is gated.

[0015] Optionally, the sampling control circuit is connected with the filter circuit, and is configured to: send an enable valid signal to the filter circuit when the bus current is gated, and send an enable invalid signal to the filter circuit when the phase currents are gated; and the filter circuit is configured to: perform filtering and shaping and counting on the comparison result signal in response to the enable valid signal, and pause filtering and shaping and counting in response to the enable invalid signal.

[0016] Optionally, the first comparison input end is connected with the bus current collection port, and the sampling control circuit is configured to: send an enable valid signal to the filter circuit; and the filter circuit is configured to: perform filtering and shaping and counting on the comparison result signal in response to the enable valid signal.

[0017] Optionally, the motor engine control circuit is configured to: determine that the bus current is overcurrent when a continuous time length of a signal output by the overcurrent detection circuit and representing overcurrent of the bus current reaches a preset overcurrent protection time length of the motor.

[0018] Optionally, the control circuit comprises a switching switch, the switching switch connects the input end of the overcurrent detection circuit to the output end of the sampling circuit and the bus current collection port; the switching switch comprises a first state and a second state, when the switching switch is in the first state, the input end of the overcurrent detection circuit and the output end of the sampling circuit are connected, when the switching switch is in the second state, the input end of the overcurrent detection circuit and the bus current collection port are connected; and the switching switch is configured to switch states according to an externally input signal.

[0019] Optionally, the motor engine control circuit is connected with the sampling control circuit, and is configured to: send a sampling trigger signal to the sampling control circuit when all phases of the motor are turned on; and the sampling control circuit is configured to: control the signal gating circuit to sequentially and discretely gate the phase currents and the bus current of the motor in response to the sampling trigger signal.

[0020] Optionally, the control circuit comprises a plurality of motor engine control circuits and a plurality of sampling circuits, the plurality of motor engine control circuits are connected with the plurality of motors one by one in a one-to-one correspondence, and the plurality of sampling circuits are connected with the plurality of motors one by one in a one-to-one correspondence; the plurality of motor engine control circuits and the plurality of sampling circuits are connected with the sampling control circuit, the plurality of motor engine control circuits are configured to control the plurality of motors to work sequentially, and when all phases of the motor that is working are turned on, the motor engine control circuit connected with the motor sends the sampling trigger signal to the sampling control circuit, and the sampling control circuit is configured to control the signal gating circuit of the sampling circuit connected with the motor.

[0021] Optionally, the control circuit comprises a plurality of phase sampling resistors for collecting a plurality of phase currents, and a bus sampling resistor for collecting a bus current, the plurality of phase sampling resistors are connected to a plurality of phase windings of the motor correspondingly, and the bus sampling resistor is connected to a bus of the motor, a plurality of phase current collection ports are connected to the plurality of phase sampling resistors correspondingly, and the bus current collection port is connected to the bus sampling resistor.

[0022] In some embodiments, the sampling circuit comprises a signal gating circuit, the signal gating circuit comprises a plurality of phase current collection ports and a bus current collection port, the plurality of phase current collection ports are connected to a plurality of phase windings of the motor correspondingly, and are respectively used for collecting phase currents of the windings connected thereto, and the bus current collection port is connected to a bus of the motor, and is used for collecting a bus current of the motor; a sampling control circuit is connected to the sampling circuit, and is used for controlling the signal gating circuit to sequentially and time-divisionally gate the plurality of phase currents and the bus current, and sampling a target signal corresponding to the current currently gated and output by the sampling circuit; in this way, the plurality of phase currents and the bus current are collected by time-division multiplexing of the sampling circuit and the sampling control circuit, which can reduce the size and cost of the circuit; the sampling control circuit directly samples the target signal corresponding to the current currently gated, which reduces the amount of calculation, reduces the complexity of control calculation, and improves the efficiency and stability of the control circuit.

[0023] It should be understood that the foregoing general description and the following detailed description are only exemplary and explanatory, and cannot limit the present application. BRIEF DESCRIPTION OF DRAWINGS

[0024] The accompanying drawings, which are incorporated into and form part of the specification, illustrate embodiments consistent with the present application and, together with the description, serve to explain the principles of the application.

[0025] Figure 1 A circuit diagram of one embodiment of a control circuit of a motor of the present application is shown.

[0026] Figure 2 A partial circuit diagram of another embodiment of the control circuit is shown. Figure 1 A partial circuit diagram of another embodiment of the control circuit is shown.

[0027] Figure 3 A partial circuit diagram of another embodiment of the control circuit is shown. Figure 2 A waveform diagram of a bus voltage signal of the motor and an output signal of the sampling circuit is shown.

[0028] Figure 4 A waveform diagram of a bus voltage signal of the motor and a comparison result signal, an enable signal, and a filtering result signal is shown. Figure 2 A waveform diagram of a bus voltage signal of the motor and a comparison result signal, an enable signal, and a filtering result signal is shown.

[0029] Figure 5 A waveform diagram of a bus voltage signal of the motor and a comparison result signal, an enable signal, and a filtering result signal is shown. Figure 1Part circuit diagram of another embodiment of the control circuit shown.

[0030] Figure 6 Corresponding to the circuit diagram shown Figure 5 Waveform diagram of the voltage signal corresponding to the bus current, comparison result signal, filtering result signal corresponding to the circuit diagram shown.

[0031] Figure 7 Waveform diagram of the sampling trigger signal, the gate signal and the enable signal shown. DETAILED DESCRIPTION

[0032] The present application provides a control circuit of a motor. The control circuit of the motor of the present application is described in detail below in conjunction with the accompanying drawings. The features in the following embodiments and implementation manners can be combined with each other without conflict.

[0033] Figure 1 The circuit diagram of one embodiment of the control circuit 10 of the motor of the present application is shown. As Figure 1 The control circuit 10 of the motor includes a sampling circuit 11 and a sampling control circuit 12, as shown.

[0034] The sampling circuit 11 includes a signal gating circuit MUX. The signal gating circuit MUX includes a plurality of phase current collection ports VP1-VP3 and VN1-VN3 and bus current collection ports VP0 and VN0. The plurality of phase current collection ports VP1-VP3 and VN1-VN3 are connected to the multi-phase coils of the motor in correspondence, and are respectively used to collect the phase currents of the coils connected thereto. The bus current collection ports VP0 and VN0 are connected to the bus of the motor, and are used to collect the bus current of the motor.

[0035] The sampling control circuit 12 is connected to the sampling circuit 11, and is used to control the signal gating circuit MUX to sequentially and time-sharingly gate the multi-phase phase currents and the bus current, and sample the target signal output by the sampling circuit 11 corresponding to the current being gated at present.

[0036] The signal gating circuit MUX includes a data selector. The input end of the signal gating circuit MUX includes a plurality of ports, which are respectively used to collect the multi-phase phase currents and the bus current of the motor. The common intersection points in the plurality of phase current collection ports VP1-VP3 and VN1-VN3 and the bus current collection ports VP0 and VN0 are VN0-VN3.

[0037] The sampling control circuit 12 sends a selection signal SMUX_PGA0 to the sampling circuit 11. Specifically, the sampling control circuit 12 sends the selection signal SMUX_PGA0 to the signal selection circuit MUX. The selection signal SMUX_PGA0 includes signals that select the multiphase phase current and the bus current in turn. The signal selection circuit MUX selects the corresponding current according to the selection signal SMUX_PGA0 and outputs a target signal corresponding to the current. For example, if the selection signal indicates that the U-phase current is selected, the phase current collection ports VP1 and VN1 of the signal selection circuit MUX corresponding to the U-phase current are turned on, and the output end of the signal selection circuit MUX outputs a target signal corresponding to the U-phase current. The sampling control circuit 12 samples the target signal to complete the collection of the U-phase current of the motor.

[0038] The sampling control circuit 12 includes an ADC circuit. The ADC circuit includes a plurality of registers. In Figure 1 In the embodiment shown, the sampling result of the VP0 port is stored in the CH0 channel conversion result register. The sampling results of the VP1-VP3 three ports can be stored in any three ADC conversion result registers other than the CH0 channel, and the three channels can be configured by registers. In this way, the collection of the multiphase current and the bus current of the motor can be realized without complex control algorithm.

[0039] In some embodiments, the sampling circuit 11 and the sampling control circuit 12 can collect a plurality of phase currents and bus currents by time division multiplexing, which can reduce the size and cost of the circuit; the sampling control circuit 12 directly samples the target signal corresponding to the current being selected, which reduces the amount of calculation, reduces the complexity of control calculation, and improves the efficiency and stability of the control circuit 10.

[0040] Figure 2 The control circuit 10 shown is Figure 1 The partial circuit diagram of another embodiment of the control circuit 10 shown.

[0041] The control circuit 10 includes a plurality of phase sampling resistors R1 for collecting a plurality of phase currents, and a total sampling resistor R0 for collecting a bus current. The plurality of phase sampling resistors R1 are connected to the multiphase coils of the motor in correspondence. The total sampling resistor R0 is connected to the bus of the motor. The plurality of phase current collection ports VP1-VP3 and VN1-VN3 are connected to the plurality of phase sampling resistors R1 in correspondence. The bus current collection ports VP0 and VN0 are connected to the total sampling resistor R0.

[0042] Each phase coil of the motor is connected to a respective phase sampling resistor R1, and the coils of different phases are connected to different phase sampling resistors R1. For example, the U-phase coil is connected to the U-phase sampling resistor R1, the V-phase coil is connected to the V-phase sampling resistor R2, and the W-phase coil is connected to the W-phase sampling resistor R3. Figure 2Taking the three-phase motor shown as an example, phases U, V, and W are connected to three phase sampling resistors R1, which are then connected to phase current acquisition ports VP1-VP3 and VN1-VN3. The phase current acquisition ports VP1-VP3 and VN1-VN3 are connected to the two ends of the three phase sampling resistors R1.

[0043] The phase current acquisition ports VP1-VP3 and VN1-VN3, and the bus current acquisition ports VP0 and VN0 determine the corresponding phase current and bus current by detecting the voltage of the phase sampling resistor R1 and the total sampling resistor R0. For example, when the signal gating circuit MUX selects the U-phase current, the phase current acquisition ports VP1 and VN1 are turned on, detecting the voltage of the phase sampling resistor R1 connected to the U-phase coil. By dividing this voltage value by the resistance value of the phase sampling resistor R1, the current value flowing through the phase sampling resistor R1 is obtained, which is the U-phase current flowing through the U-phase coil.

[0044] exist Figure 2 In the embodiment shown, the bus current acquisition port VP0 is connected to the bias voltage source V. bias Provide bias voltage V to the bus current acquisition port VP0 bias Thus, the output signal of sampling circuit 11 is superimposed with the bias voltage V. bias This ensures that it will not output a negative phase voltage, facilitating subsequent calculations.

[0045] Figure 3 As shown Figure 2 The diagram shows the waveforms of the motor's bus voltage signal and the output signal of the sampling circuit 11.

[0046] Curve A represents the motor's bus voltage signal, and curve B represents the output signal of sampling circuit 11. Curve B is based on curve A with the bias voltage V superimposed on it. bias It also outputs inverted mode. The circled part C represents the overcurrent portion of the signal.

[0047] refer to Figure 1 The control circuit 10 also includes an overcurrent detection circuit 13 and a motor control circuit 14. The input of the overcurrent detection circuit 13 is connected to the sampling circuit 11, and the output of the overcurrent detection circuit 13 is connected to the motor control circuit 14. The overcurrent detection circuit 13 is used to output a signal indicating whether the bus current is overcurrent. The motor control circuit 14 is connected to the motor and is used to determine whether the bus current is overcurrent based on the signal output by the overcurrent detection circuit 13, and to control the motor accordingly.

[0048] The overcurrent detection circuit 13 is configured to monitor whether the bus current of the motor is overcurrent based on the signal of the bus current sampled by the sampling circuit 11, so as to prevent the motor from overcurrent and affect the normal operation of the motor. The overcurrent detection circuit 13 receives a reference signal for judging whether the bus current is overcurrent. The overcurrent detection circuit 13 outputs a signal representing the comparison result of the bus current and the reference signal to the motor engine control circuit 14 according to the bus current and the reference signal. The motor engine control circuit 14 judges whether the motor is overcurrent according to the signal, and takes corresponding control measures to control the motor. When the motor is not overcurrent and other abnormal conditions, the motor engine control circuit 14 is responsible for driving the motor according to the demand, and completes the conversion from the sine / cosine wave to the PWM wave through complex operation according to the three-phase comparison data, the three-phase comparison offset data and the phase change sequence, and finally converts and controls the three-phase six-way PWM output through the remapping module to realize the expected speed, torque or position control. If it is judged that the motor is overcurrent, measures such as immediately stopping the motor, reducing the load of the motor, adjusting the driving voltage or current of the motor, triggering the alarm device, etc. can be taken.

[0049] The overcurrent detection circuit 13 and the motor engine control circuit 14 jointly cooperate in the control circuit 10 to ensure that the motor operates in a safe and efficient state, and prevent damage or failure that may be caused by overcurrent.

[0050] The motor engine control circuit 14 is connected with the sampling control circuit 12, and is configured to send a sampling trigger signal Trig to the sampling control circuit 12 when all phases of the motor are turned on. The sampling control circuit 12 controls the signal gating circuit MUX to select the multi-phase phase current and the bus current in turn in time according to the sampling trigger signal.

[0051] The sampling trigger signal Trig is generated by the motor engine control circuit 14. In some embodiments, the motor engine control circuit 14 includes a carrier counter. When the carrier counter is at the zero point or the top point of the count, it indicates that the current of each phase of the motor is turned on. At this time, the motor engine control circuit 14 generates the sampling trigger signal Trig and sends it to the sampling control circuit 12. The sampling control circuit 12 generates a selection signal SMUX_PGA0 in response to the sampling trigger signal Trig. Taking a three-phase motor as an example, the sampling control circuit 12 generates the selection signals 11->10->01->00 in turn to poll once the sampling of the three-phase currents I u , v , w and the bus current I bus .

[0052] In some embodiments, the control circuit 10 comprises a plurality of motor engine control circuits 14 and a plurality of sampling circuits 11. The plurality of motor engine control circuits 14 are connected to the plurality of motors one by one respectively. The plurality of sampling circuits 11 are connected to the plurality of motors one by one respectively. The plurality of motor engine control circuits 14 and the plurality of sampling circuits 11 are connected to the sampling control circuit 12. The plurality of motor engine control circuits 14 are configured to control the plurality of motors to work in sequence, and when all phases of the working motor are turned on, the motor engine control circuit 14 connected to the motor sends a sampling trigger signal to the sampling control circuit 12. The sampling control circuit 12 is configured to control the signal gating circuit MUX of the sampling circuit 11 connected to the motor.

[0053] The plurality of motor engine control circuits 14 are configured to control the plurality of motors respectively. The plurality of sampling circuits 11 are configured to sample the phase current and bus current of the plurality of motors respectively. The plurality of motors work in sequence and are started in phase opposition. When all phases of the working motor are turned on, the motor engine control circuit 14 connected to the motor generates a sampling trigger signal Trig. The sampling control circuit 12 controls the signal gating circuit MUX of the sampling circuit 11 connected to the motor in response to the sampling trigger signal Trig, and selects the phase current and bus current of the motor in sequence and in time. The sampling control circuit 12 samples the phase current and bus current of the motor. In this way, the sampling control circuit 12 is shared by the plurality of motors, and is used for sampling the phase current and bus current of the plurality of motors, thereby reducing the size and cost of the circuit.

[0054] The control circuit 10 further comprises a plurality of overcurrent detection circuits 13. The input ends of the plurality of overcurrent detection circuits 13 are connected to the plurality of sampling circuits 11 one by one respectively, and the output ends of the plurality of overcurrent detection circuits 13 are connected to the plurality of motor engine control circuits 14 one by one respectively. The overcurrent detection circuit 13 outputs a signal indicating whether the bus current of the motor is overcurrent to the corresponding motor engine control circuit 14. The motor engine control circuit 14 determines whether the corresponding motor is overcurrent according to the signal, and takes corresponding control measures to control the motor. In this way, the plurality of overcurrent detection circuits 13 and the plurality of motor engine control circuits 14 can cooperate to detect whether the plurality of motors are overcurrent and control the plurality of motors.

[0055] The overcurrent detection circuit 13 comprises a comparison circuit CMP. The comparison circuit CMP comprises a first comparison input end and a second comparison input end. The first comparison input end is connected to the sampling circuit 11, and the second comparison input end is configured to receive a reference signal. The output end of the comparison circuit CMP is connected to the motor engine control circuit 14. The comparison circuit CMP is configured to compare the reference signal and the voltage signal corresponding to the bus current, and output a comparison result signal.

[0056] In Figure 1In the shown embodiment, the first comparison input is connected to the voltage signal corresponding to the sampled current of the sampling circuit 11, and the second comparison input is connected to a reference voltage V1, which represents the voltage corresponding to the maximum current allowed to pass through the motor. The comparison circuit CMP compares the two signals and outputs a comparison result signal CMP_OUT. In some embodiments, the sampling circuit 11 is connected in an inverting manner, and when the voltage signal corresponding to the sampled current of the sampling circuit 11 is within the normal range, the comparison circuit CMP outputs a high level, and when the voltage signal corresponding to the sampled current of the sampling circuit 11 indicates an overcurrent, the comparison circuit CMP outputs a low level. In order to facilitate subsequent signal processing, the control circuit 10 further includes a first inverter 15, and the comparison result signal CMP_OUT is the inversion of the signal output by the comparison circuit CMP. That is, when an overcurrent occurs, the comparison result signal CMP_OUT is a positive pulse signal.

[0057] The overcurrent detection circuit 13 further includes a filter circuit FILTER. The filter circuit FILTER is connected between the output of the comparison circuit CMP and the motor engine control circuit 14, and is used to filter the comparison result signal CMP_OUT and output a filtered result signal OVI to the motor engine control circuit 14. The motor engine control circuit 14 is used to determine whether the bus current is overcurrent according to the filtered result signal OVI.

[0058] Since the sampling circuit 11 is time-multiplexed, the currents of each phase of the motor and the bus current can be selected. Therefore, the signals input to the comparison circuit CMP include signals corresponding to the currents of each phase of the motor and the bus current. When detecting the overcurrent of the motor, only the bus current of the motor needs to be detected, and therefore, the signals corresponding to the currents of each phase of the motor need to be filtered out. The filter circuit FILTER receives the comparison result signal CMP_OUT and an enable signal CMP_OK, and the enable signal CMP_OK is used to control whether the filter circuit FILTER performs filtering and shaping and counting.

[0059] The filter circuit FILTER is also used to smooth the comparison result signal CMP_OUT and remove fluctuations that may be caused by noise, electromagnetic interference or non-ideal characteristics of the circuit itself. The filtered signal is more stable and reliable, which is beneficial for the motor engine control circuit 14 to make accurate judgments.

[0060] The filtered result signal OVI includes information about whether the motor has an overcurrent. The motor engine control circuit 14 receives the filtered result signal OVI and performs overcurrent protection on the motor according to the signal.

[0061] The sampling circuit 11 comprises a signal processing circuit AMP. The signal processing circuit AMP is connected between the signal gating circuit MUX and the sampling control circuit 12, and is used to process the signal output by the signal gating circuit MUX, and output a target signal. The first comparison input is connected to the output of the signal processing circuit MUX, and the comparison circuit CMP is used to compare the reference signal and the target signal. The filter circuit FILTER is used to filter and shape the comparison result signal CMP_OUT when the bus current is gated, and to suspend filtering and counting when the phase current is gated.

[0062] In some embodiments, the signal processing circuit AMP comprises an operational amplifier, which is used to amplify the signal output by the signal gating circuit MUX, and output the target signal, so that the target signal is easy to be processed by the comparison circuit CMP. The filter circuit FILTER is used to filter the phase current signal input to the comparison circuit CMP.

[0063] In some embodiments, the sampling control circuit 12 is connected to the filter circuit FILTER, and is used to send an enable valid signal to the filter circuit FILTER when the bus current is gated, and to send an enable invalid signal to the filter circuit FILTER when the phase current is gated. The filter circuit FILTER is used to filter and shape the comparison result signal CMP_OUT and count in response to the enable valid signal, and to suspend filtering and counting in response to the enable invalid signal.

[0064] The enable valid signal and the enable invalid signal are realized by an enable signal CMP_OK. When CMP_OK is at a high level, it is the enable valid signal, and when CMP_OK is at a low level, it is the enable invalid signal.

[0065] Figure 4 The bus voltage signal of the motor is shown Figure 2 The waveform diagrams of the bus voltage signal of the motor, the comparison result signal CMP_OUT, the enable signal CMP_OK, and the filter result signal OVI are shown.

[0066] In the curve D, the part of the bus voltage signal represents the overcurrent of the motor. When the motor has overcurrent, the comparison result signal CMP_OUT outputs a high level. When CMP_OK is at a high level, the filter circuit FILTER filters and shapes and counts, and outputs the filter result signal OVI. When CMP_OK is at a low level, the filter circuit FILTER suspends filtering and counting, and the filter result signal OVI suspends changing, and will not change the waveform because CMP_OK is at a low level.

[0067] When the phase current is gated, the filter circuit FILTER suspends filtering and counting in response to the enable invalid signal, so that the filter result signal OVI can filter out the signal of the gated phase current, and only keep the signal of the gated bus current.

[0068] Figure 5 A partial circuit diagram of another embodiment of the control circuit 10 is shown. Figure 1 A partial circuit diagram of another embodiment of the control circuit 10 is shown.

[0069] Figure 6 A partial circuit diagram of another embodiment of the control circuit 10 is shown. Figure 5 A waveform diagram of the voltage signal corresponding to the bus current, the comparison result signal CMP_OUT, and the filtering result signal OVI corresponding to the circuit diagram is shown.

[0070] wherein V Bus_MAX is the voltage corresponding to the maximum bus current. Curve E The part pointed by the arrow The overcurrent portion of the bus current Figure 5 .

[0071] In Figure 5 In the embodiment shown, the first comparison input end is connected to the bus current collection port VN0. The sampling control circuit 12 is configured to send an enable valid signal to the filtering circuit FILTER. The filtering circuit FILTER is configured to filter and shape the comparison result signal CMP_OUT and count in response to the enable valid signal.

[0072] The first comparison input end is directly connected to the bus current collection port VN0, and the voltage signal corresponding to the bus current is directly sent to the comparison circuit CMP. In this way, the signal when the phase current is gated will not enter the comparison circuit CMP. In this case, the enable signal CMP_OK is always at a high level, i.e., the enable valid signal. The filtering circuit FILTER filters and shapes the comparison result signal CMP_OUT and counts. When the bus current overflows, the comparison result signal CMP_OUT is at a high level, and since the enable signal CMP_OK is always at a high level, the filtering result signal OVI is also at a high level. When the bus current does not overflow, the comparison result signal CMP_OUT is at a low level, and the filtering result signal OVI is also at a low level.

[0073] The control circuit 10 includes a switching switch that connects the input end of the overcurrent detection circuit 13 to the output end of the sampling circuit 11 and the bus current collection port VN0. The switching switch includes a first state and a second state. When the switching switch is in the first state, the input end of the overcurrent detection circuit 13 and the output end of the sampling circuit 11 are connected, and when the switching switch is in the second state, the input end of the overcurrent detection circuit 13 and the bus current collection port VN0 are connected. The switching switch is configured to switch states according to an externally input signal.

[0074] The switch switch makes the input end of the overcurrent detection circuit 13 can select the output end of the sampling circuit 11 or the bus current collection port VN0. The switch switch switches the state according to the externally input signal. The externally input signal can be determined by the user according to the actual use scene of the motor.

[0075] When the switch switch is in the first state, the corresponding connection mode is suitable for the case where the overcurrent pulse current is 1-2 times the maximum sampling current. When the switch switch is in the second state, the corresponding connection mode is suitable for the case where the overcurrent narrow pulse needs to protect the motor. The overcurrent pulse can usually reach 3-5 times the maximum sampling current, and when the short-time overcurrent phenomenon such as series tube occurs, the instantaneous voltage on the motor bus is too high. Through the connection mode as shown in Figure 1 , the overcurrent phenomenon can be quickly captured, and the overcurrent protection is triggered in time.

[0076] In the embodiment as shown in Figure 7 , the switch switch includes a first switch K1, a second switch K2, and an inverter K3. When the first switch K1 is closed and the second switch K2 is opened, the switch switch is in the first state. When the first switch K1 is opened and the second switch K2 is closed, the switch switch is in the second state. The switch switch is controlled by the port CMP_CH_Sel. When the port CMP_CH_Sel outputs a high level, due to the action of the inverter K3, the first switch K1 receives a low level and the second switch K2 receives a high level, and the switch switch is in the second state. When the port CMP_CH_Sel outputs a low level, the switch switch is in the first state.

[0077] The motor engine control circuit 14 is configured to determine that the bus current overflows when the continuous time length of the signal output by the overcurrent detection circuit 13 and representing the bus current overflow reaches the overcurrent protection time length of the motor. The overcurrent protection time length is determined according to the set preliminary protection time length and the conversion error, and the conversion error is determined according to the total time length of the gated multiphase phase current in one gating period and the carrier frequency period for controlling the motor. The multiphase phase current and the bus current are gated once for one gating period.

[0078] Figure 7 The waveforms of the sampling trigger signal Trig, the gating signal SMUX_PGA, and the enable signal CMP_OK are shown in the following table.

[0079] Wherein, the sampling trigger signal Trig triggers one gating period each time. The gating signal SMUX_PGA polls the sampling of the multiphase phase current and the bus current from 11->10->01->00. Due to the time-sharing multiplexing of the sampling circuit 11, the enable signal CMP_OK is low when the phase current is gated, and the period of the gated phase current needs to be filtered out. In the embodiment as shown in ​ , 3*TADC T is the length of the gating phase current PWM T is a gating period. Conversion error e = (3*T ADC ) / T PWM .

[0080] In the control system of the motor, the carrier frequency is generally between 10KHz and 40KHz, so the motor control carrier frequency period is between 25us and 100us. The sampling control circuit 12 selects a 40M sampling frequency, and the single-channel sampling time is 20 clks, so T ADC is 500ns.

[0081] The preliminary protection time of the motor depends on the power size and working environment of the motor, and is generally about 2-10s. The preliminary protection time is set as t, and due to the existence of the conversion error e, the overcurrent protection time t' = t*(1-e). After the application scene of the motor is determined, the preliminary protection time and the conversion error can be determined. The overcurrent protection time is pre-set in the control logic of the motor engine control circuit 14, and the motor engine control circuit 14 controls the motor according to the overcurrent protection time during the operation of the motor.

Claims

1. A control circuit for an electric machine, characterized in that The control circuit comprises: a sampling circuit and a sampling control circuit; The sampling circuit comprises a signal gating circuit, the signal gating circuit comprises a plurality of phase current collection ports and a bus current collection port, the plurality of phase current collection ports are correspondingly connected with a plurality of phase windings of the motor, and are respectively used for collecting phase currents of the connected windings; the bus current collection port is connected with a bus of the motor, and is used for collecting a bus current of the motor; The sampling control circuit is connected with the sampling circuit, and is used for controlling the signal gating circuit to sequentially and time-divisionally gate the plurality of phase currents and the bus current, and sampling a target signal corresponding to the current currently gated and output by the sampling circuit.

2. The control circuit of an electric machine according to claim 1, characterized in that The control circuit further comprises an overcurrent detection circuit and a motor engine control circuit, an input end of the overcurrent detection circuit is connected with the sampling circuit, an output end of the overcurrent detection circuit is connected with the motor engine control circuit, the overcurrent detection circuit is used for: outputting a signal representing a comparison result of the bus current and a reference signal according to the bus current and the reference signal; the motor engine control circuit is connected with the motor, and is used for judging whether the bus current is overcurrent according to the signal output by the overcurrent detection circuit, and controlling the motor.

3. The control circuit of an electric machine according to claim 2, characterized in that, The overcurrent detection circuit comprises a comparison circuit, the comparison circuit comprises a first comparison input end and a second comparison input end, the first comparison input end is connected with the sampling circuit, the second comparison input end is used for receiving the reference signal, and an output end of the comparison circuit is connected with the motor engine control circuit; The comparison circuit is used for comparing the reference signal and a voltage signal corresponding to the bus current, and outputting a comparison result signal.

4. The control circuit of an electric machine according to claim 3, characterized in that, The overcurrent detection circuit further comprises a filtering circuit, the filtering circuit is connected between the output end of the comparison circuit and the motor engine control circuit, is used for filtering the comparison result signal and outputting a filtering result signal to the motor engine control circuit, and the motor engine control circuit is used for judging whether the bus current is overcurrent according to the filtering result signal.

5. The control circuit of an electric machine according to claim 4, characterized in that, The sampling circuit comprises a signal processing circuit, the signal processing circuit is connected between the signal gating circuit and the sampling control circuit, is used for processing a signal output by the signal gating circuit, and outputs the target signal; the first comparison input end is connected with an output end of the signal processing circuit, and the comparison circuit is used for comparing the reference signal and the target signal; The filtering circuit is used for: filtering and shaping the comparison result signal and counting when the bus current is gated, and suspending filtering and shaping and counting when the phase current is gated.

6. The control circuit of an electric machine according to claim 5, characterized in that, The sampling control circuit is connected with the filtering circuit, is used for: sending an enable valid signal to the filtering circuit when the bus current is gated, and sending an enable invalid signal to the filtering circuit when the phase current is gated, and the filtering circuit is used for: filtering and shaping the comparison result signal and counting in response to the enable valid signal, and suspending filtering and shaping and counting in response to the enable invalid signal.

7. The control circuit of an electric machine according to claim 4, characterized in that, The first comparison input is connected to the bus current collection port, and the sampling control circuit is configured to send an enable valid signal to the filter circuit; the filter circuit is configured to filter and shape the comparison result signal and count in response to the enable valid signal.

8. The control circuit of an electric machine according to claim 2, characterized in that, The motor engine control circuit is configured to determine that the bus current is overcurrent when a continuous time length of a signal output by the overcurrent detection circuit and representing overcurrent of the bus current reaches a preset overcurrent protection time length of the motor.

9. The control circuit of an electric machine according to claim 2, characterized in that, The control circuit includes a switching switch, which connects an input of the overcurrent detection circuit to an output of the sampling circuit and the bus current collection port; the switching switch includes a first state and a second state, and when the switching switch is in the first state, the input of the overcurrent detection circuit and the output of the sampling circuit are connected, and when the switching switch is in the second state, the input of the overcurrent detection circuit and the bus current collection port are connected; the switching switch is configured to switch states according to an externally input signal.

10. The control circuit of an electric machine according to claim 2, characterized in that, The motor engine control circuit is connected to the sampling control circuit, and is configured to send a sampling trigger signal to the sampling control circuit when all phases of the motor are conducting, and the sampling control circuit is configured to control the signal gating circuit to sequentially and time-divisionally gate the phase currents and the bus current of the motor in response to the sampling trigger signal.

11. The control circuit of an electric machine according to claim 10, characterized in that, The control circuit includes a plurality of motor engine control circuits and a plurality of sampling circuits, and the plurality of motor engine control circuits are respectively and one-to-one connected to the plurality of motors, and the plurality of sampling circuits are respectively and one-to-one connected to the plurality of motors; the plurality of motor engine control circuits and the plurality of sampling circuits are connected to the sampling control circuit, and the plurality of motor engine control circuits are configured to control the plurality of motors to work sequentially, and when all phases of the motor working are conducting, the motor engine control circuit connected to the motor sends the sampling trigger signal to the sampling control circuit, and the sampling control circuit is configured to control the signal gating circuit of the sampling circuit connected to the motor.

12. The control circuit of an electric machine according to claim 1, characterized in that, The control circuit includes a plurality of phase sampling resistors for collecting a plurality of phase currents and a total sampling resistor for collecting a bus current, the plurality of phase sampling resistors are connected to a plurality of phase coils of the motor in correspondence, the total sampling resistor is connected to a bus of the motor, a plurality of phase current collection ports are connected to the plurality of phase sampling resistors in correspondence, and the bus current collection port is connected to the total sampling resistor.

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