Bandwidth improvement method and circuit based on switch well capacitor
By connecting a high-voltage signal to the isolation terminal and increasing the reverse bias voltage of the deep N-well to ground PN junction, the bandwidth reduction problem caused by the well capacitance in CMOS switches is solved, and the signal bandwidth is improved.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-11-13
- Publication Date
- 2026-03-10
AI Technical Summary
In high-speed signal transmission, the large-area capacitance (well capacitance) formed by the isolation trap of CMOS switches leads to a decrease in bandwidth parameters, which is difficult to solve effectively with existing technologies.
By connecting a high-voltage signal to the isolation terminal, the reverse bias voltage of the deep N-well to ground PN junction is increased, and the well capacitance is reduced to improve the signal bandwidth.
It significantly improves the signal bandwidth of CMOS switches, reduces the impact of trap capacitance, and enhances the high-frequency performance of switches.
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Figure CN121643706A_ABST
Abstract
Description
TECHNICAL FIELD
[0001] The present application relates to the technical field of signal transmission and electronic switch, and particularly relates to a bandwidth improvement method and circuit based on switch well capacitance. BACKGROUND
[0002] In the field of high-speed signal transmission, integrated CMOS high-speed switches (such as T-type switches or series T-type switches) are widely used due to their advantages of low on-resistance and high isolation. Such switches generally use one or more sets of MOS complementary pairs to realize the bidirectional high-speed on-off function of signals.
[0003] To effectively suppress external noise interference, the MOS in the CMOS switch is integrated in an isolation well. The isolation well is composed of a deep N-well (DNW) and an N-type buried layer, and its design needs to completely wrap the MOS of the CMOS switch, which results in a large physical area of the isolation well. However, a large-area isolation well will form a large ground capacitance (i.e. well capacitance), which will be coupled to the input end of the switch, ultimately negatively affecting the bandwidth parameters of the CMOS switch. SUMMARY
[0004] The purpose of the embodiments of the present application is to provide a bandwidth improvement method and circuit based on switch well capacitance, which increases the reverse bias voltage of the deep N-well PN junction to the ground by connecting a high-voltage signal to the isolation end, thereby reducing the well capacitance to improve the signal bandwidth of the target CMOS switch.
[0005] The first aspect of the present application provides a bandwidth improvement method based on switch well capacitance, comprising: obtaining the highest withstand voltage value of the deep N-well of the MOS in the target CMOS; determining a high-voltage signal applied to the corresponding isolation end based on the highest withstand voltage value, wherein the high-voltage signal is used to generate a reverse bias voltage on the PN junction to the ground formed at the deep N-well; generating the high-voltage signal by using a high-voltage control module, and connecting the high-voltage signal to the isolation end, so as to improve the signal bandwidth of the target CMOS by reducing the well capacitance of the MOS.
[0006] Optionally, the high-voltage signal is equal to the highest withstand voltage value, or equal to the highest withstand voltage value minus a preset margin.
[0007] Optionally, the high-voltage control module is a boost charge pump integrated in the target CMOS, or an external high-voltage bias source.
[0008] Optionally, the connecting of the high-voltage signal to the isolation end comprises: In a specified working period of the MOS tube, the high-voltage signal is connected to the isolation end by using a direct current bias network; wherein the specified working period includes a working full period or a conduction period.
[0009] Optionally, the target CMOS is manufactured by a high-voltage process with a deep N-well resistant to high voltage.
[0010] Optionally, the high-voltage signal at least meets the requirement of a reverse bias voltage corresponding to a target signal bandwidth.
[0011] Optionally, the well capacitance is calculated by the following formula: ; wherein C j is the well capacitance; C j0 is a junction capacitance when the PN junction is zero biased; V bi is an intrinsic conduction voltage; V is the reverse bias voltage; and m is a constant.
[0012] The second aspect embodiment of the present application provides a bandwidth improvement circuit based on a switching well capacitance, comprising: a MOS tube in a target CMOS and a high-voltage control module. The high-voltage control module is configured to generate a high-voltage signal and transmit the high-voltage signal to a corresponding isolation end of the MOS tube, so as to increase the signal bandwidth of the target CMOS by reducing the well capacitance of the MOS tube; wherein the high-voltage signal is determined based on the maximum withstand voltage of the deep N-well of the MOS tube.
[0013] The third aspect embodiment of the present application provides a bandwidth improvement circuit based on a switching well capacitance, comprising: a MOS tube in a target CMOS, a high-voltage control module and a direct current bias network; wherein an input end of the direct current bias network is connected to an output end of the high-voltage control module, and an output end of the direct current bias network is connected to a corresponding isolation end of the MOS tube. The high-voltage control module is configured to generate a high-voltage signal and transmit the high-voltage signal to the input end of the direct current bias network; wherein the high-voltage signal is determined based on the maximum withstand voltage of the deep N-well of the MOS tube. The direct current bias network is configured to receive the high-voltage signal and connect the high-voltage signal to the isolation end, so as to increase the signal bandwidth of the target CMOS by reducing the well capacitance of the MOS tube.
[0014] Further, the high-voltage control module is a boost charge pump integrated in the target CMOS, or is an external high-voltage bias source.
[0015] Compared with the prior art, the embodiment of the present application provides a bandwidth improvement method and circuit based on switch well capacitance, which comprises the following steps: first, obtaining the highest withstand voltage value of the deep N well of the MOS tube in the target CMOS; then, determining the high voltage signal applied to the corresponding isolation end based on the highest withstand voltage value, the high voltage signal being used to generate a reverse bias voltage on the PN junction formed at the deep N well; finally, generating the high voltage signal by using a high voltage control module and connecting the high voltage signal to the isolation end, so as to improve the signal bandwidth of the target CMOS by reducing the well capacitance of the MOS tube. In summary, the present application increases the reverse bias voltage of the PN junction of the deep N well by connecting the high voltage signal to the isolation end, thereby reducing the well capacitance and improving the signal bandwidth of the switch of the target CMOS. BRIEF DESCRIPTION OF DRAWINGS
[0016] Figure 1 is a structural schematic diagram of an embodiment of a multi-channel T-type switch provided by the present application; Figure 2 is a sectional schematic diagram of a single MOS tube in a CMOS switch provided by the present application; Figure 3 is a flow schematic diagram of an embodiment of a bandwidth improvement method based on switch well capacitance provided by the present application; Figure 4 is a structural schematic diagram of an embodiment of a bandwidth improvement circuit based on switch well capacitance provided by the present application; Figure 5 is a structural schematic diagram of another embodiment of a bandwidth improvement circuit based on switch well capacitance provided by the present application. DETAILED DESCRIPTION
[0017] The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by a person of ordinary skill in the art without creative work fall within the protection scope of the present application.
[0018] CMOS is a circuit structure, and P-type MOS tubes and N-type MOS tubes are two basic elements constituting such a circuit structure. Referring to Figure 1 is a structural schematic diagram of an embodiment of a multi-channel T-type switch provided by the present application; wherein, GATE_A and GATE_B are control signals with opposite phases, M1, M2, M3 and M4 are MOS tubes; D0, D1, D2 and D3 are body diodes, which are used to enhance the switching characteristics of the corresponding MOS tubes. Figure 1 A single-pole double-throw implementation is shown as follows: When the GATE_A signal is high, M0 and M1 are turned on. At this time, terminals A and B1 are directly connected through the conduction path of M0 and M1, and the signal can be transmitted bidirectionally (A→B1 or B1→A). Correspondingly, M2 and M3 are turned off, and there is a high impedance between A and B2, so the signal cannot pass through.
[0019] When the GATE_B signal is low, M2 and M3 are turned on. At this time, terminals A and B2 are directly connected through the conduction path of M2 and M3, and the signal can be transmitted bidirectionally (A→B2 or B2→A). Correspondingly, M0 and M1 are turned off, and there is a high impedance between A and B1, so the signal cannot pass through.
[0020] In practical applications, to reduce interference, the MOSFETs in the aforementioned CMOS switches are integrated into an isolation well composed of a deep N-well and an N-type buried layer. This isolation well needs to completely enclose the MOSFETs of the CMOS switch, resulting in a large physical area for the isolation well itself, thus forming a large capacitance (well capacitance) between it and ground. The inventors discovered that this capacitance couples to the input terminals A or B (B1 / B2) of the switch, causing a significant degradation effect on the switch's bandwidth parameters.
[0021] like Figure 2 The diagram shows a cross-sectional view of a single MOS transistor in the CMOS switch provided by this invention; "G", "S", and "D" represent the gate, source, and drain of the MOS transistor, respectively; "Pwell" is a P-type well; "DNW" is a deep N-well; "Psub" is a P-type substrate; and "n+" is a heavily doped N-type region. Cn is the parasitic capacitance of the N-type active region of the MOS transistor, Cp is the parasitic capacitance of the P-substrate, and Cx is the well capacitance (parasitic capacitance to ground). Thus, the total parasitic capacitance of the input terminals A or B (B1 / B2) can be approximated as a series connection of Cn, Cp, and Cx, which directly limits the high-frequency bandwidth performance of the switch.
[0022] See Figure 3 This is a flowchart illustrating an embodiment of the bandwidth improvement method based on switched-sink capacitors provided by the present invention.
[0023] To address the aforementioned technical problems, a first aspect of the present invention provides a bandwidth improvement method based on a switched-sink capacitor, comprising steps S1 to S3, as detailed below: Step S1: Obtain the highest breakdown voltage of the deep N-well of the MOS transistor in the target CMOS; Step S2: Based on the highest withstand voltage value, determine the high voltage signal applied to the corresponding isolation terminal; wherein, the high voltage signal is used to generate a reverse bias voltage on the ground PN junction formed at the deep N-well; Step S3: Use the high-voltage control module to generate the high-voltage signal and connect the high-voltage signal to the isolation terminal to increase the signal bandwidth of the target CMOS by reducing the well capacitance of the MOS transistor.
[0024] Specifically, the inventors discovered that parasitic capacitance introduces a "capacitive load," which limits the rise / fall speed of the signal, thereby reducing the switching bandwidth. Further research revealed that the signal bandwidth of the switch can be increased by reducing the trap capacitance Cx.
[0025] Total parasitic capacitance at switch input (A or B) = Cp and Cn are the intrinsic capacitances of the MOSFET itself, determined by the device's width (W), length (L), and process parameters. These are "hard characteristics" and difficult to optimize through circuit design. Therefore, reducing the well capacitance Cx is the most effective way to reduce the total parasitic capacitance.
[0026] A deep N-well junction to ground is a large-area diode (PN junction to ground) operating under reverse bias. The capacitance of the PN junction to ground is determined by the reverse bias voltage, and its calculation formula is as follows: Among them, C j The junction capacitance of the diode under reverse bias (i.e., the well capacitance Cx); C j0 V is the junction capacitance of the PN junction when it is zero-biased to ground. bi V is the intrinsic turn-on voltage; V is the reverse bias voltage; m is a constant.
[0027] As can be seen from the above formula, the larger the reverse bias voltage |V|, the smaller the well capacitance Cx. For example... Figure 4 The diagram shown is a schematic of an embodiment of the bandwidth improvement circuit based on switch well capacitor provided by the present invention. The embodiment of the present invention introduces an additional high voltage control module (HV CTRL) to generate a high voltage signal, which is connected to the isolation terminal (i.e., ISO terminal) of the CMOS switch. This generates a large reverse bias voltage on the PN junction to ground formed in the deep N-well, reduces the well capacitance Cx, and thus improves the signal bandwidth.
[0028] like Figure 2 As shown, the deep N-well (DNW) and the surrounding P-type substrate (Psub, typically grounded) form a ground-to-ground PN junction. To put this ground-to-ground PN junction in a large reverse bias state, an ISO needs to be applied to the ISO terminal (deep N-well / Figure 4 The high voltage signal at the "NW terminal" is a large positive voltage.
[0029] The reverse bias voltage of the conventional CMOS switch is-5V, but the CMOS switch of the embodiment of the present application is manufactured by high-voltage process, and the amplitude of the high-voltage signal is usually up to 40V, 60V or even 100V. The theoretical calculation shows that when the reverse bias voltage is-10V, the capacitance of the well capacitor Cx is reduced by 50% compared with the-5V bias state; if the reverse bias voltage is increased to-100V, the capacitance can be further reduced to 23% of the original-5V state. The optimization of the well capacitor Cx achieved by adjusting the reverse bias voltage can significantly improve the signal bandwidth of the switch, and the cost is relatively small compared with the SOI (Silicon on Insulator) scheme.
[0030] In an optional embodiment, the high-voltage signal is equal to the maximum withstand voltage, or equal to the maximum withstand voltage minus a preset margin.
[0031] Further, the target CMOS is manufactured by high-voltage process with deep N-well withstand high voltage.
[0032] It should be noted that the CMOS high-speed switch of the embodiment of the present application usually adopts a single NMOS tube structure, and is manufactured by high-voltage process with deep N-well withstand high voltage, so as to improve the bandwidth. Unlike the conventional low-voltage process (the deep N-well withstand voltage of which may be only about 5V), the high-voltage CMOS process with specifications such as 20V or 100V is selected in the embodiment of the present application, which enables the deep N-well to withstand a reverse bias voltage much higher than the conventional working voltage (1.2V-5V) without breakdown damage.
[0033] As described above, the greater the |V| of the reverse bias voltage, the smaller the well capacitor Cx. In an ideal case, setting the |V| of the reverse bias voltage (high-voltage signal) directly to the maximum withstand voltage of the deep N-well in the MOS tube can minimize the well capacitor Cx under the process condition, thereby bringing the highest signal bandwidth to the CMOS switch. In actual chip design and manufacturing, in order to ensure the long-term reliability of the circuit, factors such as process fluctuation need to be considered. Therefore, a preset margin is usually introduced, and |V| is set to "the maximum withstand voltage minus the preset margin", which is a robust design, although it makes a slight sacrifice in absolute performance, but greatly improves the reliability and life of the CMOS switch.
[0034] For example, when the high-voltage process with a withstand voltage of 20V is adopted, the high-voltage signal should be preferably 20V (or 20V minus the margin, such as 18.5V); When the high-voltage process with a withstand voltage of 100V is adopted, the high-voltage signal should be preferably 100V (or 100V minus the margin, such as 98.5V).
[0035] In summary, the high-voltage signal (the |V| of the reverse bias voltage) in the embodiment of the present application is set to the limit withstand voltage (or close to the limit) of the high-voltage process.
[0036] In an optional embodiment, the high voltage signal at least meets the requirement of the reverse bias voltage corresponding to the target signal bandwidth.
[0037] It should be noted that if the CMOS switch needs to meet the target signal bandwidth in actual application, the maximum total parasitic capacitance allowed by the CMOS switch tube can be deduced reversely, then the maximum well capacitance Cx is deduced, and then the minimum high voltage signal required by the ISO end is determined. Of course, the actual applied high voltage signal is greater than or equal to the minimum high voltage signal; if the minimum high voltage signal is selected, a relatively low high voltage cost process can be used.
[0038] In an optional embodiment, the high voltage control module is a boost charge pump integrated in the target CMOS or an external high voltage bias source.
[0039] Further, the connecting the high voltage signal to the isolation end comprises: In the specified working period of the MOS tube, the high voltage signal is connected to the isolation end by using a direct current bias network; wherein the specified working period includes a working full period or a conduction period.
[0040] It should be noted that the high voltage control module (HV CTRL) in the embodiment of the application can be an external high voltage bias source (i.e. an external high voltage input), or can be an integrated boost charge pump. The integrated boost charge pump can be realized by a common circuit, and is directly integrated in the internal of the target CMOS high-speed switch chip, and is used to generate a high voltage signal of a specific range (such as 20V to 100V) required by the ISO end.
[0041] As shown in Figure 5 Fig. 2 is a structure schematic diagram of another embodiment of the bandwidth improvement circuit based on the switch well capacitance provided by the application. After the HV CTRL generates the high voltage signal, in the specified working period of the MOS tube, the high voltage signal is connected to the ISO end of the CMOS by using a direct current bias network; wherein the direct current bias network is used to ensure that the high voltage signal can be stably applied to the deep N well, and is also used to isolate the high frequency signal on the switch node from the HV CTRL.
[0042] When the specified working period is the working full period, the direct current bias network always connects the high voltage signal to the ISO end, regardless of whether the MOS tube is in the conduction state or the cut-off state, so that the ground PN junction is continuously in a large reverse bias state. When the specified working period is the conduction period, the direct current bias network only connects the high voltage signal to the isolation end in a specific time period when the MOS tube is in the conduction state, so that the high voltage signal can be supplied on demand according to the working time sequence of the MOS tube, which is beneficial to reduce the overall power consumption of the circuit system.
[0043] See Figure 4 A second aspect of the present invention provides a bandwidth improvement circuit based on a switched-well capacitor, comprising: a MOS transistor in a target CMOS and a high-voltage control module; The high-voltage control module is used to generate a high-voltage signal and transmit it to the isolation terminal corresponding to the MOS transistor, so as to improve the signal bandwidth of the target CMOS by reducing the well capacitance of the MOS transistor; wherein, the high-voltage signal is determined based on the highest withstand voltage value of the deep N-well of the MOS transistor.
[0044] See Figure 5 A third aspect of the present invention also provides a bandwidth improvement circuit based on a switched-well capacitor, comprising: a MOS transistor in a target CMOS, a high-voltage control module, and a DC bias network; wherein the input terminal of the DC bias network is connected to the output terminal of the high-voltage control module, and the output terminal of the DC bias network is connected to the isolation terminal corresponding to the MOS transistor; The high-voltage control module is used to generate a high-voltage signal and transmit it to the input terminal of the DC bias network; wherein, the high-voltage signal is determined based on the highest withstand voltage of the deep N-well of the MOS transistor; The DC bias network is used to receive the high-voltage signal and connect it to the isolation terminal, so as to improve the signal bandwidth of the target CMOS by reducing the well capacitance of the MOS transistor.
[0045] Furthermore, the high-voltage control module is either a boost charge pump integrated into the target CMOS or an external high-voltage bias source.
[0046] The above description is only a preferred embodiment of the present invention. It should be noted that for those skilled in the art, several improvements and modifications can be made without departing from the technical principles of the present invention, and these improvements and modifications should also be considered within the scope of protection of the present invention.
Claims
1. A bandwidth improvement method based on switched-well capacitance, characterized by, The application relates to a method for improving signal bandwidth of a target CMOS, comprising the following steps: obtaining the maximum withstand voltage value of a deep N-well of a MOS transistor in the target CMOS; determining a high-voltage signal applied to a corresponding isolated terminal based on the maximum withstand voltage value, wherein the high-voltage signal is used to generate a reverse bias voltage on a PN junction formed at the deep N-well; generating the high-voltage signal by using a high-voltage control module and inputting the high-voltage signal into the isolated terminal, so as to improve the signal bandwidth of the target CMOS by reducing the well capacitance of the MOS transistor.
2. The bandwidth improvement method based on switched-well capacitance as claimed in claim 1, wherein, The high-voltage signal is equal to the maximum withstand voltage value or is equal to the maximum withstand voltage value minus a preset margin.
3. The bandwidth improvement method based on switched-well capacitance as claimed in claim 1, wherein, The high-voltage control module is a boost charge pump integrated in the target CMOS or is an external high-voltage bias source.
4. The bandwidth improvement method based on switched-well capacitance as claimed in claim 1, wherein, The inputting of the high-voltage signal into the isolated terminal comprises: in a specified working period of the MOS transistor, inputting the high-voltage signal into the isolated terminal by using a direct current bias network; wherein the specified working period comprises a working full period or a conduction period.
5. The bandwidth improvement method based on switched-well capacitance as claimed in claim 1, wherein, The target CMOS is manufactured by a high-voltage process in which the deep N-well can withstand high voltage.
6. The bandwidth improvement method based on switched-well capacitance as claimed in claim 1, wherein, The high-voltage signal at least meets the demand of a reverse bias voltage corresponding to a target signal bandwidth.
7. The bandwidth improvement method based on switched-well capacitance as claimed in claim 1, wherein, The well capacitance is calculated by the following formula: ； where C j is the well capacitance; C j0 is the junction capacitance of the PN junction when zero biased to ground; V bi is the intrinsic on voltage; V is the reverse bias voltage; and m is a constant.
8. A bandwidth improvement circuit based on switched-well capacitance, characterized by The application relates to a method for improving signal bandwidth of a target CMOS, comprising the following steps: a MOS transistor and a high-voltage control module in the target CMOS; the high-voltage control module is used for generating a high-voltage signal and transmitting the high-voltage signal to a corresponding isolated terminal of the MOS transistor, so as to improve the signal bandwidth of the target CMOS by reducing the well capacitance of the MOS transistor; wherein the high-voltage signal is determined based on the maximum withstand voltage value of a deep N-well of the MOS transistor.
9. A bandwidth improvement circuit based on switched-well capacitance, characterized by The application relates to a method for improving signal bandwidth of a target CMOS, comprising the following steps: a MOS transistor, a high-voltage control module and a direct current bias network in the target CMOS; wherein an input end of the direct current bias network is connected with an output end of the high-voltage control module, and an output end of the direct current bias network is connected with a corresponding isolated terminal of the MOS transistor; the high-voltage control module is used for generating a high-voltage signal and transmitting the high-voltage signal to the input end of the direct current bias network; wherein the high-voltage signal is determined based on the maximum withstand voltage value of a deep N-well of the MOS transistor; the direct current bias network is used for receiving the high-voltage signal and inputting the high-voltage signal into the isolated terminal, so as to improve the signal bandwidth of the target CMOS by reducing the well capacitance of the MOS transistor.
10. The bandwidth improvement circuit based on switched-well capacitance of claim 8 or 9, wherein, The high-voltage control module is a boost charge pump integrated in the target CMOS or is an external high-voltage bias source.