Compensation method of interleaved analog-to-digital converter and interleaved analog-to-digital converter

Abstract

The invention discloses a compensation method of an interleaved analog-to-digital converter and the interleaved analog-to-digital converter, the interleaved analog-to-digital converter comprises a plurality of sub-channels, and the compensation method comprises the following steps: for a sub-channel as an interference source, when sampling phase overlapping exists between the sub-channel as the interference source and other sub-channels as interfered objects, the sub-channel as the interference source and the other sub-channels as the interfered objects; generating a compensation charge based on a previous conversion result of the sub-channel as an interference source; wherein the compensation charges and interference charges generated by the sub-channel serving as the interference source to other sub-channels serving as interfered objects are opposite in polarity and the same in amplitude; and controlling the compensation circuit to be synchronously opened with the corresponding sub-channel serving as the interference source, and releasing compensation charges to counteract the influence of the interference charges on other sub-channels serving as interfered objects. According to the invention, errors caused by charge transfer due to overlapping of sampling phases between channels can be corrected, so that the conversion precision of the interleaved analog-to-digital converter is improved.

Description

TECHNICAL FIELD

[0001] The present application relates to the chip technical field, and especially a compensation method of interleaved analog-to-digital converter and interleaved analog-to-digital converter. BACKGROUND

[0002] An interleaved analog-to-digital converter (ADC) achieves high sampling rate by multiple sub-channels alternately sampling. Figure 1 is a sampling timing diagram of an interleaved ADC provided by an embodiment of the present application. Figure 1 As shown, a common sub-channel uses a sample-and-hold circuit with a switched-capacitor element, such as a successive approximation register (SAR) ADC or a pipelined ADC, which both need two working states, a sample state and a hold state. In the sample state, due to a fixed phase difference of the sampling clock of each sub-channel, the sampling windows of adjacent channels overlap in time (see the overlap time t in Figure 1 ).

[0003] During this sampling phase overlap, the sampling switches of multiple sub-channels (such as ADC0, ADC1, …, ADCn) are simultaneously turned on, and the front-end capacitor arrays of the sub-channels are connected together through a line. The charge on a capacitor element of a sub-channel will be transferred to another sub-channel through a common node, thereby causing mutual interference between channels. If the driving capability is insufficient, this charge transfer process will not be completed before the sampling ends, and the residual charge will directly affect the conversion result. The amount of charge transfer is related to the configuration state (i.e., the historical conversion data) of the capacitor element array of the interference source channel, so that the interference presents complex nonlinear characteristics.

[0004] However, the common calibration schemes in the prior art are mostly focused on correcting the linear mismatch between channels, such as offset, gain error, or clock skew. For the nonlinear inter-channel interference caused by the sampling phase overlap and the dynamic configuration of the interference source channel, these traditional methods are difficult to effectively compensate. SUMMARY

[0005] The present application provides a compensation method of interleaved analog-to-digital converter and interleaved analog-to-digital converter, which can correct the error caused by the charge transfer caused by the sampling phase overlap between channels, thereby improving the conversion accuracy of the interleaved analog-to-digital converter.

[0006] In a first aspect, an embodiment of the present application provides a compensation method for an interleaved analog-to-digital converter, the interleaved analog-to-digital converter comprising a plurality of sub-channels, the compensation method comprising: for a sub-channel as an interference source, when there is a sampling phase overlap with other sub-channels as interference objects, generating compensation charges based on a previous conversion result of the sub-channel as the interference source; wherein the compensation charges are opposite in polarity and identical in amplitude to interference charges generated by the sub-channel as the interference source on the other sub-channels as the interference objects; and controlling a compensation circuit to be synchronously turned on with the corresponding sub-channel as the interference source to release the compensation charges to offset the influence of the interference charges on the other sub-channels as the interference objects.

[0007] Optionally, the step of generating the compensation charges based on the previous conversion result of the sub-channel as the interference source comprises: obtaining the previous conversion result of the sub-channel as the interference source; and calculating a compensation control signal for controlling the compensation circuit based on the previous conversion result, so that the compensation circuit generates the compensation charges according to the compensation control signal.

[0008] Optionally, the step of controlling the compensation circuit to be synchronously turned on with the corresponding sub-channel as the interference source comprises: generating a switch control signal synchronized with a sampling clock of the corresponding sub-channel as the interference source; and driving a switch of the compensation circuit with the switch control signal, so that the switch is turned on during a sampling phase of the sub-channel as the interference source.

[0009] Optionally, the compensation method further comprises: setting one compensation circuit for each of the plurality of sub-channels as the interference source; and controlling the corresponding compensation circuit to be synchronously turned on and release the compensation charges only when the sub-channel as the interference source is in a sampling state with the sampling phase overlap.

[0010] Optionally, the interleaved analog-to-digital converter comprises a first sub-channel, a second sub-channel, a third sub-channel, and a fourth sub-channel; the sampling phase overlap time of two adjacent sub-channels is 1 / 4 of a sampling period, and the single sampling time of each sub-channel is 1 / 2 of the sampling period; and the compensation method comprises: setting a first compensation circuit and a second compensation circuit; and controlling the first compensation circuit and the second compensation circuit to release the compensation charges; wherein the first compensation circuit is used to synchronously turn on and release the compensation charges when the second sub-channel and the fourth sub-channel are as the interference source and a subsequent sub-channel is turned on for sampling; and the second compensation circuit is used to synchronously turn on and release the compensation charges when the first sub-channel and the third sub-channel are as the interference source and a subsequent sub-channel is turned on for sampling.

[0011] Optionally, before the step of controlling the first compensation circuit and the second compensation circuit to release the compensation charge, the compensation method comprises: identifying the sampling start timing of adjacent sub-channels in the interleaved analog-to-digital converter, determining a preceding sub-channel and a subsequent sub-channel in the adjacent sub-channel pair; wherein the preceding sub-channel is a sub-channel that starts sampling first, and the subsequent sub-channel is an adjacent sub-channel that starts sampling later during the sampling of the preceding sub-channel.

[0012] Optionally, the step of controlling the first compensation circuit and the second compensation circuit to release the compensation charge comprises: alternately driving the first compensation circuit and the second compensation circuit at a switching frequency that is twice the sampling frequency of the sub-channels; and controlling the duration for which the first compensation circuit and the second compensation circuit release the compensation charge to be equal to 1 / 4 of a sampling period.

[0013] Optionally, the method further comprises: after the compensation circuit releases the compensation charge, controlling the compensation circuit to enter a reset state to clear residual charge and prepare for the next compensation.

[0014] Optionally, the interleaved analog-to-digital converter is a successive approximation ADC or a pipeline ADC.

[0015] In a second aspect, an embodiment of the present application provides an interleaved analog-to-digital converter, comprising: a plurality of sub-channels and a compensation circuit corresponding to each sub-channel; and further comprising a compensation control module connected to the sub-channels and the compensation circuits respectively, and configured to execute the compensation method of the interleaved analog-to-digital converter according to any embodiment of the present application.

[0016] The compensation method provided by the embodiment of the present application identifies the interference source sub-channel in the overlapping scenario, generates compensation charge that is opposite in polarity and identical in amplitude to the interference charge that will be transferred by the interference source sub-channel based on the previous conversion result of the interference source sub-channel, configures a corresponding compensation circuit for each sub-channel, and controls the corresponding compensation circuit of any sub-channel to open and release compensation charge when the sub-channel opens sampling and becomes an interference source to generate charge transfer. Since the interference charge released by the interference source sub-channel and the compensation charge released by the compensation circuit are offset in real time, the net interference charge transferred by each sub-channel to the outside is always zero, thereby solving the problem of nonlinear charge transfer interference caused by the overlapping of sampling phases between sub-channels, effectively filling the gap in the prior art that cannot cope with such nonlinear interference, and improving the conversion accuracy of the interleaved analog-to-digital converter. At the same time, the method does not need to increase the driving capability of the driving circuit or reduce the RC time constant of the input network to alleviate the interference as in the prior art, avoiding the problem of additional chip area occupation, ensuring the improvement of conversion accuracy while taking into account the cost control and low power consumption requirements of the chip, and being more suitable for high integration and low power chip design scenarios.

[0017] It should be understood that the description in this section is not intended to identify key or essential features of the embodiments of the present invention, nor is it intended to limit the scope of the invention. Other features of the invention will become readily apparent from the following description. Attached Figure Description

[0018] To more clearly illustrate the technical solutions in the embodiments of the present invention, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0019] Figure 1 This is a sampling timing diagram of an interleaved ADC provided in an embodiment of the present invention;

[0020] Figure 2a This is a schematic diagram of the structure of an interleaved analog-to-digital converter provided in an embodiment of the present invention;

[0021] Figure 2b This is a schematic diagram of the structure of a charge redistribution digital-to-analog converter provided in an embodiment of the present invention;

[0022] Figure 3 This is a flowchart of a compensation method for an interleaved analog-to-digital converter provided in an embodiment of the present invention;

[0023] Figure 4 This is a timing diagram of sampling and compensation for a 4-channel interleaved ADC provided by the present invention;

[0024] Figure 5 This is a flowchart of another compensation method for an interleaved analog-to-digital converter provided in an embodiment of the present invention;

[0025] Figure 6 This is a flowchart of another compensation method for an interleaved analog-to-digital converter provided in an embodiment of the present invention;

[0026] Figure 7 This is a flowchart of another compensation method for an interleaved analog-to-digital converter provided in an embodiment of the present invention;

[0027] Figure 8 This is a flowchart of another compensation method for an interleaved analog-to-digital converter provided in an embodiment of the present invention.

[0028] Figure 9 This is another sampling and compensation timing diagram of a 4-channel interleaved ADC provided by the present invention;

[0029] Figure 10 This is a flowchart of another compensation method for an interleaved analog-to-digital converter provided in an embodiment of the present invention. Detailed Implementation

[0030] To enable those skilled in the art to better understand the present invention, the technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings of the embodiments of the present invention. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort should fall within the scope of protection of the present invention.

[0031] It should be noted that the terms "first," "second," etc., in the specification, claims, and accompanying drawings of this invention are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that the embodiments of the invention described herein can be implemented in orders other than those illustrated or described herein. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover a non-exclusive inclusion; for example, a process, method, system, product, or apparatus that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus.

[0032] To address the problems in the prior art, this application provides a compensation method for an interleaved analog-to-digital converter. The following section first introduces an interleaved analog-to-digital converter to which the thermal management control method provided in this application can be applied. Figure 2a This is a schematic diagram of the structure of an interleaved analog-to-digital converter provided in an embodiment of the present invention, as shown below. Figure 2a As shown, the interleaved analog-to-digital converter includes n sub-channels 11, and the input terminals of each sub-channel 11 are connected in parallel to a common node A1. Here, n is an integer greater than or equal to 3.

[0033] Each sub-channel 11 of the interleaved analog-to-digital converter includes a master switch K1 and a charge redistribution digital-to-analog converter 110 (CDAC).

[0034] Figure 2b This is a schematic diagram of the structure of a charge redistribution digital-to-analog converter provided in an embodiment of the present invention. Figure 2b As shown, the CDAC 110 includes M capacitors C1 and M switch networks 111. The switch network 111 includes a first control switch K2 and a second control switch K3 connected in parallel.

[0035] Where M is a positive integer greater than or equal to 2, and the specific value is set according to the conversion accuracy requirements of sub-channel 22. Figure 2b The case where M=2 is illustrated.

[0036] The main switch K1 is the sampling / holding state switching unit for sub-channel 11. One end is connected to the output of driver 12, and the other end is connected to the common node A1 of CDAC. It is used to control the on / off state according to the sampling clock signal of sub-channel 11.

[0037] When the main switch K1 is closed, the sub-channel 11 enters the sampling state. The input signal Vin is transmitted to the CDAC through the main switch K1. The M capacitors of the CDAC are selected to be connected to the positive reference voltage REFP or the negative reference voltage REFN through the corresponding switch network 111 to complete the charge storage corresponding to the input signal Vin.

[0038] When the main switch K1 is turned off, sub-channel 11 enters the holding state, the CDAC is disconnected from the input signal Vin, and the charge stored on the capacitor remains.

[0039] Optionally, the interleaved analog-to-digital converter is a successive approximation ADC or a pipelined ADC.

[0040] Figure 3 This is a flowchart of a compensation method for an interleaved analog-to-digital converter (ADC) according to an embodiment of the present invention. The method can be executed by a compensation control module, which can be integrated into the interleaved ADC.

[0041] like Figure 3 As shown, the compensation methods include:

[0042] S101. For a sub-channel that acts as an interference source, when its sampling phase overlaps with other sub-channels that act as the interference target, a compensation charge is generated based on the previous conversion result of the sub-channel that acts as the interference source.

[0043] Specifically, the sub-channel that acts as a source of interference refers to the sub-channel that, during a sampling phase overlap event, transfers the historical charge stored on its sampling capacitor through the common node A1, thereby adversely affecting the sampling process of other sub-channels. This sub-channel is the "emitter" of the interfering charge.

[0044] Other sub-channels that are the targets of interference, as opposed to "sub-channels that are the sources of interference," refer to sub-channels whose sampling accuracy decreases during sampling phase overlap events because their sampling nodes receive charge transferred from the interference source sub-channels. These sub-channels are both the "receivers" of the interference charge and the "bearers" of the interference effects.

[0045] Sampling phase overlap refers to the period during which the sampling switches of the interfering sub-channel and the other sub-channels being interfered with are simultaneously in the conducting state due to the fixed phase difference between the sampling clocks of each sub-channel in an interleaved analog-to-digital converter. This period is the physical window through which interference charges can transfer between channels.

[0046] The previous conversion result refers to the digital output determined by the sub-channel that is the source of interference after the most recent analog-to-digital conversion before the current interference event occurs.

[0047] Among them, the compensation charge has the opposite polarity and the same amplitude as the interference charge generated by the sub-channel that is the source of interference on other sub-channels that are the targets of interference.

[0048] Figure 4 This is a timing diagram of sampling and compensation for a 4-channel interleaved ADC provided by the present invention. Figure 4 As shown, the first sub-channel ADC0, the second sub-channel ADC1, the third sub-channel ADC2, and the fourth sub-channel ADC3 are cyclically activated for sampling according to a predetermined phase. The sampling phase overlap time between two adjacent sub-channels is 1 / 4 of the sampling period, and the single sampling duration of each sub-channel is 1 / 2 of the sampling period.

[0049] The first sub-channel ADC0, the second sub-channel ADC1, the third sub-channel ADC2, and the fourth sub-channel ADC3 are each configured with a first compensation circuit CDAC1, a second compensation circuit CDAC2, a third compensation circuit CDAC3, and a fourth compensation circuit CDAC4, respectively.

[0050] When the second sub-channel ADC1 starts sampling, compared to the first sub-channel ADC0 which is started first, the second sub-channel ADC1 is the "sub-channel that acts as the source of interference", while the first sub-channel ADC0 is the "other sub-channel that acts as the target of interference".

[0051] Almost simultaneously, the third sub-channel ADC2, which was activated later, also overlapped with the second sub-channel ADC1. In this new interference relationship, the third sub-channel ADC2 became the "sub-channel as the source of interference," while the second sub-channel ADC1 became "another sub-channel as the object of interference."

[0052] When the fourth sub-channel ADC3 starts sampling, relative to the third sub-channel ADC2 which started earlier, the fourth sub-channel ADC3 is the "sub-channel acting as the source of interference," while the third sub-channel ADC2 is the "other sub-channel acting as the target of interference." Simultaneously, due to the cyclical nature of the interleaving timing, the fourth sub-channel ADC3 also overlaps with the first sub-channel ADC0, which starts earliest in the new cycle. In this other set of relationships, the fourth sub-channel ADC3 is the "sub-channel acting as the source of interference," while the first sub-channel ADC0 is the "other sub-channel acting as the target of interference."

[0053] In summary, during the operation of an interleaved analog-to-digital converter, whether any sub-channel acts as an "interference source" or an "interference target" is not fixed, but dynamically determined by its relative timing position in different sampling phase overlap events.

[0054] In some embodiments, assuming that in the current sampling phase overlap event, the second sub-channel ADC1 is identified as "the sub-channel as an interference source" and then the following operations are performed to generate compensation charge:

[0055] The compensation control module reads the conversion result of the second sub-channel ADC1 during the previous complete duty cycle from the digital memory. This result is a digital code, such as an 8-bit binary number 10011010. This digital code defines the amount of charge (i.e., the corresponding voltage value) stored on the internal capacitor array of the second sub-channel ADC1 at the end of the last sampling.

[0056] Based on the previous conversion result, the compensation control module performs a specific mathematical operation. The core operation is "inversion," which aims to generate a compensation control signal that commands the compensation circuit to generate charges with "opposite polarity and equal amplitude." Specifically, the system calculates the inverse code corresponding to 10011010, or directly generates a control word to control the capacitor array to switch to a complementary configuration state.

[0057] The calculated compensation control signal is applied to the capacitor array switches of the second compensation circuit CDAC2 corresponding to the second sub-channel ADC1. These capacitor array switches change the connection state of the internal capacitor network of CDAC2 according to the control signal, so that the stored charge is opposite in polarity and the same in amplitude as the charge released by the second sub-channel ADC1 as an interference source.

[0058] S102. The control compensation circuit and the corresponding sub-channel that is the source of interference are turned on synchronously to release compensation charge in order to counteract the influence of interference charge on other sub-channels that are the objects of interference.

[0059] Specifically, synchronous activation refers to the immediate activation of the corresponding compensation circuit during the operation of an interleaved analog-to-digital converter (ADC) once a sub-channel is determined to be an "interference source" and its sampling phase overlaps with that of other sub-channels that are the targets of interference. The key point is that the activation of the compensation circuit is synchronized with the occurrence of the "interference event," rather than unconditionally synchronized with the sampling activation of its corresponding sub-channel. During periods without sampling phase overlap, even if a sub-channel is in sampling mode, its compensation circuit does not need to be activated. In other words, the corresponding compensation circuit is only activated and releases compensation charge synchronously when a sub-channel acts as an interference source and its sampling phase overlaps with that of other sub-channels. Optionally, a compensation circuit is provided for each of the multiple sub-channels acting as interference sources.

[0060] Continue to refer to Figure 2a Each compensation circuit 13 of the interleaved analog-to-digital converter includes a compensation master switch K2 and a compensation charge redistribution digital-to-analog converter 130 (hereinafter referred to as compensation CDAC).

[0061] The compensation CDAC consists of M compensation capacitors and M compensation switch networks, where M is the same positive integer as the corresponding interference source sub-channel CDAC, and each compensation capacitor can be selectively connected to a positive or negative reference voltage through its corresponding compensation switch network.

[0062] The main compensation switch K2 is the timing synchronization unit of the compensation circuit 13. One end is connected to the compensation CDAC, and the other end is connected to the common node A1 (i.e. the output of the driver 12) shared by all sub-channels of the interleaved ADC.

[0063] When the main compensation switch K2 is closed, the compensation circuit enters the compensation release state. The M compensation capacitors of the compensation CDAC are connected to the positive or negative reference voltage through the corresponding compensation switch network based on the compensation control signal generated by the previous conversion result of the interference source sub-channel. The compensation charge with the opposite polarity and the same amplitude as the interference charge of the interference source sub-channel is released and the interference charge is canceled out through the common node A1.

[0064] When the main compensation switch K2 is turned off, the compensation circuit enters the reset state, the compensation CDAC is disconnected from the common node A1, and the compensation control module drives all the switches of the compensation switch network to turn off, clearing the residual charge on the compensation capacitor and preparing for the next compensation cycle.

[0065] Continue to refer to Figure 4 When the first sub-channel ADC0 starts sampling, it overlaps with the fourth sub-channel ADC3 and the second sub-channel ADC1, so its corresponding first compensation circuit CDAC1 is turned on synchronously.

[0066] When the second sub-channel ADC1 starts sampling, it overlaps with the first sub-channel ADC0 and the third sub-channel ADC2, so its corresponding second compensation circuit CDAC2 is turned on synchronously.

[0067] When the third sub-channel ADC2 starts sampling, it overlaps with the second sub-channel ADC1 and the fourth sub-channel ADC3, so its corresponding third compensation circuit CDAC3 is turned on synchronously.

[0068] When the fourth sub-channel ADC3 starts sampling, it overlaps with the third sub-channel ADC2 and the first sub-channel ADC0, so its corresponding fourth compensation circuit CDAC4 is turned on synchronously.

[0069] The compensation method provided in this invention identifies the interference source sub-channel in the overlapping scenario and generates a compensation charge with the opposite polarity and the same amplitude as the interference charge to be transferred outward by the interference source sub-channel, based on the previous conversion result of the interference source sub-channel. Simultaneously, a corresponding compensation circuit is configured for each sub-channel. When any sub-channel starts sampling and generates charge transfer as an interference source, its corresponding compensation circuit is simultaneously activated and releases the compensation charge. Since the interference charge released by the interference source sub-channel and the compensation charge released by the compensation circuit cancel each other out in real time, the net interference charge transferred outward by each sub-channel is always zero. This solves the problem of nonlinear charge transfer interference caused by overlapping sampling phases between sub-channels, effectively filling the gap in existing technologies that struggle to handle such nonlinear interference and improving the conversion accuracy of interleaved analog-to-digital converters. Furthermore, this method does not require increasing the driving capability of the driving circuit or reducing the RC time constant of the input network to mitigate interference, as in existing technologies, avoiding the problem of additional chip area occupation. While ensuring improved conversion accuracy, it also considers chip cost control and low power consumption requirements, making it more suitable for high-integration, low-power chip design scenarios.

[0070] Figure 5 This is a flowchart of another compensation method for an interleaved analog-to-digital converter provided in an embodiment of the present invention. For example... Figure 5 As shown, the compensation method includes:

[0071] S201. Obtain the previous conversion result of the sub-channel that is the source of interference.

[0072] Specifically, continue with Figure 4 Taking an interleaved ADC with first, second, third, and fourth sub-channels as an example, the process of obtaining the previous conversion result of the sub-channel that serves as an interference source is explained:

[0073] Assuming the interleaved ADC is currently in the continuous sampling phase, the first sub-channel ADC0 has already started sampling. When the first sub-channel ADC0 has completed 1 / 4 of the sampling period, the second sub-channel ADC1 starts sampling. At this time, the first sub-channel ADC0 and the second sub-channel ADC1 enter a sampling phase overlap period. During this overlap period, the second sub-channel ADC1 acts as an "interference source sub-channel," meaning that its internal CDAC retains charge from the previous conversion. This charge is transferred through the common node to the first sub-channel ADC0, which is still in the sampling state, forming interference charge.

[0074] At this point, the compensation control module needs to perform the operation of "obtaining the previous conversion result of the sub-channel (second sub-channel ADC1) that is the source of interference": the "previous conversion result" is the digital signal output by the second sub-channel ADC1 after the most recent analog-to-digital conversion before "overlapping sampling with the first sub-channel", such as the 8-bit binary number "10100110". This digital signal has been stored in the digital storage unit (such as a register) inside the interleaved ADC, and the compensation control module directly retrieves the previous conversion result ("10100110") from the storage unit through the data read interface.

[0075] Furthermore, the result of the previous conversion is directly related to the residual charge of the CDAC in the second sub-channel. Assuming that each "1" in "10100110" corresponds to a capacitor in the CDAC connected to a positive reference voltage, and each "0" corresponds to the same capacitor connected to a negative reference voltage, the total residual charge on the CDAC can be calculated from this digital signal. The total charge Q = ΣC × V, where C is the capacitance of a single capacitor, and V is the voltage across the capacitor and its polarity (determined by the polarity of the reference voltage).

[0076] S202. Based on the previous conversion result, calculate the compensation control signal used to control the compensation circuit, so that the compensation circuit generates compensation charge according to the compensation control signal.

[0077] The compensation control signal refers to the digital control signal generated by the compensation control module through preset logic operations based on the previous conversion result of the "sub-channel as the interference source". It is used to control the switching network state of the compensation circuit, thereby enabling the compensation circuit to generate a compensation charge that is "opposite in polarity and the same in amplitude as the interference charge generated by the interference source sub-channel".

[0078] Assuming that in the current sampling period, the second sub-channel ADC1 enters the sampling state first (as the preceding sub-channel), when the second sub-channel ADC1 has sampled for 1 / 4 of the cycle, the third sub-channel ADC2 starts sampling. At this time, the second sub-channel ADC1 and the third sub-channel ADC2 enter the sampling phase overlap period. The third sub-channel ADC2 is the "sub-channel as the interference source". The charge corresponding to the previous conversion result retained on its internal CDAC will be transferred to the second sub-channel ADC1 (other sub-channels of the object being interfered with) which is still in the sampling state, forming interference charge.

[0079] For example, the compensation control module has obtained the previous conversion result of the third sub-channel ADC2 as an 8-bit binary code "10101100". A bit-inverting operation is performed on the previous conversion result "10101100" to obtain the compensation control signal "01010011". In this compensation control signal, "0" indicates that one capacitor of the compensation CDAC in the third compensation circuit CDAC3 is connected to a negative reference voltage, and "1" indicates that one capacitor of the compensation CDAC in the third compensation circuit is connected to a positive reference voltage.

[0080] The compensation control signal is sent to the third compensation circuit CDAC3. The switching network of CDAC3 adjusts the connection of its internal capacitors to the positive or negative reference voltage based on each bit of the "01010011" control signal. For example, if the first control signal is "0", the corresponding capacitor is connected to the positive reference voltage REFP; if the second control signal is "1", the corresponding capacitor is connected to the negative reference voltage. Through this control, the compensation charge stored in the third compensation circuit CDAC3 has the opposite polarity and the same amplitude as the interference charge generated by the third sub-channel ADC2. When the third sub-channel ADC2 (the sub-channel acting as the interference source) releases its interference charge, the third compensation circuit CDAC3 simultaneously releases its compensation charge. The two cancel each other out at the common node A1, preventing the sampling accuracy of the second sub-channel ADC1 (the object being interfered with) from being affected.

[0081] S203. The control compensation circuit and the corresponding sub-channel that is the source of interference are turned on synchronously to release compensation charge in order to counteract the influence of interference charge on other sub-channels that are the objects of interference.

[0082] Figure 6 This is a flowchart of another compensation method for an interleaved analog-to-digital converter provided in an embodiment of the present invention. For example... Figure 6 As shown, the compensation method includes:

[0083] S301. For a sub-channel that acts as an interference source, when it has a sampling phase overlap with other sub-channels that act as the interference target, a compensation charge is generated based on the previous conversion result of the sub-channel that acts as the interference source.

[0084] S302, Generate a switch control signal that is synchronized with the sampling clock of the corresponding sub-channel that is an interference source.

[0085] Specifically, the switch control signal refers to the digital control signal generated by the compensation control module, whose timing is aligned with the sampling clock of the sub-channel acting as the interference source. Its function is to drive the compensation master switch K2 of the compensation circuit to turn on and off. The timing characteristics of this signal (such as rising edge, falling edge, and high-level duration) are completely synchronized with the sampling clock of the interference source sub-channel, ensuring that the start-up timing of the compensation circuit matches the sampling phase of the interference source sub-channel.

[0086] Assuming the total sampling frequency of the interleaved ADC is Fs = 400MHz and the number of sub-channels is n = 4, the sampling clock frequency of each sub-channel is Fs / n = 100MHz. The single sampling duration of a single sub-channel is 1 / 2 sampling period (i.e., 5ns), and the sampling phase overlap time between adjacent sub-channels is 1 / 4 sampling period (i.e., 2.5ns). The sampling clocks of each sub-channel are triggered sequentially with fixed phases: the sampling clock of ADC0 is triggered at the rising edge at 0ns, the sampling clock of ADC1 is triggered at the rising edge at 2.5ns, the sampling clock of ADC2 is triggered at the rising edge at 5ns, and the sampling clock of ADC3 is triggered at the rising edge at 7.5ns, forming a cyclically interleaved sampling timing sequence.

[0087] When the second sub-channel ADC1 is triggered to sample at the rising edge at 2.5ns, the sampling phase of the second sub-channel ADC1 overlaps with that of the first sub-channel ADC0, which is already in the sampling state. The second sub-channel ADC1 becomes the "sub-channel as an interference source", and its sampling clock (100MHz, triggered by the rising edge at 2.5ns) is the synchronization reference.

[0088] At this time, the compensation control module performs the operation of "generating a switch control signal". First, it captures the rising edge of the sampling clock of the second sub-channel ADC1 (at 2.5ns). Based on this rising edge, it generates a switch control signal with the same timing as the sampling clock of the second sub-channel ADC1. The frequency of this switch control signal is also 100MHz. The rising edge is synchronized with the rising edge of the ADC1 sampling clock (both at 2.5ns). The duration of the high level matches the sampling phase overlap time (2.5ns). The low level is synchronized with the falling edge of the sampling clock of the second sub-channel ADC1 (at 7.5ns, the sampling of the second sub-channel ADC1 ends).

[0089] S303. Use a switch control signal to drive the switch of the compensation circuit so that it is turned on during the sampling phase of the sub-channel that is the source of interference.

[0090] Specifically, continuing with the example of the second sub-channel ADC1 acting as the "sub-channel as the interference source," the switch control signal is transmitted to the compensation master switch K2 of the second compensation circuit CDAC2 corresponding to the second sub-channel ADC1. At 2.5ns, the rising edge of the switch control signal triggers the closing of the compensation master switch K2 of the second compensation circuit CDAC2, and the second compensation circuit CDAC2 enters the compensation release state, synchronously releasing compensation charges with opposite polarity and the same amplitude as the interference charges of the second sub-channel ADC1. At 7.5ns, the falling edge of the switch control signal triggers the opening of the compensation master switch K2 of the second compensation circuit CDAC2, and the second compensation circuit CDAC2 enters the reset state. Throughout the process, the switch control signal is completely synchronized with the sampling clock of the second sub-channel ADC1, ensuring that the on-time period of the second compensation circuit CDAC2 (2.5ns~7.5ns) is the same as the sampling period of the second sub-channel ADC1 (2.5ns~7.5ns), thus achieving real-time cancellation of interference charges and compensation charges.

[0091] Figure 7 This is a flowchart of another compensation method for an interleaved analog-to-digital converter provided in an embodiment of the present invention. For example... Figure 7 As shown, the compensation method includes:

[0092] S401. For a sub-channel that is an interference source, when there is a sub-channel with overlapping sampling phases with other sub-channels that are interference targets, a compensation charge is generated based on the previous conversion result of the sub-channel that is an interference source.

[0093] S402, The control compensation circuit and the corresponding sub-channel that is the source of interference are turned on synchronously to release compensation charge in order to counteract the influence of interference charge on other sub-channels that are the objects of interference.

[0094] S403. After the compensation circuit releases the compensation charge, the control compensation circuit enters the reset state to clear the residual charge and prepare for the next compensation.

[0095] Specifically, the reset state is the "initial standby state" that the compensation circuit enters after completing a single compensation charge release, controlled by the compensation control module. Specifically, the main compensation switch remains open, disconnecting the compensation CDAC from the common node; all switches in the compensation switch network are open, disconnecting the M compensation capacitors of the compensation CDAC from the positive and negative reference voltages.

[0096] Figure 8 This is a flowchart of another compensation method for an interleaved analog-to-digital converter provided in an embodiment of the present invention. For example... Figure 8 As shown, based on the principle of compensating only for the interference charge generated by the sub-channels that are sampled later, the compensation method includes:

[0097] S501, Set up the first compensation circuit and the second compensation circuit;

[0098] This step optimizes the allocation of compensation circuit resources based on the principle of compensating only subsequent channels. Through analysis... Figure 4 From the four-channel interleaved sampling timing, it can be seen that the sampling phases of the first sub-channel ADC0 and the third sub-channel ADC2 differ by 180 degrees. Their sampling periods do not overlap and will not interfere with each other, so they can be grouped together. Similarly, the sampling phases of the second sub-channel ADC1 and the fourth sub-channel ADC3 also differ by 180 degrees, so they are grouped together. Based on this, the present invention combines the compensation tasks of the four channels into two compensation circuits.

[0099] S502 controls the first compensation circuit and the second compensation circuit to release the compensation charge.

[0100] Specifically, the first compensation circuit and the second compensation circuit are driven alternately at a switching frequency twice that of the sub-channel sampling frequency. Furthermore, the duration for which the first and second compensation circuits release compensation charge is equal to 1 / 4 of the sampling period.

[0101] First, the sub-channel sampling frequency refers to the sampling clock frequency of each sub-channel. In a 4-channel interleaved analog-to-digital converter, the total sampling frequency is Fs, and the sampling frequency of each sub-channel is Fs / 4. Therefore, the sub-channel sampling period is 4 / Fs.

[0102] The switching frequency refers to the frequency of the switching control signal that drives the first compensation circuit and the second compensation circuit. Its value is twice the sampling frequency of the sub-channel, i.e., 2×(Fs / 4)=Fs / 2.

[0103] The duration of releasing the compensation charge refers to the length of time the compensation circuit releases the compensation charge after each activation. Its value is equal to 1 / 4 of the sampling period, i.e., 1 / Fs. This duration is consistent with the sampling phase overlap time of adjacent sub-channels, ensuring that the compensation charge is released only during the overlap period when interference occurs, thereby canceling out the interference charge.

[0104] The first compensation circuit CDAC1 is used to synchronously turn on and release compensation charge when the second sub-channel ADC1 and the fourth sub-channel ADC3 are used as subsequent sub-channels for sampling.

[0105] Figure 9 This is another sampling and compensation timing diagram of a 4-channel interleaved ADC provided by the present invention. (See diagram below.) Figure 9 As shown, when the second sub-channel ADC1 is activated as the subsequent channel for sampling, its sampling phase overlaps with that of the first sub-channel ADC0, which is activated earlier. At this time, the first compensation circuit CDAC1 is activated synchronously and releases compensation charge with opposite polarity and consistent amplitude to the interference charge of the second sub-channel ADC1, so as to cancel the interference of the second sub-channel ADC1 on the first sub-channel ADC0.

[0106] When the fourth sub-channel ADC3 is activated as the subsequent channel for sampling, its sampling phase overlaps with that of the previously activated third sub-channel ADC2. At this time, the first compensation circuit CDAC1 is activated again synchronously and releases compensation charge to cancel the interference of the fourth sub-channel ADC3 on the third sub-channel ADC2.

[0107] The second compensation circuit is used to synchronously activate and release compensation charge when the first and third sub-channels are used as subsequent sub-channels for sampling.

[0108] When the first sub-channel ADC0 is activated as the subsequent channel for sampling, its sampling phase overlaps with that of the previously activated fourth sub-channel ADC3. At this time, the second compensation circuit CDAC2 is activated synchronously and releases compensation charge with opposite polarity and the same amplitude as the interference charge of ADC0, in order to cancel the interference of the first sub-channel ADC0 on the fourth sub-channel ADC3.

[0109] When the third sub-channel ADC2 is activated as the subsequent channel for sampling, its sampling phase overlaps with that of the first activated second sub-channel ADC1. At this time, the second compensation circuit CDAC2 is activated again synchronously and releases compensation charge to cancel the interference of the third sub-channel ADC2 on the second sub-channel ADC1.

[0110] The advantage of this setup is that by increasing the switching frequency of the compensation circuit and precisely controlling the duration, interference compensation for all four sub-channels can be completed with only two compensation circuits, reducing the number of compensation circuits and thus lowering chip area and power consumption. Simultaneously, because the release of compensation charge and the generation of interference charge are synchronized in real time, nonlinear charge transfer interference is effectively counteracted, improving the conversion accuracy of the interleaved analog-to-digital converter.

[0111] Figure 10 This is a flowchart of another compensation method for an interleaved analog-to-digital converter provided in an embodiment of the present invention. For example... Figure 10 As shown, the compensation method includes:

[0112] S601. Identify the sampling start timing of adjacent sub-channels in an interleaved analog-to-digital converter, and determine the preceding and following sub-channels in the adjacent sub-channel pair.

[0113] The preceding sub-channel is the sub-channel that starts sampling first, and the following sub-channel is the adjacent sub-channel that starts sampling later during the sampling process of the preceding sub-channel.

[0114] S602, Set up the first compensation circuit and the second compensation circuit.

[0115] S603 controls the first compensation circuit and the second compensation circuit to release compensation charge.

[0116] Based on the same inventive concept, embodiments of the present invention also provide an interleaved analog-to-digital converter. (Continue to refer to...) Figure 2a The interleaved analog-to-digital converter includes: multiple sub-channels 11 and compensation circuits 13 corresponding to the sub-channels 11.

[0117] The interleaved analog-to-digital converter also includes a compensation control module 14, which is connected to the sub-channel 11 and the compensation circuit 13 respectively. The compensation control module 14 is used to execute the compensation method of the interleaved analog-to-digital converter provided in any embodiment of the present invention, and has the same beneficial effects as the compensation method. This embodiment will not be described in detail here.

[0118] In some embodiments, the compensation control module 14 includes a microcontroller. Optionally, the compensation control module 14 may include a microcontroller, or a digital signal processor (DSP) or a field programmable gate array (FPGA).

[0119] It should be understood that the various forms of processes shown above can be used, with steps reordered, added, or deleted. For example, the steps described in this invention can be executed in parallel, sequentially, or in different orders, as long as the desired result of the technical solution of this invention can be achieved, and this is not limited herein.

[0120] The specific embodiments described above do not constitute a limitation on the scope of protection of this invention. Those skilled in the art should understand that various modifications, combinations, sub-combinations, and substitutions can be made according to design requirements and other factors. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of this invention should be included within the scope of protection of this invention.

Claims

1. A method of compensating for an interleaved analog-to-digital converter, the method comprising: The interleaved analog-to-digital converter comprises a plurality of sub-channels, and the compensation method comprises: For a sub-channel as an interference source, when there is a sampling phase overlap with other sub-channels as interference objects, compensation charges are generated based on a previous conversion result of the sub-channel as the interference source; wherein the compensation charges are opposite in polarity and the same in amplitude to interference charges generated by the sub-channel as the interference source on the other sub-channels as the interference objects; The compensation circuit is controlled to be opened synchronously with the corresponding sub-channel as the interference source to release the compensation charges to offset the influence of the interference charges on the other sub-channels as the interference objects.

2. The method of claim 1, wherein, The step of generating compensation charges based on the previous conversion result of the sub-channel as the interference source comprises: Obtaining the previous conversion result of the sub-channel as the interference source; Based on the previous conversion result, a compensation control signal for controlling the compensation circuit is calculated to make the compensation circuit generate the compensation charges according to the compensation control signal.

3. The method of claim 1, wherein, The step of controlling the compensation circuit to be opened synchronously with the corresponding sub-channel as the interference source comprises: Generating a switch control signal synchronized with a sampling clock corresponding to the sub-channel as the interference source; Using the switch control signal to drive the switch of the compensation circuit to be opened in the sampling stage of the sub-channel as the interference source.

4. The method of claim 1, wherein, The compensation method further comprises: Corresponding to each of the plurality of sub-channels as the interference source, a compensation circuit is arranged; Wherein, only when a sub-channel as the interference source is in a sampling state with a sampling phase overlap, the corresponding compensation circuit is controlled to be opened synchronously and release compensation charges.

5. The method of claim 1, wherein, The interleaved analog-to-digital converter comprises a first sub-channel, a second sub-channel, a third sub-channel and a fourth sub-channel; The sampling phase overlap time of two adjacent sub-channels is 1 / 4 of a sampling period, and the single sampling time of each sub-channel is 1 / 2 of a sampling period; The compensation method comprises: A first compensation circuit and a second compensation circuit are arranged; The first compensation circuit and the second compensation circuit are controlled to release the compensation charges; The first compensation circuit is used to open synchronously and release the compensation charges when the second sub-channel and the fourth sub-channel are as interference sources and the subsequent sub-channel is opened for sampling; The second compensation circuit is used to open synchronously and release the compensation charges when the first sub-channel and the third sub-channel are as interference sources and the subsequent sub-channel is opened for sampling.

6. The method of claim 5, wherein, Before the step of controlling the first compensation circuit and the second compensation circuit to release the compensation charges, the compensation method comprises: The sampling opening timing of adjacent sub-channels in the interleaved analog-to-digital converter is identified to determine a previous sub-channel and a subsequent sub-channel in an adjacent sub-channel pair; The previous sub-channel is a sub-channel that is opened for sampling first, and the subsequent sub-channel is an adjacent sub-channel that is opened for sampling later in the sampling process of the previous sub-channel.

7. The method of claim 5, wherein, The step of controlling the first compensation circuit and the second compensation circuit to release the compensation charges comprises: alternately driving the first compensation circuit and the second compensation circuit at a switching frequency twice a sampling frequency of the sub-channels; controlling the first compensation circuit and the second compensation circuit to release the compensation charge for a duration equal to 1 / 4 of a sampling period.

8. The method of interleaved ADC compensation as claimed in claim 1, wherein, The step method further comprises: after the compensation circuit releases the compensation charge, controlling the compensation circuit to enter a reset state to clear residual charge and prepare for the next compensation.

9. The method of interleaved ADC compensation as claimed in claim 1, wherein, The interleaved analog-to-digital converter is a successive approximation ADC or a pipeline ADC.

10. An interleaved analog-to-digital converter, comprising: comprises: a plurality of sub-channels and compensation circuits corresponding to the sub-channels; Further comprising a compensation control module connected to the sub-channels and the compensation circuits respectively, the compensation control module being configured to perform the compensation method of the interleaved analog-to-digital converter according to any one of claims 1-9.

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