Data processing method and device

Abstract

The invention provides a data processing method, which can be applied to a first device, and the first device performs scrambling on a plurality of first data to obtain a plurality of second data, and performs FEC coding on the plurality of second data to obtain a plurality of third data. And after obtaining the plurality of third data, performing bit pair interleaving on the plurality of third data to obtain fourth data, and inserting the fourth data into the internal code data stream. By adopting the scheme, the fourth data is inserted into the inner code data stream, so that when the fourth data stream is transmitted on the physical link, the transmission rate of the physical link corresponds to the integral multiple of the frequency of the crystal oscillator. The fourth data is the data obtained after scrambling processing, so that the DC characteristic of a physical link is not influenced when the fourth data is inserted into the internal code data stream. In addition, according to the scheme, the multiple pieces of first data obtaining the fourth data are processed respectively, and the processing efficiency of the multiple pieces of first data is improved.

Description

[0001] This application claims priority to the Chinese Patent Application No. 202411269868.1, filed on September 10, 2024, and entitled “A data processing method, network device and system”, the content of which is incorporated herein by reference in its entirety. TECHNICAL FIELD

[0002] The present application relates to the field of communication, and in particular, to a data processing method and device. BACKGROUND

[0003] The transmission rate of the physical link can correspond to an integer multiple of the crystal frequency. Wherein, the transmission rate of the physical link corresponding to an integer multiple of the crystal frequency means that the baud rate or bit rate of the signal transmitted on the physical link is an integer multiple of the crystal frequency. Wherein, the commonly used crystal frequency is 156.25 megahertz (MHz) or 312.5 MHz, etc.

[0004] At present, in the scenario that the Ethernet interface supports forward error correction (FEC) encoding, since the check bits will be introduced via the FEC encoding, the transmission rate of the physical link can no longer correspond to an integer multiple of the crystal frequency. Wherein, a commonly used FEC encoding is cascade encoding, which includes inner code encoding and outer code encoding. When the data stream obtained via the inner code encoding is transmitted on the physical link, the transmission rate of the physical link can no longer correspond to an integer multiple of the crystal frequency. In order to make the transmission rate of the physical link still correspond to an integer multiple of the crystal frequency when the data stream obtained via the inner code encoding is transmitted on the physical link, a certain number of other data, such as padding data, can be inserted every interval of a certain number of inner code codewords. Wherein, the “inner code encoding” can also be referred to as “inner code FEC encoding”, and in this application, the two can be used alternately.

[0005] However, after inserting other data, the direct-current (DC) characteristics of the physical link will be affected. Therefore, there is an urgent need for a solution to solve the above problem. SUMMARY

[0006] The present application provides a data processing method and device, which can avoid the influence of the data after FEC encoding on the DC characteristics of the physical link after inserting other data.

[0007] In a first aspect, the present application provides a data processing method, which can be applied to a first device. The first device can scramble a plurality of first data to obtain a plurality of second data, and further encode the plurality of second data by FEC to obtain a plurality of third data. After obtaining the plurality of third data, the first device can perform bit pair interleaving on the plurality of third data to obtain fourth data, and insert the fourth data into an inner code data stream. By inserting the fourth data into the inner code data stream, the transmission rate of the physical link corresponding to the integer multiple of the frequency of the crystal oscillator when the inner code data stream with the fourth data inserted is transmitted on the physical link. Moreover, the fourth data is obtained after the scrambling process, and therefore, inserting the fourth data into the inner code data stream does not affect the DC characteristic of the physical link. In addition, the plurality of first data is processed respectively to obtain the fourth data, which improves the processing efficiency of the plurality of first data. The DC characteristic can also be referred to as DC balance.

[0008] In a possible implementation, the first data is data to be inserted into the inner code data stream. As an example, the first data is pad data. That is, by using the present application, in the scenario of inserting the pad data into the inner code data stream, the DC characteristic of the physical link is not affected by the insertion of the pad data, and the plurality of first data inserted can be processed respectively, thereby improving the processing efficiency of the first data.

[0009] In a possible implementation, the length of the first data is 120 bits. For example, when the first data is pad data, the length of the first data is 120 bits. By using the present application, the plurality of 120 bits can be processed (scrambled and encoded) respectively, thereby improving the processing efficiency of the plurality of 120 bits.

[0010] In one possible implementation, considering that the valid information in the first data may be a significant factor affecting the DC characteristics of the physical link, the valid information in the first data can be scrambled. In one example, the valid information in the first data can be carried by 114 bits in the first data; therefore, scrambling these 114 bits yields the second data. In other words, each 114 bits of the plurality of first data can be scrambled separately to obtain the plurality of second data. In another example, the valid information in the first data can be carried by the in-band signaling field (IBSF) of the first data; therefore, the IBSF of the first data can be scrambled to obtain the second data. In other words, each IBSF of the plurality of first data can be scrambled separately to obtain the plurality of second data. Here, the IBSF of the first data can be one of the 114 bits in the first data. Using this method, the insertion of first data can effectively prevent it from affecting the DC characteristics of the physical link.

[0011] In one possible implementation, the 114 bits carrying valid information in the first data can be the last 114 bits of the first data. In other words, in one example, for each piece of first data, the last 114 bits of the first data can be scrambled to obtain the second data. Using this method, the insertion of first data can effectively avoid affecting the DC characteristics of the physical link.

[0012] In one possible implementation, for any second data, the second data can be encoded using an internal code to obtain third data, which is an internal codeword. In other words, the multiple second data can be encoded using internal codes respectively to obtain internal codewords corresponding to each of the multiple second data. In this scenario, the third data may include 128 bits. The first 120 bits of the third data are the first data, and the last 8 bits are a check bit obtained based on the first data.

[0013] In one possible implementation, the 6 bits in the first data are part or all of a frame alignment sequence (FAS) field. Each FAS field in the first data carries a fixed sequence corresponding to the first data. The FAS field is used by the receiver to identify padding data. In this scenario, the remaining 114 bits in the first data (excluding the 6 bits) carry valid information. In this scenario, the remaining 114 bits can be scrambled, which can both prevent padding data from affecting the DC characteristics of the physical link and enable the receiver to identify padding data based on the FAS field. The FAS is also known as the frame alignment sequence.

[0014] In one possible implementation, the first 6 bits of the first data are part or all of the FAS field, and correspondingly, the last 114 bits of the first data are used to carry valid information. In this scenario, the last 114 bits of the first data can be scrambled. This avoids the padding data from affecting the DC characteristics of the physical link, and also allows the receiver to identify the padding data based on the FAS field.

[0015] In one possible implementation, the scrambler that scrambles the multiple first data points separately uses a pseudo-random binary sequence (PRBS), such as PRBS9 or PRBS13. PRBS9 can also be referred to as a 9th-order PRBS, and PRBS13 as a 13th-order PRBS.

[0016] In one possible implementation, the polynomial corresponding to PRBS9 includes x 9 +x 5 +1, the polynomial corresponding to PRBS13 includes 1+x+x 2 +x 12 +x 13 .

[0017] In one possible implementation, the length of the fourth data is the sum of the lengths of eight third data. In a scenario where the length of the first data is 120 bits, the multiple first data consist of eight first data, and the length of the third data is 128 bits, the length of the fourth data is 1024 bits. That is, using this scheme, in a scenario where eight pad codewords (i.e., 1024 bits) are inserted every 8 × 1088 internal codewords, the processing efficiency for eight pad codewords can be improved.

[0018] Secondly, this application provides a data processing method, which can be applied, for example, to a first device. The first device can perform FEC encoding on multiple first data to obtain multiple second data, and further, scramble the multiple second data to obtain multiple third data. After obtaining the multiple third data, the multiple third data can be interleaved bit pairs to obtain fourth data, and the fourth data can be inserted into the internal code data stream. By using this scheme, inserting the fourth data into the internal code data stream ensures that when the internal code data stream with the fourth data inserted is transmitted on the physical link, the transmission rate of the physical link corresponds to an integer multiple of the crystal oscillator frequency. Furthermore, since the fourth data is obtained after scrambling, inserting the fourth data into the internal code data stream will not affect the DC characteristics of the physical link. In addition, this scheme processes the multiple first data to obtain the fourth data separately, improving the processing efficiency of the aforementioned multiple first data.

[0019] In one possible implementation, the length of the first data is 120 bits. The second data is obtained by encoding the first data using an internal code, and the length of the second data is 128 bits.

[0020] In one possible implementation, scrambling the plurality of second data to obtain a plurality of third data includes: scrambling 122 bits of each of the plurality of second data to obtain a plurality of third data.

[0021] In one possible implementation, the 122 bits of the second data are the last 122 bits of the second data.

[0022] In one possible implementation, encoding the plurality of first data to obtain a plurality of second data includes: encoding the plurality of first data with internal codes to obtain a plurality of second data.

[0023] In one possible implementation, the 6 bits of the second data are part or all of the frame location sequence (FAS) field.

[0024] In one possible implementation, the first 6 bits of the second data are part or all of the FAS field.

[0025] In one possible implementation, the scrambler that scrambles multiple second data separately uses a pseudo-random bit sequence PRBS9 or PRBS13.

[0026] In one possible implementation, the polynomial corresponding to PRBS9 includes x 9 +x 5 +1, the polynomial corresponding to PRBS9 includes 1+x+x 2 +x12 +x 13 .

[0027] In one possible implementation, the plurality of first data consists of eight first data items, each first data item having a length of 120 bits, each second data item having a length of 128 bits, and the fourth data item having a length of 1024 bits.

[0028] Thirdly, this application provides a data processing method, which can be applied, for example, to a first device. The first device can scramble multiple first data sets to obtain multiple second data sets. Further, the multiple second data sets are inserted into multiple first data streams to obtain multiple second data streams. The multiple second data streams are then encoded to obtain multiple third data streams. The multiple third data streams are then interleaved bit-by-bit to obtain a fourth data stream. Using this scheme, first data sets can be inserted into data streams encoded from first data streams. Since scrambling is performed on the first data sets before insertion, inserting the first data sets into the data streams encoded from first data streams does not affect the DC characteristics of the physical link. Furthermore, this scheme processes multiple first data sets separately, which also improves the processing efficiency of the aforementioned multiple first data sets.

[0029] In one possible implementation, each of the first data includes a portion or all of the 6-bit frame location sequence (FAS) field.

[0030] In one possible implementation, the first 6 bits of each of the first data are part or all of the FAS field.

[0031] In one possible implementation, the scrambler that scrambles the multiple first data separately uses a pseudo-random bit sequence PRBS9 or PRBS13.

[0032] In one possible implementation, the polynomial corresponding to PRBS9 includes x 9 +x 5 +1, the polynomial corresponding to PRBS13 includes 1+x+x 2 +x 12 +x 13 .

[0033] In one possible implementation, the step of scrambling the plurality of first data to obtain the plurality of second data includes: scrambling 114 bits of each of the plurality of first data to obtain the plurality of second data.

[0034] In one possible implementation, the 114 bits of each first data are the last 114 bits of each first data.

[0035] In one possible implementation, FEC encoding is performed on the plurality of second data streams to obtain a plurality of third data streams, including: internal code encoding is performed on the plurality of second data streams to obtain the plurality of third data streams.

[0036] Fourthly, embodiments of this application provide a data processing apparatus, the apparatus including a processing unit, which may specifically include a scrambling subunit, an encoding subunit, an interleaving subunit, and an insertion subunit. The scrambling subunit is used to scramble multiple first data to obtain multiple second data; the encoding subunit is used to encode the multiple second data to obtain multiple third data; the interleaving subunit is used to perform bit-pair interleaving on the multiple third data to obtain fourth data; and the insertion subunit is used to insert the fourth data into an internal code data stream.

[0037] In one possible implementation, the first data has a length of 120 bits, and the third data has a length of 128 bits.

[0038] In one possible implementation, scrambling the plurality of first data to obtain the plurality of second data includes: scrambling the 114 bits of each of the plurality of first data to obtain the plurality of second data.

[0039] In one possible implementation, the 114 bits of each first data are the last 114 bits of each first data.

[0040] In one possible implementation, the step of scrambling the plurality of first data to obtain the plurality of second data includes: scrambling the in-band signal field (IBSF) of each of the plurality of first data to obtain the plurality of second data.

[0041] In one possible implementation, the step of performing FEC encoding on the plurality of second data to obtain a plurality of third data includes: performing internal code encoding on the plurality of second data to obtain a plurality of third data.

[0042] In one possible implementation, the first 6 bits are part or all of the frame location sequence (FAS) field.

[0043] In one possible implementation, the first 6 bits of the first data are part or all of the frame location sequence (FAS) field.

[0044] In one possible implementation, the scrambler that scrambles the multiple first data separately uses a pseudo-random bit sequence PRBS9 or PRBS13.

[0045] In one possible implementation, the polynomial corresponding to PRBS9 includes x 9 +x 5 +1, the polynomial corresponding to PRBS13 includes 1+x+x 2 +x 12 +x 13 .

[0046] In one possible implementation, the first data is filler data.

[0047] In one possible implementation, the plurality of first data includes eight first data, each of which has a length of 120 bits, each of which has a length of 128 bits, and the fourth data has a length of 1024 bits.

[0048] Fifthly, this application provides a data processing apparatus, the apparatus comprising a processing unit, the processing unit including an encoding subunit, a scrambling subunit, an interleaving subunit, and an insertion subunit. The encoding subunit is used to encode a plurality of first data to obtain a plurality of second data; the scrambling subunit is used to scramble the plurality of second data to obtain a plurality of third data; the interleaving subunit is used to perform bit-pair interleaving on the plurality of third data to obtain fourth data; and the insertion subunit is used to insert the fourth data into an internal code data stream.

[0049] In one possible implementation, the length of the first data is 120 bits, and the length of the second data is 128 bits.

[0050] In one possible implementation, scrambling the plurality of second data to obtain a plurality of third data includes: scrambling 122 bits of each of the plurality of second data to obtain a plurality of third data.

[0051] In one possible implementation, the 122 bits of the second data are the last 122 bits of the second data.

[0052] In one possible implementation, the step of performing FEC encoding on the plurality of first data to obtain a plurality of second data includes: performing internal code encoding on the plurality of first data to obtain a plurality of second data.

[0053] In one possible implementation, the 6 bits of the second data are part or all of the frame location sequence (FAS) field.

[0054] In one possible implementation, the first 6 bits of the second data are part or all of the frame location sequence (FAS) field.

[0055] In one possible implementation, the scrambler that scrambles multiple second data separately uses a pseudo-random bit sequence PRBS9 or PRBS13.

[0056] In one possible implementation, the polynomial corresponding to PRBS9 includes x 9 +x 5 +1, the polynomial corresponding to PRBS9 includes 1+x+x 2 +x 12 +x 13 .

[0057] In one possible implementation, the plurality of first data includes eight first data, each first data having a length of 120 bits, each second data having a length of 128 bits, and the fourth data having a length of 1024 bits.

[0058] Sixthly, this application provides a data processing apparatus, the apparatus comprising a processing unit, the processing unit comprising a scrambling subunit, an insertion subunit, an encoding subunit, and an interleaving subunit. The scrambling subunit is used to scramble a plurality of first data streams to obtain a plurality of second data streams; the insertion subunit is used to insert the plurality of second data streams into a plurality of first data streams to obtain a plurality of second data streams; the encoding subunit is used to perform FEC encoding on the plurality of second data streams to obtain a plurality of third data streams; and the interleaving subunit is used to interleave the plurality of third data streams bit-pairs to obtain a fourth data stream.

[0059] In one possible implementation, each of the first data includes a portion or all of the 6-bit Frame Location Sequence (FAS) field.

[0060] In one possible implementation, the first 6 bits of each of the first data are part or all of the FAS field.

[0061] In one possible implementation, the scrambler that scrambles the multiple first data separately uses a pseudo-random bit sequence PRBS9 or PRBS13.

[0062] In one possible implementation, the polynomial corresponding to PRBS9 includes x 9 +x 5 +1, the polynomial corresponding to PRBS13 includes 1+x+x 2 +x 12 +x 13 .

[0063] In one possible implementation, the step of scrambling the plurality of first data to obtain the plurality of second data includes: scrambling 114 bits of each of the plurality of first data to obtain the plurality of second data.

[0064] In one possible implementation, the 114 bits of each first data are the last 114 bits of each first data.

[0065] In one possible implementation, FEC encoding is performed on the plurality of second data streams to obtain a plurality of third data streams, including: internal code encoding is performed on the plurality of second data streams to obtain the plurality of third data streams.

[0066] In a seventh aspect, this application provides an apparatus comprising a processor configured to perform data processing operations as described in the first aspect and any one of the methods described in the first aspect above; or, the processor configured to perform data processing operations as described in the second aspect and any one of the methods described in the second aspect above; or, the processor configured to perform data processing operations as described in the third aspect and any one of the methods described in the third aspect above.

[0067] In one possible implementation, the device further includes a communication interface for performing data transmission and reception operations as described in the first aspect and any one of the methods described in the first aspect above; or, the communication interface is used to perform data transmission and reception operations as described in the second aspect and any one of the methods described in the second aspect above. Alternatively, the communication interface is used to perform data transmission and reception operations as described in the third aspect and any one of the methods described in the third aspect above.

[0068] In one possible implementation, the device further includes a memory for storing instructions or computer programs, and a processor for executing the instructions or computer programs in the memory to trigger the method described in the first aspect and any one of the first aspects above; or, the processor is configured to execute the instructions or computer programs in the memory to perform the method described in the second aspect and any one of the second aspects above. Alternatively, the processor is configured to execute the instructions or computer programs in the memory to perform the method described in the third aspect and any one of the third aspects above.

[0069] Eighthly, this application provides an apparatus comprising a processing circuit configured to perform data processing operations as described in the first aspect and any one of the methods described in the first aspect above; or, the processing circuit configured to perform data processing operations as described in the second aspect and any one of the methods described in the second aspect above; or, the processing circuit configured to perform data processing operations as described in the third aspect and any one of the methods described in the third aspect above.

[0070] In one possible implementation, the device further includes an interface circuit for performing data transmission and reception operations as described in the first aspect and any one of the methods described in the first aspect above; or, the interface circuit is used to perform data transmission and reception operations as described in the second aspect and any one of the methods described in the second aspect above. Alternatively, the interface circuit is used to perform data transmission and reception operations as described in the third aspect and any one of the methods described in the third aspect above.

[0071] Ninthly, this application provides a chip, including an interface circuit and a processing circuit, the chip being used to perform the method described in the first aspect and any one of the first aspects above; or, to perform the method described in the second aspect and any one of the second aspects above; or, to perform the method described in the third aspect and any one of the third aspects above.

[0072] In a tenth aspect, this application provides an optical module, including an interface circuit and a processing circuit, wherein the optical module is used to perform the method described in the first aspect and any one of the first aspects above; or, to perform the method described in the second aspect and any one of the second aspects above; or, to perform the method described in the third aspect and any one of the third aspects above.

[0073] In one aspect, this application provides a computer-readable storage medium, including instructions or a computer program that, when run on a computer, causes the computer to perform the methods described in the first aspect and any one of the first aspects above, or, when run on a computer, causes the computer to perform the methods described in the second aspect and any one of the second aspects above, or, when run on a computer, causes the computer to perform the methods described in the third aspect and any one of the third aspects above.

[0074] In a twelfth aspect, this application provides a computer program product comprising instructions or a computer program, which, when run on a computer, causes the computer to perform the methods described in the first aspect and any one of the first aspects above, or causes the computer to perform the methods described in the second aspect and any one of the second aspects above, or causes the computer to perform the methods described in the third aspect and any one of the third aspects above. Attached Figure Description

[0075] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments recorded in this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0076] Figure 1a This is a schematic diagram of the structure of a communication device provided in an embodiment of this application;

[0077] Figure 1b This is a schematic diagram of the structure of another communication device provided in an embodiment of this application;

[0078] Figure 1c A schematic diagram illustrating the operations included in an internal code FEC provided in an embodiment of this application;

[0079] Figure 2 A flowchart illustrating a data processing method provided in an embodiment of this application;

[0080] Figure 3 A schematic diagram illustrating a data processing method provided in an embodiment of this application;

[0081] Figure 4 A flowchart illustrating a data processing method provided in an embodiment of this application;

[0082] Figure 5 A schematic diagram illustrating a data processing method provided in an embodiment of this application;

[0083] Figure 6 A flowchart illustrating another data processing method provided in an embodiment of this application;

[0084] Figure 7 A schematic diagram illustrating a data processing method provided in an embodiment of this application;

[0085] Figure 8 This is a schematic diagram of the structure of a data processing device provided in an embodiment of this application;

[0086] Figure 9 This is a schematic diagram of the structure of a device provided in an embodiment of this application;

[0087] Figure 10 This is a schematic diagram of the structure of a device provided in an embodiment of this application;

[0088] Figure 11 This is a schematic diagram of the structure of a chip or optical module provided in an embodiment of this application. Detailed Implementation

[0089] This application provides a data processing method and apparatus that can prevent FEC-encoded data from affecting the DC characteristics of the physical link after inserting other data.

[0090] In scenarios where Ethernet interfaces support FEC encoding, the physical link's transmission rate may no longer correspond to an integer multiple of the crystal oscillator frequency due to the introduction of parity bits. For example, if the internal code uses (128, 120) encoding (encoding 120 bits of data results in a 128-bit codeword with an 8-bit parity bit), and assuming the actual physical link transmission rate is 212.5 Gbps, and the signal transmitted on the physical link is obtained using four-pulse amplitude modulation (PAM4), then the corresponding baud rate is 212.5 / 2 = 106.25 gigabits (GBd). After internal code encoding, this 106.25 GBd transmission baud rate will be increased to approximately 113.333 GBd, where 106.25 * 128 / 120 ≈ 113.333. However, 113.333 is not an integer multiple of the crystal oscillator frequency of 156.25 MHz.

[0091] To ensure that the transmission rate of the physical link remains an integer multiple of the crystal oscillator frequency when the data stream encoded via the internal code is transmitted over the physical link, a certain amount of other data can be inserted at regular intervals of a certain number of internal code words. For example, inserting 1024 bits of padding every 8704 internal code words will ensure that the transmission rate of the physical link is an integer multiple of the corresponding crystal oscillator frequency. Here, the 1024-bit pad corresponds to 8 internal code words.

[0092] Adding extra pad codes can further increase the physical link speed, leading to bandwidth waste in bandwidth-constrained scenarios. To avoid bandwidth waste, the inserted pad codes can be used to transmit valid information, such as control information. This control information includes, but is not limited to, information used to instruct adjustments to optical device parameters, adjust optical module electrical characteristics, announce signal transmission and reception quality, negotiate the switching of the FEC interleaver, etc. In one example, each pad codeword consists of 128 bits, and its structure can be shown in Table 1 below:

[0093] Table 1

[0094]

[0095] Eight pad codewords can be interleaved at the bit-pair level and inserted into the internal code data stream before being sent to the physical link. The content of the IBSF field in the pad affects the DC characteristic of the physical link. The DC characteristic can be understood as a state where the number of 1s and 0s in the data stream transmitted on the physical link is approximately equal, or as a technique that ensures that the number of 1s and 0s in the data stream transmitted on the physical link is approximately equal. Affecting the DC characteristic of the physical link means causing the corresponding DC value of the physical link to be non-zero, thus rendering the circuitry related to the physical link unusable or of poor quality. The circuitry related to the physical link mentioned here can be, for example, the circuitry of the transmitting component and / or the receiving component. The transmitting and receiving components mentioned here can be, for example, serializers / deserializers (SerDes).

[0096] The bit pair interleaving mentioned here can be, for example, interleaving with PAM4 symbols, where one PAM4 symbol can represent 2 bits of logical information.

[0097] To prevent inserted pad codewords from affecting the DC characteristics of the physical link, the inserted pad codewords can be scrambled. As an example, multiple inserted pad codewords (such as the aforementioned 8 pad codewords) can be scrambled as a whole. However, scrambling multiple pad codewords as a whole results in low data processing efficiency.

[0098] In view of this, embodiments of this application provide a data processing method and apparatus that can avoid inserting other data into the internal code data stream and thus affecting the DC characteristics of the physical link, and can improve the efficiency of inserting other data into the internal code data stream.

[0099] The internal code data stream mentioned in the embodiments of this application refers to the data stream obtained through internal code encoding.

[0100] The Ethernet interface mentioned in this application includes an Ethernet media access control (MAC) layer device and a physical layer (PHY) device that support data transmission at a certain rate.

[0101] See Figure 1a , Figure 1a This is a schematic diagram of a communication device provided in an embodiment of this application. Figure 1a As shown:

[0102] Both the transmitting and receiving communication devices include: a MAC layer device ( Figure 1a In short, MAC and physical layer devices ( Figure 1aThe physical layer (PHY) is abbreviated as PHY in Chinese. The physical layer components include: the physical coding sublayer (PCS), the physical medium attachment (PMA) sublayer, and the physical medium dependent (PMD) sublayer. PCS, PMA, and PMD are PHY components. Additionally, a reconciliation sublayer (RS) may be included between the MAC layer and the physical layer. RS and PCS can communicate via a medium-independent interface (MII) channel. The MII channel can be a virtual or logical channel. In some scenarios, PCS may also be referred to as FEC.

[0103] In one example, the aforementioned MAC layer device can be a MAC chip, and the physical layer device can be a PHY chip.

[0104] In another example, the aforementioned MAC layer device and physical layer device can be different functional circuits on the same chip.

[0105] When transmitting data, communication devices can process the data according to the seven-layer model of Open Systems Interconnection (OSI). The first layer of the OSI seven-layer model is the Physical Layer, the second layer is the Data Link Layer, and the Data Link Layer includes the MAC layer. The Physical Layer can include the aforementioned PCS, PMA, and PMD.

[0106] The MAC layer of the transmitting communication device can generate MAC frames. The MAC layer of the transmitting communication device sends the MAC frames to the physical layer of the transmitting communication device. In scenarios where an RS (Responder Stream) is included between the MAC layer and the physical layer, the RS can convert the serial MAC frames into a parallel data stream and transmit this data stream to the PCS (Programmable Gate Stream) through the MII (Multi-Input Interchange) channel.

[0107] The PCS can process data streams received through the MII channel and has FEC functionality. In a specific example, the PCS can first encode (e.g., 64B / 66B encoding) and rate match the data stream, and then transcode (e.g., 256B / 257B transcoding) the encoded and rate-matched data stream. Further, scrambling is performed on the transcoded data stream. After scrambling, an alignment marker (AM) is inserted into the scrambled data stream, adding AM to it. After adding AM, FEC encoding is performed on the AM-encoded data stream, and then interleaving and distribution are performed to distribute the interleaved data to m PCS lanes connected to the PMA. A "PCS lane" can be abbreviated as "PCSL". In one example, FEC encoding can be performed using Reed-Solomon (RS) codes. "FEC encoding using RS codes" can also be called RS-FEC encoding. Correspondingly, the FEC codewords obtained by encoding can be called RS-FEC codewords.

[0108] Currently, for Ethernet interfaces of 800GE (800 Gigabit Ethernet) and below, the bandwidth of a single PCSL is 25 Gbps. Therefore, for a 100GE Ethernet interface, the number of PCSLs is 4; for a 200GE Ethernet interface, the number of PCSLs is 8; for a 400GE Ethernet interface, the number of PCSLs is 16; and for an 800GE Ethernet interface, the number of PCSLs is 32. For a 1.6TE Ethernet interface, the bandwidth of a single PCSL is 100 Gbps, and the number of PCSLs is 16.

[0109] PMA can perform m:n bit multiplexing on data from PCS (i.e., data from m PCSLs), mapping the data transmitted in the m PCSLs to n physical channels, so that the data carried by these n physical channels can be subsequently sent to the receiving communication device. The n physical channels can be physical channels connecting the sending and receiving communication devices. The n physical channels can also be internal physical channels of the sending communication device, such as attachment unit interfaces (AUIs). When the n physical channels are internal physical channels of the sending communication device, the sending communication device can further map the data on the internal physical channels of the sending communication device to the physical channels connecting the sending and receiving communication devices to send the data to the receiving communication device. Wherein:

[0110] The physical layer of the receiving communication device also includes PMD, PMA, and PCS. The operations performed by the physical layer of the receiving communication device are the inverse operations performed by the physical layer of the data sending end, which will not be described in detail here.

[0111] Additionally, an internal code FEC is inserted between PMA and PMD for FEC encoding and decoding. As an example, the FEC codeword obtained by encoding the sender's internal code FEC using internal code FEC can be called the FEC internal code codeword.

[0112] For reference Figure 1b To understand, Figure 1b This is a schematic diagram of another communication device provided in an embodiment of this application. Figure 1b As shown, the physical layer of the communication device supporting concatenated coding includes: PCS supporting FEC function, PMA 101, PMA102, internal code FEC, and PMD. PMA101 and PMA 102 interact via AUI. Specifically:

[0113] PCS and PMA 101 can belong to the first chip, while PMA102, internal code FEC, and PMD can belong to the optical module.

[0114] The inner code FEC performs operations related to the inner code.

[0115] In one example, the operations included in the internal code FEC can be referenced. Figure 1c To understand, Figure 1c This is a schematic diagram illustrating the operations included in an internal code FEC provided in an embodiment of this application.

[0116] like Figure 1c As shown:

[0117] For the transmitting communication device, the operations performed by the internal code FEC include: convolutional interleaving, 1:8 120-bit block distribution, internal code FEC processing, 8:1 four-level pulse amplitude modulation 4 (PAM4) interleaving, 8×128-bit pad insertion, and other processing. Internal code FEC processing may include circular shift and internal code FEC encoding, while other processing includes PAM4 encoding.

[0118] After performing a 1:8 120-bit block distribution, eight data streams are obtained, each consisting of multiple 120-bit data blocks. These eight data streams are then encoded using internal code, resulting in eight encoded data streams, each containing multiple internal codewords. Correspondingly, during the PAM4 interleaving stage, bit-pair interleaving is performed on these eight encoded data streams. Furthermore, every eight 1088-bit internal codewords, eight pad codewords are inserted (i.e., 1024-bit pad insertion).

[0119] Correspondingly, for the receiving communication device, the operation performed by its inner code FEC is the inverse operation of the inner code FEC operation performed by the transmitting device. Specifically, it may include: other processing, inner code FEC synchronization and pad removal, 1:8 PAM4 deinterleaving, inner code FEC processing, 120-bit block multiplexing, and de-convolutional de-interweaving. Among these, inner code FEC processing may include cyclic shifting and inner code FEC decoding, while other processing includes PAM4 encoding, etc., which will not be described in detail here.

[0120] Next, the solutions provided by the embodiments of this application will be described in conjunction with the accompanying drawings.

[0121] See Figure 2 The figure is a flowchart illustrating a data processing method provided in an embodiment of this application.

[0122] Figure 2 The method shown can be applied to a first device, which may be, for example, a network device or a server, or a component of a network device, such as a single board, network card, or line card. Alternatively, the first device may be a processing board integrating graphics processing unit (GPU) or neural network processing unit (NPU) functionality. The first device may also be a functional module or chip on a network device; this application embodiment does not specifically limit the specific implementation. The chip mentioned herein includes, but is not limited to, physical layer (PHY) chips or chips on optical modules. The first device may also be an optical module. In this application, the first device can correspond to... Figure 1a to Figure 1c The transmitting end communication device in the middle.

[0123] Figure 2 The method shown includes the following steps S101-S104.

[0124] S101: Scramble multiple first data to obtain multiple second data.

[0125] In this application, the first data is the data to be inserted into the internal code data stream. As an example, the first data is padding data. In some scenarios, padding data may be referred to as padding messages (pad massage). Of course, the first data may not be padding data, but other data; this application embodiment does not specifically limit this.

[0126] In this application, multiple first data are scrambled to obtain multiple second data, wherein each of the multiple second data corresponds to one of the multiple first data.

[0127] In one example, the first data is padding data. In the specific implementation of S101, the eight padding data can be scrambled to obtain eight second data.

[0128] The embodiments of this application do not specifically limit the length of the first data. In one example, the length of the first data is 120 bits. For example, when the first data is padding data, the length of the first data is 120 bits.

[0129] In this application, in a specific implementation of S101, for any first data, all or part of the bits in the first data can be scrambled to obtain the second data.

[0130] As a concrete example, considering that the valid information in the first data may be a significant factor affecting the DC characteristics of the physical link, the valid information in the first data can be scrambled. In one example, the valid information in the first data can be carried by 114 bits in the first data; therefore, scrambling these 114 bits yields the second data. In other words, each of the multiple sets of first data can be scrambled individually to obtain the multiple sets of second data. In another example, the valid information in the first data can be carried by the IBSF (Independent First Format) of the first data; therefore, scrambling these IBSFs yields the second data. In other words, each of the multiple sets of first data can be scrambled individually to obtain the multiple sets of second data. Here, the IBSF of the first data can be one of the 114 bits in the first data.

[0131] In one example, the 114 bits carrying valid information in the first data can be the last 114 bits of the first data. In other words, the last 114 bits of each of the plurality of first data can be scrambled to obtain the plurality of second data.

[0132] In one example, the first 6 bits of the first data are part or all of the FAS field, and the FAS field of each first data item is used to carry a fixed sequence corresponding to itself. The FAS field is used by the receiver to identify the padding data. In this scenario, the other 114 bits of the first data, excluding the 6 bits, are used to carry valid information. In this scenario, the other 114 bits of the first data, excluding the 6 bits, can be scrambled, which can both prevent the padding data from affecting the DC characteristics of the physical link and enable the receiver to identify the padding data based on the FAS field. In one example, the first 6 bits of the first data are part or all of the FAS field, and in this scenario, the last 114 bits of the first data carry valid information.

[0133] In one example, when 6 bits of the first data are part of the FAS field, the FAS fields included in multiple first data can constitute the complete FAS field. For example, if there are 8 first data, the complete FAS field consists of 48 bits. For example, the first 6 bits of the 8 first data constitute the complete FAS field. For instance, the 48 bits of the complete FAS field could be "01011001 01010010 01100100 1010011010101101 10011011". This 48 bits of the complete FAS field are sent to the physical link in order from most significant bit to least significant bit. In the example above, the most significant bit of the FAS field is 0, and the least significant bit is 1; that is, the complete FAS field represents the order from most significant bit to least significant bit from left to right. The FAS fields contained in the first 8 data are: 01 0110, 01 10 10, 10 01 11, 01 00 01, 01 10 10, 01 10 01, 00 01 10 and 10 10 11.

[0134] In addition, for ease of description, although the 6 bits in the first data may be part of the FAS field, in this application, the 6 bits in the first data are also referred to as the "FAS field of the first data".

[0135] In this application, a scrambler can be used to scramble each piece of first data separately. The embodiments of this application do not specifically limit the scrambler; in one example, the scrambler can be PRBS9 or PRBS13, that is, the first data is scrambled using PRBS9 or PRBS13 to prevent the first data from affecting the DC specificity of the physical link. In one example, the polynomial corresponding to PRBS9 is x. 9 +x 5+1, the polynomial corresponding to PRBS13 is 1+x+x 2 +x 12 +x 13 .

[0136] Of course, the polynomial of PRBS9 can also be other polynomials, and the polynomial of PRBS13 can also be other polynomials, which will not be listed here.

[0137] The length of the second data is the same as the length of the first data. For example, if the length of the first data is 120 bits, then the length of the second data is also 120 bits.

[0138] S102: Perform FEC encoding on the plurality of second data respectively to obtain a plurality of third data.

[0139] After obtaining the plurality of second data, each of the plurality of second data can be FEC encoded to obtain a plurality of third data. The plurality of second data and the plurality of third data correspond one-to-one; that is, one second data, after FEC encoding, yields one third data.

[0140] In a specific example, for any second data, the second data can be encoded using internal codes to obtain third data, which is an internal codeword. In other words, the multiple second data can be encoded using internal codes respectively to obtain internal codewords corresponding to each of the multiple second data. In this scenario, the third data may include 128 bits. The structure of the third data can be referred to in Table 1, where the first 120 bits of the third data are the first data, and the last 8 bits are a check bit obtained based on the first data.

[0141] S103: Interleave the multiple third data pairs bit by bit to obtain the fourth data.

[0142] After obtaining multiple third data sets, bit pairs can be interleaved to obtain fourth data. The fourth data is a bitstream obtained by interleaving the multiple third data sets. The bit pair interleaving mentioned here can be based on PAM symbols, for example, it can be based on PAM4 symbols, where one PAM4 symbol consists of 2 bits.

[0143] In this application, the length of the fourth data is the sum of the lengths of the eight third data. In a scenario where the length of the first data is 120 bits, the multiple first data consists of eight first data, and the length of the third data is 128 bits, the length of the fourth data is 1024 bits.

[0144] S104: Insert the fourth data into the internal code data stream.

[0145] After obtaining the fourth data, it can be inserted into the internal code data stream. In one example, the internal code data stream may include several internal code codewords. For instance, the internal code data stream may include 8*1088 (i.e., 8704) internal code codewords, meaning the length of the internal code data stream is 8*1088*128 bits. Here, S204 can correspond to... Figure 1c "8×128-bit padding data insertion".

[0146] In one example, after inserting a fourth data stream into the internal code data stream, the internal code data stream with the inserted fourth data can be sent to the physical link. Since the fourth data is obtained after scrambling, the internal code data stream with the inserted fourth data, when transmitted on the physical link, will not affect the DC characteristics of the physical link. Furthermore, Figure 2 The proposed solution processes the multiple first data points that yield the fourth data point separately, rather than treating them as a whole, which improves the processing efficiency of the aforementioned multiple first data points.

[0147] Next, combined Figure 3 ,introduce Figure 2 A specific embodiment of the method shown.

[0148] Figure 3 This is a schematic diagram illustrating a data processing method provided in an embodiment of this application. Figure 3 As shown:

[0149] For the eight pad messages (pad0 to pad7), each of these eight pad messages is scrambled. Then, the scrambled data of each pad message is encoded using internal encoding to obtain eight pad codewords (pad codewords, pad cws). Among them:

[0150] The padding codeword obtained by scrambling the data of pad0 message and then encoding it with internal code is pad0 cw; the padding codeword obtained by scrambling the data of pad1 message and then encoding it with internal code is pad1 cw; and so on, the padding codeword obtained by scrambling the data of pad7 message and then encoding it with internal code is pad7 cw.

[0151] For the eight pad cws from pad0 to pad7, interleaving is performed at a granularity of PAM4 symbols (i.e., 2 bits) to obtain the interleaved data stream pad<1023,0>. This interleaved data stream pad<1023,0> is then inserted into the internal code data stream. The length of pad<1023,0> is 1024 bits. Wherein:

[0152] Figure 3 The eight pad messages shown are from pad0 to pad7. Figure 2 The method shown includes eight first data points; Figure 3 The data shown is obtained by scrambling the eight pad messages from pad0 to pad7. Figure 2 The method shown has 8 second data points; the 8 first data points and 8 second data points correspond one-to-one. Figure 3 The eight pad cws shown are pad0 cw to pad7 cw, corresponding to Figure 2 The method shown includes eight third data points; Figure 3 The pad<1023,0> shown corresponds to Figure 2 The fourth data in the method shown.

[0153] This application also provides another data processing method, which will be discussed below in conjunction with... Figure 4 This paper introduces the data processing method.

[0154] See Figure 4 The figure is a flowchart illustrating a data processing method provided in an embodiment of this application. Figure 4 The method shown can be applied to the first device. For a description of the first device, please refer to the preceding description of the first device. It will not be repeated here.

[0155] Figure 4 The method shown includes the following steps S201-S204.

[0156] S201: Perform FEC encoding on multiple first data to obtain multiple second data.

[0157] In this application, the first data is the data to be inserted into the internal code data stream. As an example, the first data is padding data. Of course, the first data may not be padding data, but other data; this application does not specifically limit this.

[0158] In this application, multiple first data are respectively FEC encoded to obtain multiple second data, wherein the multiple second data correspond one-to-one with the multiple first data.

[0159] In one example, the first data is padding data. In the specific implementation of S201, the eight padding data can be FEC encoded separately to obtain eight second data.

[0160] The embodiments of this application do not specifically limit the length of the first data. In one example, the length of the first data is 120 bits. For example, when the first data is padding data, the length of the first data is 120 bits.

[0161] In a specific example, for any first data, the first data can be encoded using an internal code to obtain second data, which is an internal code codeword. In other words, the multiple first data can be encoded using internal codes respectively to obtain internal codewords corresponding to the multiple first data. In this scenario, the second data may include 128 bits. The structure of the second data can be referred to in Table 1, where the first 120 bits of the second data are the first data, and the last 8 bits are a check bit obtained based on the first data.

[0162] S202: Scramble the plurality of second data respectively to obtain the third data.

[0163] In this application, in a specific implementation of S202, for any second data, all or part of the bits in the second data can be scrambled to obtain the third data.

[0164] As a concrete example, the first data (e.g., padding data) contains 6 bits that are part or all of the FAS field, and each FAS field of the first data carries a fixed sequence corresponding to itself. Correspondingly, the second data obtained by encoding the first data also includes a 6-bit FAS field, which is used by the receiver to identify the first data (e.g., padding data). Therefore, in one example, in a specific implementation of S202, the other 122 bits of the second data besides the aforementioned 6-bit FAS field can be scrambled, while the aforementioned 6-bit FAS field itself is not scrambled. This approach avoids the padding data affecting the DC characteristics of the physical link while allowing the receiver to identify the padding data based on the FAS field. In one example, the first 6 bits of the first data are part or all of the FAS field; correspondingly, in this scenario, the last 122 bits of the second data can be scrambled.

[0165] In this application, a scrambler can be used to scramble each piece of second data separately. The embodiments of this application do not specifically limit the scrambler; in one example, the scrambler can be PRBS9 or PRBS13, that is, the second data is scrambled using PRBS9 or PRBS13 to prevent the second data from affecting the DC specificity of the physical link. In one example, the polynomial corresponding to PRBS9 is x. 9 +x 5 +1, the polynomial corresponding to PRBS13 is 1+x+x 2 +x 12 +x 13 .

[0166] Of course, the polynomial of PRBS9 can also be other polynomials, and the polynomial of PRBS13 can also be other polynomials, which will not be listed here.

[0167] The length of the third data is the same as the length of the second data. For example, if the length of the second data is 128 bits, then the length of the third data is also 128 bits.

[0168] S203: Interleave the multiple third data pairs to obtain the fourth data.

[0169] After obtaining multiple third data sets, bit pairs can be interleaved to obtain fourth data. The fourth data is a bitstream obtained by interleaving the multiple third data sets. The bit pair interleaving mentioned here can be based on PAM symbols, for example, it can be based on PAM4 symbols, where one PAM4 symbol consists of 2 bits.

[0170] In this application, the length of the fourth data is the sum of the lengths of multiple third data, wherein the length of the third data is the same as the length of the second data. In a scenario where the length of the first data is 120 bits, the length of each second data is 128 bits, and the multiple first data consists of 8 first data, the length of the fourth data is 1024 bits.

[0171] S204: Insert the fourth data into the internal code data stream.

[0172] After obtaining the fourth data, it can be inserted into the internal code data stream. In one example, the internal code data stream may include several internal code codewords. For instance, the internal code data stream may include 8*1088 internal codewords, meaning the length of the internal code data stream is 8*1088*128 bits. Here, S204 can correspond to... Figure 1c "8×128-bit padding data insertion".

[0173] In one example, after inserting a fourth data stream into the internal code data stream, the internal code data stream with the inserted fourth data can be sent to the physical link. Since the fourth data is obtained after scrambling, the internal code data stream with the inserted fourth data, when transmitted on the physical link, will not affect the DC characteristics of the physical link. Furthermore, Figure 4 The proposed solution processes the multiple first data points that yield the fourth data point separately, rather than treating them as a whole, which improves the processing efficiency of the aforementioned multiple first data points.

[0174] Next, combined Figure 5 ,introduce Figure 3 A specific embodiment of the method shown.

[0175] Figure 5 This is a schematic diagram illustrating a data processing method provided in an embodiment of this application. Figure 5 As shown:

[0176] For the eight pad messages (pad0 to pad7), each message is encoded using internal codes, resulting in eight pad codewords (pad cw). Specifically: the pad0 message's internal code encoding yields the pad0 cw; the pad1 message's internal code encoding yields the pad1 cw; and so on, with the pad7 message's internal code encoding yielding the pad7 cw. Each of these eight pad cws (pad0 to pad7 cw) is then scrambled. The scrambled data is then interleaved at a granularity of PAM4 symbols (2 bits), resulting in the interleaved data stream pad<1023,0>. This interleaved data stream pad<1023,0> is then inserted into the internal code data stream. The length of pad<1023,0> is 1024 bits.

[0177] Figure 5 The eight pad messages shown are from pad0 to pad7. Figure 4 The method shown includes eight first data points; Figure 5 The eight pad cws shown are pad0 cw to pad7 cw, corresponding to Figure 4 The method shown includes eight second data points; Figure 5 The data shown is obtained by scrambling the eight pad cws from pad0 cw to pad7 cw. Figure 4 The method shown includes eight third data points;Figure 5 The pad<1023,0> shown corresponds to Figure 4 The fourth data in the method shown.

[0178] This application also provides a data processing method, which will be discussed in conjunction with the following embodiments. Figure 6 This paper introduces the data processing method.

[0179] See Figure 6 The figure is a flowchart illustrating another data processing method provided in an embodiment of this application. Figure 6 The method shown can be applied to the first device. For a description of the first device, please refer to the preceding description of the first device. It will not be repeated here.

[0180] Figure 6 The method shown includes the following steps S301-S304.

[0181] S301: Scramble multiple first data to obtain multiple second data.

[0182] For details regarding the first data and the specific implementation of S301, please refer to the description of S101 above; it will not be repeated here.

[0183] S302: Insert the plurality of second data into the plurality of first data streams respectively to obtain a plurality of second data streams.

[0184] In this application, the number of second data points and the number of first data streams can be the same, and there is a one-to-one correspondence between the second data points and the first data streams. For example, after scrambling eight first data points, eight second data points can be obtained. In specific implementation of S302, the eight second data points can be inserted into eight first data streams to obtain eight second data streams. Specifically, for any one of the eight second data points, it can be inserted into the first data stream corresponding to itself among the eight first data streams. After executing S302, one second data point is inserted into each first data stream, thus multiple second data streams can be obtained. The second data streams are the data obtained by inserting the second data points into the first data streams.

[0185] In this application, the plurality of first data streams may be executed by a first device. Figure 1c The "1:8 120-bit block distribution" shown results in 8 data streams, with one first data stream corresponding to one data stream. In other words, each first data stream can include multiple data blocks of 120 bits in length. In a specific example, each first data stream can include 1088 data blocks of 120 bits in length. Correspondingly, each second data stream can include 1089 data blocks of 120 bits in length.

[0186] S303: Perform FEC encoding on the plurality of second data streams respectively to obtain a plurality of third data streams.

[0187] After obtaining the plurality of second data streams, each of the plurality of second data streams can be encoded to obtain a plurality of third data streams. The plurality of second data streams and the plurality of third data streams correspond one-to-one; that is, one second data stream, after being encoded, yields one third data stream.

[0188] In a specific example, for any second data stream, the second data stream can be encoded using internal code to obtain a third data stream, which is an internal code codeword. In other words, the multiple second data streams can be encoded using internal code respectively to obtain internal codewords corresponding to the multiple second data streams. In this scenario, the third data stream can have multiple internal codewords. The structure of each internal codeword can be referred to Table 1 above. The first 120 bits of the internal codeword are a 120-bit data block in the second data stream, and the last 8 bits are a check bit obtained based on the first 120 bits of the internal codeword.

[0189] In a scenario where each second data stream comprises 1089 data blocks of 120 bits each, each third data stream comprises 1089 internal codewords, each internal codeword being 128 bits long.

[0190] S304: Interleave the multiple third data streams bit pairs to obtain a fourth data stream.

[0191] After obtaining the multiple third data streams, bit-pair interleaving can be performed on the multiple third data streams to obtain a fourth data stream, which is then sent to the physical link. The fourth data stream mentioned here is an internal code data stream with inserted pad codewords. For the specific implementation of S304, please refer to the previous description of bit-pair interleaving; it will not be repeated here.

[0192] As described above, the scheme of this application embodiment can insert other data (i.e., multiple first data) of a certain length at intervals of a certain number of internal codewords, thereby ensuring that the transmission rate of the physical link corresponds to an integer multiple of the crystal oscillator frequency when the fourth data stream is transmitted on the physical link. Furthermore, since the first data is scrambled before insertion, the DC characteristics of the physical link are not affected when the fourth data stream is transmitted on the physical link. Additionally, this scheme processes the multiple first data of the obtained fourth data stream separately, rather than treating them as a whole, which also improves the processing efficiency of the aforementioned multiple first data.

[0193] Next, combinedFigure 7 ,introduce Figure 6 A specific embodiment of the method shown.

[0194] Figure 7 This is a schematic diagram illustrating a data processing method provided in an embodiment of this application. Figure 7 As shown:

[0195] For the eight pad messages (pad0 to pad7), each of them is scrambled. This results in eight scrambled pad messages. These eight scrambled pad messages are then inserted into the eight data streams (stream0 to stream7), resulting in eight data streams (stream0' to stream7'). Specifically:

[0196] The pad message obtained by scrambling the pad0 message is inserted into stream0, resulting in stream0'; the pad message obtained by scrambling the pad1 message is inserted into stream1, resulting in stream0'; and so on, the pad message obtained by scrambling the pad7 message is inserted into stream7, resulting in stream7'.

[0197] Then, internal code encoding is performed on each of the eight data streams from stream0' to stream7', and bit-pair interleaving is further performed on the data obtained from the internal code encoding of these eight data streams. Specifically:

[0198] Figure 7 The eight pad messages shown are from pad0 to pad7. Figure 6 The method shown includes eight first data points; Figure 7 The data shown is obtained by scrambling the eight pad messages from pad0 to pad7. Figure 6 The method shown includes eight second data points; Figure 7 The streams 0 to 7 shown can correspond to Figure 6 The eight first data streams shown; Figure 7 The streams 0' to 7' shown can correspond to Figure 6 The second data stream is shown.

[0199] It should be noted that, although inFigure 6 In the method shown, each first data point is first scrambled to obtain multiple second data points, which are then inserted into multiple first data streams. However, in another example, multiple first data points can be inserted into multiple first data streams separately to obtain multiple seventh data points. These seventh data points are then encoded to obtain multiple eighth data points. For each eighth data point, the first data points included within it are scrambled to obtain ninth data points. Furthermore, bit-pair interleaving is performed on the obtained ninth data points to obtain an inner code data stream.

[0200] Based on the data processing method provided in the above embodiments, this application also provides a corresponding device, which will be described below with reference to the accompanying drawings.

[0201] See Figure 8 The figure is a schematic diagram of the structure of a data processing device provided in an embodiment of this application.

[0202] Figure 8 The data processing device 800 shown can be applied to the first device to perform the steps performed by the first device as provided in the above embodiments.

[0203] like Figure 8 As shown, the device 800 includes a processing unit 801, and optionally, the device 800 further includes a sending unit 802.

[0204] In one example, the device 800 is used to perform the above. Figure 2 or Figure 3 The method shown is for this situation:

[0205] The processing unit 801 is used for:

[0206] Multiple first data are scrambled to obtain multiple second data; the multiple second data are FEC encoded to obtain multiple third data; the multiple third data are bit-pair interleaved to obtain fourth data; and the fourth data is inserted into the internal code data stream.

[0207] The sending unit 802 is used to send an internal code data stream in which the fourth data has been inserted.

[0208] In a specific example, the processing unit 801 includes a scrambling subunit, an encoding subunit, an interleaving subunit, and an insertion subunit. The scrambling subunit is used to scramble multiple first data to obtain multiple second data; the encoding subunit is used to encode the multiple second data to obtain multiple third data; the interleaving subunit is used to perform bit-pair interleaving on the multiple third data to obtain fourth data; and the insertion subunit is used to insert the fourth data into the internal code data stream.

[0209] In one possible implementation, the first data has a length of 120 bits, and the third data has a length of 128 bits.

[0210] In one possible implementation, scrambling the plurality of first data to obtain the plurality of second data includes: scrambling the 114 bits of each of the plurality of first data to obtain the plurality of second data.

[0211] In one possible implementation, the 114 bits of each first data are the last 114 bits of each first data.

[0212] In one possible implementation, the step of scrambling the plurality of first data to obtain the plurality of second data includes: scrambling the in-band signal field (IBSF) of each of the plurality of first data to obtain the plurality of second data.

[0213] In one possible implementation, the step of performing FEC encoding on the plurality of second data to obtain a plurality of third data includes: performing internal code encoding on the plurality of second data to obtain a plurality of third data.

[0214] In one possible implementation, the first 6 bits are part or all of the frame location sequence (FAS) field.

[0215] In one possible implementation, the first 6 bits of the first data are part or all of the frame location sequence (FAS) field.

[0216] In one possible implementation, the scrambler that scrambles the multiple first data separately uses a pseudo-random bit sequence PRBS9 or PRBS13.

[0217] In one possible implementation, the polynomial corresponding to PRBS9 includes x 9 +x 5 +1, the polynomial corresponding to PRBS13 includes 1+x+x 2 +x 12 +x 13 .

[0218] In one possible implementation, the first data is filler data.

[0219] In one possible implementation, the plurality of first data includes eight first data, each of which has a length of 120 bits, each of which has a length of 128 bits, and the fourth data has a length of 1024 bits.

[0220] In another example, the device 800 is used to perform the above. Figure 4 or Figure 5 The method shown is for this situation:

[0221] The processing unit 801 is used for:

[0222] Multiple first data are encoded to obtain multiple second data; the multiple second data are scrambled to obtain multiple third data; the multiple third data are bit-interleaved to obtain fourth data; and the fourth data is inserted into the internal code data stream.

[0223] The sending unit 802 is used to send an internal code data stream in which the fourth data has been inserted.

[0224] In a specific example, the processing unit 801 includes an encoding subunit, a scrambling subunit, an interleaving subunit, and an insertion subunit. The encoding subunit is used to encode multiple first data to obtain multiple second data; the scrambling subunit is used to scramble the multiple second data to obtain multiple third data; the interleaving subunit is used to perform bit-pair interleaving on the multiple third data to obtain fourth data; and the insertion subunit is used to insert the fourth data into the internal code data stream.

[0225] In one possible implementation, the length of the first data is 120 bits, and the length of the second data is 128 bits.

[0226] In one possible implementation, scrambling the plurality of second data to obtain a plurality of third data includes: scrambling 122 bits of each of the plurality of second data to obtain a plurality of third data.

[0227] In one possible implementation, the 122 bits of the second data are the last 122 bits of the second data.

[0228] In one possible implementation, the step of performing FEC encoding on the plurality of first data to obtain a plurality of second data includes: performing internal code encoding on the plurality of first data to obtain a plurality of second data.

[0229] In one possible implementation, the 6 bits of the second data are part or all of the frame location sequence (FAS) field.

[0230] In one possible implementation, the first 6 bits of the second data are part or all of the frame location sequence (FAS) field.

[0231] In one possible implementation, the scrambler that scrambles multiple second data separately uses a pseudo-random bit sequence PRBS9 or PRBS13.

[0232] In one possible implementation, the polynomial corresponding to PRBS9 includes x 9 +x 5 +1, the polynomial corresponding to PRBS9 includes 1+x+x 2 +x 12 +x 13 .

[0233] In one possible implementation, the plurality of first data includes eight first data, each first data having a length of 120 bits, each second data having a length of 128 bits, and the fourth data having a length of 1024 bits.

[0234] In yet another example, the device 800 is used to perform the above. Figure 6 or Figure 7 The method shown is for this situation:

[0235] The processing unit 801 is configured to: scramble multiple first data to obtain multiple second data; insert the multiple second data into multiple first data streams to obtain multiple second data streams; encode the multiple second data streams to obtain multiple third data streams; and interleave the multiple third data streams bit pairs to obtain a fourth data stream.

[0236] The sending unit 802 is used to send the fourth data stream.

[0237] In a specific example, the processing unit 801 includes a scrambling subunit, an insertion subunit, an encoding subunit, and an interleaving subunit. The scrambling subunit is used to scramble multiple first data streams to obtain multiple second data streams; the insertion subunit is used to insert the multiple second data streams into multiple first data streams to obtain multiple second data streams; the encoding subunit is used to perform FEC encoding on the multiple second data streams to obtain multiple third data streams; and the interleaving subunit is used to interleave the multiple third data streams bit pairs to obtain a fourth data stream.

[0238] In one possible implementation, each of the first data includes a portion or all of the 6-bit Frame Location Sequence (FAS) field.

[0239] In one possible implementation, the first 6 bits of each of the first data are part or all of the FAS field.

[0240] In one possible implementation, the scrambler that scrambles the multiple first data separately uses a pseudo-random bit sequence PRBS9 or PRBS13.

[0241] In one possible implementation, the polynomial corresponding to PRBS9 includes x 9 +x 5 +1, the polynomial corresponding to PRBS13 includes 1+x+x 2 +x 12 +x 13 .

[0242] In one possible implementation, the step of scrambling the plurality of first data to obtain the plurality of second data includes: scrambling 114 bits of each of the plurality of first data to obtain the plurality of second data.

[0243] In one possible implementation, the 114 bits of each first data are the last 114 bits of each first data.

[0244] In one possible implementation, FEC encoding is performed on the plurality of second data streams to obtain a plurality of third data streams, including: internal code encoding is performed on the plurality of second data streams to obtain the plurality of third data streams.

[0245] See Figure 9 The figure is a schematic diagram of the structure of a device provided in an embodiment of this application. Figure 9 The device 900 shown includes an interface circuit 901 and a processing circuit 902. The interface circuit 901 is used to receive and / or transmit data, and the processing circuit 902 is used to perform data processing. The interface circuit 901 is optional.

[0246] In a specific example, the device 900 is used to perform the above and Figure 2 The corresponding method for this situation is:

[0247] The processing circuit 902 is used to scramble multiple first data to obtain multiple second data; to perform FEC encoding on the multiple second data to obtain multiple third data; to perform bit-pair interleaving on the multiple third data to obtain fourth data; and to insert the fourth data into the internal code data stream.

[0248] Optionally, the interface circuit 901 is used to send an internal code data stream with the fourth data inserted.

[0249] In yet another specific example, the device 900 is used to perform the above and Figure 4 The corresponding method for this situation is:

[0250] The processing circuit 902 is used to perform FEC encoding on multiple first data to obtain multiple second data; to scramble the multiple second data to obtain multiple third data; to perform bit-pair interleaving on the multiple third data to obtain fourth data; and to insert the fourth data into the internal code data stream.

[0251] Optionally, the interface circuit 901 is used to send an internal code data stream with the fourth data inserted.

[0252] In another specific example, the device 900 is used to perform the above and Figure 6 The corresponding method for this situation is:

[0253] The processing circuit 902 is used to scramble multiple first data to obtain multiple second data; insert the multiple second data into multiple first data streams to obtain multiple second data streams; perform FEC encoding on the multiple second data streams to obtain multiple third data streams; and interleave the multiple third data streams bit pairs to obtain a fourth data stream.

[0254] Optionally, the interface circuit 901 is used to send the fourth data stream.

[0255] See Figure 10 The figure is a schematic diagram of the structure of a device provided in an embodiment of this application.

[0256] In one example Figure 10 The device 1000 shown can be used to execute the data processing method provided in the above method embodiments.

[0257] Please see Figure 10 As shown, device 1000 includes a processor 1010. The number of processors 1010 in device 1000 can be one or more. Figure 10 Taking a processor as an example, processor 1010 is used to execute the data processing method provided in the above method embodiments.

[0258] Processor 1010 may be a central processing unit (CPU), an NP, or a combination of CPU and NP. Processor 1010 may further include hardware chips. The aforementioned hardware chips may be ASICs, programmable logic devices (PLDs), or combinations thereof. The aforementioned PLD may be complex programmable logic devices (CPLDs), field-programmable gate arrays (FPGAs), generic array logic (GALs), or any combination thereof.

[0259] In one example, device 1000 also includes a communication interface 1020 for receiving and / or sending data.

[0260] In a specific example, the device 1000 is used to perform the above and Figure 2 The corresponding method for this situation is:

[0261] The processor 1010 is used to scramble multiple first data to obtain multiple second data; to perform FEC encoding on the multiple second data to obtain multiple third data; to perform bit-pair interleaving on the multiple third data to obtain fourth data; and to insert the fourth data into the internal code data stream.

[0262] Optionally, the communication interface 1020 is used to send an internal code data stream with the fourth data inserted.

[0263] In yet another specific example, the device 1000 is used to perform the above and Figure 4 The corresponding method for this situation is:

[0264] The processor 1010 is used to perform FEC encoding on multiple first data to obtain multiple second data; to scramble the multiple second data to obtain multiple third data; to perform bit-pair interleaving on the multiple third data to obtain fourth data; and to insert the fourth data into the internal code data stream.

[0265] Optionally, the communication interface 1020 is used to send an internal code data stream with the fourth data inserted.

[0266] In another specific example, the device 1000 is used to perform the above and Figure 6 The corresponding method for this situation is:

[0267] The processor 1010 is used to scramble multiple first data to obtain multiple second data; insert the multiple second data into multiple first data streams to obtain multiple second data streams; perform FEC encoding on the multiple second data streams to obtain multiple third data streams; and perform bit-pair interleaving on the multiple third data streams to obtain a fourth data stream.

[0268] Optionally, the communication interface 1020 is used to send the fourth data stream.

[0269] In one example, the device 1000 further includes a memory 1030. The memory 1030 may include volatile memory, such as random-access memory (RAM); the memory 1030 may also include non-volatile memory, such as flash memory, a hard disk drive (HDD), or a solid-state drive (SSD); the memory 1030 may also include combinations of the above types of memory. The memory 1030 may, for example, store the aforementioned first data.

[0270] Optionally, the memory 1030 stores an operating system and programs, executable modules, or data structures, or subsets thereof, or extended sets thereof. The programs may include various operation instructions for implementing various operations. The operating system may include various system programs for implementing various basic services and handling hardware-based tasks. The processor 1010 can read the programs in the memory 1030 to implement the methods provided in the embodiments of this application.

[0271] In one example, processor 1010, communication interface 1020, and memory 1030 can be connected via a bus system or other means, wherein, Figure 10 Taking the connection between China and Israel via the 1040 bus system as an example.

[0272] The bus system 1040 can be a Peripheral Component Interconnect (PCI) bus or an Extended Industry Standard Architecture (EISA) bus, etc. The bus system 1040 can be divided into address bus, data bus, control bus, etc. For ease of representation, Figure 10 The bus is represented by a single thick line, but this does not mean that there is only one bus or one type of bus.

[0273] SeeFigure 11 The figure is a schematic diagram of the structure of a chip or optical module provided in an embodiment of this application. Figure 11 The chip or optical module 1100 shown includes an interface circuit 1101 and a processing circuit 1102. The interface circuit 1101 is used to receive and / or transmit data, and the processing circuit 1102 is used to perform data processing. The interface circuit 1101 is optional.

[0274] In one example, the chip or optical module 1100 can be used to perform the method provided by the first device in the above method embodiments.

[0275] In a specific example, the chip or optical module 1100 is used to perform the above-mentioned functions. Figure 2 The corresponding method for this situation is:

[0276] The processing circuit 1102 is used to scramble multiple first data to obtain multiple second data; to perform FEC encoding on the multiple second data to obtain multiple third data; to perform bit-pair interleaving on the multiple third data to obtain fourth data; and to insert the fourth data into the internal code data stream.

[0277] Optionally, the interface circuit 1101 is used to send an internal code data stream with the fourth data inserted.

[0278] In yet another specific example, the chip or optical module 1100 is used to perform the above-mentioned functions. Figure 4 The corresponding method for this situation is:

[0279] The processing circuit 1102 is used to perform FEC encoding on multiple first data to obtain multiple second data; to scramble the multiple second data to obtain multiple third data; to perform bit-pair interleaving on the multiple third data to obtain fourth data; and to insert the fourth data into the internal code data stream.

[0280] Optionally, the interface circuit 1101 is used to send an internal code data stream with the fourth data inserted.

[0281] In another specific example, the chip or optical module 1100 is used to perform the above-mentioned functions. Figure 6 The corresponding method for this situation is:

[0282] The processing circuit 1102 is used to scramble multiple first data to obtain multiple second data; insert the multiple second data into multiple first data streams to obtain multiple second data streams; encode the multiple second data streams to obtain multiple third data streams; and interleave the multiple third data streams bit pairs to obtain a fourth data stream.

[0283] Optionally, the interface circuit 1101 is used to send the fourth data stream.

[0284] This application provides a computer-readable storage medium, including instructions or a computer program, which, when run on a computer, causes the computer to perform the methods described in the above method embodiments (e.g., Figure 2 to Figure 7 (The method shown in any of the attached figures).

[0285] This application provides a computer program product containing instructions or a computer program, which, when run on a computer, causes the computer to perform the methods described in the above method embodiments (e.g., Figure 2 to Figure 7 (The method shown in any of the attached figures).

[0286] The terms “first,” “second,” “third,” “fourth,” etc. (if present) in the specification, claims, and accompanying drawings of this application are used to distinguish similar objects and are not necessarily used to describe a particular order or sequence. It should be understood that such data can be interchanged where appropriate so that the embodiments described herein can be implemented in a sequence other than that illustrated or described herein. Furthermore, the terms “comprising” and “having,” and any variations thereof, are intended to cover a non-exclusive inclusion; for example, a process, method, system, product, or apparatus that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus.

[0287] Those skilled in the art will clearly understand that, for the sake of convenience and brevity, the specific working processes of the systems, devices, and units described above can be referred to the corresponding processes in the foregoing method embodiments, and will not be repeated here.

[0288] In the embodiments provided in this application, it should be understood that the disclosed systems, apparatuses, and methods can be implemented in other ways. For example, the apparatus embodiments described above are merely illustrative; for instance, the division of units is only a logical business division, and in actual implementation, there may be other division methods. For example, multiple units or components may be combined or integrated into another system, or some features may be ignored or not executed. Furthermore, the coupling or direct coupling or communication connection shown or discussed may be through some interfaces, indirect coupling or communication connection between apparatuses or units, and may be electrical, mechanical, or other forms.

[0289] The units described as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the units can be selected to achieve the purpose of this embodiment according to actual needs.

[0290] Furthermore, the various business units in the embodiments of this application can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit. The integrated unit can be implemented in hardware or as a software business unit.

[0291] If the integrated unit is implemented as a software business unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of this application, in essence, or the part that contributes to the prior art, or all or part of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute all or part of the steps of the methods of the various embodiments of this application. The aforementioned storage medium includes various media capable of storing program code, such as USB flash drives, portable hard drives, read-only memory (ROM), random access memory (RAM), magnetic disks, or optical disks.

[0292] Those skilled in the art will recognize that, in one or more of the examples above, the services described in this invention can be implemented using hardware, software, firmware, or any combination thereof. When implemented in software, these services can be stored in a computer-readable medium or transmitted as one or more instructions or code on a computer-readable medium. Computer-readable media include computer storage media and communication media, wherein communication media include any medium that facilitates the transmission of computer programs from one place to another. Storage media can be any available medium accessible to general-purpose or special-purpose computers.

[0293] The above specific embodiments further illustrate the purpose, technical solution, and beneficial effects of the present invention. It should be understood that the above are merely specific embodiments of the present invention.

[0294] The above embodiments are only used to illustrate the technical solutions of this application, and are not intended to limit it. Although this application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of this application.

Claims

1. A data processing method, characterized by, The method comprises: scrambling a plurality of first data to obtain a plurality of second data; forward error correction (FEC) encoding the plurality of second data to obtain a plurality of third data; bit pair interleaving the plurality of third data to obtain fourth data; inserting the fourth data into an inner code data stream.

2. The method of claim 1, wherein, The first data has a length of 120 bits, and the third data has a length of 128 bits.

3. The method according to claim 1 or 2, characterized in that, The scrambling the plurality of first data to obtain the plurality of second data comprises: scrambling 114 bits of each of the plurality of first data to obtain the plurality of second data.

4. The method of claim 3, wherein, The 114 bits of each of the first data are the last 114 bits of each of the first data.

5. The method according to claim 1 or 2, characterized in that, The scrambling the plurality of first data to obtain the plurality of second data comprises: scrambling an in-band signal field (IBSF) of each of the plurality of first data to obtain the plurality of second data.

6. The method according to any one of claims 1 to 5, characterized in that, The FEC encoding the plurality of second data to obtain the plurality of third data comprises: inner code FEC encoding the plurality of second data to obtain the plurality of third data.

7. The method according to any one of claims 1 to 5, characterized in that, The first data has a length of 120 bits, and the third data has a length of 128 bits.

8. The method of claim 7, wherein, The first data has a length of 120 bits, and the third data has a length of 128 bits.

9. The method according to any one of claims 1 to 8, characterized in that, The scrambler for scrambling the plurality of second data uses a pseudo-random bit sequence (PRBS) 9 or PRBS 13.

10. The method of claim 9, wherein, The polynomial corresponding to the PRBS 9 includes x 9 +x 5 +1, and the polynomial corresponding to the PRBS 13 includes 1+x+x 2 +x 12 +x 13 .

11. The method of any one of claims 1-10, wherein the first data is padding data.

12. The method according to any one of claims 1 to 11, characterized in that, The plurality of first data comprises eight first data, each of the first data has a length of 120 bits, each of the third data has a length of 128 bits, and the fourth data has a length of 1024 bits.

13. A data processing method, characterized by, The method comprises: forward error correction (FEC) encoding a plurality of first data to obtain a plurality of second data; scrambling the plurality of second data to obtain a plurality of third data; bit pair interleaving the plurality of third data to obtain fourth data; inserting the fourth data into an inner code data stream.

14. The method of claim 13, wherein, The first data has a length of 120 bits, and the second data has a length of 128 bits.

15. The method according to claim 13 or 14, characterized in that, The scrambling the plurality of second data to obtain the plurality of third data comprises: scrambling 122 bits of each of the plurality of second data to obtain the plurality of third data.

16. The method of claim 15, wherein, The 122 bits of each of the second data are the last 122 bits of each of the second data.

17. The method according to any one of claims 13-16, characterized by, The FEC encoding the plurality of first data to obtain the plurality of second data comprises: inner code FEC encoding the plurality of first data to obtain the plurality of second data.

18. The method according to any one of claims 13-17, characterized by, The second data has a length of 120 bits, and the third data has a length of 128 bits.

19. The method of claim 18, wherein, The second data has a length of 120 bits, and the third data has a length of 128 bits.

20. The method of any of claims 13-19, wherein, The scrambler for scrambling the plurality of second data uses a pseudo-random bit sequence (PRBS) 9 or PRBS 13.

21. The method of claim 20, wherein, The polynomial corresponding to the PRBS9 includes x 9 +x 5 +1, the polynomial corresponding to the PRBS9 includes 1+x+x 2 +x 12 +x 13 .

22. The method of any of claims 13-21, wherein, The first data includes 8 first data, each of which has a length of 120 bits, each of the second data has a length of 128 bits, and the fourth data has a length of 1024 bits.

23. A data processing method, characterized by, The method comprises: scrambling a plurality of first data to obtain a plurality of second data; inserting the plurality of second data into a plurality of first data streams to obtain a plurality of second data streams; forward error correction (FEC) encoding the plurality of second data streams to obtain a plurality of third data streams; bit pair interleaving the plurality of third data streams to obtain a fourth data stream.

24. The method of claim 23, wherein, Each of the first data includes part or all of a 6-bit frame alignment sequence (FAS) field.

25. The method of claim 24, wherein, The first 6 bits of each of the first data are part or all of the FAS field.

26. The method of any one of claims 23-25, wherein, The scrambler for scrambling the plurality of first data uses a pseudo-random bit sequence (PRBS) 9 or PRBS 13.

27. The method of claim 26, wherein, The polynomial corresponding to the PRBS 9 includes x 9 +x 5 +1, the polynomial corresponding to the PRBS 13 includes 1+x+x 2 +x 12 +x 13 .

28. The method of any one of claims 23 to 27, wherein, The scrambling the plurality of first data to obtain a plurality of second data comprises: scrambling 114 bits of each of the plurality of first data to obtain the plurality of second data.

29. The method of claim 28, wherein, The 114 bits of each of the first data are the last 114 bits of each of the first data.

30. The method of any of claims 23-29, wherein, The FEC encoding the plurality of second data streams to obtain a plurality of third data streams comprises: inner code FEC encoding the plurality of second data streams to obtain the plurality of third data streams.

31. A data processing apparatus, characterized in that, The apparatus comprises units for performing the method of any of claims 1-30.

32. A data processing apparatus, characterized in that, The apparatus comprises a processor and a communication interface for receiving and sending signals, and the processor is configured to perform the method of any of claims 1-30.

33. The apparatus of claim 32, the apparatus comprising: a chip, an optical module, a network device, or a server.

34. A chip, characterized by The chip comprises a processor configured to perform the method of any of claims 1-30.

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