CAN transmitter circuit with current smoothing

Abstract

The invention relates to a CAN transmitter circuit with current smoothing. In described examples, an apparatus includes a bias voltage circuit (108), an output circuit (118), and a plurality of current source circuits (112) and (114). A first plurality of the current source circuits (112) is coupled between a first output of the bias voltage circuit (108) and a first input of the output circuit (118). A second plurality of the current source circuits (114) is coupled between a second output of the bias voltage circuit (108) and a second input of the output circuit (118). Each of the current source circuits (112) and (114) includes first and second resistors, first and second switches, and a transistor. The first switch is coupled between a gate of the transistor and the bias voltage circuit. The second switch is coupled between the gate of the transistor and a first terminal of the transistor. A second terminal of the transistor is coupled to the output circuit.

Description

[0001] Cross Reference to Related Applications

[0002] This application claims the benefit and priority of Indian Provisional Application No. 202441064913, filed on August 28, 2024, which is incorporated herein by reference. Technical Field

[0003] This application generally relates to Controller Area Network (CAN) systems, and more specifically, to CAN transmitter circuitry for driving the CAN high and low bus lines. Background Technology

[0004] The CAN standard was developed to enable efficient communication between electronic components (e.g., electronic control units (ECUs)) in vehicles. CAN systems are used to transmit data and commands between components in various applications, such as automotive and industrial applications. The CAN standard specifies differential signaling. Differential signaling can be used to transmit signals with reduced noise and increased signal amplitude margin. Summary of the Invention

[0005] In the described example, an apparatus includes a bias voltage circuit, an output circuit, and a plurality of current source circuits. A first plurality of said current source circuits are coupled between a first output of the bias voltage circuit and a first input of the output circuit. A second plurality of said current source circuits are coupled between a second output of the bias voltage circuit and a second input of the output circuit. Each of the current source circuits includes first and second resistors, first and second switches, and a transistor. The first switch is coupled between the gate of the transistor and the bias voltage circuit. The second switch is coupled between the gate of the transistor and a first terminal of the transistor. A second terminal of the transistor is coupled to the output circuit.

[0006] In the described example, an apparatus includes a bias voltage circuit, an output circuit, multiple current source circuits, and a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, and a sixth transistor. The current source circuits are coupled between the bias voltage circuit and the output circuit. A first terminal of the third transistor is coupled to a first terminal of the first transistor. A control terminal of the third transistor is coupled to a control terminal and a second terminal of the first transistor, as well as a control terminal and a first terminal of the second transistor. The second terminal of the second transistor is coupled to a second terminal of the fifth transistor. The first terminal of the fourth transistor is coupled to a first terminal of the sixth transistor. The second terminals of the third transistor and the sixth transistor are coupled to the output circuit. A control terminal of the sixth transistor is coupled to a control terminal and a second terminal of the fourth transistor, as well as a control terminal and a first terminal of the fifth transistor. Attached Figure Description

[0007] Figure 1 This is a functional block diagram of a CAN transmitter.

[0008] Figure 2A yes Figure 1 Functional blocks and circuit diagram of the bias voltage circuit.

[0009] Figure 2B yes Figure 1 Functional blocks and circuit diagrams for the output control stage.

[0010] Figure 2C yes Figure 1 The circuit diagram of the output stage.

[0011] Figure 3 yes Figure 1 and 2C The circuit diagram of the common-mode voltage circuit.

[0012] Figure 4 yes Figure 1 and 2B Functional blocks and circuit diagrams of the control circuit.

[0013] Figure 5 yes Figure 2B The graphs of the source-gate voltage or gate-source voltage relative to time for the current source MP5 and the current sink MN5 (respectively).

[0014] Figure 6 It is used for Figure 1 The output control stage provides a graph of the current supplied to the high-side lines of the CAN bus relative to time.

[0015] Figure 7 yes Figure 1 The graph of the total impedance of the current path of the first or second current source circuit relative to time. Detailed Implementation

[0016] The CAN transmitter controls the voltage on the CAN bus to transmit signals. The CAN bus is a differential bus, therefore it consists of high and low CAN bus lines. The first state of the CAN bus, for example, corresponding to a logic 1 transmission, is called the recessive (REC) state. The REC state corresponds to the high and low CAN bus lines having the same voltage, which is equal to half the supply voltage, for example, 2.5 volts. The REC state voltage is equal to the common-mode voltage (Vcm). The second state of the CAN bus, for example, corresponding to a logic 0 transmission, is called the dominant (DOM) state. The DOM state corresponds to the high and low CAN bus lines having different voltages symmetrical about Vcm (e.g., 3.25 volts (high voltage) and 1.75 volts (low voltage)). The data value transmitted by the CAN bus corresponds to the differential voltage of the CAN bus lines, and therefore corresponds to the voltage of the high CAN bus line minus the voltage of the low CAN bus line. In the described example, this differential voltage is zero volts in the REC state and 1.5 volts in the DOM state.

[0017] When the CAN transmitter receives data corresponding to the DOM state, it pulls the high CAN bus line up to high voltage and pulls the low CAN bus line down to low voltage. When the CAN transmitter receives data corresponding to the REC state, it releases the high CAN bus line from high voltage (e.g., decouples it from high voltage) and releases the low CAN bus line from low voltage, causing both the high and low CAN bus lines to return to Vcm. In some instances, the high and low CAN bus lines are pulled back to Vcm.

[0018] Electromagnetic frequency (EMF) radiation may be emitted if the voltages of the high and low CAN bus lines are asymmetrical around Vcm, during the transition between the DOM and REC states. Some or all of the following conditions may be applied to the transition of the CAN transmitter from the DOM state to the REC state and from the REC state to the DOM state: (1) the current values ​​supplied to and absorbed from the CAN bus change with a linear slope over time. And / or (2) the resistance from the high CAN bus line to the power supply changes with time, and the resistance from the low CAN bus line to ground changes with time, each with a linear slope. The benefits provided by these conditions may include some or all of the following: improved symmetry of the voltages of the high and low CAN bus lines around Vcm, and / or reduced EMF radiation emitted by the CAN transmitter. This is further described below with reference to the accompanying drawings.

[0019] Metal-oxide-semiconductor field-effect transistors (MOSFETs) are designated M[channel type][number], where the number increases for each different transistor of the same channel type. Channel types include n-channel MOSFETs (NMOS) and p-channel MOSFETs (PMOS). The channel type of each transistor is merely an example, and other examples can be substituted for any transistor shown with another transistor of a different type. Furthermore, the same reference numerals or other reference indicators are used in the accompanying drawings to indicate structurally and / or functionally related features.

[0020] In this document, some different but related structures or signals are indicated by reference numerals in the format of [number][dash][number], such as MP5-1 226-1 and MN5-3 238-3. Some structures affecting signals on the high and low CAN bus lines are indicated by [underscore][H or L] (H for high, L for low), such as Rchg_H 230 and SW_L240. In some instances, these numbering conventions are combined to indicate specific high or low CAN bus line side structures, such as Rchg_1H 230-1 and SW_2L 240-2. In some instances, these structures or signals are often mentioned in the singular or as groups using [number] or [underscore][H or L] and [number] without [dash][number], such as MP5 226 or Rchg_H 230.

[0021] In addition, the same reference numerals or other reference indicators are used in the accompanying drawings to indicate structurally and / or functionally related features.

[0022] Figure 1 This is a functional block diagram of a CAN transmitter 100. The CAN transmitter 100 includes a bias voltage stage 102, an output control stage 104, and an output stage 106. The bias voltage stage 102 includes a bias voltage circuit 108. The output control stage 104 includes a control circuit 110, a first current source block 112, and a second current source block 114. The output stage 106 includes a common-mode voltage circuit 116, an output circuit 118, and a CAN bus 120. The CAN bus 120 includes a high CAN bus line (CAN_H) 120H and a low CAN bus line (CAN_L) 120L.

[0023] The first output of the bias voltage circuit 108 provides a first bias voltage, such as a bias voltage for a p-channel MOSFET, to the first input of the first current source block 112. The second output of the bias voltage circuit 108 provides a second bias voltage, such as a bias voltage for an n-channel MOSFET, to the first input of the second current source block 114.

[0024] The input of control circuit 110 receives a data signal corresponding to the data value to be transmitted by CAN transmitter 100 via CAN bus 120. The first output of control circuit 110 provides a first control signal to the second (control) input of first current source block 112. The second output of control circuit 110 provides a second control signal to the second (control) input of second current source block 114. The output of first current source block 112 provides a first current to the first input of output circuit 118. The first current is responsive to the first control signal. The output of second current source block 114 provides a second current to the second input of output circuit 118. The second current is responsive to the second control signal.

[0025] The output of common-mode voltage circuit 116 provides a common-mode voltage to the third input of output circuit 118. The common-mode voltage sets the REC signal voltage of CAN bus 120, thus setting the voltages of CAN_H 120H and CAN_L 120L. Simultaneously, output circuit 118 transmits the REC signal through CAN bus 120. The first output of output circuit 118 provides a third current to CAN_H 120H. The second output of output circuit 118 provides a fourth current to CAN_L 120L. The third current responds to the first current, and the fourth current responds to the second current. The first states of the third and fourth currents correspond to the REC signal, and the second states of the third and fourth currents correspond to the DOM signal.

[0026] about Figure 2A Further description of bias voltage stage 102. Regarding... Figure 2B Further description of output control stage 104. About Figure 2C Further description of output stage 106. Figure 2A , 2B Together with 2C, this corresponds to an example implementation of the CAN transmitter 100.

[0027] Figure 2A yes Figure 1 The functional blocks and circuit diagram of the bias voltage circuit 108 are described below. The bias voltage circuit 108 includes a bias circuit 201, a first current source 202, a second current source 204, a first p-channel MOSFET (MP1) 206, a second p-channel MOSFET (MP2) 208, a third p-channel MOSFET (MP3) 210, a fourth p-channel MOSFET (MP4) 212, a first n-channel MOSFET (MN1) 214, a second n-channel MOSFET (MN2) 216, a third n-channel MOSFET (MN3) 218, a fourth n-channel MOSFET (MN4) 220, a voltage source (Vcc) 222, and a ground terminal (GND) 224. The bias circuit 201 controls (and / or provides) the current supplied by the first current source 202 and the second current source 204, respectively.

[0028] The first terminal of the bias circuit 201 is coupled to the second terminal of the first current source 202. The first terminal of the first current source 202 is coupled to the gate and drain of MP1 206 and the gate of MP3 210. The drain of MP3 210 is coupled to the ground terminal 224. The source of MP1 206 is coupled to the gate and drain of MP2 208 and the gate of MP4 212. The sources of MP2 208 and MP4 212 are coupled to Vcc 222. The source of MP3 210 and the drain of MP4 212 are coupled to the first bias voltage terminal 213.

[0029] The second terminal of bias circuit 201 is coupled to the first terminal of second current source 204. The second terminal of second current source 204 is coupled to the gate and drain of MN1 214 and the gate of MN3 218. The drain of MN3 218 is coupled to Vcc 222. The source of MN1 214 is coupled to the gate and drain of MN2 216 and the gate of MN4 220. The sources and back gates (body terminals) of MN2 216 and MN4 220 are coupled to ground terminal 224. The source of MN3 218 and the drain of MN4 220 are coupled to the second bias voltage terminal 219.

[0030] The current supplied by the first current source 202 pulls down the voltage at the gates of p-channel MOSFETs MP1 206, MP2 208, MP3 210, and MP4 212, causing them to turn on (activate / conduct). In this example, the pull-down gate voltage discharges the gate-source capacitance of the MOSFETs. When MP1 206 and MP2 208 are turned on, the current supplied by the first current source 202 flows through the source-drain paths of MP1 206 and MP2 208.

[0031] Diodes MP1 206 and MP3 210 form a first current mirror. Diodes MP2 208 and MP4 212 form a second current mirror. Therefore, when MP1 206, MP2 208, MP3 210, and MP4 212 are turned on, the current flowing through the source-drain paths of MP1 206 and MP2 208 is reflected through the source-drain paths of MP3 210 and MP4 212. The current through the source-drain path of MP3 210 responds to the multiplier of the first current mirror (MP1 206 and MP3 210). The current through the source-drain path of MP4 212 responds to the multiplier of the second current mirror (MP2 208 and MP4 212). The bias voltage BIAS_P at the first bias voltage terminal 213 is determined in response to the current through MP3 210 and the current through MP4 212. Provide BIAS_P to the first current source block 112.

[0032] The current supplied by the second current source 204 pulls up the voltage at the gates of n-channel MOSFETs MN1 214, MN2 216, MN3 218, and MN4 220, turning them on. In this example, the pull-up gate voltage charges the gate-source capacitance of the MOSFETs. When MN1 214 and MN2 216 are on, the current supplied by the second current source 204 flows through the drain-source paths of MN1 214 and MN2 216.

[0033] Diodes MN1 214 and MN3 218 form a third current mirror. Diodes MN2 216 and MP4 220 form a fourth current mirror. Therefore, when MN1 214, MN2 216, MN3 218, and MN4 220 are turned on, the current flowing through the source-drain paths of MN1 214 and MN2 216 is reflected through the source-drain paths of MN3 218 and MN4 220. The current through the source-drain path of MN3 218 responds to the multiplier of the first current mirror (MN1 214 and MN3 218). The current through the source-drain path of MN4 220 responds to the multiplier of the second current mirror (MN2 216 and MN4 220). The bias voltage BIAS_N at the second bias voltage terminal 219 is determined in response to the current through MN3 218 and the current through MN4 220. Provide BIAS_N to the second current source block 114.

[0034] Figure 2B yes Figure 1 The function blocks and circuit diagram of the output control stage 104. Initially, provided... Figure 2B An overview of the functions of the output control stage 104.

[0035] exist Figure 2B The high-side components of the output control stage 104, depicted above the control circuit 110, control the current (I_H) supplied to CAN_H120H. Figure 2B The low-side components of the output control stage 104, depicted below the control circuit 110, control the current (I_L) drawn from CAN_L 120L. The control circuit 110 controls the on and off timing of the high-side and low-side switches. In this document, a switch described as on means closed, and therefore conducting. A switch described as off means open, and therefore not conducting.

[0036] Recall that in some instances, a single reference numeral was used in this document to refer to multiple similarly positioned devices using the numbering format [reference numeral]-[number]. When turned on, a total of N high-side fifth p-channel MOSFETs MP5 226-1 to 226-N supply current to CAN_H 120H. The components corresponding to a specific current source MP5 226 are within the same dashed box (current source circuit 236) as the specific current source MP5 226. The corresponding high-side switches SW_H 228-1 to 228-N and high-side charging resistors Rchg_H 230-1 to 230-N control the charging rate of the gate-source capacitance of the corresponding current source MP5 226-1 to 226-N, and thus control the turn-on rate of the corresponding current source MP5 226. The high-side inverting switches SWb_H232-1 to 232-N and the high-side discharge resistors Rdschg_H 234-1 to 234-N control the discharge rate of the gate-source capacitance of the corresponding current sources MP5 226-1 to 226-N, thus controlling the turn-off rate of the corresponding current sources MP5 226-1 to 226-N. Control circuit 110 provides a control signal that turns on SW_H 228 or its corresponding SWb_H 232 at a time, but not both. Current source MP5 226, along with its corresponding SW_H 228, Rchg_H 230, SWb_H 232, and Rdschg_H 234, together constitute current source circuit 236.

[0037] When turned on, a total of N low-side fifth n-channel MOSFETs MN5 238-1 to 238-N draw current from CAN_L 120L. Components corresponding to specific current traps MN5 238 are within the same dashed box (current trap circuit 248) as specific current traps MN5 238. Low-side switches SW_L 240-1 to 240-N and low-side charging resistors Rchg_L 242-1 to 240-N control the charging rate of the gate-source capacitance of the corresponding current traps MN5 238-1 to 238-N, thus controlling the turn-on rate of the corresponding current traps MN5 238-1 to 238-N. The low-side inverting switches SWb_L 244-1 to 244-N and the low-side discharge resistors Rdschg_L 246-1 to 246-N control the discharge rate of the gate-source capacitance of the corresponding current sinks MN5 238-1 to 238-N, thus controlling the turn-off rate of the corresponding current sinks MN5 238-1 to 238-N. Control circuit 110 provides a control signal that turns on SW_L 240-1 to 240-N or their corresponding SWb_L 244-1 to 244-N at one time, but not both. The current sinks MN5 238-1 to 238-N and their corresponding SW_L 240, Rchg_L 242, SWb_L 244, and Rdschg_L 246 together form current sink circuit 248.

[0038] Now, let's describe it further. Figure 2BThe output control stage 104 includes control circuitry 110, high-side circuitry, and low-side circuitry. The high-side circuitry includes N MP5 226 transistors (MP5-1 226-1 to MP5-N 226-N), N SW_H228 transistors (SW_H1 228-1 to SW_HN 228-N), N Rchg_H 230 transistors (Rchg_H1 230-1 to Rchg_HN 230-N), N SWb_H232 transistors (SWb_H1 232-1 to SWb_HN 232-N), and N Rdschg_H 234 transistors (Rdschg_H1 234-1 to Rdschg_HN234-N), wherein the transistors, switches, and resistors provide N current source circuits 236 (236-1 to 236-N). The low-side circuitry comprises N MN5 238s (MN5-1 238-1 to MN5-N238-N), N SW_L 240s (SW_L1 240-1 to SW_LN 240-N), N Rchg_L 242s (Rchg_L1 242-1 to Rchg_LN 242-N), N SWb_L 244s (SWb_L1 244-1 to SWb_LN 244-N), and N Rdschg_L246s (Rdschg_L1 246-1 to Rdschg_LN 246-N), wherein the transistors, switches, and resistors provided N current trap circuits 248 (248-1 to 248-N).

[0039] SW_H 228, SW_L 240, SWb_H 232 and SWb_L 244 are collectively referred to as switches in this paper.

[0040] Therefore, for index i ranging from 1 to N, the i-th current source circuit 236-i includes MP5-i 226-i, SW_Hi 228-i, Rchg_Hi 230-i, SWb_Hi 232-i, and Rdschg_Hi 234-i. The i-th current sink circuit 248-i includes MN5-i 238-i, SW_Li 240-i, Rchg_Li 242-i, SWb_Li 244-i, and Rdschg_Li 246-i. The current source circuit 236 is coupled in parallel between the bias voltage circuit 108 and CAN_H 120H. The current sink circuit 248 is coupled in parallel between the bias voltage circuit 108 and CAN_L 120L.

[0041] In current source 236-i, the first terminal of Rchg_Hi 230-i is coupled to the first bias voltage terminal 213 and receives BIAS_P. The second terminal of Rchg_Hi 230-i is coupled to the first terminal of SW_Hi 228-i. The second terminal of SW_Hi 228-i is coupled to the gate of MP5-i 226-i and the first terminal of SWb_Hi 232-i. The second terminal of SWb_Hi 232-i is coupled to the first terminal of Rdschg_Hi 234-i. The second terminal of Rdschg_Hi 234-i and the source of MP5-i 226-i are coupled to Vcc 222. The drain of MP5-i 226-i is coupled to the first bus current terminal 250.

[0042] In current sink 248-i, the first terminal of Rchg_Li 242-i is coupled to the second bias voltage terminal 219 and receives BIAS_N. The second terminal of Rchg_Li 242-i is coupled to the first terminal of SW_Li 240-i. The second terminal of SW_Li 240-i is coupled to the gate of MN5-i 238-i and the first terminal of SWb_Li 244-i. The second terminal of SWb_Li 244-i is coupled to the first terminal of Rdschg_Li 246-i. The second terminal of Rdschg_Li 246-i, as well as the source and back gate (body terminal) of MN5-i 238-i, are coupled to ground terminal 224. The drain of MN5-i 238-i is coupled to the second bus current terminal 252.

[0043] The high-side control output of control circuit 110 is coupled to the control terminals of SW_H1 228-1 to SW_HN 228-N and SWb_H1 232-1 to SWb_HN 232-N. The low-side control output of control circuit 110 is coupled to the control terminals of SW_L1 240-1 to SW_LN 240-N and SWb_L1 244-1 to SWb_LN 244-N. The control signal provided to SW_Hi 228-i is the same as the control signal provided to SW_Li 240-i. The control signal provided to SWb_Hi 232-i is the same as the control signal provided to SWb_Li 240-i, and is the logic inverse of the control signals provided to SW_Hi 228-i and SW_Li 240-i (high instead of low, or low instead of high). Regarding Figure 4 The control circuit 110 is described further.

[0044] When control circuit 110 controls SW_Hi 228-i to close and SWb_Hi 232-i to open, the gate of MP5-i 226-i receives the signal BIAS_P via Rchg_Hi 230-i. The gate-source capacitance of Rchg_Hi 230-i and MP5-i 226-i is an RC circuit. The product of the resistor Rchg_Hi 230-i and the corresponding gate-source capacitance of MP5-i 226-i corresponds to the RC time constant. Therefore, the gate-source capacitance of MP5-i 226-i charges at a rate corresponding to the resistance of Rchg_Hi 230-i and the gate-source capacitance of MP5-i 226-i to turn on MP5-i 226-i.

[0045] Such as about Figure 5 Further, each MP5-i 226-i is initially turned on in the saturation region and then in the linear region. Each MP5-i 226-i is turned on according to the corresponding RC time constant. Initially, in the saturation region, the turn-on and the corresponding decrease in equivalent resistance are relatively slow. This allows the continuous turn-on (incrementing i) of MN5-i 238-i to be controlled to begin intermittently, causing the total equivalent resistance of all MP5-i 226-i to decrease linearly, and the voltage of CAN_H 120H to increase linearly accordingly (gradual pull-up). As the corresponding MP5-i 226-i is turned on into the linear region, the linear decrease in equivalent resistance continues according to the characteristics of the MOSFET's linear region operation.

[0046] When control circuit 110 controls SW_Li 228-i to close and SWb_Li 232-i to open, the gate of MN5-i 238-i receives the signal BIAS_N via Rchg_Li 242-i. The gate-source capacitance of Rchg_Li 242-i and MN5-i 238-i is an RC circuit. The product of resistors Rchg_Hi 230-i and Rchg_Li 242-i with the corresponding gate-source capacitances of MP5-i 226-i and MN5-i 238-i corresponds to the RC time constant. Therefore, the gate-source capacitance of MN5-i 238-i charges at a rate corresponding to the resistance of Rchg_Li 242-i and the gate-source capacitance of MN5-i 238-i to turn on MN5-i 238-i.

[0047] Such as about Figure 5Further, each MN5-i 238-i is initially turned on in the saturation region and then in the linear region. Each MN5-i 238-i is turned on according to the corresponding RC time constant. Initially, in the saturation region, the turn-on and the corresponding decrease in equivalent resistance are relatively slow. This allows the continuous turn-on (incrementing i) of MN5-i 238-i to be controlled to begin at certain times, causing the total equivalent resistance of all MN5-i 238-i to decrease linearly, and the voltage of CAN_L 120L to decrease linearly accordingly (gradually pulled down). As the turn-on of the corresponding MN5-i 238-i progresses into the linear region, the linear decrease in equivalent resistance continues according to the characteristics of the MOSFET's linear region operation.

[0048] The delays provided by the gate-source capacitances of resistors Rchg_Hi 230-i and MP5-i 226-i, and by the gate-source capacitances of resistors Rchg_Li 242-i and MN5-i 238-i, are matched. MP5-i 226-i and MN5-i 238-i are also matched. This matched delay, along with the matched high-side and low-side current control FETs, allows for a matched rate of decrease in the high-side and low-side resistances. It also allows the rate of increase (or decrease) of the CAN_H 120H voltage to match the rate of decrease (or increase) of the CAN_L 120L voltage.

[0049] In some instances, the various MP5 226-i and MN5 238 components are designed such that their corresponding equivalent resistances during on and off periods fit into a resistance curve, thereby facilitating linear changes in resistance and voltage over time as described. In some instances, the various MP5 226, MN5 238, Rchg_Hi 230, and Rchg_Li 242 components are designed to provide RC values ​​and corresponding delays to facilitate linear changes in resistance and voltage over time as described. In some instances, these design guidelines also respond to the maximum permissible data switching time according to the device specifications of CAN transmitter 100.

[0050] When control circuit 110 controls SWb_Hi 228-i to open and SWb_Hi 232-i to close, the gate of MP5-i 226-i is decoupled from BIAS_P and coupled to Vcc 222 via Rdschg_Hi 234-i. The gate-source capacitance of Rdschg_Hi 234-i and MP5-i 226-i is an RC circuit. Therefore, the gate-source capacitance of MP5-i 226-i discharges at a rate corresponding to the resistance of Rdschg_Hi 234-i and the gate-source capacitance of MP5-i 226-i to turn off MP5-i 226-i. The equivalent resistance of MP5-i 226-i increases linearly, and the voltage of CAN_H 120H decreases linearly (discharges) back to Vcm accordingly.

[0051] When control circuit 110 controls SW_Li 228-i to open and SWb_Li 232-i to close, the gate of MN5-i 238-i is decoupled from BIAS_N and coupled to ground terminal 224 via Rdschg_Li 246-i. The gate-source capacitance of Rdschg_Li 246-i and MN5-i 238-i is an RC circuit. Therefore, the gate-source capacitance of MN5-i 238-i discharges at a rate corresponding to the resistance of Rdschg_Li 246-i and the gate-source capacitance of MN5-i 238-i to turn off MN5-i 238-i. The equivalent resistance of MN5-i 238-i increases linearly, and the voltage of CAN_L 120L increases (charges) accordingly linearly back to Vcm.

[0052] As described above, the RC time constants corresponding to Rchg_Hi 230-i and MP5-i 226-i are equal to the RC time constants corresponding to Rchg_Li242-i and MN5-i 238-i (for each value of i). Furthermore, MP5-i 226-i and MN5-i238-i are matched. This makes the rate at which the high-side resistance decreases when the current source MP5 226 is sequentially turned on equal to the rate at which the low-side resistance decreases when the current source MP6 238 is sequentially turned on. Similarly, the RC time constants corresponding to Rdschg_Hi 234-i and MP5-i226-i are equal to the RC time constants corresponding to Rdschg_Li 246-i and MN5-i 238-i (for each value of i). This makes the rate at which the high-side resistance increases when the current source MP5 226 is sequentially turned off equal to the rate at which the low-side resistance increases when the current source MP6 238 is sequentially turned off.

[0053] In some instances, the RC time constants corresponding to Rchg_Hi 230-i and MP5-i 226-i are equal to the RC time constants corresponding to Rdschg_Hi 234-i and MP5-i 226-i (for each value of i). Similarly, the RC time constants corresponding to Rchg_Li 242-i and MN5-i 238-i are equal to the RC time constants corresponding to Rdschg_Li 246-i and MN5-i 238-i (for each value of i). This allows the turn-off procedures for MP5 226 and MN5 238 to be executed similarly in the reverse order of the turn-on procedures (i from N to 1 instead of from 1 to N).

[0054] Therefore, the rate of change of the high-side current supplied to CAN_H 120H by the first current source block 112 is designed to be equal to the rate of change of the low-side current supplied to CAN_L 120L by the second current source block 114. Furthermore, the current supplied by the separate current source circuit 236 and absorbed by the separate current sink circuit 248 changes gradually, rather than as a step function. This allows the rate of change (increase or decrease) of the voltage on CAN_H 120H to be more closely equal to the rate of change of the voltage on CAN_L 120L without significant additional process or design area costs to reduce or eliminate the mismatch between the turn-on and turn-off times of the corresponding high-side and low-side switches. It also allows the voltages on CAN_H 120H and CAN_L 120L to be more symmetrical around Vcm in response to changes in the turn-on and turn-off timings of SW_H 228 and SW_L 240 and SWb_H 232 and SWb_L 244.

[0055] In this paper, the MP5 226 network cumulatively refers to all MP5 226, and the MN5 238 network cumulatively refers to all MN5 238.

[0056] As described above, the various Rchg_H 230 and Rchg_L 242 control the corresponding current source MP5 226 and current sink MN5238 to turn on at a rate that is approximately (and therefore, within design constraints) linear and responsive to the corresponding Rchg resistance values ​​and the gate-source capacitance values ​​of MP5 226 and MN5238. Similarly, the various Rdschg_H 234 and Rdschg_L 246 control the corresponding current source MP5 226 and current sink MN5 238 to turn off at a rate that is approximately linear and responsive to the corresponding Rdschg resistance values ​​and the gate-source capacitance values ​​of MP5 226 and MN5 238. The sequential pairing activation and deactivation of MP5 226 and MN5 238 for linearly decreasing or increasing the resistance, and correspondingly linearly increasing or decreasing the voltages seen by CAN_H 120H and CAN_L 120L, respectively, achieves some or all of the various benefits.

[0057] These benefits include improved resistance matching between the MP5 226 and MN5 238 networks during MP5 226 and MN5 238 turn-on and turn-off; improved voltage matching between CAN_H120H and CAN_L120L during MP5 226 and MN5 238 network turn-on and turn-off; improved voltage symmetry between CAN_H120H and CAN_L120L relative to Vcm in response to CAN_H120H and CAN_L120L; reduced EMF radiation emitted by CAN transmitter 100; and reduced device area cost. In some instances, device area cost is reduced by avoiding the need for trimming bits to match the current supplied to CAN_H120H during device turn-on with the current drawn from CAN_L120L. In some instances, timing and other parameter errors are caused by process, voltage, or temperature variations. In some instances, the described CAN transmitter 100 and the corresponding benefits described herein reduce EMF transmissions associated with timing and other parameter errors (e.g., parameter errors corresponding to device mismatch).

[0058] In some instances, because voltage and resistance change linearly during on and off, improved voltage and resistance matching during on and off is further enhanced. Therefore, a timing error of the SW shorter than the time interval between consecutive switch activations corresponds to a voltage or resistance mismatch seen by the CAN bus 120, which is less than the contribution of a single MP5 226 or MN5 238. Moreover, the smaller the timing error, the smaller the value of the voltage or resistance mismatch.

[0059] In a first illustrative example, a step current is supplied to CAN_H 120H (or CAN_L 120L), and the same step current is supplied to CAN_L 120L (or CAN_H 120H) with a first delay. Responsibly, a first voltage mismatch corresponding to the step current exists between CAN_H 120H and CAN_L 120L. The first voltage mismatch has a duration corresponding to the first delay.

[0060] In the second illustrative example, the linearly changing current has a slope (current over time). A linearly changing current is supplied to CAN_H 120H, and the same linearly changing current is supplied to CAN_L 120L with a second delay. Responsibly, a second voltage mismatch exists between CAN_H 120H and CAN_L 120L, corresponding to the slope of the linearly changing current multiplied by the second delay. If the amplitude of the step-changing current is equal to the maximum amplitude of the linearly changing current, the second voltage mismatch is less than the first voltage mismatch. Therefore, the proportional difference between the first and second voltage mismatches responds to the second delay multiplied by the slope of the linearly changing current.

[0061] about Figures 4 to 7 Further describe the functionality of output control stage 104.

[0062] Figure 2C yes Figure 1 The circuit diagram of output stage 106. Output stage 106 includes common-mode voltage circuit 116, sixth p-channel MOSFET (MP6) 254, sixth n-channel MOSFET (MN6) 256, seventh p-channel MOSFET (MP7) 258, seventh n-channel MOSFET (MN7) 260, first common-mode resistor (Rcm1) 262 and second common-mode resistor (Rcm2) 264.

[0063] The source of MN6 256 is coupled to the cathode of its body diode and the first bus current terminal 250. The drain of MN6 256 is coupled to the anode of its body diode, the back gate (body terminal) of MP7 256, and the source and back gate of MP6 254. The gate of MN6 256 receives a recessive bias voltage timeout (RTO). The drain of MP6 254 is coupled to CAN_H 120H and the first terminal of Rcm1 262. The second terminal of Rcm1 262 is coupled to the second terminal of Rcm2 264 and node A 266. Node A 266 is coupled to the terminal of common-mode voltage circuit 116. The gate of MP6 254 is coupled to ground terminal 224, such that when MN6 256 is turned on, MP6 254 is also turned on.

[0064] The source of MN7 260 is coupled to the anode of its body diode, the back gate of MN7 260, and the second bus current terminal 252. The drain of MN7 260 is coupled to the cathode of its body diode and to the source and back gate of MP7 258. The gate of MN7 260 receives a bias voltage RT0. The drain of MP7 258 is coupled to the first terminal of CAN_L 120L and Rcm2 264. The gate of MP7 258 is coupled to ground terminal 224, such that MP7 258 is also turned on when MN7 260 is turned on. In some instances, MP6 254 helps prevent reverse leakage current between Vcc 222 and CAN_H120H in the "off state" if the voltage of CAN_H 120H deviates from the designed voltage range. In some instances, if the voltage of the CAN_L120L deviates from the designed voltage range, the MP7 258 helps prevent reverse leakage current in the off state between the ground node and the CAN_L 120L.

[0065] Common-mode voltage circuit 116 maintains the common-mode voltage (Vcm) on CAN_L 120H and CAN_L, which is equal to the voltage corresponding to the REC signal. When CAN transmitter 100 receives a data signal corresponding to the DOM signal, SWb_H 232 and SWb_L 244 are sequentially deactivated, and SW_H 228 and SW_L 240 are sequentially activated, causing I_H to flow through MP5 226 and I_L to flow through MN5 238. I_H pulls up the voltage on CAN_H 120H, and I_L symmetrically pulls down the voltage on CAN_L 120L. I_H and I_L (respectively) pull the voltages on CAN_H 120H and CAN_L 120L so that those voltages are symmetrical with respect to Vcm, and so that the difference between those voltages corresponds to the DOM signal. As described above, maintaining the symmetry of the voltages on CAN_H 120H and CAN_L 120L relative to Vcm enables the CAN transmitter 100 to reduce EMF emissions. Regarding Figure 3 The common-mode voltage circuit 116 is described further.

[0066] Therefore, if the duration between data signals with a DOM value (e.g., logic zero) is less than the threshold duration, then RTO is high (e.g., with a high voltage, such as Vcc) when the CAN transmitter 100 actively signals. Thus, if the duration between logic zero data signal values ​​is less than the threshold duration, MP6 254, MN6 256, MP7 258, and MN7 260 are turned on. If the data signal has a REC value (e.g., logic one) longer than the threshold duration, then RTO is low (e.g., with a low voltage, such as ground or zero voltage) and MP6 254, MN6 256, MN6 258, and MN7 260 are turned off. MP6 254, MN6 256, MP7 258, and MN7 260 are turned off when transmission is not active to allow the capacitance on CAN_H 120H to be balanced with the capacitance on CAN_L 120L. CAN_H120H and CAN_L120L continue to have common-mode voltages corresponding to the REC signal, while RTO is low.

[0067] In some instances, using the RTO signal to disconnect the CAN bus 120 from the current source circuit 236 and the current sink circuit 248 reduces or avoids the capacitor matching design requirements for meeting the EMF transmit specification. Therefore, it allows the design to avoid the requirement to match the MP5 226 capacitor with the MN5 238 capacitor in the corresponding off (deactivated) state. In some instances, this allows for a reduction in the size of the MN5 238 transistor, for example, a 75% reduction, correspondingly reducing it to 25% of the size required to implement the capacitor matching requirement.

[0068] In some instances, the RTO signal is replaced by coupling the gates of MN6 256 and MN7 260 to Vcc 222.

[0069] Figure 3 yes Figure 1 and 2C The circuit diagram of the common-mode voltage circuit 116 is shown. The common-mode voltage circuit 116 includes an eighth p-channel MOSFET (MP8) 302, a third common-mode resistor (Rcm3) 304, an eighth n-channel MOSFET (MN8) 306, a ninth n-channel MOSFET (MN9) 308, a fourth common-mode resistor (Rcm4) 310, a ninth p-channel MOSFET (MP9) 312, a tenth n-channel MOSFET (MN10) 314, and a tenth p-channel MOSFET (MP10) 316.

[0070] The source of MP8 302 and the drain of MN10 314 are coupled to Vcc 222. The gate and drain of MP8 302 are coupled to the first terminal of Rcm3 304. The second terminal of Rcm3 304 is coupled to the gate and drain of MN8 306 and the gate of MN10 314. The source of MN8 306 and the source of MP9 312 are coupled to node B 318. Node B 318 has a reference voltage (Vref). In some instances, Vref is equal to Vcc / 2, or half the difference between Vcc and ground. The gate and drain of MP9 312 are coupled to the gate of MP10 316 and the first terminal of Rcm4 310. The second terminal of Rcm4 310 is coupled to the gate and drain of MN9 308. The source of MN9 308 and the source of MP10 316 are coupled to ground terminal 224.

[0071] If the difference between Vcc and the ground voltage is greater than the threshold voltage (V) of MP8 302, MN8 306, MN9 308 and MP9 312 T The sum of these parameters enables MP8 302, MN8 306, MN9 308, and MP9 312 to turn on. The use of the p-channel MOSFET MP8 302 coupled to Vcc and the n-channel MOSFET MN9 coupled to ground terminal 224 allows the common-mode voltage circuit 116 to function. Rcm3304 and Rcm4 310 prevent high-current shoot-through. MN8 306 and MP9 312 enable V... T The process variation can be balanced between node A318 and Vcc222, and between node A318 and ground terminal 224.

[0072] MP8 302, MN8 306, MN9 308, MP9 312, Rcm3 304, and Rcm4 310 are designed such that the voltage Vref at node A318 is equal to the designed Vcm. The gate voltages of MN8 306 and MP9 312 control MN10 314 and MP10 316, respectively. MN10 314 and MP10 316 are controlled such that the voltage at node A266 is equal to Vref and therefore equal to Vcm. MP8 302, Rcm3 304, and MN8 306 together correspond to the upper half of the common-mode voltage circuit 116. MN9 308, Rcm4 310, and MP9 312 together correspond to the upper half of the common-mode voltage circuit 116. The upper half passively controls MN10 314, and the lower half passively controls MP10 316. In some instances, such as when Vcm is designed to be equal to Vcc / 2, these passive controls are symmetrical. The symmetrical passive control of the upper and lower halves of the common-mode voltage circuit 116 allows the upper and lower halves to have equal equivalent resistance when switched on. Therefore, the voltage at node A264 is equal to Vcm, which is equal to Vcc / 2.

[0073] Figure 4 yes Figure 1 and 2B The functional blocks and circuit diagram of the control circuit 110 are as follows. The control circuit 110 includes a gate driver 402 and N delay circuits, namely delay circuits 1 404-1 to delay circuit N 404-N. Each delay circuit includes a first buffer 406, delay resistors Rdelay 408-1 to 408-N, capacitors C1 410-1 to CN 410-N, a Schmitt trigger 412, a second buffer 414, and an inverter 416. The first buffer 406 is numbered as first buffer 1406-1 to first buffer N406-N. The Schmitt trigger is numbered as Schmitt trigger 1 412-1 to Schmitt trigger N 412-N. The second buffer 414 is numbered as second buffer 1 414-1 to second buffer N 414-N. The inverter 416 is numbered as inverter 1 416-1 to inverter N 416-N.

[0074] The input of gate driver 402 receives a data signal (e.g., logic 1 or logic 0). In response to the input of gate driver 402, CAN transmitter 100 transmits a DOM signal or a REC signal. The output of gate driver 402 is coupled to the input of delay unit 1404-1. For i equal to 1 through N-1, the inverted output of delay unit i 404-i is coupled to the control terminals of swb_Hi232-i and swb_Li 244-i. The non-inverted output of delay unit i 404-i is coupled to the input of delay unit (i+1)404-(i+1) and to the control terminals of sw_Hi 228-i and sw_Li 240-i. For i equal to N, the inverted output of delay unit N 404-N is coupled to the control terminals of swb_HN 232-N and swb_LN 244-N. The non-inverting output of delay unit i 404-i is coupled to the control terminals of sw_HN 228-N and sw_LN 240-N.

[0075] The input of delay unit i 404-i is coupled to the input of first buffer i 406-i. The output of first buffer i 406-i is coupled to the first terminal of resistor Rdelay i 408-i. The second terminal of Rdelay i 408-i is coupled to the first terminal of capacitor Ci410-i and the input of Schmitt trigger i 412-i. The output of Schmitt trigger i 412-i is coupled to the input of second buffer i 414-i and the input of inverter i 416-i. The output of first buffer i 414-i is coupled to the inverted output of delay unit i 404-i. The output of inverter i 416-i is coupled to the non-inverted output of delay unit i 404-i. In some instances, the Schmitt trigger provides a digital output that is inverted relative to its input and lags changes in its input according to the designed hysteresis. In some instances, the use of Schmitt triggers allows the circuit to avoid shoot-through.

[0076] Gate driver 402 provides a first signal or a second signal. Each Ci 410-i and its corresponding Rdelayi 408-i form an RC circuit that charges or discharges in response to a (charging) high voltage signal or a (discharging) low voltage signal provided by gate driver 402 or by sequentially preceding Schmitt triggers (i-1) 412-(i-1). The first or second signal is a high voltage signal that controls the various Ci 410-i to charge at a rate corresponding to the RC time constant corresponding to the respective Ci 410-i and Rdelayi 408-i. The other signal (the second signal or the first signal) is a low voltage signal that controls the various Ci 410-i to discharge at a rate corresponding to the RC time constant corresponding to the respective Ci 410-i. The charging and discharging rates are also responsive to the voltage of the signal provided by gate driver 402 or sequentially preceding Schmitt triggers (i-1) 412-(i-1) at the input of the corresponding delay unit i 404-i.

[0077] Therefore, the time response between the sequential turn-on of MP5 226 and / or MN5 238 (numbered i-1 and i) corresponds to Schmitt trigger (i-1)412-(i-1), Rdelay i 408-i, and Ci 410-i. Similarly, the time response between the sequential turn-off of MP5 226 and / or MN5 238 (numbered i+1 and i) corresponds to Schmitt trigger (i+1)412-(i+1), Rdelay i 408-i, and Ci 410-i. MP5 226 and MN5 238 are turned on sequentially from i equal to 1 to N, and MP5 226 and MN5 238 are turned off sequentially from i equal to N to 1. Regarding Figure 5 , 6 Section 7 further describes the on and off states of MP5 226 and MN5 238.

[0078] The first signal controls the non-inverting switches SW_Hi 228-i and SW_Li 240-i to close and the inverting switches SWb_Hi 232-i and SWb_Li 244-i to open. The second signal controls the non-inverting switches SW_Hi 228-i and SW_Li 240-i to open and the inverting switches SWb_Hi 232-i and SWb_Li 244-i to close.

[0079] In this example, when the gate driver 402 provides the first signal, SW_Hi 226-i and SW_Li 226-i sequentially close and SWb_Hi 232-i and SWb_Li 244-i open, where i equals 1 to N. Various resistors of Rdelay-i 408-i, various capacitors of Ci 410-i, and delays contributed by various Schmitt triggers i 412-i are selected such that when the gate driver 402 provides the first signal, switches SW_Hi 226-i and SW_Li 226-i close and SWb_Hi 232-i and SWb_Li 244-i open at a designed timing.

[0080] Similarly, in this example, when the gate driver 402 provides the second signal, SW_Hi 226-i and SW_Li 226-i are sequentially turned off and SWb_Hi 232-i and SWb_Li 244-i are turned on, where i equals 1 to N. The resistors of various Rdelay-i408-i, the capacitors of various Ci 410-i, and the delay contributed by various Schmitt triggers i 412-i are chosen such that when the gate driver 402 provides the second signal, switches SW_Hi 226-i and SW_Li 226-i are turned off and SWb_Hi232-i and SWb_Li 244-i are turned on at a designed timing. In some examples, the delay contributed by the RC circuit and the Schmitt trigger i 412-i is sufficiently greater than the delay contributed by the inverter 416, such that the delay contributed by the inverter 416 is negligible.

[0081] about Figure 5 The timing of the control signals provided by the control circuit 110 is further described.

[0082] Figure 5 yes Figure 2BA graph 500 showing the source-gate voltage (Vsg) or gate-source voltage (Vgs) of the current source MP5 226 and current sink MN5 238 (respectively) relative to time. The vertical axis corresponds to voltage and the horizontal axis corresponds to time. Recall that MP5-1 226-1 and MN5-1 238-1 are turned on simultaneously, MP5-2 226-2 and MN5-2 238-2 are turned on simultaneously, MP5-3 226-3 and MN5-3 238-3 are turned on simultaneously, and so on. The first Vgs curve (Vgs_1) 502-1 corresponds to the Vgs of each of MP5-1226-1 and MN5-1238-1, the second Vgs curve (Vgs_2) 502-2 corresponds to the Vgs of each of MP5-2 226-2 and MN5-2 238-2, and the third Vgs curve (Vgs_3) 502-3 corresponds to the Vgs of each of MP5-3 226-3 and MN5-2 238-3, and so on.

[0083] Figure 500 corresponds to the various MP5 226 and MN5 238 turn-on. The Vgs502 of each of the MP5 226 and MN5 238 starts at zero volts. In some instances, Vgs starts at a different zero-volt value below the threshold gate-source voltage (Vth) of each MP5 226 and MN5 238. When an MP5 226 or MN5 238 is fully turned on, the current through its corresponding charging resistor Rchg_H 230 or Rchg_L 242 is zero, and the Vgs of said MP5 226 or MN5 238 is equal to the design value Vgs_SET. The Vgs_SET of MP5 226 corresponds to or is equal to the difference between Vcc and BIAS_P. The Vgs_SET of MN5 238 corresponds to or is equal to the difference between the ground voltage and BIAS_N.

[0084] At time T1, SWb_H1 232-1 is open and SW_H1 228-1 is closed, and SWb_L1 244-1 is open and SW_L1 240-1 is closed. This causes Vgs_1 502-1 to start rising for both MP5-1 226-1 and MN5-1 238-1. Therefore, MP5-1 226-1 and MN5-1 238-1 are turned on at time T1.

[0085] At T2, SWb_H2 232-2 is open and SW_H1 228-2 is closed, and SWb_L2 244-2 is open and SW_L2 240-2 is closed. This causes Vgs_2 502-2 to start rising for both MP5-2 226-2 and MN5-2 238-2. Therefore, MP5-2 226-2 and MN5-1 238-2 begin to turn on at T2. Similarly, MP5-3 226-3 and MN5-1 238-3 begin to turn on at T3. (See also: Regarding...) Figure 4 As described, there is a design time T_STAG between T1 and T2. The resistance value of Rdelayi 408-i, the capacitance of Ci410-i, and the delay contributed by Schmitt trigger i 414-i are designed such that there is a constant time T_STAG between the continuous activation state changes of the high-side switch and the low-side switch. Therefore, the time from T2 to T3 is equal to T_STAG.

[0086] MP5-1 226-1 and MN5-1 238-1 are turned on at T4. The time from T1 to T4 (which is the amount of time it takes for MP5-1 226-1 and MN5-1 238-1 to be turned on) is equal to Ton_1. The amount of time it takes for MP5-2 226-2 and MN5-2 238-2 to be turned on is shorter than Ton_1. As mentioned above, the amount of time it takes for each MP5 226 and MN5 238 to be turned on responds to its gate-source capacitance and its corresponding Rchg_H 230 or Rchg_L 240. Moreover, the amount of time it takes for each MP5 226 and MN5 238 to be turned off responds to its gate-source capacitance and its corresponding Rdschg_H 234 or Rdschg_L246.

[0087] In some instances, shorter turn-on or turn-off times correspond to faster Vgs changes. Longer turn-on or turn-off times correspond to slower Vgs changes. The consecutively short turn-on times for MP5 226 and MN5 238 ensure a constant rate of change in resistance for both the MP5 226 and MN5 238 networks. Similarly, the consecutively long turn-off times for MP5 226 and MN5 238 ensure a constant rate of change in resistance for both the MP5 226 and MN5 238 networks. Therefore, the turn-on time Ton_N for MP5-N 226-N and MN5-N 238-N is the shortest turn-on time.

[0088] In some instances, the earlier-turned-on MP5 226 and MN5 238 (e.g., i = 1) initially do this in the saturation region, such that the decrease in resistance over time contributed by that (or those) MP5 226 and MN5 238 is relatively large when in the saturation region. In some instances, the later-turned-on MP5 226 and MN5 238 (e.g., i = N) initially do this in the linear region, such that the decrease in resistance over time contributed by that (or those) MP5 226 and MN5 238 is relatively small. In some instances, the turn-on in the saturation region responds to a relatively high drain-source voltage, and the turn-on in the linear region responds to a relatively low drain-source voltage.

[0089] The total time taken to connect all MP5 226 and MN5 238 is Tswitch. Tswitch equals the time from T1 (when MP5-1 226-1 and MN5-1 238-1 begin to connect) to T5 (when MP5-N 226-N and MN5-N 238-N complete to connection). T_STAG is designed to be less than the connection time Ton_i for each individual MP5 226 (or MN5 238). Therefore, Tswitch equals (N-1) × T_STAG + Ton_N, which is less than the sum of the connection times for MP5 226 (or MN5 238) (Ton_1 plus Ton_2 plus ..., Ton_N). In this example, Ton_1 equals 4 × T_STAG and Ton_N equals T_STAG.

[0090] The Vgs curves for MP5 226 and MN5 238 when turned off (not shown) decrease from Vgs_SET to 0 (or other baseline voltage). As mentioned above, in some instances, the turn-off time differs from the turn-on time, but they remain equal (matched) between the corresponding MP5-i 226-i and MN5-i 238-i. In some instances, the Vgs curves for MP5 226 and MN5 238 when turned off are approximately the same as those for MP5 226 and MN5 238 when turned on (within design constraints), but the duration order is reversed.

[0091] To achieve this, the current-outflow switch MP5-i 226-i and the current-inflow switch MN5-i 238-i are turned off in the same order they were turned on (i equals 1, then 2, then 3, etc.). The resistor values ​​of Rdschg_H 234 and Rdschg_L 246 are chosen such that the turn-off times are initially longer and then gradually shortened. MP5-1 226-1 and MN5-1 238-1 are turned off first, with a turn-off time Toff_1 equal to Ton_N. MP5-1 226-N and MN5-1 238-N are turned off last, with a turn-off time Toff_N equal to Ton_1. Therefore, Toff_1 equals Ton_N, Toff_2 equals Ton_(N-1), Toff_3 equals Ton_(N-2), and so on.

[0092] In this example, if all MP5 226 matches and all MN5 238 matches, then the resistance of Rdscg_H1 234-1 is equal to the resistance of Rchg_HN 230-N, and the resistance of Rdschg_L1 246-1 is equal to the resistance of Rchg_HN 242-N. Assume R (component) represents the resistance of the component. Therefore, Rdschg_Hi 234-i is equal to Rchg_H(N-i+1)230-(N-i+1), and Rdschg_Li 246-i is equal to Rchg_L(N-i+1)242-(N-i+1).

[0093] Figure 6 It is used for Figure 1 The graph shows the current supplied to CAN_H 120H by the output control stage 104 relative to time. The vertical axis corresponds to current and the horizontal axis corresponds to time. The total current supplied to CAN_H 120H by the MP5 226 network is I_H. The total current supplied to CAN_L 120L by the MN5 238 network is I_L. Curve 602 represents I_H and I_L. Therefore, curve 602 represents the ideal equal current supplied to CAN_H 120H and CAN_L 120L during the MP5 226 network turn-on and MN5 238 network turn-on periods, respectively. Improved current matching is achieved by turning on the corresponding MP5-i 226-i and MN5 238-i transistors in a time-interleaved sequence at a controlled linear rate. As described above, the controlled linear turn-on rate responds to Rchg_H 230 and Rchg_L 242 and the corresponding gate-source capacitances of MP5 226 and MN5 238.

[0094] Before the MP5 226 network and MN5 238 network are turned on, I_H and I_L 602 have a reference (initial) value, such as zero amperes. When MP5-1 226-1 and MN5-1 238-1 are turned on, I_H and I_L 602 begin to increase, which corresponds to the control circuit 110 controlling SWb_H1 232-1 and SWb_L1 244-1 to turn off, and controlling SW_H1 228-1 and SW_L1 240-1 to turn on. Therefore, as described above, when the respective gates of MP5-1 226-1 and MN5-1 238-1 are decoupled from Vcc 222 and ground terminal 224 and coupled to P_BIAS and N_BIAS respectively, MP5-1 226-1 and MN5-1 238-1 are turned on at T1. MP5-1 226-1 and MN5-1 238-1 are fully turned on at T4. In some instances, therefore, after MP5-1 226-1 and MN5-1 238-1 are fully turned on, I_H and I_L 602 exceed 90% of the maximum value I_NETWORK at T4. In some instances, after all switches MP5-i 226-i and MN5-i 238-i controlling the current supply to the CAN bus 120 are fully turned on, I_H and I_L 602 reach the maximum value I_NETWORK at T5.

[0095] During the shutdown of the MP5 226 and MN5 238 networks, the reduced I_H and I_L curves 602, relative to when the MP5 226 and MN5 238 networks are on, are similar to those in... Figure 6 The increased I_H and I_L curves 602 are illustrated in graph 600. During the MP5 226 network and MN5 238 network uptime, the decreased I_H and I_L curves 602 decrease from I_NETWORK to the baseline value.

[0096] In some instances, the timing of the current decrease differs from the timing of the current increase, corresponding to the relationship between the two currents. Figure 5 The timing difference described is between the turn-on and turn-off states. The timing difference is in response to the resistance difference between the MP5 226 and MN5 238 gate charging resistors (Rchg_H230 and Rchg_L242) and the MP5 226 and MN5 238 gate discharging resistors (Rdschg_H234 and Rdschg_L246).

[0097] Figure 7 yes Figure 1The graph 700 shows the total impedance of the current path of the first current source block 112 or the second current source block 114 relative to time. The vertical axis corresponds to resistance and the horizontal axis corresponds to time. As described above, the MP5 226 network and the MN5 238 network are turned on such that during the turn-on period, the total resistance of the MP5 226 network is equal to the total resistance of the MN5 238 network. Therefore, during the turn-on period of MP5 226 and MN5 238, the resistance curve 702 corresponds to the resistance of the MP5 226 network and the resistance of the MN5 238 network. As described above, the resistance curve 702 runs from T1 (start of turn-on) to T5 (end of turn-on). Figure 5 The resistance is approximately linear (e.g., linear enough to satisfy design constraints). In T5, the resistance of the MP5 226 network is equal to the resistance of the MN5 238 network, which is equal to the value R_NETWORK.

[0098] In some instances, the structures and processes described herein are applicable to differential signaling systems other than CAN systems.

[0099] In some instances, a current trap can be described as a negative current source.

[0100] In some instances, T_STAG is greater than Ton_N.

[0101] In some instances, there is an external 60-ohm load coupled between CAN_H 120H and CAN_L 120L.

[0102] In some instances, delay unit 404 contains components that are different from those described herein.

[0103] The circuits or devices described herein as containing certain components may be substantially adapted to be coupled to those components to form the described circuit system or device. For example, a structure described as containing one or more semiconductor elements (e.g., transistors), one or more passive elements (e.g., resistors, capacitors, and / or inductors), and / or one or more sources (e.g., voltage sources and / or current sources) may conversely contain semiconductor elements (e.g., semiconductor dies and / or IC packages) within only a single physical device, and may be adapted to be coupled to at least some of the passive elements and / or sources to form the described structure, for example, during or after manufacture by an end user and / or a third party.

[0104] The techniques described in this disclosure may also be embodied or encoded in articles of art comprising non-transitory computer-readable storage media. Examples of non-transitory computer-readable storage media may include random access memory (RAM), read-only memory (ROM), programmable ROM, erasable programmable ROM, electronically erasable programmable ROM, flash memory, solid-state drive, hard disk, magnetic media, optical media, or any other computer-readable storage device or tangible computer-readable medium. The term "non-transitory" may indicate that the storage medium is not embodied in a carrier wave or propagating signal. In some instances, non-transitory storage media may store data that may change over time (e.g., in RAM or cache).

[0105] While the use of specific transistors is described herein, other transistors (or equivalent devices) may be used alternatively with little or no change to the remaining circuitry. For example, metal-oxide-semiconductor FETs (“MOSFETs”) (e.g., n-channel MOSFETs, nMOSFETs, or p-channel MOSFETs, pMOSFETs), bipolar junction transistors (BJTs, such as NPN or PNP), insulated-gate bipolar transistors (IGBTs), and / or junction field-effect transistors (JFETs) may be used in place of or in combination with the devices disclosed herein. Transistors may be depletion-mode devices, drain-extended devices, enhancement-mode devices, natural transistors, or other types of device structure transistors. Furthermore, the devices may be implemented on / above a silicon (Si) substrate, a silicon carbide (SiC) substrate, a silicon-germanium (SiGe) substrate, a gallium nitride (GaN) substrate, or a gallium arsenide (GaAs) substrate.

[0106] The circuits described herein can be reconfigured to include replacement components to provide functionality at least partially similar to that available before the component replacement. Unless otherwise stated, components shown as resistors generally represent any one or more elements coupled in series and / or parallel to provide the amount of impedance represented by the shown resistor. For example, a resistor or capacitor shown and described herein as a single component may alternatively be multiple resistors or capacitors coupled in parallel between the same nodes. For example, a resistor or capacitor shown and described herein as a single component may actually be multiple resistors or capacitors coupled in series between the same two nodes as the single resistor or capacitor.

[0107] While some components of the described examples may be included in the IC and others may be external to the IC, in other example embodiments, additional or fewer features may be incorporated into the IC. Additionally, some or all features shown as external to the IC may be included in the IC, and / or some features shown as internal to the IC may be incorporated externally. As used herein, the term "integrated circuit" means one or more circuits that are: (i) incorporated in / on a semiconductor substrate; (ii) incorporated in a single semiconductor package; (iii) incorporated in the same module; and / or (iv) incorporated in / on the same printed circuit board.

[0108] The use of the phrase “ground” in the preceding description includes chassis ground, ground wire ground, floating ground, virtual ground, digital ground, general ground, and / or any other form of grounding connection applicable to or suited to the teachings of this description. Unless otherwise stated, “about,” “approximately,” or “substantially” preceding a value indicates + / - 10% of said value, or, if the value is zero, a reasonable range of values ​​near zero.

[0109] Although this disclosure has been described with reference to illustrative embodiments, this specification is not intended to be limiting. Those skilled in the art will understand, upon referring to this specification, various modifications and combinations of the illustrative embodiments and other embodiments.

[0110] Within the scope of the claims, modifications to the described instances are possible, and other instances are also possible.

Claims

1. An apparatus comprising: a bias voltage circuit having a first output and a second output; an output circuit having first and second inputs and first and second outputs; and a plurality of current source circuits, each current source circuit having a first input, a second input, and an output, the first inputs of a first plurality of the current source circuits coupled to the first output of the bias voltage circuit, the first inputs of a second plurality of the current source circuits coupled to the second output of the bias voltage circuit, the outputs of the first plurality of the current source circuits coupled to the first input of the output circuit, and the outputs of the second plurality of the current source circuits coupled to the second input of the output circuit, each of the current source circuits including: a first resistor having first and second terminals, the first terminal of the first resistor coupled to the first input of the current source circuit; a second resistor having first and second terminals; a first switch having first and second terminals and a control terminal, the first terminal of the first switch coupled to the second terminal of the first resistor; a second switch having first and second terminals and a control terminal, the first terminal of the second switch coupled to the second terminal of the second resistor; and a transistor having first and second terminals and a control terminal, the first terminal of the transistor coupled to the first terminal of the second resistor and the second input of the current source circuit, the second terminal of the transistor coupled to the output of the current source circuit, and the control terminal of the transistor coupled to the second terminal of the first switch and the second terminal of the second switch.

2. The apparatus of claim 1, wherein the first output of the output circuit is responsive to the first input of the output circuit; and wherein the second output of the output circuit is responsive to the second input of the output circuit.

3. The apparatus of claim 1, wherein the transistor is a first transistor, and wherein the output circuit includes: a third resistor having first and second terminals; a fourth resistor having first and second terminals, the first terminal of the fourth resistor coupled to the first terminal of the third resistor; a second transistor having first and second terminals and a control terminal, the first terminal of the second transistor coupled to the first input of the output circuit; a third transistor having first and second terminals and a control terminal, the first terminal of the third transistor coupled to the second terminal of the second transistor, and the second terminal of the third transistor coupled to the second terminal of the third resistor and the first input of the output circuit; a fourth transistor having first and second terminals and a control terminal, the first terminal of the fourth transistor coupled to the second input of the output circuit; and a fifth transistor having first and second terminals and a control terminal, the first terminal of the fifth transistor coupled to the second terminal of the fourth transistor, and the second terminal of the fifth transistor coupled to the second terminal of the third resistor and the second input of the output circuit. ​ a fifth transistor having first and second terminals and a control terminal, the first terminal of the fifth transistor coupled to the second terminal of the fourth transistor, and the second terminal of the fifth transistor coupled to the second terminal of the fourth resistor and the second input of the output circuit.

4. The apparatus of claim 1, wherein the output circuit has a third input, the apparatus further comprising a common mode voltage circuit having an output, the output of the common mode voltage circuit coupled to the third input of the output circuit, and the first terminals of the third and fourth resistors coupled to the third input of the output circuit.

5. The apparatus of claim 4, wherein the first output of the output circuit is responsive to the first and third inputs of the output circuit; and wherein the second output of the output circuit is responsive to the second and third inputs of the output circuit.

6. The apparatus of claim 1, wherein the second inputs of the first plurality of the current source circuits are coupled together; and wherein the second inputs of the second plurality of the current source circuits are coupled together.

7. The apparatus of claim 1, further comprising: a plurality of delay circuits, each of the delay circuits having an input and first and second outputs; wherein the first output of each of the delay circuits is coupled to a different pair of control terminals of first switches of the first plurality of the control circuits and first switches of the second plurality of the control circuits.

8. The apparatus of claim 7, wherein the second output of each of the delay circuits is coupled to a different pair of control terminals of second switches of the first plurality of the control circuits and first switches of the second plurality of the control circuits.

9. The apparatus of claim 7, wherein each of the delay circuits includes: a third resistor having first and second terminals, the first terminal of the third resistor coupled to the input of the delay circuit; a capacitor having first and second terminals; and a Schmitt trigger having an input and an output, the input of the Schmitt trigger coupled to the first terminal of the third resistor and the first output of the delay circuit.

10. The apparatus of claim 9, wherein the resistance of the third resistor, the capacitance of the capacitor, and the delay of the Schmitt trigger are selected so that the first switches of the first plurality of control circuits are sequentially closed, and have equal delays between sequentially adjacent pairs of first switches.

11. The apparatus of claim 7, wherein the delay circuits are coupled in series.

12. The apparatus of claim 11, further comprising a gate driver having an output coupled to the input of a first one of the delay circuits in the series.

13. The apparatus of claim 1, wherein each transistor of the second plurality of current source circuits has a body terminal coupled to the second input of a respective current source circuit.

14. The apparatus of claim 1, wherein the apparatus is a controller area network transmitter.

15. An apparatus comprising: a bias voltage circuit having a first output and a second output; a first current source circuit having an input and an output, the input of the first current source circuit coupled to the first output of the bias voltage circuit; a second current source circuit having an input and an output, the input of the second current source circuit coupled to the second output of the bias voltage circuit; an output circuit having a first input, a second input, a third input, a first output, and a second output, the first input of the output circuit coupled to the output of the first current source circuit and the second input of the output circuit coupled to the output of the second current source circuit; a first transistor having a first terminal, a second terminal, and a control terminal; a second transistor having a first terminal, a second terminal, and a control terminal; a third transistor having a first terminal, a second terminal, and a control terminal, the first terminal of the third transistor coupled to the first terminal of the first transistor and the control terminal of the third transistor coupled to the control terminal and the second terminal of the first transistor and the control terminal and the first terminal of the second transistor; a fourth transistor having a first terminal, a second terminal, and a control terminal; a fifth transistor having a first terminal, a second terminal, and a control terminal, the second terminal of the fifth transistor coupled to the second terminal of the second transistor; and a sixth transistor having a first terminal, a second terminal, and a control terminal, the first terminal of the sixth transistor coupled to the first terminal of the fourth transistor, the second terminal of the sixth transistor coupled to the second terminal of the third transistor and the third input of the output circuit, and the control terminal of the sixth transistor coupled to the control terminal and the second terminal of the fourth transistor and the control terminal and the first terminal of the fifth transistor.

16. The apparatus of claim 15, further comprising: a first resistor having first and second terminals, the first terminal of the first resistor coupled to the control terminal and the second terminal of the first transistor and the second terminal of the first resistor coupled to the control terminal and the first terminal of the second transistor and the control terminal of the third transistor; and a second resistor having first and second terminals, the first terminal of the second resistor coupled to the control terminal and the second terminal of the fourth transistor and the second terminal of the second resistor coupled to the control terminal and the first terminal of the fifth transistor and the control terminal of the sixth transistor. ​ ​ 17. The apparatus of claim 15, wherein the first transistor and the fifth transistor are p-channel metal-oxide-semiconductor field-effect transistors (MOSFETs); and wherein the second transistor and the fourth transistor are n-channel MOSFETs.

18. The apparatus of claim 17, wherein the third transistor is an n-channel MOSFET; and wherein the sixth transistor is a p-channel MOSFET.

19. The apparatus of claim 15, wherein the first output of the output circuit is responsive to the first and third inputs of the output circuit; and wherein the second output of the output circuit is responsive to the second and third inputs of the output circuit.

20. The apparatus of claim 15, wherein the apparatus is a controller area network transmitter.

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