AFDX network redundant port self-loop communication test system and method
By constructing an AFDX network redundant port self-loop communication test system, the problems of high cost, low efficiency, and poor accuracy of existing test systems are solved, realizing accurate simulation and quantitative evaluation of the entire process of avionics networks and providing an efficient test solution.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-12-03
- Publication Date
- 2026-03-10
AI Technical Summary
Existing AFDX network testing systems rely on a large amount of dedicated hardware, resulting in high procurement and maintenance costs, low testing efficiency, poor accuracy, and susceptibility to electromagnetic interference and network fluctuations, thus failing to meet the high-precision testing requirements of avionics networks.
The AFDX network redundant port self-loop communication test system simplifies the test architecture and constructs a self-loop test architecture to achieve comprehensive evaluation of BAG, LMAX, and JITTER parameters. Utilizing modular design and hardware acceleration, it achieves full-process test coverage, including data sending, transmission, reception, and analysis, and supports redundancy mode switching to ensure that data meets protocol and test scenario requirements.
It enables accurate simulation and quantitative evaluation of the entire AFDX network process, improves testing accuracy and efficiency, reduces testing costs, provides technical support for avionics networks, and ensures network performance optimization and reliability.
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Figure CN121644404A_ABST
Abstract
Description
Technical Field
[0001] This invention belongs to the field of avionics network testing technology, specifically relating to an AFDX network redundant port self-loop communication testing system and method. Background Technology
[0002] As the core transmission network of the avionics system, the AFDX network's BAG (minimum transmit interval), LMAX (maximum frame length), and JITTER (jitter) parameters directly affect the network's real-time performance, throughput, and stability. Its determinism, reliability, and real-time performance are verified through a systematic approach.
[0003] Currently, common testing methods include protocol conformance testing, end-to-end latency testing, and throughput testing. Protocol conformance testing verifies whether the end system and switch conform to the ARINC664 protocol (such as MAC address allocation and IP / UDP header format) and test frame format (such as check fields and redundancy management fields). End-to-end latency measures the maximum / minimum delay of a frame from the sender to the receiver, which must meet the timing requirements of the avionics system. Throughput testing verifies whether the bandwidth utilization of the VL exceeds the theoretical limit. Existing testing systems are generally stand-alone, single-device testing modes, lacking multi-indicator testing capabilities, often leading to compromised equipment accuracy and impacting product delivery. The following problems exist in existing technologies, both in the market and during network testing: 1) The test environment is complex and relies on a large amount of dedicated hardware, resulting in high procurement and maintenance costs: There are many network indicator parameters, which makes the required test resources extremely complex. Different hardware needs to be built for environment setup, relying on a large amount of dedicated hardware, resulting in high testing costs and easy waste of resources. 2) Low testing efficiency and high time cost: The network indicator test data volume is large and the data types are numerous. Due to the strong uniformity of equipment testing, the indicator test runs in a complicated manner according to the established procedure, resulting in low testing efficiency and high time cost.
[0004] 3) Poor test accuracy: Traditional index tests are easily affected by external factors such as electromagnetic interference and network fluctuations, resulting in insufficient accuracy and failing to meet the AFDX network card's requirement for accurate test data. Summary of the Invention
[0005] This invention proposes a self-loop communication testing method and system for redundant ports in AFDX networks during network testing. By simplifying the testing architecture and constructing a self-loop testing architecture, it enables a comprehensive evaluation of BAG, LMAX, and JITTER parameters, providing technical support for performance optimization and reliable application of avionics networks.
[0006] To achieve the above, the present invention adopts the following technical solution: In a first aspect, this application provides an AFDX network redundant port self-loop communication test system, comprising: a test control module, a parameter allocation module, a bus management module, and a data calculation closed-loop processing module, wherein: The test control module, parameter adjustment module, bus management module, and data calculation closed-loop processing module are interconnected; The test control module is used to manage the process of AFDX data transmission testing. The parameter configuration module is used to inject and configure AFDX data parameters, so that the sent data frames conform to the AFDX protocol and test requirements, simulating the data transmission of real devices. The test port management module is used to implement port redundancy management, simulate and detect redundant ports, and enable link switching of multiple ports; The data calculation closed-loop processing module is used to implement AFDX data test calculation process control and result analysis.
[0007] Specifically, the parameter allocation module includes a parameter configuration module, a transmission scheduling module, a timestamp generation module, and a time synchronization module; the bus management module includes a redundancy management module, an AFDX network card A port module, and an AFDX network card B port module; the data calculation closed-loop processing module includes a receiving processing module, a data acquisition module, a data analysis module, a calculation module, a test logic module, and a register storage module. The test control module generates and sends control commands to start the self-loop communication test, sends control signals to the sending scheduling module and the parameter configuration module, controls the start / stop of the sending scheduling module and configures the test scenario, and realizes process control of AFDX data transmission test. The parameter configuration module is responsible for sending configuration signals to the transmission scheduling module to configure parameters, define the transmission attributes of AFDX data frames, and ensure that the transmitted data conforms to the AFDX protocol and test requirements, simulating the data transmission behavior of real avionics equipment.
[0008] Specifically, the AFDX network card A port module is the data transmission interface of the AFDX network card. It encapsulates the data frames prepared by the transmission scheduling module into signals that conform to the protocol according to the AFDX physical layer and data link layer specifications, and sends them to the AFDX switch through the physical connection. At the same time, it receives control signals from the redundancy management module to realize link switching. The AFDX network card B port module serves as the data receiving interface of the AFDX network card. It receives data frames from the AFDX switch, performs physical layer signal parsing and link layer verification, extracts valid data and transmits it to the receiving processing module, and simultaneously receives control signals from the redundancy management module to achieve link switching.
[0009] Specifically, the sending scheduling module manages the data to be sent according to the instructions of the test control module and the parameters of the parameter configuration module. At the same time, it reports the working status to the test control module in real time through status feedback signals, including data frame assembly, sending timing control, traffic shaping, etc., to ensure that the sent data meets the requirements of the protocol and test scenario.
[0010] Specifically, the timestamp generation module receives the synchronization signal provided by the time synchronization module, marks the reception time of the data frame, generates a high-precision timestamp for the transmitted / received data frame, and reports the clock synchronization status to the time synchronization module. The clock synchronization module adjusts the calibration strategy based on the feedback information. During transmission, the timestamp generation module sends the transmission time of the marked data frame to the transmission scheduling module and the reception processing module. The receiving and processing module receives AFDX data frames from the timestamp generation module and performs preprocessing, including parsing the frame structure, verifying data integrity, filtering invalid frames, and distributing valid data to the data acquisition module, calculation module, and test logic module for acquisition and calculation.
[0011] Specifically, the data acquisition module obtains raw data from the receiving and processing module, collects key information according to test requirements, and stores or uploads it to the data analysis module in real time; the acquisition rules can be configured to retain raw data samples for subsequent analysis. The data analysis module analyzes the raw data from the data acquisition module, including statistical data traffic, analyzing data frame loss rate, verifying the correctness of data content (comparing the consistency of sent / received data), calculating transmission delay distribution by associating timestamps, and outputting visualized analysis results to help determine whether the AFDX network transmission performance and functions meet expectations. It also calculates and evaluates the data values of the calculation module and provides analysis results to the system. The calculation module calculates the jitter during data frame transmission. By statistically analyzing the delay deviation of multiple data frames and the jitter distribution characteristics, it evaluates the time determinism of AFDX network transmission. The receiving and processing module, along with its corresponding sending and receiving timestamps and calculation trigger signals, performs data calculations and then feeds back the calculation status to the receiving and processing module.
[0012] Specifically, the redundancy management module monitors the working status of the AFDX network card A port module and the AFDX network card B port module in real time. The A port and the B port transmit their own status information to the redundancy management module through the status signal line to realize redundancy switching. The test logic module executes test logic according to the test scenario requirements; according to the preset scenario, it sends business data injection instructions to the test control module and data verification rules to the receiving and processing module. The test logic module monitors the data transmission during the redundancy switching process and realizes the generation of network test cases. The register storage module stores the configuration parameters, status information, calculation results, etc. of the AFDX network card and the test system, and saves the frame statistics information and test results of the test logic module and the calculation module, providing data caching and persistence support for system operation and test analysis.
[0013] Secondly, this application provides a method for testing the self-loop communication of redundant ports in an AFDX network, comprising the following: Step 1: Run the test computer, connect the test cable between the AFDX switch and the system, turn on the test system power, and power on both the system and the AFDX switch; Step 2: The test computer sends control commands to the test control module. The test control module receives the command data and sends it to the parameter configuration module. After completing the parameter configuration, the parameter configuration module sends the parameters to the sending scheduling module for test scheduling. Step 3: The test control module sends test commands to the sending scheduling module and simultaneously receives feedback signals from the sending scheduling module to perform test control scheduling; Step 4: The dispatch module sends data frames to the AFDX network card A port module. After processing by the port, the module sends the data to the switch, completing the data transmission. Step 5: The AFDX network card B port module receives data from the AFDX switch and sends received data frame information to the receiving processing module; Step 6: The redundancy management module monitors and controls the redundancy switching between the AFDX network card A port module and the AFDX network card B port module, thus completing redundancy management; Step 7: The receiving and processing module reads the data frame, receives the time synchronization signal from the time synchronization module and the timestamp generation module, and completes the data triggering and frame information generation; Step 8: The receiving and processing module generates frame information and sends the raw data to the data acquisition module. The data acquisition module sends an acquisition signal to the receiving and processing module and sends a data frame to the calculation module at the same time. Step 9: After the data acquisition module completes data acquisition, it sends a signal to the data analysis module. The data analysis module performs data analysis and calculations, and transmits the analysis results to the test computer. Step 10: The receiving and processing module transmits the data to the test logic module. The test logic module sends the data verification rules to the receiving and processing module, synchronously sends a trigger signal to the redundancy management module, and sends the result to the register storage module. Step 11: The calculation module sends the calculated data to the register storage module for data storage; Step 12: After the test results are generated, it will show whether the AFDX network function performance is normal. At this time, the test is complete. Turn off the power of the AFDX switch and the computer, and disconnect the test cable.
[0014] Compared with the prior art, the beneficial effects of the present invention are as follows: 1. This invention constructs a set of AFDX network redundant port self-loop communication test method and system, which only requires testing network cards, switches, test modules and other hardware. Through the collaborative work of the modules, it can realize the full process test of AFDX network from "data sending-transmission-reception-analysis-verification", covering avionics network test scenarios such as functional verification, performance evaluation, and redundancy test.
[0015] 2. This invention constructs a timing system based on a clock synchronization module hardware, avoiding timing errors and clock asynchrony problems in traditional testing modes, ensuring the accuracy of timestamps and the consistency of time among various modules of the system, and improving the system testing accuracy.
[0016] 3. This invention supports enabling / disabling redundancy mode. Combined with the sending scheduling module, it schedules and manages the data to be sent according to the instructions of the test control module and the parameters of the parameter configuration module, ensuring that the sent data meets the requirements of the protocol and test scenario, and can be adapted to different test scenarios.
[0017] 4. This invention designs an AFDX network card port module to realize the sending and receiving of AFDX data frames, completes physical layer signal parsing and link layer verification, extracts valid data, and can provide dynamic performance data. At the same time, a register storage module is designed to directly access internal registers to obtain data, thereby improving analysis efficiency.
[0018] 5. This invention constructs a test system that integrates control configuration, data transmission and reception, analysis and verification, and test execution. Through modular design and hardware acceleration, it achieves accurate simulation and quantitative evaluation of the entire AFDX network transmission process, solves the testing pain points of avionics equipment in terms of protocol compliance, transmission performance, redundancy and reliability, and provides technical support for the stability of key services such as flight control and data interaction. Attached Figure Description
[0019] Figure 1 This is a hardware architecture diagram of the test system platform for this invention; Detailed Implementation To achieve the above, the present invention adopts the following technical solution: Example 1 like Figure 1As shown, this application provides an AFDX network redundant port self-loop communication test system, including: a test control module, a parameter allocation module, a bus management module, and a data calculation closed-loop processing module, wherein: The test control module, parameter adjustment module, bus management module, and data calculation closed-loop processing module are interconnected; The test control module is used to manage the process of AFDX data transmission testing. The parameter configuration module is used to inject and configure AFDX data parameters, so that the sent data frames conform to the AFDX protocol and test requirements, simulating the data transmission of real devices. The test port management module is used to implement port redundancy management, simulate and detect redundant ports, and enable link switching of multiple ports; The data calculation closed-loop processing module is used to implement AFDX data test calculation process control and result analysis.
[0020] Specifically, the parameter allocation module includes a parameter configuration module, a transmission scheduling module, a timestamp generation module, and a time synchronization module; the bus management module includes a redundancy management module, an AFDX network card A port module, and an AFDX network card B port module; the data calculation closed-loop processing module includes a receiving processing module, a data acquisition module, a data analysis module, a calculation module, a test logic module, and a register storage module. Specifically, the test control module generates and sends control commands to initiate the self-loop communication test, sends control signals to the sending scheduling module and the parameter configuration module, controls the start / stop of the sending scheduling module and configures the test scenario, and realizes process control of AFDX data transmission test.
[0021] The parameter configuration module is responsible for sending configuration signals to the transmission scheduling module to configure parameters, define the transmission attributes of AFDX data frames, and ensure that the transmitted data conforms to the AFDX protocol and test requirements, simulating the data transmission behavior of real avionics equipment.
[0022] The AFDX network card A port module is the data transmission interface of the AFDX network card. It encapsulates the data frames prepared by the transmission scheduling module into signals that conform to the protocol according to the AFDX physical layer and data link layer specifications, and sends them to the AFDX switch through the physical connection. At the same time, it receives control signals from the redundancy management module to realize link switching.
[0023] The AFDX network card B port module serves as the data receiving interface of the AFDX network card. It receives data frames from the AFDX switch, performs physical layer signal parsing and link layer verification, extracts valid data and transmits it to the receiving processing module, and simultaneously receives control signals from the redundancy management module to achieve link switching.
[0024] The sending scheduling module manages the data to be sent according to the instructions of the test control module and the parameters of the parameter configuration module. At the same time, it reports the working status to the test control module in real time through status feedback signals, including data frame assembly, sending timing control, traffic shaping, etc., to ensure that the sent data meets the requirements of the protocol and test scenario.
[0025] The timestamp generation module receives the synchronization signal provided by the time synchronization module, marks the reception time of the data frame, generates a high-precision timestamp for the transmitted / received data frame, and reports the clock synchronization status to the time synchronization module. The clock synchronization module adjusts the calibration strategy based on the feedback information. During transmission, it sends the transmission time of the marked data frame to the transmission scheduling module and the reception processing module.
[0026] The receiving and processing module receives AFDX data frames from the timestamp generation module and performs preprocessing, including parsing the frame structure, verifying data integrity, filtering invalid frames, and distributing valid data to the data acquisition module, calculation module, and test logic module for acquisition and calculation.
[0027] The time synchronization module provides a unified and accurate time reference for the entire test system through an internal high-precision clock. It outputs a synchronization signal to the timestamp generation module to ensure the accuracy of the timestamps and the consistency of time across all modules in the system, meeting the time synchronization requirements of the AFDX network.
[0028] The data acquisition module obtains raw data from the receiving and processing module, collects key information according to test requirements, and stores or uploads it to the data analysis module in real time. Acquisition rules can be configured to retain raw data samples for subsequent analysis. The data analysis module analyzes the raw data from the data acquisition module, including statistical data traffic, analyzing data frame loss rate, verifying the correctness of data content (comparing the consistency of sent / received data), calculating transmission delay distribution by associating timestamps, and outputting visualized analysis results to help determine whether the AFDX network transmission performance and functions meet expectations. It also calculates and evaluates the data values of the calculation module and provides analysis results to the system.
[0029] The calculation module calculates the jitter during data frame transmission. By statistically analyzing the delay deviation of multiple data frames and the jitter distribution characteristics, it evaluates the time determinism of AFDX network transmission. The receiving and processing module, along with its corresponding sending and receiving timestamps and calculation trigger signals, performs data calculations and then feeds back the calculation status to the receiving and processing module.
[0030] The redundancy management module monitors the working status of the AFDX network card A port module and the AFDX network card B port module in real time. The A port and the B port transmit their own status information to the redundancy management module through the status signal line to realize redundancy switching.
[0031] The test logic module executes test logic according to the requirements of the test scenario. Based on the preset scenario, it sends a business data injection command to the test control module and simultaneously sends data verification rules to the receiving and processing module. The test logic module monitors the data transmission during the redundancy switchover process, thereby generating network test cases.
[0032] The register storage module stores the configuration parameters, status information, calculation results, etc. of the AFDX network card and the test system, and saves the frame statistics information and test results of the test logic module and the calculation module, providing data caching and persistence support for system operation and test analysis.
[0033] In summary, this invention provides an AFDX network redundant port self-loop communication test system, constructing a test system integrating control configuration, data transmission and reception, analysis and verification, and test execution. Through modular design and FPGA hardware acceleration, it achieves accurate simulation and quantitative evaluation of the entire AFDX network transmission process, solving the testing pain points of avionics equipment in terms of protocol compliance, transmission performance, and redundancy reliability, and providing technical assurance for the stability of critical services such as data control and data interaction.
[0034] Example 2 Taking AFDX network testing as an example, this invention provides a method for testing AFDX network redundant port loopback communication, including the following: Step 1: Run the test computer, connect the test cable between the AFDX switch and the system, turn on the test system power, and power on the system and the AFDX switch.
[0035] Step 2: The test computer sends control commands to the test control module. The test control module receives the command data and sends it to the parameter configuration module. After completing the parameter configuration, the parameter configuration module sends the parameters to the sending scheduling module for test scheduling.
[0036] Specifically, the test computer sends control commands to the test control module. The test control module activates the parameter configuration module by sending these commands. Upon receiving the enable signal, the parameter configuration module enters the working state. The test control module sends specific test scenario information (simulating different data flows and periods) to the parameter configuration module. Based on this information, the parameter configuration module generates a corresponding parameter configuration request, including parameters such as data frame length, transmission period, and priority. The parameter configuration module stores these parameters and transmits the parameter configuration data to the transmission scheduling module via the data bus. Simultaneously, it sends a parameter validity signal to inform the transmission scheduling module that it is ready, thus realizing data configuration scheduling.
[0037] Step 3: The test control module sends test commands to the sending scheduling module and simultaneously receives feedback signals from the sending scheduling module to perform test control scheduling.
[0038] Specifically, the test control module sends a start command to the transmission scheduling module. When sending the start command, it also transmits the trigger signal for the test scenario and the start time of transmission. Upon receiving the start command and trigger signal, the transmission scheduling module, in conjunction with the parameters obtained from the parameter configuration module, begins assembling data frames and controlling the transmission timing. During transmission, the transmission scheduling module reports its working status to the test control module in real time through status feedback signals. The test control module adjusts its control strategy based on the feedback information and sends a pause command when an anomaly occurs.
[0039] Step 4: The dispatch module sends data frames to the AFDX network card A port module. After processing by the port, the module sends the data to the switch, completing the data transmission.
[0040] Specifically, after the transmission scheduling module assembles the data frame, it transmits the data frame to the transmission buffer of the AFDX network card A port module via the internal data bus and sends a data ready signal. Upon detecting the data ready signal, the A port module performs physical layer and data link layer encapsulation processing on the data frame, adding a preamble, start-of-frame character, and checksum. After encapsulation, the A port module sends an enable signal to the transmission scheduling module. Upon receiving this signal, the transmission scheduling module controls the transmission of the data frame to the physical transmission circuit of the A port. The A port then sends the encapsulated signal to the AFDX switch via the physical connection and sends a completion signal to the transmission scheduling module, indicating that data transmission is complete.
[0041] Step 5: The AFDX network card B port module receives data from the AFDX switch and sends the received data frame information to the receiving processing module.
[0042] Specifically, after receiving the signal from the AFDX switch, the AFDX network card's B port module parses the signal, removes the preamble and start-of-frame character, and performs link-layer verification. If the verification passes, the B port stores the valid data frame in its receive buffer and sends a receive data signal to the receive processing module. Upon receiving this signal, the receive processing module reads the data frame from the B port via its internal data bus, completing redundant data port reception.
[0043] Step 6: The redundancy management module performs redundancy switching control and monitoring on the AFDX network card A port module and the AFDX network card B port module to complete redundancy management.
[0044] Specifically, the redundancy management module monitors the working status of ports A and B in real time, determines whether the link is normal and the data transmission status. Ports A and B transmit their own status information to the redundancy management module through status signal lines. During the redundancy switching process, they send a switching status signal to the test control module to inform it of the switching status.
[0045] Step 7: The receiving and processing module reads the data frame, receives the time synchronization signal from the time synchronization module and the timestamp generation module, and completes the data triggering and frame information generation.
[0046] Specifically: After reading a data frame, the time synchronization module periodically sends a synchronization calibration signal to the timestamp generation module. The timestamp generation module fine-tunes its own clock based on the calibration signal to ensure that the generated timestamp is consistent with the system time base. When the transmission scheduling module transmits a data frame to the AFDX network card A port module, it sends a trigger signal to the timestamp generation module. The timestamp generation module generates a transmission timestamp the instant it receives the signal and transmits the timestamp to the transmission scheduling module via the signal line. The transmission scheduling module associates and stores the timestamp with the corresponding data frame. When the AFDX network card B port module completes the data frame reception and verification, B port receives data from the AFDX switch and passes the received timestamp and data frame to the receiving processing module.
[0047] Step 8: The receiving and processing module generates frame information and sends the raw data to the data acquisition module. The data acquisition module sends an acquisition signal to the receiving and processing module and sends a data frame to the calculation module at the same time.
[0048] Specifically: After parsing the data frame, the receiving and processing module classifies the raw data according to rules. For raw data that needs to be stored, the receiving and processing module transmits it to the data acquisition module via the data bus and sends an acquisition enable signal. Upon receiving the signal, the data acquisition module stores the data according to the preset acquisition rules and sends an acquisition completion signal to the receiving and processing module. For calculation data, the receiving and processing module transmits the data frame and its corresponding send and receive timestamps to the calculation module. Upon receiving this signal, the calculation module begins to perform indicator calculations.
[0049] Step 9: After the data acquisition module completes data acquisition, it sends a signal to the data analysis module. The data analysis module performs data analysis and calculations, and then transmits the analysis results to the test computer.
[0050] Specifically, the data acquisition module records the arrival timestamps of received frames in real time. After completing data acquisition, it sends a ready signal to the data analysis module. Upon receiving this signal, the data analysis module reads the raw data from the data acquisition module via the data bus. Simultaneously, the calculation module calculates the jitter value of each frame based on the transmission / reception timestamps and transmits the calculation results to the data analysis module. The data analysis module integrates the raw data and calculation results to perform in-depth analysis, statistically analyzing data traffic, calculating packet loss rate, and analyzing latency distribution, and then transmits the analysis results to the test computer.
[0051] Step 10: The receiving and processing module transmits the data to the test logic module. The test logic module sends the data verification rules to the receiving and processing module, synchronously sends a trigger signal to the redundancy management module, and sends the result to the register storage module.
[0052] Specifically, the test logic module sends a business data injection command to the test control module according to the specified test scenario. The test control module then generates the corresponding business data frame based on the command. Simultaneously, the test logic module sends data verification rules to the receiving and processing module. Upon receiving the data, the receiving and processing module verifies it according to the rules and feeds back the verification result to the test logic module. When simulating a fault, the test logic module sends a fault trigger signal to the redundancy management module. The redundancy management module triggers a link fault based on the signal. The test logic module monitors the data transmission during the redundancy switchover process and sends the result to the register storage module to record the data.
[0053] Step 11: The calculation module sends the calculated data to the register storage module for data storage.
[0054] Specifically, after the calculation module processes the data, the register storage module stores the frame statistics, calculation results, and other data. When other modules need to read the data, the test computer sends a read address and read enable signal to the register storage module, and the register storage module outputs the data at the corresponding address to display the test results.
[0055] Step 12: After the test results are generated, it will show whether the AFDX network function performance is normal. At this time, the test is complete. Turn off the power of the AFDX switch and the computer, and disconnect the test cable.
[0056] This invention has been successfully applied to aircraft AFDX network equipment testing and field power-on verification. It constructs a self-loop communication testing method and system for redundant ports in AFDX networks. By building a self-loop test architecture, it achieves accurate testing of key parameters of the AFDX network. Through parameter configuration, time synchronization, data acquisition and analysis, combined with the high-precision timing capabilities of the hardware modules, it can accurately evaluate performance indicators such as network latency and packet loss rate, providing data support for AFDX network design optimization and performance improvement. It has the advantages of simplified test architecture, low cost, and high accuracy, realizing full-process testing of AFDX networks from "data sending-transmission-reception-analysis-verification," covering functional verification, performance evaluation, redundancy testing, and other avionics network testing needs. It has been successfully applied to equipment delivery verification, product fault diagnosis, and design verification testing. Through self-loop testing, approximately 50% of manpower and time costs are saved, conserving human resources, shortening the test cycle, and improving troubleshooting efficiency, resulting in significant economic and social benefits.
Claims
1. An AFDX network redundant port self-loop communication test system, characterized in that, The application relates to an AFDX data transmission test system, which comprises a test control module, a parameter deployment module, a bus management module and a data calculation closed-loop processing module, wherein the test control module, the parameter deployment module, the bus management module and the data calculation closed-loop processing module are connected with each other. The test control module is used for realizing flow control of AFDX data transmission test. The parameter deployment module is used for realizing AFDX data parameter injection configuration, so that the sent data frame meets the AFDX protocol and test requirements and simulates the data sending of a real device. The test port management module is used for realizing redundancy management of the port, simulating detection of a redundant port and realizing link switching of multiple ports. The data calculation closed-loop processing module is used for realizing AFDX data test calculation flow control and result analysis. The parameter deployment module comprises a parameter configuration module, a sending scheduling module, a timestamp generation module and a time synchronization module. The bus management module comprises a redundancy management module, an AFDX network card A port module and an AFDX network card B port module.
2. The system of claim 1, wherein, The data calculation closed-loop processing module comprises a receiving processing module, a data acquisition module, a data analysis module, a calculation module, a test logic module and a register storage module. The test control module generates and sends control instructions, starts a self-loop communication test, sends control signals to the sending scheduling module and the parameter configuration module, controls starting / stopping of the sending scheduling module, configures a test scene and realizes flow control of AFDX data transmission test. The parameter configuration module is responsible for sending configuration signals to the sending scheduling module to configure parameters, defines transmission attributes of the AFDX data frame, makes the sent data meet the AFDX protocol and test requirements and simulates the data sending behavior of a real avionics device.
3. The system of claim 1, wherein, The AFDX network card A port module is a data sending interface of the AFDX network card, encapsulates the data frame prepared by the sending scheduling module into a signal meeting the protocol according to the AFDX physical layer and data link layer specification, sends the signal to an AFDX switch through physical connection and receives a control signal of the redundancy management module to realize link switching. The AFDX network card B port module is a data receiving interface of the AFDX network card, receives the data frame from the AFDX switch, completes physical layer signal analysis and link layer verification, extracts valid data and transmits the valid data to the receiving processing module and receives a control signal of the redundancy management module to realize link switching.
4. The system of claim 1, wherein, The sending scheduling module schedules and manages the data to be sent according to the instructions of the test control module and the parameters of the parameter configuration module, reports the working state to the test control module in real time through a state feedback signal, assembles the data frame, controls the sending opportunity, performs flow shaping and ensures that the sent data meet the protocol and test scene requirements.
5. The system of claim 1, wherein, The timestamp generation module receives a synchronization signal provided by the time synchronization module, marks a receiving time of a data frame, generates a high-precision timestamp for the transmitted / received data frame, and reports a clock synchronization state to the time synchronization module. The receiving processing module receives the AFDX data frame from the timestamp generation module and performs preprocessing, including analyzing the frame structure, checking data integrity, filtering invalid frames, and distributing valid data to the data acquisition module, the calculation module, and the test logic module for acquisition and calculation.
6. The system of claim 1, wherein, The data acquisition module obtains raw data from the receiving processing module, acquires key information according to test requirements, and stores or uploads the raw data to the data analysis module in real time. The data analysis module analyzes the raw data from the data acquisition module, including statistical data flow, analysis of data frame loss rate, verification of data content correctness (comparison of transmitted / received data consistency), association of timestamps for calculation of transmission delay distribution, output of visual analysis results, and assistance in determining whether the AFDX network transmission performance and function meet the expectations. The calculation module calculates the jitter in the data frame transmission process by statistically analyzing the delay deviation of multiple data frames and analyzing the jitter distribution characteristics to evaluate the time determinacy of the AFDX network transmission.
7. The system of claim 1, wherein, The redundancy management module monitors the working states of the AFDX network card A port module and the AFDX network card B port module in real time, and transmits the state information of the A port and the B port to the redundancy management module through the state signal line to realize redundancy switching. The test logic module executes test logic according to test scenario requirements, sends business data injection instructions to the test control module according to the preset scenario, and sends data verification rules to the receiving processing module. The register storage module stores the configuration parameters, state information, and calculation results of the AFDX network card and the test system, and saves the frame statistical information and test results of the test logic module and the calculation module.
8. A method of testing for self-loop communication on redundant ports of an AFDX network, characterized in that, The AFDX network redundancy port self-loop communication test system and method according to any one of claims 1-7, comprising the following steps: Step 1: Run the test computer, connect the AFDX switch and the system test cable, start the test system power supply, and power on the system and the AFDX switch. Step 2: The test computer sends a control instruction to the test control module, the test control module receives the instruction data and sends it to the parameter configuration module, and the parameter configuration module completes parameter configuration and sends the parameters to the sending scheduling module for test scheduling. Step 3: The test control module sends test instructions to the sending scheduling module, and receives feedback signals from the sending scheduling module to perform test control scheduling; Step 4: The sending scheduling module sends data frames to the AFDX network card A port module, and the module sends data to the switch after port processing, completing data sending; Step 5: The AFDX network card B port module receives AFDX switch data and sends receiving data frame information to the receiving processing module; Step 6: The redundancy management module controls and monitors the redundancy switching of the AFDX network card A port module and the AFDX network card B port module, completing redundancy management; Step 7: The receiving processing module reads data frames and receives time synchronization signals from the time synchronization module and the timestamp generation module, completing data triggering and frame information generation; Step 8: The receiving processing module generates frame information and sends original data to the data acquisition module, which sends acquisition signals to the receiving processing module and data frames to the calculation module; Step 9: After completing data acquisition, the data acquisition module sends signals to the data analysis module, which performs data analysis and calculation, and transmits the analysis results to the test computer; Step 10: The receiving processing module transmits data to the test logic module, which sends data verification rules to the receiving processing module, synchronously sends trigger signals to the redundancy management module, and sends results to the register storage module; Step 11: The calculation module sends the calculated data to the register storage module for data storage; Step 12: After the test results are generated, it is displayed whether the AFDX network function performance is normal, at which time the test is completed, the AFDX switch and the computer power are turned off, and the test cable is removed.
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