Low-power-consumption system based on dynamic adjustment updating mechanism

Abstract

The embodiment of the invention relates to the technical field of communication, and discloses a low-power-consumption system based on a dynamic adjustment updating mechanism, the system is integrated on a physical layer chip, and the system comprises a signal performance monitoring module which is used for outputting a monitoring result signal representing a link health state; a period timer module; the EEE protocol control module is used for receiving the monitoring result signal and the timing pulse signal, and selecting an execution period timer control mode or a performance control mode based on the monitoring result signal so as to generate an update trigger instruction; the updating module is used for driving the sending end to send an updating fragment to the link; wherein when the monitoring result signal indicates that the link health state is deteriorated, the EEE protocol control module enters a performance control mode; and the triggering module is used for triggering the next updated fragment after the current updated fragment is finished, so that low-power-consumption operation is maintained while the signal transmission quality is guaranteed.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of communication, and particularly relates to a low-power-consumption system based on a dynamic adjustment updating mechanism. BACKGROUND

[0002] With the continuous evolution of Ethernet technology in the direction of low power consumption and high integration, the energy-efficient Ethernet (EEE) standard defined by IEEE 802.3 Clause 78 protocol has become the core basis for physical layer chip to realize energy saving. The protocol reduces power consumption by turning off part of the circuit when the network traffic is low through the low-power idle mode (LPI), and introduces an updating mechanism, that is, it is stipulated that an update fragment needs to be periodically sent in the LPI mode to maintain link synchronization and avoid the additional time and power consumption caused by reestablishing the connection after the link is disconnected. The power consumption of the mainstream physical layer chip in the LPI mode can be reduced to less than 20% of the normal mode, and the updating period is usually fixed at the default value (such as 20ms), which has significant energy-saving significance in large-scale deployment scenarios such as data centers.

[0003] However, the existing physical layer chip has obvious limitations in the application of EEE low-power-consumption design and updating mechanism. First, the existing updating mechanism is relatively rigid. After the chip enters the LPI mode, it only relies on the fixed-period updating fragment to maintain the link. Since part of the signal processing unit is turned off to reduce power consumption, once the link environment appears to have increased noise interference, the signal-to-noise ratio (SNR) of the receiving end will quickly decrease, resulting in an increase in the bit error rate.

[0004] Secondly, the existing chip fails to establish a correlation between the updating mechanism and the convergence process of the signal performance. When it is detected that the convergence time in the previous update fragment is abnormally prolonged (for example, from the normal 500ns to 1.5us) or the clock data recovery (CDR) module has excessive lock jitter, the existing system still starts the next update according to the fixed period. This non-closed-loop control method can further worsen the link synchronization state and even cause the link to be disconnected unexpectedly. In addition, the existing chip has a single evaluation dimension for signal quality, and only relies on the SNR index, lacks comprehensive consideration of key synchronization parameters such as convergence time and CDR lock state, and is difficult to accurately judge the real health status of the link. It is impossible to realize the closed-loop control of "signal abnormality detection-fast start updating-performance convergence" in the chip, and it is difficult to achieve a dynamic balance between low power consumption and high reliability. SUMMARY

[0005] An object of the present application is to provide a low-power-consumption system based on a dynamic adjustment updating mechanism, at least to solve the technical problem that the signal transmission reliability and low power consumption are difficult to be considered in the existing physical layer chip in the low-power idle mode (LPI) due to the existing fixed updating mechanism.

[0006] To achieve the above object, the application provides a low-power system based on a dynamic adjustment and update mechanism, which is integrated in a physical layer chip and comprises:

[0007] a signal performance monitoring module, configured to collect a plurality of performance parameters of a receiving link in a low-power sleep mode, compare the collection results with preset threshold values and / or historical reference values, and output a monitoring result signal representing a link health state;

[0008] a periodic timer module, configured to generate a timing pulse signal with a default period;

[0009] an EEE protocol control module, configured to receive the monitoring result signal and the timing pulse signal, and select a periodic timer control mode or a performance control mode based on the monitoring result signal to generate an update trigger instruction;

[0010] an update module, configured to drive a transmitting end of the physical layer chip to transmit an update segment to the link in response to the update trigger instruction;

[0011] When the monitoring result signal indicates that the link health state deteriorates, the EEE protocol control module enters the performance control mode, and the performance control mode is used to trigger the next update segment immediately after the current update segment ends.

[0012] Compared with the related art, in the scheme provided by the application, first, through the linkage mechanism of the signal performance monitoring module and the EEE protocol control module integrated in the chip, the system can automatically switch from the periodic timer control mode to the performance control mode when the signal-to-noise ratio decreases, the convergence time is prolonged, or the CDR jitter is too large. This mechanism breaks the shackles of the traditional fixed period, can trigger the next update segment immediately after the current update segment ends, uses high-frequency training sequences to quickly promote link performance convergence, thereby maintains low-power operation on the premise of ensuring signal transmission quality, and effectively avoids data retransmission or link disconnection caused by link quality degradation.

[0013] Secondly, unlike the prior art which only relies on a single signal-to-noise ratio (SNR) index, the application combines multiple key parameters such as SNR, convergence time of the update segment, and CDR lock state (such as lock jitter). In particular, the convergence time is monitored, the historical average value is stored in the hardware register and compared with the current value, which can more sensitively capture early signs of link performance deterioration, thereby more accurately triggering the dynamic adjustment mechanism to ensure that the link is always in the best synchronization state.

[0014] Finally, the system integrates an exception handling module, which can force the LPI mode to exit in time to guarantee the service continuity when the link quality cannot be restored through the fast update. This hierarchical processing strategy not only maximizes the energy saving mode, but also guarantees the reliability of communication through the closed-loop logic, perfectly solving the contradiction between energy saving and performance of the physical layer device. BRIEF DESCRIPTION OF DRAWINGS

[0015] One or more embodiments are illustrated by way of example in the figures that are part of this disclosure and which are illustrative, and not restrictive, of the embodiments, wherein elements having the same reference number designates like elements throughout the various figures, and the figures are not necessarily to scale.

[0016] Figure 1 An architecture diagram of a low-power system based on a dynamic adjustment update mechanism according to an example embodiment of the present disclosure;

[0017] Figure 2 An architecture diagram of another low-power system based on a dynamic adjustment update mechanism according to an example embodiment of the present disclosure. DETAILED DESCRIPTION

[0018] In order to make the objects, technical solutions and advantages of the embodiments of the present application clearer, the technical solutions in the embodiments of the present application will be described clearly and completely below with reference to the drawings in the embodiments of the present application. Obviously, the described embodiments are some but not all of the embodiments of the present application. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without creative work fall within the scope of protection of the present application.

[0019] Figure 1 An architecture diagram of a low-power system based on a dynamic adjustment update mechanism according to an example embodiment of the present disclosure, the system is integrated in a physical layer chip, and the system comprises:

[0020] A signal performance monitoring module 1, configured to collect a plurality of performance parameters of a receiving link in a low-power sleep mode, and compare the collected results with preset threshold values and / or historical reference values, and output a monitoring result signal representing a link health state;

[0021] A periodic timer module 2, configured to generate a timing pulse signal with a default period;

[0022] An EEE protocol control module 3, configured to receive the monitoring result signal and the timing pulse signal, and select to execute a periodic timer control mode or a performance control mode based on the monitoring result signal, to generate an update trigger instruction;

[0023] Update module 4 is used to respond to the update trigger command and drive the transmitter of the physical layer chip to send an update segment to the link;

[0024] When the monitoring result signal indicates that the link health status has deteriorated, the EEE protocol control module enters the performance control mode; the performance control mode is used to trigger the next update segment after the current update segment ends.

[0025] Specifically, the system is integrated within the Ethernet physical layer chip, designed to achieve intelligent link maintenance in Low Power Sleep Mode (LPI). For example... Figure 1 As shown, the system mainly consists of a closed-loop control architecture comprised of a signal performance monitoring module 1, a periodic timer module 2, an EEE protocol control module 3, and an update module 4. The signal performance monitoring module 1, acting as a sensing unit, is configured to receive update segments when the chip is in a low-power state. It is responsible for real-time acquisition of various key performance parameters in the receiving link and comparing these parameters with preset thresholds or stored historical reference values ​​within the chip. Once an abnormality is detected, it outputs a monitoring result signal indicating a deterioration in the link's health status. The periodic timer module 2 is responsible for maintaining the system's time base. According to standards such as IEEE 802.3, it continuously generates timing pulse signals with a default period to ensure the maintenance of a normal heartbeat mechanism when the link is stable.

[0026] The core decision-making of the system is executed by the EEE protocol control module 3, which implements all the logic of the IEEE 802.3 Clause 78 protocol using pure hardware circuits (such as state machines). This module receives status feedback from the signal performance monitoring module 1 and timing signals from the periodic timer module 2. Based on the content of the monitoring result signals, the EEE protocol control module 3 dynamically selects to execute either the "periodic timer control mode" or the "performance control mode" and generates an update trigger command accordingly. The update module 4 is connected to the EEE protocol control module and is used to respond to the trigger command, driving the transmitter of the physical layer chip to send update segments to the link. When the signal performance monitoring module 1 indicates that the link health status has deteriorated, the EEE protocol control module 3 will enter the performance control mode. In this mode, the system will break the conventional timing constraints and no longer wait for the periodic timer countdown to end. Instead, it will quickly trigger the transmission process of the next update segment after the currently being transmitted update segment ends, thereby forming a continuous training sequence to cope with harsh link environments.

[0027] In the embodiment, by constructing a "monitor-decision-execute" closed-loop control loop at the bottom of the chip, the system overcomes the rigid defect of the traditional physical layer chip that can only rely on fixed period to send update fragments. When detecting that the link signal-to-noise ratio decreases or the convergence performance becomes poor, the system can quickly increase the sending density of the update fragment by using the "performance control mode", and help the receiving end to quickly relock the clock and converge the filter parameters through continuous training sequences. This mechanism can actively repair the signal quality of the link without waking up the entire chip (i.e. without exiting the low-power mode), effectively avoiding the increase of bit error rate, data retransmission or even link disconnection caused by environmental noise. This not only greatly improves the communication reliability of the Ethernet device in low-power mode, but also avoids the additional power consumption caused by frequent switching to normal working mode, achieving the best balance between energy saving and performance.

[0028] In one embodiment, the EEE protocol control module is internally integrated with an update mechanism subunit, which is configured to:

[0029] In the periodic timer control mode, the update trigger instruction is generated in response to the timing pulse signal of the periodic timer module;

[0030] In the performance control mode, in response to the link deterioration state indicated by the monitoring result signal, the waiting time of the periodic timer module is ignored, and after the current update fragment is sent and the fast trigger signal is received, the update trigger instruction for starting the next update fragment is generated.

[0031] Specifically, the EEE protocol control module is internally integrated with a core update mechanism subunit. As the core of the execution logic, the update mechanism subunit is configured to run two different control strategies to adapt to different link environments. First is the periodic timer control mode, which is the default working way of the system in the healthy state of the link. In this mode, the update mechanism subunit strictly follows the timing constraints of the IEEE802.3 standard protocol, and only generates the update trigger instruction when receiving the timing pulse signal from the periodic timer module, thereby maintaining the standard and low-frequency update fragment sending, and ensuring the maximum energy saving effect.

[0032] When the system detects an anomaly, the update mechanism subunit switches to performance control mode. Once the monitoring result signal indicates link deterioration (such as a sudden drop in signal-to-noise ratio or excessive CDR jitter), this subunit immediately takes over control and executes preemptive logic. Specifically, it masks or ignores the waiting time originally set by the periodic timer module, no longer passively waiting for the next timing pulse. At this time, the subunit closely monitors the current transmission status. Once it detects that the current update segment has been transmitted and receives a rapid trigger signal indicating the need for urgent maintenance, it will quickly generate an update trigger instruction to start the next update segment without any idle waiting time or within a very short period. This logic enables the physical layer chip to continuously and back-to-back transmit update segments, forming a high-density training sequence stream.

[0033] In this embodiment, by introducing an update mechanism subunit with dual-mode switching functionality within the EEE protocol control module, dynamic intervention in the timing of update transmission is successfully achieved. In particular, its logic design in performance control mode breaks the rigid limitation of traditional low-power protocols that require waiting for a fixed quiet period. By immediately generating an update trigger command to initiate the next update segment, the equalizer and clock recovery unit at the receiving end can quickly complete parameter convergence and locking under harsh signal-to-noise ratio conditions. This allows for the fastest response speed to repair the unstable state of the link, preventing further link deterioration due to prolonged waiting for the next update cycle, and significantly improving communication robustness in low-power mode.

[0034] In one embodiment, the signal performance monitoring module includes at least one of the following hardware monitoring units:

[0035] The signal-to-noise ratio (SNR) detection unit is used to acquire signal power and noise power in real time and calculate the SNR.

[0036] A convergence time monitoring unit is used to connect to the performance convergence unit of the physical layer chip and record the time difference from the start of sending the update fragment to the completion of parameter convergence by the performance convergence unit.

[0037] The clock data recovery monitoring unit is used to extract lock jitter data from the clock data recovery module of the physical layer chip in real time.

[0038] Specifically, the signal performance monitoring module is designed as a core sensing component in the physical layer chip's receive link. It integrates various dedicated hardware monitoring units to achieve multi-dimensional, in-depth perception of the link's physical characteristics. This module may include one or more combinations of a signal-to-noise ratio (SNR) detection unit, a convergence time monitoring unit, and a clock data recovery monitoring unit. The SNR detection unit incorporates a high-precision power detection circuit configured to acquire the signal power and noise power of the received signal in real time and calculate the real-time SNR. This unit is designed to capture minute signal quality fluctuations during the duration of update segments, ensuring sensitivity to changes in the channel environment in low-power mode. The convergence time monitoring unit incorporates a timing circuit. This timing circuit establishes a direct hardware connection with the performance convergence unit within the physical layer chip to accurately measure the time overhead required for link synchronization recovery. Furthermore, the clock data recovery monitoring unit incorporates a state extraction circuit directly connected to the physical layer chip's clock data recovery (CDR) module to extract key locking information, including lock jitter, in real time to monitor the link's temporal stability.

[0039] In this embodiment, by introducing convergence time monitoring and CDR lock-in status monitoring, the link condition can be evaluated from a deeper physical dimension, such as time-domain convergence speed and clock lock-in stability. For example, it monitors whether the convergence time has abnormally increased relative to the historical average (e.g., deteriorating from 500ns to 1.5μs), or whether the CDR lock-in jitter exceeds the safety threshold. This multi-parameter fusion monitoring mechanism significantly improves the evaluation accuracy, enabling the system to keenly detect signs of link instability before the actual increase in bit error rate, thereby accurately triggering the dynamic adjustment of the update mechanism and completely solving the technical problem of untimely response or misjudgment caused by traditional single-indicator evaluation.

[0040] In one embodiment, the convergence time monitoring unit records the time difference in the following way:

[0041] Use the moment when the update fragment begins to be sent as the timing start point;

[0042] The moment when the performance convergence unit completes the parameter adjustment is taken as the timing termination point;

[0043] The time difference between the timing start point and the timing end point is calculated and transmitted to the threshold comparison unit as the update convergence time.

[0044] Specifically, the timing circuit inside the convergence time monitoring unit is configured to execute a precise time difference measurement logic to quantify the recovery speed of the link performance. First, the timing circuit monitors the sending status of the update module in real time. When it detects that the physical layer chip has started sending update segments to the link, the timing circuit marks this as the timing start point. Subsequently, the timing circuit continuously monitors the status feedback from the performance convergence unit inside the physical layer chip (the module responsible for tasks such as equalizer parameter adjustment and clock recovery locking). When it receives a signal from the performance convergence unit indicating that parameter adjustment is complete, signifying that the link has reached a stable synchronization state, the timing circuit marks this moment as the timing end point. Finally, the timing circuit automatically calculates the time difference between the timing start point and the timing end point through hardware logic and defines this time difference as the "update-convergence time." This data is then directly transmitted to the backend threshold comparison unit for subsequent health assessment.

[0045] In this embodiment, by clearly defining the start point of update transmission and the end point of parameter convergence, the time-consuming changes in the link performance convergence process can be accurately captured. This time difference data directly reflects the degree of obstruction to signal recovery by the current link environment—the longer the convergence time, the greater the link noise interference or the worse the signal integrity. Therefore, by monitoring this time indicator in real time, the system can detect the trend of link deterioration earlier than simply monitoring the bit error rate (e.g., detecting that the convergence time has increased from the normal 500ns to 1.5μs), thereby triggering the "performance control mode" in time before data transmission errors occur, achieving highly proactive preventive maintenance.

[0046] In one embodiment, the signal performance monitoring module further includes a threshold comparison unit:

[0047] The threshold comparison unit is used to receive the signal-to-noise ratio, the time difference, or the lock jitter data, and compare the signal-to-noise ratio, the time difference, or the lock jitter data with the corresponding preset threshold and / or historical reference value;

[0048] When any data exceeds the corresponding preset threshold and / or historical reference value, the threshold comparison unit generates the monitoring result signal indicating that the link health status has deteriorated.

[0049] Specifically, the signal performance monitoring module further integrates a threshold comparison unit. This unit, as the core logic component for determining the link health status, is responsible for intelligent analysis of the collected raw data. The threshold comparison unit establishes data paths with the aforementioned signal-to-noise ratio (SNR) detection unit, convergence time monitoring unit, and clock data recovery monitoring unit, respectively, to receive key performance data such as SNR, convergence time difference, and CDR lock jitter in real time. This unit has a built-in comparison circuit to compare these real-time data with preset thresholds or historical reference values ​​in the chip's internal configuration register. The judgment logic covers various abnormal scenarios: for example, when the real-time SNR is detected to be lower than the configured minimum threshold, it means that the signal quality is insufficient to maintain low bit error rate transmission; or when the current "update-convergence time" exceeds a preset multiple of the historical average (e.g., the default setting is 1.5 times), it is determined to be a deterioration in convergence performance; or when the CDR lock jitter data exceeds the allowed jitter threshold, it is determined to be a lock anomaly. Once any of the above conditions are met, the threshold comparison unit will immediately generate a monitoring result signal indicating a deterioration in the link health status and transmit the signal to the update mechanism subunit in the EEE protocol control module to trigger subsequent mode switching.

[0050] In this embodiment, by combining multi-dimensional real-time data with preset thresholds and dynamic historical reference values ​​(such as historical average convergence time), this unit can not only identify sudden severe faults (such as a sharp drop in SNR), but also keenly perceive the gradual degradation of link performance (such as slower convergence). This hardware-based parallel comparison mechanism greatly reduces the judgment latency, ensuring that the system can complete the transition from "data acquisition" to "state determination" within milliseconds or even microseconds. This provides a timely and reliable decision-making basis for the subsequent immediate triggering of the update mechanism, effectively preventing the risk of link disconnection due to judgment lag.

[0051] In one embodiment, the convergence time monitoring unit integrates a hardware register:

[0052] The hardware register is used to store the average of the update convergence times collected most recently (N times).

[0053] The threshold comparison unit reads the average value as a historical reference value. When the current update convergence time collected in real time exceeds a preset multiple of the average value, it generates the monitoring result signal indicating that the health status of the link has deteriorated.

[0054] Specifically, to more accurately capture the dynamic trends of link performance changes, the convergence time monitoring unit integrates a dedicated hardware register. This register is configured to implement an adaptive benchmark maintenance mechanism, which not only records single data points but also stores the average of the most recent N (N can be configured to be 3) "update-convergence times". This design allows the system to establish a dynamic benchmark that reflects the current normal performance of the link. In actual operation, the threshold comparison unit reads the average value in this hardware register in real time as a historical reference value. The judgment logic no longer relies on a single absolute time threshold but adopts a relative comparison method: the system allows setting a multiple threshold (default is 1.5 times) through an internal configuration register. When the current update convergence time collected in real time exceeds this preset multiple of the historical average (for example, a sudden change from the historical average of 500ns to more than 1.5μs currently detected), the system determines that a "convergence time increase" event has occurred and generates a monitoring result signal indicating a deterioration in the health status of the link.

[0055] In this embodiment, a dynamic baseline is constructed by storing the average of the most recent N (e.g., 3) values ​​in hardware registers, enabling the system to determine the normal state of the current link. This method, which compares the current value with the historical average multiple (e.g., 1.5 times), can sensitively eliminate environmental baseline differences and accurately identify abnormal performance convergence changes caused by sudden noise or interference. This ensures that the dynamic triggering of the update mechanism is only for real link deterioration events, greatly improving the robustness and accuracy of low-power systems in complex industrial or data center environments.

[0056] In one embodiment, the clock data recovery monitoring unit is further configured to transmit the real-time extracted lock jitter data to the threshold comparison unit;

[0057] The threshold comparison unit is used to compare the received lock jitter data with a preset jitter threshold. When the lock jitter data exceeds the jitter threshold, the clock data recovery module is determined to be locked abnormally, and the monitoring result signal indicating link deterioration is output.

[0058] Specifically, to ensure the stability of the link in the time domain synchronization, the system is specifically configured with data interaction logic between the clock data recovery monitoring unit and the threshold comparison unit. The state extraction circuit integrated within the clock data recovery monitoring unit establishes a direct hardware data path with the clock data recovery (CDR) module of the physical layer chip. This unit is configured to extract the lock jitter data from the CDR module in real time, which reflects the accuracy of the phase alignment between the receiving clock and the input signal. The extracted lock jitter data is transmitted in real time to the backend threshold comparison unit. Upon receiving this data, the threshold comparison unit uses its internal comparison circuit to compare it with a preset jitter threshold (e.g., 100ps depending on the actual application scenario). The judgment logic is set as follows: once the real-time monitored lock jitter data exceeds the preset jitter threshold, the CDR module is determined to be in a "locking abnormality" state. At this time, the threshold comparison unit will immediately output a monitoring result signal indicating link deterioration. This signal serves as a key trigger source, notifying the EEE protocol control module to quickly intervene and initiate performance control mode to repair the synchronization deviation.

[0059] In this embodiment, by directly monitoring the lock jitter data of the CDR and setting a threshold judgment mechanism, it is possible to penetrate deep into the physical layer and detect the synchronization risk of the link in advance when the clock has already started to drift or the jitter is too large (e.g., exceeding 100ps) before the data has produced bit errors. This monitoring capability allows the chip to perform phase correction by quickly triggering the update mechanism before the link completely loses synchronization, thereby effectively preventing sudden link interruptions caused by clock lockout and significantly enhancing the system's anti-interference capability and connection stability in low-power mode.

[0060] In one embodiment, the signal performance monitoring module further includes a trend analysis unit:

[0061] The trend analysis unit is used to calculate the signal-to-noise ratio and / or the first derivative of the locked jitter data in real time to obtain the rate of change.

[0062] The trend analysis unit is used to compare the rate of change with a preset slope threshold. When the rate of change exceeds the slope threshold, even if the signal-to-noise ratio or the locked jitter data is still within the allowable range, the trend analysis unit will still directly generate the monitoring result signal indicating the deterioration of the link health status, triggering the EEE protocol control module to enter the performance control mode.

[0063] Specifically, existing technologies typically focus only on the absolute values ​​of performance parameters (such as whether the SNR is below 26dB). This mechanism is inherently lagging, often triggering repair only when the link quality has deteriorated to a critical point. In contrast, the trend analysis unit in this embodiment incorporates a slope calculation circuit. This circuit is configured to perform real-time first-order derivative calculations on the collected key performance parameters (especially SNR or CDR lock jitter) to obtain the rate of change of the parameters over time (i.e., the slope). The system has a dedicated "slope threshold" to define the speed boundary of signal deterioration. The system no longer relies solely on a single static threshold for judgment but monitors in parallel. Assuming the system's set safe static SNR threshold is 26dB, and the current measured SNR is 30dB (within the absolutely safe range), if a sudden strong external interference causes the SNR to drop by 4dB in a very short time (e.g., 1ms), the rate of change calculated by the slope calculation circuit will significantly exceed the preset slope threshold. Although the absolute value of 26dB is still within the safe range, the trend analysis unit will determine the risk of link interruption based on the extremely steep downward slope. Therefore, the system will ignore the currently acceptable absolute values ​​and directly generate a monitoring result signal indicating link deterioration, thus triggering the EEE protocol control module to enter the performance control mode in advance.

[0064] In this embodiment, when faced with sudden pulse interference or drastic changes in the channel environment caused by rapid movement, the system does not need to wait for the link to be completely disconnected before it begins to react. Instead, it can keenly detect dangerous trends in the early stages of signal quality degradation. This triggering mechanism allows the receiver to quickly adjust the equalization parameters to resist interference using this millisecond-level time window, greatly reducing the probability of unexpected link loss in low-power mode.

[0065] Furthermore, in one embodiment, the system further includes:

[0066] The power consumption mode management module is used to output a first control signal to shut down the data processing circuits except for the signal performance monitoring module in the silent state of low power sleep mode; and to output a second control signal to turn on the transmitter and receiver front-end circuits of the physical layer chip during the transmission of update segments, while keeping the non-critical data processing circuits in the off state.

[0067] Specifically, the power mode management module, as the central hub for physical layer chip energy efficiency control, aims to achieve fine-grained power gating of various circuit modules within the chip. This module is configured to execute adaptive circuit-on strategies based on different sub-states of the EEE protocol. When the physical layer chip is in a quiet state of low-power sleep mode (LPI), the system enters a deep power-saving phase. At this time, the power mode management module outputs a first control signal, which acts on the chip's power distribution network, forcibly shutting down most high-power data processing circuits (such as the DSP unit responsible for complex packet parsing). However, to maintain the core monitoring function of this invention, this control signal deliberately preserves the power supply to the signal performance monitoring module and its detection logic, ensuring it is in a "standby" state and can continuously sense silent noise or sudden interference in the link. When the system enters the update segment transmission period (whether periodically triggered or triggered by performance control mode), the power mode management module quickly switches strategies and outputs a second control signal. The logic of this signal is designed to wake up only the "necessary" hardware resources: it immediately turns on the physical layer chip's transmitter to send update signals and simultaneously turns on the receiver front-end circuit to receive the response signal from the other end and provide parameters for the monitoring module to collect. At the same time, the module will strictly lock other non-critical data processing circuits that are not related to link maintenance, keeping them in a closed state, thereby keeping instantaneous power consumption at a minimum while completing the link training task.

[0068] In this embodiment, by distinguishing between the silent state and the update state and defining first and second control signals, granular control of the circuit module is achieved. In particular, the strategy of enabling the receiving front-end while keeping non-critical logic disabled ensures that the physical channels required for the signal performance monitoring module to acquire critical data such as SNR and convergence time remain open, while avoiding the power consumption penalty of waking up the massive data processing logic. This design significantly reduces the average power consumption during the update process, making it possible to trigger high-frequency performance control modes, and greatly improving the reliability of link maintenance without sacrificing energy-saving advantages.

[0069] In one embodiment, the system further includes:

[0070] An exception handling module, which has a counter for recording the number of consecutive transmissions of update segments in the performance control mode;

[0071] When the value of the counter reaches a preset threshold and the monitoring result signal still indicates link deterioration, the anomaly handling module sends an exit signal to the EEE protocol control module, triggering the system to exit the low-power sleep mode and return to the normal working mode.

[0072] Specifically, to prevent the system from getting stuck in an infinite loop of repair attempts when the link is severely damaged, an exception handling module has been added. This module maintains real-time communication with the EEE protocol control module and integrates a dedicated counter. This counter is specifically designed to track update segment transmission behavior in performance control mode. Whenever the EEE protocol control module triggers a rapid update segment transmission due to detected link deterioration, the counter automatically increments. The exception handling module continuously monitors the counter value and the real-time monitoring results from the signal performance monitoring module. The judgment logic is set as follows: when the counter value accumulates to a chip-preset threshold (e.g., 3 consecutive times), and simultaneously, the monitoring results still indicate that the link is in a "deteriorating health state," the system will determine that the current low-power repair methods are insufficient to resolve the link problem. At this time, the exception handling module will immediately send a forced exit signal to the EEE protocol control module, instructing the system to terminate all operations in LPI mode, triggering the physical layer chip to exit low-power sleep mode and fully wake up, restoring to full-function normal operation mode to re-establish a stable link connection.

[0073] In this embodiment, a counter is used to set an upper limit for attempts (e.g., 3 times), enabling the chip to first attempt a low-cost update and repair, and then decisively switch back to the high-reliability normal mode if the attempt fails. This tiered strategy maximizes the possibility of energy saving while providing a solid safety net for business continuity, ensuring that the chip can make optimal survival decisions in any harsh environment.

[0074] In one embodiment, the EEE protocol control module further includes a low-power sleep mode control logic unit:

[0075] The low-power sleep mode control logic unit is used to manage the switching of the physical layer chip between normal mode, preparing to enter low-power sleep mode, low-power sleep mode and wake-up state;

[0076] The low-power sleep mode control logic unit is also used to perform a wake-up operation only in response to an external wake-up signal in low-power sleep mode, without responding to an internal update trigger instruction.

[0077] Specifically, the EEE protocol control module further integrates a Low Power Sleep Mode (LPI) control logic unit, which uses a built-in finite state machine (FSM) to tightly manage the physical layer chip's operating state. This state machine is configured to precisely control the timing of the chip's transitions between four core states: "normal operating mode," "ready to enter LPI mode," "LPI sleep mode," and "wake-up state." Particularly noteworthy is its signal response logic design in "LPI sleep mode": in this state, the state machine is in a deeply gated monitoring state, programmed to be highly selective. The state machine is only sensitive to "external wake-up signals" from the Media Access Control (MAC) layer or the link peer; upon receiving such a signal, it immediately executes a complete wake-up operation to resume data service transmission. However, for "update trigger instructions" (whether periodic or performance-triggered) generated internally by the EEE protocol control module, the state machine treats them as in-mode maintenance actions rather than wake-up requests. This means that when the system drives the transmitter to send update segments in LPI mode, the state machine still determines that the system is in sleep logic and will not trigger the entire chip to switch back to the high-power normal mode.

[0078] In this embodiment, through the logical isolation of the state machine, it is clarified that the update is only a maintenance behavior in sleep mode, rather than a wake-up signal. This ensures that when the chip performs high-frequency dynamic updates (especially when continuously sending updates to repair signal quality in performance control mode), its main state machine remains firmly anchored in low-power sleep mode, only activating the necessary transceiver circuits. This ensures uninterrupted link synchronization while keeping overall power consumption at a minimum, avoiding power consumption penalties caused by false wake-ups.

[0079] Furthermore, in one embodiment, in order to enhance the stability of the system under critical conditions, the threshold comparison unit in the signal performance monitoring module is also used to execute dual threshold decision logic based on hysteresis intervals.

[0080] Specifically, the configuration register inside this unit no longer stores only a single judgment value, but instead presets a set of hysteresis threshold pairs with safety margins for each key performance parameter (such as signal-to-noise ratio, convergence time, or jitter value): including a "first threshold" as the degradation trigger boundary and a "second threshold" as the recovery confirmation boundary, forming a differentiated hysteresis range between the two. Taking the signal-to-noise ratio (SNR) of the received signal as an example, the system can set the first threshold to 26dB and the second threshold to 28dB in the hardware register, thereby constructing a numerical buffer between 26dB and 28dB that can accommodate small signal fluctuations.

[0081] Based on the above hardware configuration, the EEE protocol control module and the threshold comparison unit collaboratively execute the following closed-loop control process: When the physical layer chip is running in periodic timer control mode, the threshold comparison unit continuously compares the real-time collected performance parameters with the first threshold. Assuming the current signal-to-noise ratio (SNR) gradually decreases from 28dB due to external interference, even if it drops to 26dB (within the hysteresis range), the comparison circuit still determines that the link is within a tolerable range and does not trigger a mode switching signal; only when the SNR further deteriorates and falls below the first threshold of 26dB does the system determine that a substantial link failure has occurred and immediately generate a trigger signal to drive the EEE protocol control module to switch to performance control mode. Conversely, when the system is already in performance control mode performing high-frequency refresh repair, the threshold comparison unit continuously evaluates the repair effect and compares it with the second threshold. Assuming the signal-to-noise ratio (SNR) begins to recover, even if it rises to 26dB (i.e., higher than the trigger point but not yet the recovery point), the decision logic still considers the link state to be unstable and refuses to output a recovery signal. The system continues to maintain high-density update transmissions to consolidate the link. Only when the SNR continues to rise and stably exceeds the second threshold of 28dB will the threshold comparison unit confirm that the interference has been completely eliminated and the link quality has sufficient safety margin. Only then will a mode switching instruction be generated, allowing the state machine to safely switch back to the periodic timer control mode.

[0082] In this embodiment, by introducing a hysteresis comparison mechanism at the hardware level, the "ping-pong effect" that easily occurs in control systems under critical disturbance environments is fundamentally solved. In practical applications, if only a single threshold is used, random small fluctuations in link parameters around the threshold will cause the system to oscillate repeatedly between "low-power mode" and "high-performance mode," resulting in clock jitter and wasted power. By constructing a numerical hysteresis interval, sufficient controllability and determinism in mode switching are ensured; that is, the system only adjusts the control strategy when there is a definite and significant change in the link quality. This design avoids ineffective mode switching and significantly improves the operational stability and logic robustness of the physical layer chip in complex electromagnetic environments.

[0083] The scope of this application is defined by the appended claims rather than the foregoing description, and is therefore intended to encompass all variations falling within the meaning and scope of equivalents of the claims. No reference numerals in the claims should be construed as limiting the scope of the claims. Furthermore, it is clear that the word "comprising" does not exclude other units or steps, and the singular does not exclude the plural. Multiple units or devices recited in a device claim may also be implemented by a single unit or device in software or hardware. Terms such as "first," "second," etc., are used only for distinguishing descriptions and do not indicate any particular order, nor should they be construed as indicating or implying relative importance.

[0084] The above description is merely a specific embodiment of this application, but the scope of protection of this application is not limited thereto. Any variations or substitutions that can be easily made by those skilled in the art within the scope of the technology disclosed in this application should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims, and the above embodiments should be regarded as exemplary and non-limiting.

Claims

1. A low power system based on dynamic adjustment update mechanism, characterized in that, The system is integrated into a physical layer chip, and comprises: a signal performance monitoring module, configured to collect a plurality of performance parameters of a receiving link in a low-power sleep mode, compare the collected results with preset threshold values and / or historical reference values, and output a monitoring result signal representing a link health state; a periodic timer module, configured to generate a timing pulse signal with a default period; an EEE protocol control module, configured to receive the monitoring result signal and the timing pulse signal, and select a periodic timer control mode or a performance control mode based on the monitoring result signal to generate an update trigger instruction; an update module, configured to drive a transmitting end of the physical layer chip to transmit an update segment to the link in response to the update trigger instruction; wherein, when the monitoring result signal indicates that the link health state deteriorates, the EEE protocol control module enters the performance control mode; and the performance control mode is used to trigger a next update segment after a current update segment ends.

2. The low power consumption system based on dynamic adjustment update mechanism according to claim 1, characterized in that, The EEE protocol control module is internally integrated with an update mechanism subunit, which is configured to: generate the update trigger instruction in response to the timing pulse signal of the periodic timer module in the periodic timer control mode; and ignore the waiting time of the periodic timer module, and generate the update trigger instruction for starting the next update segment after the current update segment is transmitted and a fast trigger signal is received in the performance control mode in response to the link deterioration state indicated by the monitoring result signal.

3. The low power consumption system based on dynamic adjustment update mechanism according to claim 1, wherein, The signal performance monitoring module comprises at least one of the following hardware monitoring units: a signal-to-noise ratio detection unit, configured to collect signal power and noise power in real time and calculate a signal-to-noise ratio; a convergence time monitoring unit, configured to be connected to a performance convergence unit of the physical layer chip, and record a time difference from the start of update segment transmission to the completion of parameter convergence of the performance convergence unit; a clock data recovery monitoring unit, configured to extract lock jitter data in real time from a clock data recovery module of the physical layer chip.

4. The low power consumption system based on dynamic adjustment update mechanism according to claim 3, characterized in that, The signal performance monitoring module further comprises a threshold comparison unit: the threshold comparison unit is configured to receive the signal-to-noise ratio, the time difference or the lock jitter data, and compare the signal-to-noise ratio, the time difference or the lock jitter data with corresponding preset threshold values and / or historical reference values; when any data exceeds the corresponding preset threshold value and / or historical reference value, the threshold comparison unit generates the monitoring result signal indicating that the link health state deteriorates.

5. The low power consumption system based on dynamic adjustment update mechanism according to claim 4, characterized in that, The convergence time monitoring unit records the time difference in the following manner: taking a time point when the update segment starts to be transmitted as a starting point of timing; taking a time point when the performance convergence unit feeds back parameter adjustment completion as a termination point of timing; calculating a time difference between the starting point of timing and the termination point of timing as an update convergence time, and transmitting the update convergence time to the threshold comparison unit.

6. The low power consumption system based on dynamic adjustment update mechanism according to claim 5, characterized in that, The convergence time monitoring unit further comprises a hardware register: the hardware register is configured to store an average value of update convergence times collected in the last N times; and the threshold comparison unit is configured to compare the average value of the update convergence times with a preset threshold value and / or a historical reference value. The threshold comparison unit reads the average value as a historical reference value, and generates the monitoring result signal indicating link health state deterioration when a current update convergence time collected in real time exceeds a preset multiple of the average value.

7. The low power consumption system based on dynamic adjustment update mechanism according to claim 5, characterized in that, The clock data recovery monitoring unit is further configured to transmit the lock jitter data extracted in real time to the threshold comparison unit. The threshold comparison unit is further configured to compare the received lock jitter data with a preset jitter threshold, and determine that the clock data recovery module is locked abnormally when the lock jitter data exceeds the jitter threshold, and output the monitoring result signal indicating link deterioration.

8. The low power consumption system based on dynamic adjustment update mechanism according to claim 3, characterized in that, The signal performance monitoring module further comprises a trend analysis unit. The trend analysis unit is configured to calculate a first derivative of the signal-to-noise ratio and / or the lock jitter data in real time to obtain a change rate. The trend analysis unit is further configured to compare the change rate with a preset slope threshold, and generate the monitoring result signal indicating link health state deterioration when the change rate exceeds the slope threshold, triggering the EEE protocol control module to enter the performance control mode.

9. The low power consumption system based on dynamic adjustment update mechanism according to claim 1, wherein, The system further comprises: An exception handling module having a counter configured to record a number of consecutive update segments transmitted in the performance control mode; When the value of the counter reaches a preset threshold and the monitoring result signal still indicates link deterioration, the exception handling module is configured to send an exit signal to the EEE protocol control module, triggering the system to exit the low-power sleep mode and restore to a normal working mode.

10. The low power consumption system based on dynamic adjustment update mechanism according to any one of claims 1 to 9, characterized in that, The EEE protocol control module further comprises a low-power sleep mode control logic unit: The low-power sleep mode control logic unit is configured to manage switching of the physical layer chip between a normal mode, a low-power sleep mode, and a wake-up state; The low-power sleep mode control logic unit is further configured to perform a wake-up operation only in response to an external wake-up signal in the low-power sleep mode, and not in response to an internal update trigger instruction.

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