Energy storage system, address calibration method and electronic equipment

Abstract

The invention discloses an energy storage system, an address calibration method and electronic equipment, and belongs to the technical field of energy storage systems, and the energy storage system comprises a first module which is configured to output an address calibration signal through a communication bus during address calibration; the plurality of second modules are connected with the first module through the communication bus, and the plurality of second modules are configured to receive the address calibration signal through the communication bus so as to feed back address calibration data; the second module is provided with a first connecting end and a second connecting end, and the first connecting end is sequentially connected with the second connecting ends of other second modules through signal lines. According to the system, the first connecting ends and the second connecting ends of the adjacent second modules are sequentially connected in series through the signal lines, so that all the second modules can work independently, and normal work of other second modules cannot be affected even if a single second module breaks down.

Description

Technical Field

[0001] The embodiments of this application relate to the field of energy storage system technology, and particularly to an energy storage system, an address calibration method, and an electronic device. Background Technology

[0002] Battery energy storage systems typically consist of a master unit and multiple slave units. To distinguish each slave unit, the master unit needs to form an address mapping network with each slave unit to map the addresses of each slave unit. A common issue with the address mapping network in battery energy storage systems is that a failure in this network can affect the normal energy storage operation of the slave units. Summary of the Invention

[0003] The purpose of the embodiments of this application is to provide an energy storage system, an address calibration method, and an electronic device to solve the technical problem that the address calibration network of the energy storage system in the prior art will affect the normal energy storage operation of the slave device when a fault occurs.

[0004] To address the aforementioned technical problems, embodiments of this application disclose the following technical solutions:

[0005] In a first aspect, an energy storage system is provided, the system comprising:

[0006] The first module is configured to output an address calibration signal via a communication bus during address calibration.

[0007] Multiple second modules are connected to a communication bus and are connected to the first module through the communication bus; the second modules are configured to receive the address calibration signal to feed back address calibration data.

[0008] In this configuration, two adjacent second modules are connected in series via a signal line. Each second module has a first connection terminal and a second connection terminal. One end of the signal line is connected to the first connection terminal of one of the second modules, and the other end of the signal line is connected to the second connection terminal of the other second module. The signal line is configured to output the signal from the first connection terminal through the series-connected second modules.

[0009] In conjunction with the first aspect, the second module includes a second control unit, which has a bus interface, a first interface, and a second interface. The bus interface is connected to the communication bus, the first interface is connected to the first connection terminal, and the second interface is connected to the second connection terminal.

[0010] The second control unit is configured to receive the address calibration signal to configure the first interface to output a first level signal;

[0011] The first connection terminal is configured to output a second level signal based on the first level signal;

[0012] The second connection terminal is configured to receive the second level signal so that the second interface outputs a third level signal;

[0013] Wherein, the first level signal and the second level signal have the same potential, and the second level signal and the third level signal have different potentials.

[0014] In conjunction with the first aspect, the second module further includes a first driving circuit, which is connected between the first interface and the first connection terminal;

[0015] The first driving circuit includes a first coupling unit and a first switching unit, wherein the first switching unit is configured to be turned on based on the third level signal;

[0016] The first coupling unit is configured to output the second level signal to the first connection terminal based on the conduction of the first switching unit;

[0017] The first coupling unit includes a first drive input terminal, a first drive output terminal, a first detection input terminal, a first detection output terminal, and a first detection control terminal;

[0018] The first switching unit has a first switch control terminal, a first switch output terminal, and a first switch input terminal;

[0019] Wherein, the first drive input terminal is connected to the first power supply, the first drive output terminal is connected to the first switch input terminal, the first detection input terminal is connected to the second power supply, the first detection control terminal is connected to the first detection output terminal, the first detection output terminal is connected to the first connection terminal, the first switch control terminal is connected to the first interface, and the first switch output terminal is grounded.

[0020] In conjunction with the first aspect, the first driving circuit further includes a first resistor, a second resistor, a fourth resistor, a sixth resistor, and a third capacitor. The first resistor is connected between the first interface and the first switch control terminal. The second resistor is connected between the first switch control terminal and the first switch output terminal. The fourth resistor is connected between the first switch input terminal and the first driving input terminal. The two ends of the sixth resistor and the third capacitor connected in parallel are respectively connected between the first detection output terminal and the first detection control terminal.

[0021] In conjunction with the first aspect, the second module further includes a second driving circuit, which is connected between the second interface and the second connection terminal;

[0022] The second driving circuit includes a second coupling unit, which has a second driving input terminal, a second driving output terminal, a second detection input terminal, and a second detection output terminal. The second driving input terminal is connected to the second connection terminal, the second driving output terminal is grounded, the second detection input terminal is connected to the second interface and the first power supply respectively, and the second detection output terminal is grounded.

[0023] In conjunction with the first aspect, the second driving circuit further includes a first capacitor, a third resistor, a fifth resistor, and a second capacitor. The first capacitor is connected between the second driving input terminal and the second driving output terminal, and the third resistor is connected between the first power supply and the second driving input terminal. The two ends of the fifth resistor and the second capacitor connected in parallel are respectively connected to the second detection input terminal and the second detection output terminal.

[0024] In conjunction with the first aspect, the communication bus adopts at least one of the CAN bus protocol, RS485 bus protocol, and RS422 bus protocol.

[0025] Secondly, an address calibration method is provided, applied to a first module in an energy storage system as described in any one of the first aspects, the method comprising:

[0026] Send calibration commands and address requests to the second module;

[0027] In response to the address response from the second module, the address data is updated;

[0028] If the feedback time of the second module exceeds the time threshold, a calibration failure message is output.

[0029] Upon completion of calibration of the second module, a calibration success message is output.

[0030] Thirdly, an address calibration method is provided, applied to a second module in an energy storage system as described in any one of the first aspects, the method comprising:

[0031] In response to the calibration command sent by the first module, the first interface is configured to output a first potential signal, and the address calibration status bit is configured to the first state;

[0032] In response to the address request sent by the first module, it is determined that the second interface has received the second potential signal and that the address calibration status bit is in the first state, and an address response is generated;

[0033] Send the address response to the first module, configure the first interface to output a second potential signal, and configure the address calibration status bit to the second state;

[0034] The second state of the address calibration status bit is configured to indicate that the second module has completed address calibration.

[0035] Fourthly, an electronic device is provided, including a memory and a processor; the memory is used to store a computer program; the processor is used to implement, when executing the computer program, the address marking method as described in the second aspect, or the address marking method as described in the third aspect.

[0036] One of the above technical solutions has the following advantages or beneficial effects:

[0037] This application provides an energy storage system comprising: a first module configured to output an address calibration signal via a communication bus during address calibration; and multiple second modules, each connected to the communication bus and linked to the first module via the communication bus; each second module configured to receive the address calibration signal and feed back address calibration data; wherein adjacent second modules are connected in series via signal lines, each second module having a first connection terminal and a second connection terminal, one end of the signal line being connected to the first connection terminal of one of the second modules, and the other end being connected to the second connection terminal of another second module, the signal line being configured to output the signal from the first connection terminal through the series-connected second modules. The system provided by this application connects the first and second connection terminals of adjacent second modules in series via signal lines, enabling each second module to operate independently, and ensuring that a failure in a single second module will not affect the normal operation of the other second modules.

[0038] This application also provides an address calibration method applied to a first module in an energy storage system. The method includes: sending a calibration command and an address request to a second module; updating address data in response to an address response from the second module; outputting calibration failure information in response to the second module's feedback time exceeding a time threshold; and outputting calibration success information in response to the total number of calibrations completed by the second module reaching zero. The address calibration method provided in this application, applied to a first module in an energy storage system, involves the first module sending a calibration command and an address request to the second module, updating the address data based on the second module's feedback address response, and determining whether calibration is complete based on the number of calibrations completed by the second module.

[0039] This application also provides an address calibration method applied to a second module in an energy storage system. The method includes: responding to a calibration command sent by a first module, configuring a first interface to output a first potential signal and configuring an address calibration status bit to a first state; responding to an address request sent by the first module, determining that a second interface has received a second potential signal and determining that the address calibration status bit is in the first state, and generating an address response; sending the address response to the first module, configuring the first interface to output a second potential signal, and configuring the address calibration status bit to a second state; the second state of the address calibration status bit is configured to indicate that the second module has completed address calibration. The address calibration method provided in this application, applied to a second module in an energy storage system, allows the second module to receive and send a calibration command and an address request, and then generate an address response to feed back to the first module, thereby completing the address calibration. Attached Figure Description

[0040] The technical solution and other beneficial effects of this application will become apparent from the following detailed description of specific embodiments in conjunction with the accompanying drawings.

[0041] Figure 1 A schematic diagram of an energy storage system provided in an embodiment of this application;

[0042] Figure 2 This is a schematic diagram of the module connection of an energy storage system provided in an embodiment of this application;

[0043] Figure 3 This is a connection diagram of the first driving circuit provided in an embodiment of this application;

[0044] Figure 4 This is a connection diagram of the second driving circuit provided in an embodiment of this application;

[0045] Figure 5 A schematic diagram illustrating the steps of the address marking method for the first module provided in this application embodiment;

[0046] Figure 6 A flowchart illustrating the address marking method for the first module provided in this application embodiment;

[0047] Figure 7 A schematic diagram illustrating the steps of the address marking method for the second module provided in this application embodiment;

[0048] Figure 8 A flowchart illustrating the address marking method for the second module provided in this application embodiment;

[0049] The attached figures are labeled as follows:

[0050] 100 - First module, 200 - Second module, 300 - Signal line, 400 - Communication bus, 500 - Power ground line, 600 - Power positive line. Detailed Implementation

[0051] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. In the description of this application, it should be understood that the terms "center," "longitudinal," "lateral," "length," "width," "thickness," "upper," "lower," "front," "rear," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," "outer," "clockwise," and "counterclockwise," etc., indicating the orientation or positional relationship, are based on the orientation or positional relationship shown in the accompanying drawings and are only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this application. Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Thus, features defined with "first" and "second" may explicitly or implicitly include one or more of the stated features. In the description of this application, "multiple" means two or more, unless otherwise explicitly specified.

[0052] The specific implementation methods of this application are illustrated below through examples:

[0053] like Figure 1 As shown, this application embodiment provides an energy storage system, the system including: a first module 100, the first module 100 being configured to output an address calibration signal via a communication bus during address calibration; and a plurality of second modules 200, the second modules 200 being connected to the first module 100 via a communication bus 400, the plurality of second modules 200 being configured to receive the address calibration signal via the communication bus 400 to feed back address calibration data; wherein, two adjacent second modules 200 are connected by a signal line 300, each second module 200 having a first connection terminal A and a second connection terminal B, one end of the signal line 300 being connected to the first connection terminal A of one of the second modules 200, and the other end of the signal line 300 being connected to the second connection terminal B of another second module, the signal line 300 being configured to output the signal of the first connection terminal A through the series-connected second modules.

[0054] The energy storage system provided in this application connects the first connection terminal A and the second connection terminal B of adjacent second modules 200 in series via signal line 300, so that each second module 200 can work independently, and even if a single second module 200 fails, it will not affect the normal operation of other second modules 200.

[0055] Specifically: Module 100 includes a master unit, and Module 200 includes slave units. One master unit connects to multiple slave units to achieve data exchange. It is worth noting that the master and slave units can be configured in various ways in different energy storage systems. For example, in CAN bus communication, the master unit includes a Battery System Controller (BSC), and the slave unit includes a Battery Cluster Management Unit (CMU); in RS485 bus communication, the master unit includes a BSC controller, and the slave unit includes a fire fan controller.

[0056] like Figure 1 and Figure 2 As shown, the first module 100 includes a first control unit, which has a communication connection terminal connected to a communication bus. The first control unit includes a host control chip. There are n second modules 200, where n is greater than or equal to 3, arranged sequentially from 1 to n. Each second module 200 has the same first connection terminal A and second connection terminal B. Except for the second connection terminal B of the first second module 200 and the first connection terminal A of the nth second module 200, the first connection terminal A of all other second modules 200 is connected to the second connection terminal of the next second module 200. That is, each second module 200 is connected to its adjacent second module 200 via a single signal line 300. The first control unit in the first module 100 sends an address calibration signal to each second module 200 via the communication bus 400. The address calibration signal includes an address calibration instruction. When a second module 200 receives the address calibration signal, it begins to execute the address calibration task. The second module 200 also sends back address response and calibration completion information to the first module 100 via the communication bus 400.

[0057] The specific working process and principle include: taking the second module 200 as an example, when the address calibration task of the second module 200 is completed, the second connection terminal B of the second module 200 outputs a corresponding level signal through the signal line 300; after receiving the level signal, the first connection terminal A of the third module 200 starts to execute the address calibration task. When the third module 200 completes the address calibration task, the second connection terminal B of the third module 200 outputs a corresponding level signal to the fourth module 200 through the signal line 300, and so on, until all n modules 200 have completed the address calibration task.

[0058] As described above, each second module 200 only begins its address calibration task after receiving the address calibration signal from the first module 100 via the first control unit. Furthermore, after each second module 200 completes its address calibration task, it changes the level signal at the second connection terminal B and transmits the signal to the next second module 200 via signal line 300 to initiate the address calibration task for that module. Therefore, the signal line 300 between the second modules 200 is only used after the communication bus 400 sends the address calibration signal. During normal operation, the signal lines 300 between the second modules 200 do not interfere with each other, and even a fault will not affect normal operation.

[0059] like Figure 1 and Figure 2 As shown in the embodiment of this application, the energy storage system further includes a power positive line 600 and a power ground line 500. The first module 100 has a first positive input terminal and a first ground terminal, and the second module 200 has a second positive input terminal and a second ground terminal. Both the first and second positive input terminals are connected to the power positive line 600, and the first and second ground terminals are connected through a grounding wire. Specifically, the power positive line 600 is used to provide positive voltage or positive current. The power positive line 600 connects the positive terminal of the power supply to the positive terminals of the first module 100 and the second module 200, providing the required positive voltage or positive current to the first module 100 and the second module 200. The power ground line 500 (also called a ground wire or ground conductor) is used to connect the metal casings of the first module 100 and the second module 200 to the earth or ground surface to form a ground potential.

[0060] The power grounding wire 500 grounds the casings of the first module 100 and the second module 200, forming a safe path to guide current to ground in the event of leakage or fault in the circuit, thereby reducing the risk of electric shock. The power grounding wire 500 also eliminates interference and electromagnetic noise by grounding the metal parts of the first module 100 and the second module 200. This provides a stable ground reference point for the system circuit, reducing interference to other devices. The power grounding wire 500 also prevents the accumulation of static electricity in the first module 100 and the second module 200, protecting electronic components from damage caused by electrostatic discharge.

[0061] like Figure 1 and Figure 2As shown in this embodiment, the second module 200 includes a second control unit. The second control unit has a bus interface, a first interface out, and a second interface in. The bus interface is connected to a communication bus 400. The first interface out is connected to a first connection terminal A, and the second interface in is connected to a second connection terminal B. The second control unit is configured to receive an address calibration signal to configure the first interface out to output a first level signal. The first connection terminal A is configured to output a second level signal based on the first level signal. The second connection terminal B is configured to receive the second level signal to cause the second interface in to output a third level signal. The first level signal and the second level signal have the same potential, while the second level signal and the third level signal have different potentials.

[0062] Specifically, the first and second level signals are both high-level signals, and the third level signal is a low-level signal. The second control unit connects to the communication bus 400 via a bus interface to transmit and receive data. When the first control unit receives the address calibration signal sent by the first module 100 via its bus interface, it judges the signal state of the second connection terminal B. If the second connection terminal B receives a high-level signal, the second control unit configures the state of the first interface OUT to a high-level signal. After the second module 200 completes the address calibration task, the second control unit changes the state of the first interface OUT to a low-level signal. At this time, the first connection terminal A outputs a low-level signal to the second connection terminal B of the next second module 200 according to the signal state of the first interface OUT.

[0063] In this embodiment, the high-level signal and the low-level signal are referenced to the operating voltage VCC of the second control unit. If the operating voltage VCC is 3.3V, then a voltage greater than 1.6V is a high-level signal, and a voltage less than 1.6V is a low-level signal. If the operating voltage VCC is 5.5V, then a voltage greater than 2.7V is a high-level signal, and a voltage less than 2.7V is a low-level signal.

[0064] In some embodiments of this application, high-level signals and low-level signals can also be distinguished by other parameters. The specific values ​​can be selected according to the actual situation, and this application will not list them in detail here.

[0065] In some embodiments of this application, the first level signal and the second level signal may also be low level signals, and the third level signal may also be a high level signal. The specific type of the first level signal, the second level signal, and the third level signal can be selected according to the actual situation, and this application does not impose further restrictions here.

[0066] It is understood that in this embodiment of the application, the second control unit controls the bus interface to send an address calibration signal to each second module 200 through the communication bus 400 to control each second module 200 to start the address calibration task; then the second control unit controls the first interface out to output high and low potential signals to control the potential state of the second interface in, thereby controlling the timing and order in which the second module 200 starts the address calibration task, so as to avoid confusion caused by the second modules 200 performing address calibration at the same time after receiving the address calibration signal.

[0067] like Figure 2 and Figure 3 As shown in the embodiment of this application, the second module 200 further includes a first driving circuit, which is connected between the first interface out and the first connection terminal A. The first driving circuit includes a first coupling unit U2 and a first switching unit N1. The first switching unit N1 is configured to conduct based on a third level signal. The first coupling unit U2 is configured to output a second level signal to the first connection terminal based on the conduction of the first switching unit N1. The first coupling unit U2 includes a first driving input terminal, a first driving output terminal, a first detection input terminal, a first detection output terminal, and a first detection control terminal. The first switching unit N1 has a first switch control terminal, a first switch output terminal, and a first switch input terminal. The first driving input terminal is connected to a first power supply, the first driving output terminal is connected to the first switch input terminal, the first detection input terminal is connected to a second power supply, the first detection control terminal is connected to the first detection output terminal, and the first detection output terminal is connected to the first connection terminal. The first switch control terminal is connected to the first interface, and the first switch output terminal is grounded. Specifically, the first coupling unit U2 includes an optocoupler. The first driving input terminal of the first coupling unit U2 is pin 1 of the optocoupler, the first driving output terminal is pin 2 of the optocoupler, the first detection input terminal is pin 5 of the optocoupler, the first detection output terminal is pin 4 of the optocoupler, and the first detection control terminal is pin 6 of the optocoupler. A light-emitting diode (LED) is connected between the first driving input terminal and the first driving output terminal, and a photodiode is connected between the first detection input terminal and the first detection output terminal. When a suitable current is input to the first driving input terminal, the LED emits light, which is transmitted to the photodiode. Through light energy conversion, the photodiode converts light energy into electrical energy, generating current. Therefore, by controlling the current at the first driving input terminal, the current at the first detection output terminal is controlled.

[0068] The first coupling unit U2 can isolate the input and output signals between the first interface out and the first connection terminal A, thereby protecting the system circuit from external noise and interference.

[0069] In the embodiments of this application, the first power supply is used to provide the working voltage VCC, and the second power supply is used to provide the supply voltage. It is understood that the working voltage VCC and the supply voltage may be equal or unequal, depending on the actual situation of the circuit. This application embodiment does not impose too many restrictions here.

[0070] like Figure 2 and Figure 3 As shown in the embodiment of this application, the first switching unit N1 includes a transistor, wherein the first switching control terminal of the first switching unit N1 is the base of the transistor, the first switching output terminal is the emitter of the transistor, and the first switching input terminal is the collector of the transistor. The switching on and off of the first switching input terminal and the first switching output terminal can be achieved by controlling the level of the first switching control terminal. This allows the first drive output terminal to be grounded through the first switching input terminal and the first switching output terminal, thereby pulling down the potential of the first drive output terminal to facilitate control of the conduction of the first drive input terminal and the first drive output terminal. It should be noted that the first switching unit N1 can be an NPN type transistor or a PNP type transistor. Different voltages can be selected for the first interface out terminal depending on the type of transistor. The specific transistor used can be selected according to the actual situation, and this embodiment of the application does not impose any restrictions here.

[0071] like Figure 2 and Figure 3 As shown in the embodiment of this application, the first driving circuit further includes a first resistor R1, a second resistor R2, a fourth resistor R4, a sixth resistor R6, and a third capacitor C3. The first resistor R1 is connected between the first interface out and the first switch control terminal; the second resistor R2 is connected between the first switch control terminal and the first switch output terminal; the fourth resistor R4 is connected between the first switch input terminal and the first drive input terminal; the two ends of the parallel connection of the sixth resistor R6 and the third capacitor C3 are respectively connected between the first detection output terminal and the first detection control terminal. Specifically, the first resistor R1 and the second resistor R2 both serve to limit current, preventing the instantaneous current output from the first interface out from being too large, which could cause a surge in current in the first switch unit N1 and damage it. The fourth resistor R4 is used to limit the output of the first drive output terminal, preventing the current generated by the working voltage VCC connected to the first drive output terminal of the first coupling unit U2 from being too large and damaging the first switch unit N1. The sixth resistor R6 is used to limit the current of the first detection output terminal, preventing the excessive current output by the first detection output terminal from affecting the first detection control terminal. The third capacitor, C3, mainly serves as a filter, used to filter out noise in the circuit.

[0072] like Figure 2 and Figure 3As shown in the embodiment of this application, the first driving circuit further includes a first diode D1. The cathode of the first diode D1 is connected to the first detection input terminal, and the anode of the first diode D1 is connected to the positive power supply line 600. The direction of current in the positive power supply line 600 can be limited by the first diode D1.

[0073] like Figure 2 and Figure 4 As shown in this embodiment, the second module 200 further includes a second driving circuit connected between the second interface in and the second connection terminal B. The second driving circuit includes a second coupling unit U1, which has a second driving input terminal, a second driving output terminal, a second detection input terminal, and a second detection output terminal. The second driving input terminal is connected to the second connection terminal B, the second driving output terminal is grounded, the second detection input terminal is connected to the second interface in and the first power supply, and the second detection output terminal is grounded. Specifically, the second coupling unit U1 includes an optocoupler, wherein the second driving input terminal of the second coupling unit U1 is pin 1 of the optocoupler, the second driving output terminal is pin 2 of the optocoupler, the second detection input terminal is pin 4 of the optocoupler, and the second detection output terminal is pin 3 of the optocoupler. A light-emitting diode (LED) is connected between the second drive input terminal and the second drive output terminal, while a photodiode is connected between the second detection input terminal and the second detection output terminal. When the second drive input terminal outputs a suitable current, the LED emits light, which is transmitted to the photodiode. Through light energy conversion, the photodiode converts light energy into electrical energy, generating current. Therefore, the current at the second detection output terminal is controlled by controlling the current at the second drive input terminal. The second coupling unit U1 isolates the input and output signals between the second interface in and the second connection terminal B, thereby protecting the system circuit from external noise and interference.

[0074] like Figure 2 and Figure 4As shown in the embodiment of this application, the second driving circuit further includes a first capacitor C1, a third resistor R3, a fifth resistor R5, and a second capacitor C2. The first capacitor C1 is connected between the second driving input terminal and the second driving output terminal, and the third resistor R3 is connected between the first power supply and the second driving input terminal. The two ends of the fifth resistor R5 and the second capacitor C2 connected in parallel are respectively connected to the second detection input terminal and the second detection output terminal. Specifically, the first capacitor C1 is mainly used to isolate the second interface in from the ground terminal, thereby preventing the second interface in or the working voltage VCC from being directly grounded, which would prevent the second coupling unit U1 from conducting. The third resistor R3 acts as a voltage divider, limiting the current at the second driving input terminal after dividing the working voltage VCC, thereby preventing the current at the second driving input terminal from being too large and damaging the second coupling unit U1. The fifth resistor R5 mainly acts as a current shunt, preventing the current of the light-emitting diode in the second coupling unit U1 from being too large, while the second capacitor C2 mainly acts as a filter.

[0075] In some embodiments of this application, it should be noted that the second connection terminal B of the first second module 200 is not connected to the first connection terminal A of any other second module 200. Therefore, the second coupling unit U1 in the second driving circuit of this second module 200 is always in the off state. However, the first interface in is always connected to the operating voltage VCC, so the first interface in is always in a high-level state. Thus, when the second module 200 receives the address calibration information sent by the first module 100, it can start the address calibration task. Therefore, the start of address calibration for the first second module 200 does not require control from other second modules 200; it can start as soon as it receives the address calibration information sent by the first module 100.

[0076] like Figure 2 and Figure 4 As shown in the embodiment of this application, the second driving circuit further includes a second diode D2, a third diode D3, and a seventh resistor R7. The anode of the second diode D2 is connected to the second detection output terminal, and the cathode of the second diode D2 is connected to one end of the seventh resistor R7. The other end of the seventh resistor R7 is connected to the power ground wire 500. The anode of the third diode D3 is connected to the second connection terminal B, and the cathode of the third diode D3 is connected to the second detection input terminal. Specifically, the second diode D2 is a light-emitting diode, which emits light when current flows through it, thus serving as a signal indicator. The third diode D3 is used to limit the direction of current flow, ensuring that the signal during the address calibration process is transmitted in the set direction, preventing current from flowing from the second detection input terminal to the second connection terminal B, which could lead to address calibration failure. The seventh resistor R7 is mainly used to limit the magnitude of the current flowing out of the second detection output terminal.

[0077] like Figure 1 and Figure 2As shown in the embodiments of this application, the communication bus adopts at least one of the CAN bus protocol, RS485 bus protocol, and RS422 bus protocol. Specifically, the CAN bus protocol, RS485 bus protocol, and RS422 bus protocol are all based on the principle of serial communication, and data is transmitted in the form of bit streams. Multiple signals can be transmitted through the same signal line. Furthermore, the CAN bus protocol, RS485 bus protocol, and RS422 bus protocol all use differential signal transmission, where the voltage difference between the positive and negative signals represents the value of the data bit. This differential transmission method can improve anti-interference capability and reduce the bit error rate. At the same time, the CAN bus protocol, RS485 bus protocol, and RS422 bus protocol all have good long-distance transmission capabilities. RS485 and RS422 support full-duplex communication, enabling the establishment of multi-master or multi-slave networks among multiple nodes, with transmission distances reaching several kilometers.

[0078] It is understood that in the energy storage system provided in this application embodiment, the first module 100 sends an address calibration signal to each second module 200 through the communication bus 400. The second module 200 starts the address calibration task only after confirming that it has received the address calibration signal, so as to ensure that the failure of a single second module 200 will not affect the normal operation of other second modules 200. The first module 100 controls the timing and order of the subsequent second modules 200 to start address calibration by controlling the level signal output by the first interface out, so that all the second modules 200 in the energy storage system can be calibrated sequentially.

[0079] like Figure 5 and Figure 6 As shown, this application embodiment also provides an address marking method, applied to a first module in an energy storage system as provided in any of the above embodiments, the method comprising:

[0080] S1: Send calibration commands and address requests to the second module.

[0081] Specifically, the calibration command is used to start the address calibration task of the second module. The address request is set by the first module. After the second module adds data to the address request, it forms an address response and sends it back to the first module. The first module records the address response and then updates the address data to complete the address calibration.

[0082] Specifically, before the first module sends calibration commands and address requests to the second module, the first module needs to initialize. The initialization steps include: setting the number of second modules, N, where N represents the total number of second modules. Simultaneously, the first module also needs to set the calibration timeout T1 and delay T2. The timeout T1 represents the maximum time threshold required for all second modules to complete calibration. Timer T starts counting from the moment the calibration command is sent; if the time recorded by timer T exceeds the timeout T1, calibration has failed. Typically, the timeout T1 is determined by the number of second modules, N; the more second modules N, the larger the timeout T1, and vice versa. The typical range for the timeout T1 is 10–20 seconds. The delay T2 is the time to wait for feedback from the second module after each calibration command issued by the first module; this time is typically 80–120 ms.

[0083] Specifically, after initialization is complete, the first module sends a calibration command to all second modules, and after waiting for a delay time T2, it starts to determine whether the quantity N is greater than 0. If it is greater than 0, the timer T is started and reset, and the first module sends an address request to the second module.

[0084] S21: In response to the address response from the second module, update the address data.

[0085] Specifically, after receiving an address request, the second module generates an address response based on the request's content. The second module then sends this response back to the first module, which updates its address data accordingly. Upon receiving the response, the first module decrements the number N representing the second module by 1, signifying the completion of one address calibration.

[0086] S22: In response to the feedback time of the second module exceeding the time threshold, output calibration failure information.

[0087] Specifically, if the first module fails to receive the completed address calibration information sent by the second module, it uses timer T to determine whether the time exceeds the timeout period T1. If the time in timer T is less than or equal to the timeout period T1, it continues to wait. If the actual time in timer T is greater than the timeout period T1, the first module sends a completed calibration command to indicate that the address calibration has failed.

[0088] S23: In response to the completion of calibration of the second module, output calibration success message.

[0089] Specifically, if the number N of the second modules is not greater than 0, it means that the addresses of all the second modules have been marked, and the first module sends a completion marking command to indicate that the address marking was successful.

[0090] It is understood that in the address calibration method provided in this application embodiment, the first module starts the address calibration task of the second module by sending a calibration command, and at the same time, the number of second modules N is set to determine whether all second modules have completed address calibration to avoid omissions; a timeout T1 is set to ensure that the second modules can complete address calibration on time to avoid system crashes due to excessive address calibration time and affect the normal operation of the system; and a delay time T2 is set to give the second modules sufficient address calibration time and feedback time.

[0091] like Figure 7 and Figure 8 As shown, this application embodiment also provides an address marking method, applied to a second module in an energy storage system as provided in any of the above embodiments, the method comprising:

[0092] M1: In response to the calibration command sent by the first module, configure the first interface to output the first potential signal and configure the address calibration status bit to the first state.

[0093] Specifically, after the second module confirms receipt of the calibration command sent by the first module, it first configures the first interface to output a first potential signal, i.e., a high-level signal, and simultaneously configures the address calibration status bit (flag) to the first state, i.e., a low-level state. To avoid confusion caused by all second modules performing address calibration simultaneously, the level state of the first interface is controlled to determine whether the next second module starts the calibration task. When the current second module is performing an address calibration task, the next second module cannot start calibration, thus achieving sequential calibration of all second modules. Therefore, when the first interface is configured to a high-level signal, the first connection terminal outputs a low-level state, and the next second module cannot start the calibration task (when the first switching unit is an NPN transistor, configuring the first interface to a high-level signal can turn off the first switching unit; while when the first switching unit is a PNP transistor, the first interface should be configured to a low-level signal to turn off the first switching unit).

[0094] M2: In response to the address request sent by the first module, it determines that the second interface has received the second potential signal and that the address calibration status bit is in the first state, and generates an address response.

[0095] Specifically, after confirming receipt of the calibration request X sent by the first module, it then confirms whether the previous second module has completed the address calibration task, that is, it determines whether the level of the second interface is a high-level signal. If it is a low-level signal, it continues to wait; if it is a high-level signal, it generates an address response, which includes incrementing the value in the address request X by 1.

[0096] M3: Sends an address response to the first module, configures the first interface to output a second potential signal, and configures the address calibration status bit to the second state; the second state of the address calibration status bit is configured to indicate that the second module has completed address calibration.

[0097] Specifically, after sending the generated address response to the first module, the first interface needs to be configured with a low-level signal so that the low-level signal can be transmitted to the next second module, enabling the next second module to start the address calibration task; at the same time, the address calibration status bit flag is configured with a high-level signal to indicate that the second module has completed the address calibration task, and the calibration completion information can also be sent to the first module.

[0098] It is understood that in the address calibration method provided in this application embodiment, the second module takes the address calibration command sent by the first module as the first element for starting the address calibration task, and at the same time, the second module takes the level state at the first interface in as the second element for starting the address calibration task. Only after both elements are satisfied will the second module start address calibration. The first module activates the address calibration task of the second module by controlling the first element, and controls the timing and order of starting the address calibration task of the second module by controlling the second element, thereby avoiding confusion or omissions in the address calibration process of the second module. Through this address calibration method, it can be ensured that the normal operation of other second modules will not be affected when a single second module fails.

[0099] This application also provides an electronic device, including a memory and a processor; the memory is used to store a computer program; the processor is used to implement the address marking method provided in the above embodiments when executing the computer program, specifically including:

[0100] F1: Initialize the quantity N, timeout T1, and delay T2. The steps include: setting the quantity N of the second module, where N represents the total number of all second modules, and setting the calibration timeout T1 and delay T2.

[0101] F2: The first module sends a calibration command to all second modules, and after waiting for a delay time T2, it starts to determine whether the quantity N is greater than 0. If it is greater than 0, the timer T is started and reset, and the first module sends an address request to the second module.

[0102] F3: The second module confirms receipt of the calibration command sent by the first module. It first configures the first interface to 1 (high level) and sets the address calibration status bit flag to 0 (low level).

[0103] To prevent confusion caused by all second modules performing address calibration simultaneously, the state of the first interface is controlled to determine whether the next second module starts its calibration task. While the current second module is performing address calibration, the next second module cannot start calibration, thus ensuring sequential calibration of all second modules. Therefore, when the first interface is configured as 1, the first connection end outputs 0, and the next second module cannot start its calibration task.

[0104] F4: Confirm receipt of address request X from the first module and that the level of the second interface is high. If the second interface is low, continue to wait. If it is high, generate an address response. The address response includes incrementing the address request by 1 and setting the address calibration status flag to 1 to indicate that the address calibration has been completed. Send the address response and calibration completion information to the first module. At this time, the second module also needs to set the first interface to low to start the next address calibration task of the second module.

[0105] F5: When the first module receives the address response and calibration completion information from the second module, the first module will decrement the number N of the second module by 1 to indicate that an address calibration has been completed, and at the same time update the address data;

[0106] F61: If the first module fails to receive the completed address calibration information sent by the second module, it will use timer T to determine whether the time exceeds the timeout period T1. If the time in timer T is less than or equal to the timeout period T1, it will continue to wait. If the actual time in timer T is greater than the timeout period T1, the first module will send a completed calibration command to indicate that the address calibration has failed.

[0107] F62: If the number N of the second modules is not greater than 0, it means that all the second modules have been calibrated. The first module sends a calibration completion command to indicate that the address calibration was successful.

[0108] It is understood that in the electronic device provided in this application embodiment, the first module initiates the address calibration task of the second module by sending a calibration command. Simultaneously, the number N of the second modules is set to determine whether all second modules have completed address calibration, avoiding omissions. A timeout T1 is set to ensure that the second modules can complete address calibration on time, preventing system crashes due to excessively long calibration times and affecting normal system operation. A delay T2 is set to provide sufficient address calibration time and feedback time for the second modules. The second module uses the address calibration command sent by the first module as the first element for starting the address calibration task, and the level state at the first interface in as the second element. After both elements are satisfied, the second module begins address calibration. The first module activates the address calibration task of the second module by controlling the first element and controls the timing and order of the second module's address calibration task by controlling the second element, thereby preventing confusion or omissions during the address calibration process. This address calibration method ensures that a failure in a single second module will not affect the normal operation of other second modules.

[0109] The energy storage system, address calibration method, and electronic device provided in the embodiments of this application have been described in detail above. Specific examples have been used to illustrate the principles and implementation methods of this application. The descriptions of the above embodiments are only for the purpose of helping to understand the technical solutions and core ideas of this application. Those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. These modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of this application.

Claims

1. An energy storage system, characterized by, The system comprises: a first module configured to output an address calibration signal through a communication bus when address calibration is performed; a plurality of second modules respectively connected to the communication bus, the second modules being connected to the first module through the communication bus; the second modules being configured to receive the address calibration signal to feed back address calibration data; wherein two adjacent second modules are connected in series through a signal line, each second module has a first connection end and a second connection end, one end of the signal line is connected to the first connection end of one second module, the other end of the signal line is connected to the second connection end of another second module, and the signal line is configured to output a signal at the first connection end through the second modules connected in series.

2. The energy storage system of claim 1, wherein, The second module comprises a second control unit having a bus interface, a first interface and a second interface, the bus interface being connected to the communication bus, the first interface being connected to the first connection end, and the second interface being connected to the second connection end; the second control unit is configured to receive the address calibration signal to configure the first interface to output a first level signal; the first connection end is configured to output a second level signal based on the first level signal; the second connection end is configured to receive the second level signal to make the second interface output a third level signal; wherein the first level signal and the second level signal have the same potential, and the second level signal and the third level signal have different potentials.

3. The energy storage system of claim 2, wherein, The second module further comprises a first driving circuit connected between the first interface and the first connection end; the first driving circuit comprises a first coupling unit and a first switching unit, the first switching unit being configured to be turned on based on the third level signal; the first coupling unit is configured to output the second level signal to the first connection end based on the turn-on of the first switching unit; wherein the first coupling unit comprises a first driving input end, a first driving output end, a first detection input end, a first detection output end and a first detection control end; the first switching unit has a first switching control end, a first switching output end and a first switching input end; wherein the first driving input end is connected to a first power supply, the first driving output end is connected to the first switching input end, the first detection input end is connected to a second power supply, the first detection control end is connected to the first detection output end, and the first detection output end is connected to the first connection end; the first switching control end is connected to the first interface, and the first switching output end is grounded.

4. The energy storage system of claim 3, wherein, The first driving circuit further comprises a first resistor, a second resistor, a fourth resistor, a sixth resistor and a third capacitor, the first resistor being connected between the first interface and the first switching control end, the second resistor being connected between the first switching control end and the first switching output end, the fourth resistor being connected between the first switching input end and the first driving input end; The sixth resistor and the third capacitor are connected in parallel, and two ends of the parallel connection are connected between the first detection output end and the first detection control end, respectively.

5. The energy storage system of claim 2, wherein, The second module further comprises a second driving circuit connected between the second interface and the second connection end. The second driving circuit comprises a second coupling unit having a second driving input end, a second driving output end, a second detection input end and a second detection output end.

6. The energy storage system of claim 5, wherein, The second driving circuit further comprises a first capacitor, a third resistor, a fifth resistor and a second capacitor.

7. The energy storage system of claim 1, wherein, The communication bus adopts at least one of CAN bus protocol, RS485 bus protocol and RS422 bus protocol.

8. An address calibration method characterized by comprising: The first module applied to the energy storage system of any one of claims 1-7, the method comprising: sending a calibration command and an address request to the second module; updating address data in response to an address response fed back by the second module; outputting a calibration failure information in response to a feedback time of the second module exceeding a time threshold; outputting a calibration success information in response to the second module completing calibration.

9. An address calibration method characterized by comprising: The second module applied to the energy storage system of any one of claims 1-7, the method comprising: configuring a first interface to output a first potential signal and configuring an address calibration state bit to a first state in response to receiving a calibration command sent by the first module; generating an address response in response to the second interface receiving a second potential signal and determining that the address calibration state bit is in the first state in response to receiving an address request sent by the first module; sending the address response to the first module, configuring the first interface to output a second potential signal, and configuring the address calibration state bit to a second state; the second state of the address calibration state bit is configured to represent that the second module completes address calibration.

10. An electronic device, comprising: comprising a memory and a processor; the memory is used to store a computer program; the processor is used to realize the address calibration method of claim 8 or the address calibration method of claim 9 when executing the computer program.

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