A low-power-consumption architecture implementation method of a DSC decoder applying a power consumption dynamic isolation technology

Abstract

The application discloses a kind of DSC decoder low-power consumption architecture implementation methods of application power consumption dynamic isolation technology, comprising: code stream pre-analysis unit, BP vector pre-search unit, P mode power consumption control unit for dynamic isolation P mode power consumption, and ICH behavior simulation unit for dynamic isolation I mode power consumption.During DSC decoding process, power consumption mainly comes from the prediction reconstruction under P mode and the encoding index update under I mode, so the application respectively carries out dynamic isolation to the power consumption of decoder P mode and I mode to realize accurate power consumption control optimization, and the application significantly reduces the power consumption of DSC decoder under the premise of not reducing video image display effect and compression efficiency.

Description

Technical Field

[0001] This invention relates to the field of video image encoding and decoding technology, specifically to a low-power architecture implementation method for a DSC decoder using dynamic power isolation technology. Background Technology

[0002] To alleviate the bandwidth pressure on transmission media such as MIPI (Mobile Industry Processor Interface) and DP (DisplayPort) caused by high-resolution, high-refresh-rate video images such as 2K, 4K, 120Hz, and 144Hz, the Video Electronic Devices Standards Association (VEDS) proposed a display stream compression (DSC) technology for video images. Meanwhile, as DSC encoding and decoding methods are widely used in mobile display devices such as smartphones and tablets, more stringent requirements are being placed on the low-power consumption of DSC decoders.

[0003] However, as a codec method aiming for "visual losslessness," DSC's prediction reconstruction in P mode involves a large number of mathematical logic operations, while index retrieval and updating in I mode (Index Color History Mode) require frequent access and lookup operations to memory. Furthermore, when the DSC algorithm is applied alone to the decoder, it cannot meet the prediction reconstruction modes expected from the upstream encoding units, thus requiring support for all features defined in the protocol. All of these factors result in the DSC decoder design requiring substantial hardware and power consumption, which contradicts the expectation of low-power performance for DSC decoders in mobile display scenarios.

[0004] Therefore, this invention proposes a low-power architecture implementation method for a DSC decoder based on dynamic power isolation technology, which significantly reduces the power consumption of the DSC decoder without reducing the video image display effect and compression efficiency. Summary of the Invention

[0005] This invention provides a method for implementing a low-power architecture of a DSC decoder using dynamic power isolation technology. The method comprises: a bitstream pre-parsing unit, a BP vector pre-lookup unit, a P-mode power control unit for dynamically isolating P-mode power consumption, and an ICH behavior simulation unit for dynamically isolating I-mode power consumption.

[0006] Furthermore, the bitstream pre-parsing unit is used to pre-parse the bitstream, predict the decoder's working mode and obtain the residual size, and the remaining bitstream information is sent to the entropy decoder after a delay through the bitstream buffer pool.

[0007] The BP vector pre-lookup unit obtains candidate BP vectors by pre-starting the calculation of the SAD value of the reconstructed value pipeline;

[0008] The P-mode power consumption control unit receives information from the code stream pre-parsing unit and the BP vector pre-lookup unit to select and activate the corresponding prediction branch circuit.

[0009] The ICH behavior simulation unit continuously simulates the read, write, and update behavior of the ICH based on the index information in the code stream, thus isolating the direct interaction between the code stream and the ICH storage.

[0010] Furthermore, the bitstream pre-parsing unit includes a bitstream buffer pool, a mode determination unit, and a residual size acquisition unit;

[0011] The bitstream buffer pool is used to delay the bitstream to postpone the start time of entropy decoding;

[0012] The mode determination unit and the residual size acquisition unit perform directional parsing of the bitstream prefix, thereby predicting the working mode and residual size of the decoder.

[0013] Furthermore, the BP vector pre-lookup unit includes a reconstructed value cache, SAD calculation, and hit_bp cache;

[0014] The reconstruction value cache and SAD calculation are used to advance the calculation logic of the reconstruction value pipeline to obtain candidate vectors. The hit_bp cache is responsible for storing information such as whether BP is activated and the index of the BP vector.

[0015] Furthermore, the P-mode power consumption control unit is used to provide a start signal for each prediction branch circuit, activate the corresponding prediction circuit, and isolate the clock network, data path and power domain of inactive prediction branches.

[0016] When the decoder is working in P mode, it determines whether to start block prediction (BP) through the BP vector pre-lookup unit. If BP is not activated, it further obtains the parameters res_size and qlevel and determines whether to start median prediction (MPP). If MPP is not activated, it defaults to using median prediction (MMAP).

[0017] Furthermore, the ICH behavior simulation unit includes an index mapping unit, a pointer dynamic update unit, a pointer management and arbitration unit, a read / write control unit, and an ICH storage unit.

[0018] Furthermore, the index mapping unit,

[0019] The index range of ICH in the decoder is 0~31. When it is not the first line, in invalid code stream and P mode, the ICH input index is updated to positions 22, 23, and 24, and the output index is updated to 0.

[0020] For the input index in I mode, the index positions from 0 to 24 are consistent with the bitstream index, and the index positions beyond 24 are mapped to positions 22, 23, and 24 according to certain rules. The output index is consistent with the bitstream index.

[0021] In the first row, the mapped index is consistent with the bitstream index.

[0022] Furthermore, the pointer dynamic update unit is used to further process the mapped code stream index, determine the address position of the ICH memory bank that needs to be read and written, and dynamically update the pointer corresponding to each ICH memory address according to a series of logical rules within the clock cycle;

[0023] The pointer management and arbitration unit is used to handle pointer update conflicts that may occur when the index of the same period code stream includes both the range of 0~24 and the range of 25~31, and to arbitrate the pointer position that needs to be updated first, so as to ensure the accuracy of the dynamic update of the ICH pointer.

[0024] The read / write control unit is responsible for directly interacting with the ICH memory, enabling read operations on up to three addresses in I mode and write operations on up to six addresses during the valid period of the code stream, significantly reducing the access frequency to the ICH memory.

[0025] This invention achieves dynamic isolation of the DSC decoder's P-mode power consumption through a bitstream pre-parsing unit, a BP vector pre-lookup unit, and a P-mode power consumption control unit. The ICH behavior simulation unit continuously simulates the ICH read, write, and update behavior based on the index information in the bitstream, isolating the direct interaction between the bitstream and the ICH memory, thus achieving dynamic isolation of the decoder's I-mode power consumption. This significantly reduces the DSC decoder's power consumption without affecting video image display quality or bitstream compression efficiency. Attached Figure Description

[0026] Figure 1 The figure shows a low-power architecture implementation method for a DSC decoder that applies dynamic power isolation technology, provided by the present invention.

[0027] Figure 2 The figure shows the implementation method of power consumption in the dynamic isolation P mode of the present invention;

[0028] Figure 3 The diagram illustrates an implementation method of the ICH behavior simulation unit of the present invention;

[0029] Figure 4 The diagram shows the startup process of the BP vector pre-lookup unit of the present invention. Detailed Implementation

[0030] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0031] Please see Figure 1-4 This invention provides a low-power architecture implementation method for a DSC decoder using dynamic power isolation technology, comprising: a bitstream pre-parsing unit, a BP vector pre-lookup unit, a P-mode power consumption control unit, and an ICH behavior simulation unit, such as... Figure 1 As shown.

[0032] The code stream pre-parsing unit is used to pre-parse the code stream, predict the decoder's operating mode, and obtain the residual size. The remaining code stream information is sent to the entropy decoder after a delay through the code stream buffer pool. The BP vector pre-lookup unit obtains candidate BP vectors by pre-starting the SAD (Sum of Absolute Difference) calculation of the reconstructed value pipeline. The P-mode power consumption control unit receives information from the code stream pre-parsing unit and the BP vector pre-lookup unit to select and activate the corresponding prediction branch circuit. The ICH behavior simulation unit includes an index mapping unit, a pointer dynamic update unit, a pointer management and arbitration unit, a read / write control unit, and an ICH memory. It continuously simulates the read, write, and update behavior of the ICH based on the index information in the code stream, isolating the direct interaction between the code stream and the ICH memory, and reducing the access frequency of the ICH memory.

[0033] A method for implementing a low-power architecture for a DSC decoder using dynamic power isolation technology includes the following steps:

[0034] Step 1: After the valid bitstream is input, the bitstream pre-parsing unit starts working first to obtain the working mode and residual size of the next coding group.

[0035] In P mode, the DSU-VLC (delta-size unit-variable-length coding) encoding method is adopted. This method has a prefix + suffix encoding structure, with units as the encoding and decoding units, and three pixels as a group. In the bitstream pre-parsing, only the prefix is ​​analyzed. The encoded prefix uses unary code encoding. Therefore, when the unit prefix is ​​less than the maximum coding size limited by MPP, the bitstream pre-parsing unit is mainly responsible for counting the number of "0"s (zero_num) before the first "1" in the prefix. It then uses a series of judgment logic to obtain the decoder's operating mode and residual size. These two parts correspond to the mode judgment unit and residual size acquisition unit in the bitstream pre-parsing unit, respectively. Figure 2 As shown, its basic logic is:

[0036] If the previous group was in P mode, then zero_num == (bpc - qlevel + 1), indicating that the next group will operate in I mode. If the previous group was in I mode, then zero_num == 0, indicating that the next group will operate in I mode. During the valid bitstream period, if it is not in I mode, it must be in P mode.

[0037] The residual size exists only in P mode; the residual size obtained in I mode is 5 by default. In P mode, if the force_mpp signal is raised, then res_size = bpc - qlevel; otherwise, res_size = pred_size + zero_num.

[0038] Here, bpc is the number of bits per component, pred_size is the predictive coding size at the encoder, and qlevel is the quantization level. bpc can be obtained through the PPS parameter, pred_size can be obtained from the previous group, and qlevel is obtained through the decoder's rate control module.

[0039] The above logic allows us to determine the decoder's operating mode and the residual size res_size in P mode in advance. After pre-parsing, the bitstream is sent to the entropy decoder after a delay in the bitstream buffer pool, thus postponing the start time of entropy decoding.

[0040] Step 2: The BP vector pre-lookup unit obtains candidate BP vectors by pre-starting the SAD calculation of the reconstructed value pipeline. To obtain BP information in advance and reduce hardware overhead, the BP candidate vector lookup is started in the row preceding the current row. Simultaneously, SAD value calculation begins only after at least 12 reconstructed values ​​(9 basic reconstructed values ​​+ 3 offset reconstructed values) have entered the reconstructed value cache unit. Figure 4As shown, after three cycles, the candidate vector and information on whether BP is started at the corresponding position of the current row are obtained. This information is then input into the hit_bp cache. Figure 2 .

[0041] Step 3: The information output from the bitstream pre-parsing unit and the BP vector pre-lookup unit is input into the P-mode power consumption control unit to select and activate the corresponding prediction branch circuit. The clock network, data path, and power domain of the inactive branch prediction circuit are all isolated. If the decoder is operating in P mode, the BP vector pre-lookup unit determines whether to start block BP. This information is stored in the hit_bp buffer. If BP prediction is selected, the data paths of MPP and MMAP are cut off, the clocks of MPP and MMAP are terminated by a gated clock, and their voltages are dynamically reduced. If BP is not activated, parameters such as res_size and qlevel are further obtained to determine whether to start MPP. If res_size == bpc-qlevel or the force_mpp signal is pulled up, MPP prediction is started. At this time, operand isolation is performed on BP and MMAP, the clocks of BP and MMAP are terminated by a gated clock, and their voltages are dynamically reduced. If MPP is not activated, MMAP is used by default. At this time, operand isolation is performed on BP and MPP, the clocks of BP and MMAP are terminated by a gated clock, and their voltages are dynamically reduced. If the decoder operates in I mode, then all three prediction methods—BP, MPP, and MMAP—are disabled. Figure 2 As shown.

[0042] Step 4: When the decoder operates in I mode, the BP, MPP, and MMAP prediction methods are all disabled. At this time, the ICH behavior simulation unit is active. The ICH behavior simulation unit continuously simulates the read, write, and update behavior of the ICH based on the index information in the bitstream, isolating the direct interaction between the bitstream and the ICH memory, such as... Figure 3 As shown. First, the bitstream index enters the index mapping unit for preprocessing. In the DSC decoder, the ICH index range is 0~31, and correspondingly, 32 dynamically updatable pointers DYN_PTR[31:0][4:0] are set. When it is not the first line, and it is in the bitstream invalid stage or P mode, the updated ICH input index is fixed at positions 22, 23, and 24, and the output index is fixed at 0. In I mode, the index positions 0~24 are consistent with the bitstream index, and the index beyond position 24 is mapped to positions 22, 23, and 24. In the first line, the mapped index is consistent with the bitstream index.

[0043] After the index mapping unit completes the preprocessing of the index, the dynamic pointers corresponding to positions 0-31 in the ICH memory will simulate the behavior of the ICH and dynamically update each cycle according to the code stream index through the pointer dynamic update unit. The specific update logic is as follows:

[0044] First, valid bitstream indices are obtained. Since ICH searches for three index values ​​per cycle, any duplicate indices are invalid. Furthermore, for indices not in the first row, it's necessary to check if their value exceeds 24. A value exceeding 24 indicates that the index will index the last seven addresses of the ICH memory. These last seven addresses have independent update and indexing rules, so index values ​​falling into these last seven addresses must be distinguished. In summary, two parameters can be obtained: the number of valid indices in the first twenty-five addresses (pre25_valid_num) and the number of valid indices in the last seven addresses (nxt7_valid_num).

[0045] Secondly, the logic for dynamically updating pointers can be divided into the following scenarios:

[0046] ① All three index values ​​are less than 25, i.e., nxt7_valid_num == 0. At this point, for the three index values ​​index0, index1, and index2 (not all of which are necessarily valid index values), subtract index0, index1, and index2 from the dynamic pointer DYN_PTR[31:0][4:0] respectively, and take their sign bits to obtain the pointer interval increment judgment array INDEX_CMP[31:0][2:0]. The increment coefficient calculation formula is then provided:

[0047] Inc_coef[31:0] = INDEX_CMP[31:0][0]+ INDEX_CMP[31:0][1]+ INDEX_CMP[31:0][2]

[0048] If `pre25_valid_num` = 3, it means that all three index values ​​are valid indices, and the pointers corresponding to the index values ​​are set to 0, 1, and 2 respectively, i.e., `DYN_PTR[index0] = 0`, `DYN_PTR[index1] = 1`, and `DYN_PTR[index0] = 2`. When `Inc_coef[i] = 0`, the pointer at position `i` dynamically increases by 3; when `Inc_coef[i] = 0`, the pointer at position `i` dynamically increases by 2; when `Inc_coef[i] = 2`, the pointer at position `i` dynamically increases by 1; when `Inc_coef[i] = 3`, the pointer at position `i` remains unchanged.

[0049] If `pre25_valid_num` = 2, it means that only two of the three index values ​​are valid, and the pointers corresponding to the index values ​​are set to 0 and 1 respectively. In addition, when `Inc_coef[i]` is less than or equal to `nxt7_valid_num`, the pointer at position `i` is dynamically incremented by 2; when `Inc_coef[i]` = 3, the pointer at position `i` remains unchanged; otherwise, the pointer at position `i` is dynamically incremented by 1.

[0050] If pre25_valid_num=1, it means that only one of the three index values ​​is a valid index, and the pointer corresponding to the index value is set to 0. When Inc_coef[i]=0, the pointer at position i is dynamically incremented by 1; otherwise, the pointer at position i remains unchanged.

[0051] When decoding the first line, all indices are no longer checked for being less than 25, but are all processed in a manner similar to that described above.

[0052] ② If there is exactly one index value that is not less than 25, i.e., nxt7_valid_num=1, then the index value greater than 24 is fixedly updated to the position DYN_PTR[i]=24, and the pointer is cleared to 0. If pre25_valid_num=2, it means that there are two valid index values ​​in the range of 0~24. If pre25_valid_num=1, it means that there is one valid index value in the range of 0~24. The method for handling these index values ​​is the same as the method described in ①.

[0053] ③ If two of the three index values ​​are not less than 25, and if nxt7_valid_num=1, then the index value greater than 24 is updated to the position DYN_PTR[i]=24, and the pointer is cleared to 0. If nxt7_valid_num=2, then they are updated to the positions DYN_PTR[i]=23 and 24 respectively, and the pointers are cleared to 0 and 1 respectively. For the last index value in the range of 0~24, the processing method is the same as described in ①.

[0054] ④ If all three index values ​​are greater than 25, then pre25_valid_num = 0. If pre25_valid_num = 1, it means the three index values ​​are duplicated. This index value is then updated to position DYN_PTR[i] = 24, and the pointer is cleared to 0. If pre25_valid_num = 2, it means there are only two valid index values. These are then updated to positions DYN_PTR[i] = 23 and 24 respectively, and the pointers are cleared to 0 and 1 respectively. If pre25_valid_num = 3, it means all three index values ​​are valid. These are then updated to positions DYN_PTR[i] = 22, 23, and 24 respectively, and the pointers are cleared to 0, 1, and 2 respectively.

[0055] Step 5: When the decoder is operating in I mode and the dynamic update of the pointers is completed, the pointer management and arbitration unit needs to handle conflicting pointers. Pointer conflicts mainly occur in parts ② and ③ of Step 4. When pre25_valid_num ≠ 0 and nxt7_valid_num ≠ 0, two update requests may occur for positions DYN_PTR[i] = 23 and 24. For example, when the three index values ​​are 23, 24, and 25, index 23 wants to update the pointer position DYN_PTR[i] = 23, index 24 wants to update the pointer position DYN_PTR[i] = 24, and index 25 also wants to update the pointer position DYN_PTR[i] = 24, thus causing a conflict. At this point, the pointer management and arbitration unit will prioritize ensuring that index values ​​less than 25 are updated to the correct pointer position. Therefore, index 23 will be updated to the pointer position DYN_PTR[i]=23, index 24 will be updated to the pointer position DYN_PTR[i]=24, and index 25 will be updated to the pointer position DYN_PTR[i]=22 because both DYN_PTR[i]=24 and 23 conflict.

[0056] Step 5: After the decoder completes the dynamic update and arbitration of the pointers, it needs to interact with the ICH memory through the read / write control unit. First, there are indices index0_remap, index1_remap, and index2_remap that have been remapped by the index mapping unit. Then, the corresponding ICH memory addresses DYN_PTR[i] = index0_remap, DYN_PTR[i] = index1_remap, and DYN_PTR[i] = index2_remap are obtained. When the decoder is working in P mode or there is a situation where data is updated from the last seven addresses of the ICH, write operations need to be performed on the above three addresses. Otherwise, only the pointer is updated and no operation is performed on any address of the ICH memory. When the last seven addresses of the ICH are not the first row, the three reconstructed values ​​are always updated from the previous row, and the update positions are always DYN_PTR[i] = 25, 26, and 27. Through the above methods, the read / write control unit enables read operations on up to three addresses in I mode and write operations on up to six addresses during the valid period of the code stream, which significantly reduces the access frequency of the ICH memory and thus greatly reduces power consumption in I mode.

[0057] This invention provides a low-power architecture implementation method for a DSC decoder using dynamic power isolation technology, which has the following advantages compared with the prior art:

[0058] Based on the existing DSC decoder architecture, a bitstream pre-parsing unit, a BP vector pre-lookup unit, and a P-mode power consumption control unit are introduced to dynamically isolate P-mode power consumption. An ICH behavior simulation unit is introduced to dynamically isolate I-mode power consumption. The low-power architecture of the DSC decoder provided by this invention, which utilizes dynamic power isolation technology, significantly reduces the power consumption of the DSC decoder without compromising video image display quality or bitstream compression efficiency.

[0059] Although embodiments of the invention have been shown and described, it will be understood by those skilled in the art that various changes, modifications, substitutions and alterations can be made to these embodiments without departing from the principles and spirit of the invention, the scope of which is limited by the appended claims and their equivalents.

Claims

1. A method for implementing a low-power architecture for a DSC decoder using dynamic power isolation technology, characterized in that, include: The code stream pre-parsing unit, the BP vector pre-lookup unit, the P-mode power consumption control unit for dynamically isolating P-mode power consumption, and the ICH behavior simulation unit for dynamically isolating I-mode power consumption. The bitstream pre-parsing unit is used to pre-parse the bitstream, predict the decoder's working mode and obtain the residual size. The remaining bitstream information is sent to the entropy decoder after being delayed by the bitstream buffer pool. The BP vector pre-lookup unit obtains candidate BP vectors by pre-starting the calculation of the SAD value of the reconstructed value pipeline; The P-mode power consumption control unit receives information from the code stream pre-parsing unit and the BP vector pre-lookup unit to select and activate the corresponding prediction branch circuit. The ICH behavior simulation unit continuously simulates the read, write, and update behavior of ICH based on the index information in the code stream, thus isolating the direct interaction between the code stream and the ICH storage. The P-mode power consumption control unit is used to provide start signals for each prediction branch circuit and activate the corresponding prediction circuit. The clock network, data path and power domain of inactive prediction branches are isolated. When the decoder is working in P mode, it determines whether to start block prediction (BP) through the BP vector pre-lookup unit. If BP is not activated, it further obtains the parameters res_size and qlevel and determines whether to start median prediction (MPP). If MPP is not activated, it uses median prediction (MMAP) by default. The ICH behavior simulation unit includes an index mapping unit, a pointer dynamic update unit, a pointer management and arbitration unit, a read / write control unit, and an ICH storage unit; The index mapping unit, The index range of ICH in the decoder is 0~31. When it is not the first line, in invalid code stream and P mode, the ICH input index is updated to positions 22, 23, and 24, and the output index is updated to 0. For the input index in I mode, the index positions from 0 to 24 are consistent with the bitstream index, and the index positions beyond 24 are mapped to positions 22, 23, and 24 according to certain rules. The output index is consistent with the bitstream index. In the first line, the mapped index is consistent with the bitstream index; The pointer dynamic update unit is used to further process the mapped code stream index, determine the address location of the ICH memory bank that needs to be read and written, and dynamically update the pointer corresponding to each ICH memory address according to a series of logical rules within the clock cycle. The pointer management and arbitration unit is used to handle pointer update conflicts that may occur when the index of the same period code stream includes both the range of 0~24 and the range of 25~31, and to arbitrate the pointer position that needs to be updated first, so as to ensure the accuracy of the dynamic update of the ICH pointer. The read / write control unit is responsible for directly interacting with the ICH memory, enabling read operations on up to three addresses in I mode and write operations on up to six addresses during the valid period of the code stream, significantly reducing the access frequency to the ICH memory.

2. The method for implementing a low-power architecture of a DSC decoder using dynamic power isolation technology according to claim 1, characterized in that: The bitstream pre-parsing unit includes a bitstream buffer pool, a mode judgment unit, and a residual size acquisition unit; The bitstream buffer pool is used to delay the bitstream to postpone the start time of entropy decoding; The mode determination unit and the residual size acquisition unit perform directional parsing of the bitstream prefix, thereby predicting the working mode and residual size of the decoder.

3. The method for implementing a low-power architecture of a DSC decoder using dynamic power isolation technology according to claim 2, characterized in that: The BP vector pre-lookup unit includes a reconstructed value cache, SAD calculation, and hit_bp cache; The reconstruction value cache and SAD calculation are used to advance the calculation logic of the reconstruction value pipeline to obtain candidate vectors. The hit_bp cache is responsible for storing information such as whether BP is activated and the index of the BP vector.

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