Wiring board and method for manufacturing same

Abstract

The invention provides a wiring substrate and a method for manufacturing the same, which are a technique for suppressing the generation of voids between wirings. A wiring board according to an embodiment includes: a conductive layer including a parallel wiring portion in which a plurality of wires are arranged in parallel; and an insulating layer laminated on the conductive layer and containing a resin and an inorganic filler, in which a plurality of wirings of the parallel wiring portion are covered with an adhesive film, the insulating layer having a single layer including: a first structure portion filled between the wirings of the parallel wiring portion; and a second structural part located above the parallel wiring part, the second structural part having a higher content of the inorganic filler than the first structural part.

Description

Technical Field

[0001] The present invention relates to a wiring substrate having an insulating layer laminated on a conductive layer comprising a plurality of parallel wiring portions arranged in parallel, and a method thereof for manufacturing the same. Background Technology

[0002] For this type of wiring substrate, a highly integrated technology for parallel wiring sections has been proposed (for example, see Patent Document 1).

[0003] Patent Document 1: Japanese Patent Application Publication No. 2024-015869 (paragraph

[0010] and) Figure 1 )

[0004] However, with the increasing integration of parallel wiring sections, the resin in the insulating layer cannot penetrate the wiring spaces between the parallel wiring sections, creating voids between the wiring spaces. Therefore, this invention provides a technique to suppress the generation of voids between wiring spaces. Summary of the Invention

[0005] A first aspect of the present invention, made in view of the above-mentioned problems, is a wiring substrate having: a conductive layer comprising a plurality of parallel wiring portions arranged in parallel; and an insulating layer laminated on the conductive layer, comprising a resin and an inorganic filler, wherein the plurality of wirings of the parallel wiring portions are covered by an adhesive film, and the insulating layer has a single layer comprising: a first structural portion filling the spaces between the wirings of the parallel wiring portions; and a second structural portion located above the parallel wiring portions, wherein the inorganic filler content of the second structural portion is higher than that of the first structural portion. Attached Figure Description

[0006] Figure 1 This is a cross-sectional view of a wiring substrate according to one embodiment of the present invention.

[0007] Figure 2 This is an enlarged side sectional view of the parallel wiring section.

[0008] Figure 3A , Figure 3B This is a side sectional view showing a method for manufacturing a wiring substrate.

[0009] Figures 4A to 4D This is a side sectional view showing a method for manufacturing a wiring substrate.

[0010] Figures 5A to 5C This is a side sectional view showing a method for manufacturing a wiring substrate.

[0011] Label Explanation

[0012] 10: Wiring substrate; 20: Conductive layer; 21: Insulating layer; 30A, 30B: Parallel wiring section; 31: Wiring; 40: Adhesive film; 41: Inorganic filler; C1: First structural section; C2: Second structural section; C3: Third structural section. Detailed Implementation

[0013] The following is for reference Figures 1 to 5C One embodiment of the present invention will be described. Figure 1 The wiring substrate 10 of this embodiment shown, for example, has a core substrate 11, a plurality of conductive layers 20 and a plurality of insulating layers 21 alternately stacked on its front and back sides, and a solder resist layer (not shown) as the outermost layer. Figure 1 This diagram shows only the portion of the wiring substrate 10 closer to the front side than the core substrate 11, and shows a side cross-sectional view of the wiring substrate 10 without the solder mask layer. The front side of the wiring substrate 10 will be described in detail below. Furthermore, in the wiring substrate 10, when distinguishing between conductive layers 20, each conductive layer 20 is sequentially referred to as "first conductive layer 20A", "second conductive layer 20B", and "third conductive layer 20C" from the side closest to the core substrate 11; when distinguishing between insulating layers 21, each insulating layer 21 is sequentially referred to as "first insulating layer 21A" and "second insulating layer 21B" from the side closest to the core substrate 11.

[0014] The core substrate 11 has an insulating substrate 11K and a first conductive layer 20A stacked on both its front and back sides. The insulating substrate 11K, for example, is constructed by stacking multiple prepregs (a B-stage sheet formed by resin impregnation of a core material made of fibers such as glass cloth). The insulating layer 21 is composed of a resin sheet containing resin and inorganic filler 41 without a core material, as detailed later. Additionally, the outermost solder resist layer (not shown) is, for example, an ultraviolet-curable photosensitive film made of epoxy resin or the like. Furthermore, the insulating substrate 11K may also be constructed by stacking multiple resin sheets. Alternatively, the solder resist layer may be formed by curing a liquid solder resist layer.

[0015] A plurality of through holes 15H are formed in the insulating substrate 11K of the core substrate 11, and through hole conductors 15 are filled inside them. Furthermore, the first conductive layers 20A on the front and back sides of the core substrate 11 are connected to each other through the plurality of through hole conductors 15.

[0016] Conductor patterns are formed on each of the multiple conductive layers 20 in a manner that constitutes a predetermined circuit. Each conductive layer 20 is entirely covered by an insulating layer 21 stacked thereon. Multiple vias 12H are formed in each of the multiple insulating layers 21, and via conductors 12 are filled inside them. Furthermore, on both sides of the core substrate 11, the circuits of the multiple conductive layers 20 are connected to each other through the multiple via conductors 12. In addition, the pads 16 included in the conductor pattern of the third conductive layer 20C are exposed through openings formed in a solder resist layer (not shown), for example, to connect to electrical components.

[0017] The conductor pattern of the second conductive layer 20B includes parallel wiring portions 30A and 30B in which multiple wirings 31 are arranged in parallel. The parallel wiring portions 30A and 30B form high-wire integration portions with narrow spacing between the wirings 31. For example, the width L of each wiring 31 is 3 μm or less, and the spacing S between adjacent wirings 31 is 3 μm or less. In this embodiment, the width L of each wiring 31 is 2 μm, and the spacing S between adjacent wirings 31 is 2 μm (see reference). Figure 2 In addition, each wiring 31 is a signal line that connects the pads (not shown) contained in the second conductive layer 20B to each other.

[0018] In this embodiment, the second conductive layer 20B is covered by the adhesive film 40. Specifically, the adhesive film 40 is arranged between the second conductive layer 20B and the second insulating layer 21B stacked thereon, such as... Figure 2 As shown, the surface (upper surface and side surface) of the second conductive layer 20B is covered. The adhesive film 40 improves the adhesion between the conductive layer 20 and the insulating layer 21, and ensures the reliability of insulation between the conductor patterns of the conductive layer 20. The thickness of the adhesive film 40 is preferably 10 nm to 500 nm.

[0019] The material of the adhesive film 40 is preferably a material that can bond with both the resin (organic material) constituting the insulating layer 21 and the metal (inorganic material) constituting the conductive layer 20. For example, a silane coupling agent having both a reactive group R1 that can chemically bond with organic materials and a reactive group R2 that can chemically bond with inorganic materials is preferred. Examples of reactive groups R1 as silane coupling agents include amino, epoxy, vinyl, methacryl, acrylate, mercapto, thioether, and isocyanate groups. Examples of reactive groups R2 include alkoxy, methoxy, ethoxy, azole, and silanol groups. In this embodiment, a silane coupling agent containing a triazole compound or other azole silane compound is used as the material of the adhesive film 40. However, the adhesive film 40 is not limited to a silane coupling agent as long as it improves the adhesion between the conductive layer 20 and the insulating layer 21; for example, it can be a titanium coupling agent, azole compound, thiol compound, triazine thiol compound, etc. In addition, the adhesive film 40 can be an inorganic material, such as silicon nitride, silicon dioxide, etc.

[0020] As described above, the insulating layer 21 is composed of a resin sheet containing resin and inorganic filler 41. The resin is composed of thermosetting resin, thermoplastic resin, photosensitive resin, or a mixture thereof, such as epoxy resin, acrylic resin, phenolic resin, melamine resin, silicone resin, polyimide resin, liquid crystal polymer, fluororesin, etc., or a combination of two or more of these. Examples of inorganic filler 41 include microparticles such as silica, alumina, mica, silicon nitride, and aluminum nitride. When the insulating layer 21 contains inorganic filler 41, compared to the case where the insulating layer 21 is composed only of resin, it is possible to improve the mechanical strength and thermal conductivity of the insulating layer 21, and adjust its coefficient of thermal expansion. Furthermore, the average particle size of the inorganic filler 41 is preferably 0.05 μm to 0.2 μm.

[0021] In addition, in this embodiment, the content of inorganic filler 41 near the parallel wiring portions 30A and 30B in the insulating layer 21 varies depending on its positional relationship with the wiring 31.

[0022] Specifically, such as Figure 2 As shown, in the vicinity of parallel wiring sections 30A and 30B, the inorganic filler content 41 varies in the first structural section C1 between the wirings 31 of parallel wiring sections 30A and 30B, the second structural section C2 above the parallel wiring sections 30A and 30B, and the third structural section C3 further above the second structural section C2. The first structural section C1 is configured such that the inorganic filler content 41 is lower than that of the second and third structural sections C2 and C3, while the third structural section C3 is configured such that the inorganic filler content 41 is higher than that of the first structural section C1 and lower than that of the second structural section C2. For example, the inorganic filler content 41 of the first structural section C1 is 15wt% to 55wt%, the inorganic filler content 41 of the second structural section C2 is 75wt% to 85wt%, and the inorganic filler content 41 of the third structural section C3 is 65wt% to 80wt%.

[0023] The above is a description of the structure of the wiring substrate 10 according to this embodiment. Next, referring to... Figures 3A to 5C An example illustrating the manufacturing method of the wiring substrate 10. (1) As shown Figure 3A As shown, a laminate 11S is prepared with metal foil 11D stacked on both sides of an insulating substrate 11K. Multiple through holes 15H are formed by drilling or laser irradiation, and adhesive residue inside the through holes 15H is removed by adhesive residue removal treatment.

[0024] (2) Next, as Figure 3BAs shown, for the laminate 11S and the interior of the through-hole 15H, for example, using a known subtractive process, chemical plating, electroplating, and etching are performed to laminate the first conductive layer 20A on both sides of the insulating substrate 11K, and the through-hole conductor 15 is filled into the through-hole 15H. Thus, the core substrate 11 is formed. Alternatively, the through-hole conductor 15 can also be a conductive paste or the like.

[0025] (3) Next, as Figure 4A As shown, resin sheets are stacked on the core substrate 11 and pressurized under heating. At this time, the stacked resin sheets melt and enter the gaps between the conductor patterns of the first conductive layer 20A, thus flattening the upper surface of the first insulating layer 21A. Furthermore, Figures 4A to 5C Only the front side of the wiring substrate 10 is shown.

[0026] (4) After the first insulating layer 21A is cooled, as Figure 4B As shown, a plurality of vias 12H are formed by irradiating a specified portion of the first insulating layer 21A with a laser, and then the adhesive residue inside the vias 12H is removed by a descaling process.

[0027] (5) Next, chemical plating, resist treatment, and electroplating, for example, a known semi-additive process, are performed on the first insulating layer 21A and inside the via 12H. This results in the deposition of the second conductive layer 20B and the filling of the via conductor 12 in the via 12H. Specifically, the electronic circuitry of the second conductive layer 20B is formed in the portion of the first insulating layer 21A not covered by the resist, while the portion covered by the resist exposes the first insulating layer 21A (see reference). Figure 4C The conductor pattern of the second conductive layer 20B includes parallel wiring portions 30A and 30B having multiple wirings 31.

[0028] (6) Next, an adhesive film 40 is formed on the surface of the second conductive layer 20B. The adhesive film 40 can be formed, for example, by immersing a core substrate 11, on which the first insulating layer 21A and the second conductive layer 20B are stacked, in a diluted solution of a silane coupling agent and then drying it. In this case, the silane coupling agent bonds with the metal, thus allowing the adhesive film 40 to be easily formed only on the surface of the second conductive layer 20B. Figure 4D The text shows that in Figure 4C The image shows an enlarged view of the region enclosed by double-dotted lines, forming an adhesive film 40. The concentration of the diluted silane coupling agent solution is preferably 0.1% to 10%.

[0029] Furthermore, in the process of forming the adhesive film 40, acid cleaning and water cleaning are performed before immersing the core substrate 11, on which the first insulating layer 21A and the second conductive layer 20B are stacked, into a diluted solution of the silane coupling agent. Water cleaning is then performed after immersion and before drying, thereby suppressing uneven film thickness. Alternatively, the diluted solution of the silane coupling agent can be sprayed or coated onto the surface of the second conductive layer 20B without immersion in the diluted solution.

[0030] (7) Next, the second insulating layer 21B is formed in the same manner as in step (3) (see reference). Figure 5A ).

[0031] Here, the resin sheet used to form the first insulating layer 21A and the second insulating layer 21B is a sheet in which inorganic filler 41 is uniformly dispersed. The content of inorganic filler 41 in the resin sheet before processing is preferably 65 wt% to 80 wt%. Furthermore, when the resin sheet is disposed on the first conductive layer 20A and the second conductive layer 20B and is pressurized under heating, the resin sheet melts and fills the gaps between the conductor patterns of the first conductive layer 20A and the second conductive layer 20B. At this time, in the formed second insulating layer 21B, as described above, a gradient in the content of inorganic filler 41 occurs near the parallel wiring portions 30A and 30B. This is presumably due to the following reasons.

[0032] That is, in the second insulating layer 21B, by covering the second conductive layer 20B with an adhesive film 40, the adhesive film 40 is tightly present between the wires 31 of the parallel wire portions 30A and 30B, which are high wire integration portions. As a result, the first structural portion C1 between the wires 31 becomes a region with a higher affinity for resin than the inorganic filler 41 compared to other regions, and the resin in the molten resin sheet can easily enter. Therefore, the content of inorganic filler 41 in the first structural portion C1 becomes lower. Along with this, the inorganic filler 41 that does not enter the first structural portion C1 accumulates in the second structural portion C2 above the first structural portion C1, so the content of inorganic filler 41 in the second structural portion C2 becomes higher. On the other hand, for the third structural portion C3, which is higher than the second structural portion C2, the influence of the adhesive film 40 is difficult to affect, and the content of inorganic filler 41 close to that of the resin sheet before processing (refer to Figure 2 ).

[0033] (8) After the second insulating layer 21B is cooled, a plurality of vias 12H are formed in the second insulating layer 21B in the same manner as in step (4) (see reference). Figure 5B Furthermore, in the same manner as step (5), a third conductive layer 20C and a via conductor 12 (see reference) are formed. Figure 5C ).

[0034] Then, after step (8), a solder resist layer is stacked on the third conductive layer 20C.

[0035] Furthermore, the wiring substrate 10 in this embodiment is not limited to... Figures 1 to 5C The illustrated structure, shape, and materials are described herein. For example, the wiring substrate 10 may also be a coreless substrate that does not include the core substrate 11. Furthermore, the wiring substrate 10 may have any number of conductive layers 20 and multiple insulating layers 21. Additionally, in this embodiment, the number of conductive layers 20 and insulating layers 21, and the structure of the electronic circuitry of the conductive layers 20, may differ between the front and back sides of the core substrate 11.

[0036] The above describes the structure and manufacturing method of the wiring substrate 10 according to this embodiment. Next, the effects of the wiring substrate 10 will be explained. In the wiring substrate 10 of the present invention, the following structure is adopted: In the insulating layer 21 covering the parallel wiring portions 30A and 30B, the inorganic filler content is different in the first structural portion C1 between the wirings 31 of the parallel wiring portions 30A and 30B and the second structural portion C2 above the parallel wiring portions 30A and 30B. The inorganic filler content of the second structural portion C2 is higher than that of the first structural portion C1, and conversely, the inorganic filler content of the first structural portion C1 is lower than that of the second structural portion C2. As in this embodiment, in the case of a high wiring integration portion where the wiring spacing of the wiring 31 is 3 μm or less, when manufacturing the wiring substrate 10, the inorganic filler 41 enters between the wirings 31, while the resin has difficulty entering, and voids are easily generated. Moreover, when the average particle size of the inorganic filler 41 is 0.2 μm or less, voids are more likely to be generated. However, in this embodiment, the content of inorganic filler 41 between the wirings 31 is reduced, so the resin in the insulating layer 21 can easily enter between the wirings 31, which can suppress the generation of voids.

[0037] In the wiring substrate 10 of this embodiment, the surface of the second conductive layer 20B is covered by an adhesive film 40. Therefore, it is presumed that in the first structural portion C1 between the wirings 31 of the parallel wiring portions 30A and 30B, which are high wiring integration portions, the adhesive film 40 is tightly present, making it a region with a higher affinity for resin than the inorganic filler 41 compared to other regions. In this state, if a resin sheet is pressed onto the second conductive layer 20B in a heated state, as described above, the resin in the melted resin sheet easily enters between the wirings 31 of the parallel wiring portions 30A and 30B, thus presumably the content of inorganic filler 41 in the first structural portion C1 becomes lower. Furthermore, it is presumed that since the inorganic filler 41 that does not enter the first structural portion C1 accumulates in the second structural portion C2 above the first structural portion C1, the content of inorganic filler 41 in the second structural portion C2 above the first structural portion C1 becomes higher. That is, by covering the surface of each wiring 31 of the parallel wiring portions 30A and 30B with an adhesive film 40, it is possible to use a resin sheet with a uniform content of inorganic filler 41 to manufacture an insulating layer 21 with different contents of inorganic filler 41 in the first structural portion C1 and the second structural portion C2 in a single layer.

[0038] [Other Implementation Methods]

[0039] In the above embodiment, only the second conductive layer 20B among the plurality of conductive layers 20 includes parallel wiring portions 30A and 30B having a plurality of wirings 3131, but parallel wiring portions 30A and 30B may also be included in other conductive layers 20A and 20C.

[0040] In the above embodiment, the entire surface of the second conductive layer 20B is covered by the adhesive film 40, but it is also possible that only the surfaces of the multiple wirings 31 of the parallel wiring portions 30A and 30B in the second conductive layer 20B are covered by the adhesive film 40.

[0041] Furthermore, specific examples of the technology included in the claims are disclosed in this specification and the accompanying drawings, but the technology described in the claims is not limited to these specific examples, and also includes examples obtained by various modifications and alterations to the specific examples, as well as examples obtained by taking a part of the specific examples separately.

Claims

1. A wiring substrate, comprising: a conductive layer including a plurality of parallel wiring portions in which wirings are arranged in parallel; and an insulating layer laminated on the conductive layer, including a resin and an inorganic filler, wherein the wirings of the parallel wiring portions are covered with an adhesive film, the insulating layer has a single layer, the single layer includes: a first structure portion which fills between the wirings of the parallel wiring portions from each other; and a second structure portion which is located above the parallel wiring portions, the second structure portion having a higher content of the inorganic filler than the first structure portion.

2. The wiring substrate according to claim 1, wherein the insulating layer includes a third structure portion which is located above the second structure portion, the third structure portion having a lower content of the inorganic filler than the second structure portion, and the third structure portion having a higher content of the inorganic filler than the first structure portion.

3. The wiring substrate according to claim 1 or 2, wherein the wirings of the parallel wiring portions are spaced apart from each other by 3 μm or less.

4. The wiring substrate according to claim 3, wherein the inorganic filler has an average particle diameter of 0.2 μm or less.

5. A method of manufacturing a wiring substrate, comprising the steps of: forming a conductive layer including a plurality of parallel wiring portions in which wirings are arranged in parallel; covering the conductive layer with an adhesive film; and forming an insulating layer on the conductive layer, wherein the forming of the insulating layer includes the step of pressing a resin sheet in which an inorganic filler is uniformly dispersed in a heated state to form a first structure portion which fills between the wirings of the parallel wiring portions from each other and a second structure portion which is located above the parallel wiring portions and has a higher content of the inorganic filler than the first structure portion.

6. The method of manufacturing a wiring substrate according to claim 5, wherein the inorganic filler has an average particle diameter of 0.2 μm or less. ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​

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