Printed circuit board

Abstract

The present disclosure provides a printed circuit board including: a glass layer; a cavity penetrating a portion of the glass layer from an upper surface of the glass layer; an interconnection unit including at least a portion disposed in the cavity and including a polymer layer and a plurality of first through vias each penetrating the polymer layer; and a plurality of second through-vias each penetrating the glass layer from a lower surface of the glass layer to a bottom surface of the cavity, where the plurality of first through-vias are connected to the plurality of second through-vias, respectively.

Description

[0001] This application claims the benefit of priority to Korean Patent Application No. 10-2024-0121211, filed on September 6, 2024, with the Korean Intellectual Property Office, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0002] This disclosure relates to a printed circuit board. Background Technology

[0003] To achieve high performance in products used for high-performance computing (HPC), such as servers, artificial intelligence (AI), and networks, the body size of packages has increased, as has the number of wiring layers. In this context, controlling substrate warpage can become difficult, so the core may be constructed with increased thickness. However, when the core has increased thickness, signal or power paths may also be lengthened accordingly. Consequently, signal and power characteristics may deteriorate. Summary of the Invention

[0004] One aspect of this disclosure is to provide a printed circuit board that may have a relatively large body, can easily perform warp control, and can improve signal and / or power characteristics by improving signal and / or power paths.

[0005] One aspect of this disclosure is to form an electrical path having micro-fine pitch and micro-size in a region of a glass core by: forming a cavity with a blind shape in the glass core; disposing an interconnect unit in the cavity, the interconnect unit including a first through-via having micro-fine pitch; and forming a second through-via penetrating the glass core on the underside of the cavity, the second through-via having micro-fine pitch and being connected to the first through-via.

[0006] According to one aspect of this disclosure, a printed circuit board includes: a glass layer; a cavity extending through a portion of the glass layer from an upper surface; an interconnect unit including at least a portion disposed in the cavity, and including a polymer layer and a plurality of first through-vias, all of the plurality of first through-vias extending through the polymer layer; and a plurality of second through-vias extending through the glass layer from a lower surface of the glass layer to a bottom surface of the cavity, wherein the plurality of first through-vias are respectively connected to the plurality of second through-vias.

[0007] According to another aspect of this disclosure, a printed circuit board includes: a glass core having a blind cavity; an interconnect unit having at least a portion disposed in the blind cavity; a plurality of second through vias, wherein, when viewed from above, the plurality of second through vias all penetrate a region of the glass core overlapping with the blind cavity; a plurality of third through vias, wherein, when viewed from above, the plurality of third through vias all penetrate a region of the glass core spaced apart from the blind cavity; a first stacking structure disposed on an upper side of the glass core and including a plurality of first wiring layers; and a second stacking structure disposed on a lower side of the glass core and including a plurality of second wiring layers.

[0008] According to another aspect of this disclosure, a printed circuit board includes: a glass layer having a top surface and a bottom surface; a cavity extending through only a portion of the glass layer from the top surface of the glass layer; an adhesive layer disposed on the bottom surface of the cavity; and a via extending through the glass layer from the bottom surface of the glass layer to the bottom surface of the cavity and into the cavity, and further through the adhesive layer. Attached Figure Description

[0009] The above and other aspects, features, and advantages of this disclosure will be more clearly understood through the following detailed embodiments, taken in conjunction with the accompanying drawings, in which: Figure 1 This is a block diagram illustrating an example of an electronic device system; Figure 2 This is a cross-sectional view showing an example of a printed circuit board according to an embodiment; Figure 3 It shows the manufacturing process. Figure 2 The process diagram of the printed circuit board shown; Figure 4 It is shown Figure 2 A cross-sectional view of a variant example of the printed circuit board shown; Figure 5 This is a cross-sectional view showing another example of a printed circuit board according to an embodiment; Figure 6 It is shown Figure 5 A cross-sectional view of a variant example of the printed circuit board shown; Figure 7 This is a cross-sectional view showing another example of a printed circuit board according to an embodiment; and Figure 8 It is shown Figure 7 A cross-sectional view of a variant example of the printed circuit board shown. Detailed Implementation

[0010] In the following description, embodiments of the present disclosure will be illustrated with reference to the accompanying drawings. In the drawings, some elements may be exaggerated, omitted, or simplified, and the dimensions of the elements do not necessarily reflect their actual dimensions.

[0011] Figure 1 This is a block diagram illustrating an example of an electronic device system.

[0012] Reference Figure 1 The electronic device 1000 houses a motherboard 1010. The motherboard 1010 can be physically or electrically connected to chip-related components 1020, network-related components 1030, other components 1040, etc. These components can be connected to other electronic components described below via various signal lines 1090.

[0013] Chip-related components 1020 may include: memory chips, such as volatile memory (e.g., dynamic random access memory (DRAM)), non-volatile memory (e.g., read-only memory (ROM) or flash memory); application processor chips, such as central processing units (e.g., central processing unit (CPU)), graphics processing units (e.g., graphics processing unit (GPU)), digital signal processors, cryptographic processors, microprocessors, microcontrollers, etc.; and logic chips, such as analog-to-digital converters (ADCs), application-specific integrated circuits (ASICs), etc. However, chip-related components 1020 are not limited to these and may also include other types of chip-related components. Furthermore, chip-related components 1020 may be combined with each other.

[0014] Network-related components 1030 may include components compatible with or operating according to protocols such as: Wi-Fi (IEEE 802.11 series, etc.), WiMAX (IEEE 802.16 series, etc.), IEEE 802.20, LTE, Ev-DO, HSPA+, HSDPA+, HSUPA+, GSM+, EDGE+, GPS, GPRS, CDMA, TDMA, DECT, Bluetooth, 3G, 4G, and 5G protocols, as well as any other wireless and wired protocols specified after the aforementioned protocols. However, network-related component 1030 is not limited to this, and may also include components compatible with or operating according to various other wireless or wired standards or protocols. Furthermore, network-related component 1030 may be combined with the aforementioned chip-related component 1020.

[0015] Other components 1040 may include high-frequency inductors, ferrite inductors, power inductors, ferrite beads, low-temperature co-fired ceramic (LTCC) components, electromagnetic interference (EMI) filters, multilayer ceramic capacitors (MLCCs), etc. However, other components 1040 are not limited to these and may also include passive components for various other purposes. Furthermore, other components 1040 may be combined with the aforementioned chip-related components 1020 and / or network-related components 1030.

[0016] Depending on the type of electronic device 1000, it may include other electronic components that are physically and / or electrically connected to the motherboard 1010 or not physically and / or electrically connected to the motherboard 1010. These other electronic components may include, for example, a camera 1050, an antenna 1060, a display 1070, and a battery 1080. However, other electronic components are not limited to these and may also include audio codecs, video codecs, power amplifiers, compasses, accelerometers, gyroscopes, speakers, mass storage units (e.g., hard disk drives), optical disc (CD) drives, digital versatile optical disc (DVD) drives, etc. Depending on the type of electronic device 1000, it may also include other electronic components for various purposes.

[0017] Electronic device 1000 can be a smartphone, personal digital assistant (PDA), digital camera, digital video camera, network system, computer, monitor, tablet PC, laptop PC, netbook PC, television, video game console, smartwatch, automotive component, etc. However, electronic device 1000 is not limited to these and can be any other electronic device capable of processing data.

[0018] Figure 2 This is a cross-sectional view showing an example of a printed circuit board according to an embodiment.

[0019] Reference Figure 2 The printed circuit board 500A according to the example may include: a glass layer 110; a cavity C extending through a portion of the glass layer 110 from its upper surface; an interconnect unit 200 having at least a portion disposed in the cavity C, and including a polymer layer 211 and a plurality of first through vias 231, each of the plurality of first through vias 231 extending through the polymer layer 211; and a plurality of second through vias 132, each extending through the glass layer 110 from its lower surface to the bottom surface of the cavity C. The plurality of first through vias 231 may be respectively connected to the plurality of second through vias 132.

[0020] Since the printed circuit board 500A, as described above, includes a glass layer 110, it can easily have a relatively large body size and effectively control warpage. Furthermore, interconnect units 200 including a plurality of first through-vias 231 can be disposed in the cavity C, and a plurality of second through-vias 132, respectively connected to the plurality of first through-vias 231, can be disposed on the underside of the cavity C. In this case, the plurality of first through-vias 231 and the plurality of second through-vias 132 can be formed with micro-pitch and micro-size, such that even when the glass layer 110 has an increased thickness, an electrical path with micro-pitch and micro-size can be provided in a region of the glass layer 110. Therefore, for semiconductor chips mounted on the printed circuit board 500A, signal paths and / or power paths can be improved. Thus, signal characteristics and / or power characteristics can be improved. Furthermore, since the interconnect units 200 are manufactured separately, yield can also be improved.

[0021] Cavity C may have a blind shape extending from the upper surface of glass layer 110 toward the lower surface through a portion of glass layer 110. For example, cavity C may be a blind cavity C. Interconnect unit 200 may be attached to the bottom surface of blind cavity C via adhesive layer 250. In this case, a plurality of second through vias 132 may further penetrate adhesive layer 250, so that each of the plurality of second through vias 132 can be easily connected to a corresponding one of the plurality of first through vias 231. For example, each of the plurality of second through vias 132 may be formed in a plurality of via holes extending from the lower surface of glass layer 110 through both glass layer 110 and adhesive layer 250 to interconnect unit 200, and may have a tapered shape substantially wider at the lower end than at the upper end in a cross section taken along its central axis.

[0022] Both cavities C and interconnect units 200 can be multiple. For example, multiple cavities C can be spaced apart from each other in the glass layer 110, and multiple interconnect units 200 can be respectively disposed in multiple cavities C. In addition, multiple second through holes 132 can be disposed on the underside of a corresponding one of the multiple cavities C. However, embodiments of this disclosure are not limited thereto, and if desired, at least two of the multiple interconnect units 200 can be disposed in one of the multiple cavities C.

[0023] The interconnect unit 200 may include a polymer layer 211 and a plurality of first through-holes 231, all of which penetrate the polymer layer 211. For example, the interconnect unit 200 may be an organic substrate. Therefore, the manufacturing process can be performed in a simplified manner, and costs can be effectively reduced. Furthermore, since the polymer layer 211 may have a relatively small thickness, it is easy to achieve fine pitch and micro-size of the plurality of first through-holes 231.

[0024] The interconnect unit 200 may further include a plurality of first pads 221, a plurality of second pads 222, a first passivation layer 212, and / or a second passivation layer 213. The plurality of first pads 221 are disposed on the underside of the polymer layer 211 and are respectively connected to the underside of a plurality of first through-holes 231. The plurality of second pads 222 are disposed on the upper side of the polymer layer 211 and are respectively connected to the upper side of the plurality of first through-holes 231. The first passivation layer 212 is disposed on the underside of the polymer layer 211 and exposes at least a portion of the plurality of first pads 221. The second passivation layer 213 is disposed on the upper side of the polymer layer 211 and exposes at least a portion of the plurality of second pads 222. For example, the interconnect unit 200 may be a double-layer organic substrate, but the embodiments of this disclosure are not limited thereto. The plurality of second through-holes 232 may be respectively connected to the plurality of first through-holes 231 through the plurality of first pads 221.

[0025] The printed circuit board 500A may also include a plurality of third through vias 133, which penetrate between the upper and lower surfaces of the glass layer 110 in a region spaced apart from the region where the cavity C is provided. The plurality of third through vias 133 may be through-glass vias (TGVs) corresponding to the entire thickness of the glass layer 110. In this case, the minimum pitch between the plurality of first through vias 231 and the minimum pitch between the plurality of second through vias 132 may be smaller than the minimum pitch between the plurality of third through vias 133. Furthermore, the minimum diameter of each of the plurality of first through vias 231 and the minimum diameter of each of the plurality of second through vias 132 may be smaller than the minimum diameter of each of the plurality of third through vias 133. Therefore, electrical paths with micro-pitches and micro-dimensions can be easily provided in a region of the glass layer 110.

[0026] The pitch between multiple through-holes can be the distance between the centerlines of each of two adjacent through-holes, and the minimum pitch between multiple through-holes can be the minimum value among the pitches between multiple through-holes. Furthermore, the diameter of each of the multiple through-holes can be measured on a cross-section taken along the central axis in the thickness direction, and the minimum diameter of each of the multiple through-holes can be the minimum value among the diameters of the multiple through-holes.

[0027] When viewed from above, each of the plurality of second through-holes 132 can penetrate the glass layer 110 in a region of the glass layer 110 overlapping with the cavity C. When viewed from above, each of the plurality of third through-holes 133 can penetrate the glass layer 110 in a region of the glass layer 110 spaced apart from the cavity C, thus making it easy to provide an electrical path with micro-pitch and micro-size in a region of the glass layer 110.

[0028] The printed circuit board 500A may also include a plurality of third pads 123, a plurality of fourth pads 124, and / or a plurality of fifth pads 125. The plurality of third pads 123 are disposed on the lower surface of the glass layer 110 and are respectively connected to the lower side of the second through-hole 132. The plurality of fourth pads 124 are disposed on the upper surface of the glass layer 110 and are respectively connected to the upper side of the third through-hole 133. The plurality of fifth pads 125 are disposed on the lower surface of the glass layer 110 and are respectively connected to the lower side of the third through-hole 133. Therefore, electrical connection reliability can be further improved. If necessary, in addition to the third pads 123, fourth pads 124, and fifth pads 125, a plurality of conductive patterns for various purposes may be formed on the upper and / or lower surface of the glass layer 110.

[0029] The components of the printed circuit board 500A according to the example will be described in more detail below with reference to the accompanying drawings.

[0030] Glass layer 110 may comprise glass (an amorphous solid). The glass may include, for example, pure silica (approximately 100% SiO2), soda-lime glass, borosilicate glass, aluminosilicate glass, etc. However, embodiments of this disclosure are not limited thereto, and alternative glass materials (e.g., fluorine-based glasses, phosphate glasses, chalcogenide glasses, etc.) may also be used. Furthermore, other additives may be included to form a glass with specific physical properties. Such additives may include magnesium, calcium, manganese, aluminum, lead, boron, iron, chromium, potassium, sulfur, and antimony, as well as carbonates (e.g., calcium carbonate (e.g., limestone) and sodium carbonate (e.g., soda ash)) and / or oxides of these elements and other elements. Glass layer 110 may be distinguished from organic insulating materials (e.g., copper-clad laminates (CCL), prepregs (PPG), etc.) that include glass fibers (e.g., glass fabrics, such as glass cloth). For example, glass layer 110 may be a relatively large glass panel (e.g., a glass plate).

[0031] Each of the plurality of second through-vias 132 and the plurality of third through-vias 133 may include a metal. The metal may include copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti), and / or alloys thereof. Preferably, copper (Cu) may be included, but embodiments of this disclosure are not limited thereto. Each of the plurality of second through-vias 132 and the plurality of third through-vias 133 may include a filled via (i.e., a filled VIA) with metal filling the via hole, for example, a glass through-via (TGV). The plurality of second through-vias 132 and the plurality of third through-vias 133 may perform various functions according to design. For example, each of the plurality of second through-vias 132 and the plurality of third through-vias 133 may include a grounding through-via, a power through-via, and a signal through-via. Each of the plurality of second through-vias 132 may have a substantially tapered shape in a cross-section taken along its central axis. Each of the plurality of third through-holes 133 may substantially have an hourglass shape in a cross-section taken along its central axis. Each of the plurality of second through-holes 132 and the plurality of third through-holes 133 may include a sputtered layer as a seed layer and may also include an electroplated layer that substantially fills the via. The sputtered layer may be a multilayer structure comprising a titanium (Ti) layer and a copper (Cu) layer. The electroplated layer may be a copper (Cu) layer formed by electroplating copper. However, embodiments of the present disclosure are not limited thereto, and an electroless layer may be used as a seed layer, and both the sputtered layer and the electroless layer may be formed as seed layers if desired.

[0032] Each of the plurality of third pads 123, the plurality of fourth pads 124, and the plurality of fifth pads 125 may include a metal. The metal may include copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti), and / or alloys thereof. Preferably, copper (Cu) may be included, but embodiments of this disclosure are not limited thereto. Each of the plurality of third pads 123, the plurality of fourth pads 124, and the plurality of fifth pads 125 may perform various functions according to design. For example, it may include a signal pad, a power pad, a ground pad, etc. Each of the plurality of third pads 123, the plurality of fourth pads 124, and the plurality of fifth pads 125 may include a sputtered layer as a seed layer, and may also include an electrolytic plating layer disposed on the seed layer. The sputtered layer may be a multilayer structure including a titanium (Ti) layer and a copper (Cu) layer. The electrolytic plating layer may be a copper (Cu) layer formed by electrolytic copper plating. However, the embodiments disclosed herein are not limited thereto, and an electroless layer can be used as a seed layer, and both the sputtered layer and the electroless layer can be formed as seed layers if desired.

[0033] The polymer layer 211 may include an organic insulating material. The organic insulating material may include thermosetting resins (such as epoxy resins), thermoplastic resins (such as polyimide), or materials comprising inorganic fillers and / or organic fillers, as well as thermosetting resins and / or thermoplastic resins. For example, the polymer layer 211 may include an Ajinomoto laminate (ABF). However, embodiments of this disclosure are not limited thereto, and the organic insulating material may also include glass fibers (such as glass fabrics, for example, glass cloth). For example, the polymer layer 211 may be a copper-clad laminate (CCL), a prepreg (PPG), etc. The polymer layer 211 may be a single layer, but may include multiple layers if desired.

[0034] Each of the first passivation layer 212 and the second passivation layer 213 may comprise a thermosetting resin (such as epoxy resin), a thermoplastic resin (such as polyimide), or a material comprising inorganic fillers and / or organic fillers, as well as thermosetting resins and / or thermoplastic resins. For example, each of the first passivation layer 212 and the second passivation layer 213 may comprise an Ajinomoto deposited film (ABF), solder resist (SR), etc., but embodiments of the present disclosure are not limited thereto. The first passivation layer 212 may expose a plurality of first pads 221, and the second passivation layer 213 may expose a plurality of second pads 222, and, if desired, each of the first passivation layer 212 and the second passivation layer 213 may have a plurality of openings in a solder mask defined (SMD) and / or non-solder mask defined (NSMD) form, but embodiments of the present disclosure are not limited thereto.

[0035] Each of the plurality of first through-holes 231 may include a metal. The metal may include copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti), and / or alloys thereof. Preferably, copper (Cu) may be included, but embodiments of this disclosure are not limited thereto. Each of the plurality of first through-holes 231 may include a filled via (i.e., a filled VIA) in which the metal fills the via. The plurality of first through-holes 231 may perform various functions depending on the design. For example, they may include power through-holes, signal through-holes, etc. Each of the plurality of first through-holes 231 may substantially have an hourglass shape in its cross-section. Each of the plurality of first through-holes 231 may include an electroless plating layer as a seed layer and an electrolytic plating layer that substantially fills the via. The electroless plating layer may include a copper (Cu) layer formed by electroless copper plating, and the electrolytic plating layer may include a copper (Cu) layer formed by electrolytic copper plating. However, the embodiments disclosed herein are not limited thereto, and the sputtered layer may be formed as a seed layer, and both the sputtered layer and the electroless layer may be formed as seed layers if desired.

[0036] Each of the plurality of first pads 221 and the plurality of second pads 222 may include a metal. The metal may include copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti), and / or alloys thereof. Preferably, copper (Cu) may be included, but embodiments of this disclosure are not limited thereto. Each of the plurality of first pads 221 and the plurality of second pads 222 may perform various functions according to design. For example, it may include a signal pad, a power pad, etc. Each of the plurality of first pads 221 and the plurality of second pads 222 may include an electroless plating layer as a seed layer, and may include an electrolytic plating layer formed on the seed layer. The electroless plating layer may include a copper (Cu) layer formed by electroless copper plating, and the electrolytic plating layer may include a copper (Cu) layer formed by electrolytic copper plating. However, embodiments of this disclosure are not limited thereto, and a sputtered layer may be formed as a seed layer, and both the sputtered layer and the electroless plating layer may be formed as seed layers if desired.

[0037] Adhesive layer 250 may include an adhesive. The adhesive may include epoxy resin, silicone resin, polyimide, acrylic resin and / or polyurethane. For example, adhesive layer 250 may include a bare film attachment (DAF).

[0038] Figure 3 It shows the manufacturing process. Figure 2 The process diagram of the printed circuit board shown is a schematic diagram.

[0039] Reference Figure 3First, a glass layer 110 can be prepared. The glass layer 110 can be a relatively large panel shape (e.g., a glass plate), but embodiments of this disclosure are not limited thereto. Subsequently, a cavity C with a blind shape can be formed in the glass layer 110, the cavity C having a bottom surface. The cavity C can be formed by processes such as wet etching, dry etching, laser processing, and / or injection molding. The bottom surface of the cavity C can be formed in the thickness direction at approximately half the thickness of the glass layer 110. Subsequently, interconnect units 200 manufactured by separate substrate processes can be embedded. For example, an adhesive layer 250 can be used to attach the interconnect units 200 to the bottom surface of the cavity C. Subsequently, a plurality of via holes V can be formed in the underside of the cavity C, penetrating both the glass layer 110 and the adhesive layer 250. The plurality of via holes V can be formed by laser processing and etching processes. When the plurality of via holes V are formed, a plurality of first pads 221 can be used as stop layers. Subsequently, a plurality of second through-holes 132 can be formed by filling the plurality of via holes V with metal. Furthermore, a plurality of third pads 123, respectively connected to a plurality of second through-holes 132, can be formed on the lower surface of the glass layer 110. The plurality of second through-holes 132 and the plurality of third pads 123 can be formed by sputtering and electroplating, and electroless plating can also be used if desired. Subsequently, a plurality of third through-holes 133 can be formed in the glass layer 110, and a plurality of fourth pads 124 and a plurality of fifth pads 125 can be formed on the glass layer 110. The vias for forming the plurality of third through-holes 133 can also be formed by laser processing and etching processes. The plurality of third through-holes 133, as well as the plurality of fourth pads 124 and the plurality of fifth pads 125, can also be formed by sputtering and electroplating, and electroless plating can also be used if desired. When the plurality of fifth pads 125 are formed, the plurality of third pads 123 can also be formed.

[0040] The printed circuit board 500A according to the above example can be manufactured through a series of processes, and other aspects are substantially the same as those described above.

[0041] Figure 4 It is shown Figure 2 A cross-sectional view of a variant example of the printed circuit board shown.

[0042] Reference Figure 4The printed circuit board 500B according to the variant example can be implemented as a multilayer printed circuit board structure with a double-sided stacked shape, including the printed circuit board 500A according to the above example as the core structure (i.e., including the glass layer 110 according to the above example as the glass core). For example, the printed circuit board 500B may include: a glass layer 110, as the glass core 110; a first stacked structure 310 disposed on the upper side of the glass core 110; and a second stacked structure 320 disposed on the lower side of the glass core 110. If desired, the printed circuit board 500B may also include a first resist layer 331 disposed on the first stacked structure 310, a second resist layer 332 disposed on the second stacked structure 320, a plurality of first electrical connection metals 341 respectively disposed in a first opening of the first resist layer 331 and / or a plurality of second electrical connection metals 342 respectively disposed in a second opening of the second resist layer 332.

[0043] Since the printed circuit board 500B, as described above, includes the printed circuit board 500A as a core structure, it can include the same technical effects described with respect to the printed circuit board 500A. For example, it can have a relatively large body, allowing for easy warpage control, and improving signal and / or power characteristics by enhancing signal and / or power paths. Therefore, applications on large-area substrates for servers can be easily implemented. Furthermore, due to reduced signal loss, the design freedom and flexibility of the second stacked structure 320 disposed on the underside of the core structure can be improved.

[0044] In the following text, reference will be made to Figure 4 The components of the printed circuit board 500B according to the variant example are described in more detail.

[0045] The first stacked structure 310 may include a plurality of first insulating layers 311 stacked on the upper surface of the glass layer 110, a plurality of first wiring layers 312 respectively disposed on and / or in the plurality of first insulating layers 311, and a plurality of first via layers 313 respectively disposed in the plurality of first insulating layers 311. The first stacked structure 310 (more specifically, the first insulating layer 311 disposed on the lowest side of the plurality of first insulating layers 311) may cover at least a portion of the interconnect unit 200 and may fill at least a portion of the space of cavity C not occupied by the interconnect unit 200. The second stacked structure 320 may include a plurality of second insulating layers 321 stacked on the lower surface of the glass layer 110, a plurality of second wiring layers 322 respectively disposed on and / or in the plurality of second insulating layers 321, and a plurality of second via layers 323 respectively disposed in the second insulating layers 321.

[0046] Each of the plurality of first insulating layers 311 and the plurality of second insulating layers 321 may be a stacked insulating layer and may include thermosetting resins (such as epoxy resins), thermoplastic resins (such as polyimide), or materials including inorganic fillers, organic fillers, and / or glass fibers (such as glass fabrics, exemplified by glass cloth) and thermosetting and / or thermoplastic resins. For example, each of the plurality of first insulating layers 311 and the plurality of second insulating layers 321 may be prepreg (PPG), Ajinomoto laminated film (ABF), etc., but the embodiments of this disclosure are not limited thereto. The plurality of first insulating layers 311 and the plurality of second insulating layers 321 may have substantially the same material, but the embodiments of this disclosure are not limited thereto. The plurality of first insulating layers 311 and the plurality of second insulating layers 321 may have the same number of layers, but the embodiments of this disclosure are not limited thereto.

[0047] Each of the plurality of first wiring layers 312 and the plurality of second wiring layers 322 may be a stacked wiring layer and may include metal. Metals may include copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti), and / or alloys thereof. Preferably, copper (Cu) may be included, but embodiments of this disclosure are not limited thereto. Each of the plurality of first wiring layers 312 and the plurality of second wiring layers 322 may perform various functions according to design. For example, it may include signal patterns, power patterns, ground patterns, etc. Patterns may have various shapes such as lines, planes, pads, etc. Each of the plurality of first wiring layers 312 and the plurality of second wiring layers 322 may include a seed layer and a plating layer. The seed layer may be formed by chemical plating (e.g., chemical copper plating), or, if desired, by a sputtering process. Optionally, both chemical plating and sputtering processes may be used. The plating layer may be formed by electrolytic plating (e.g., electrolytic copper plating). If desired, copper foil may also be included.

[0048] Each of the plurality of first via layers 313 and the plurality of second via layers 323 may be a stacked via layer and may include a metal. The metal may include copper (Cu), aluminum (Al), silver (Ag), tin (Sn), gold (Au), nickel (Ni), lead (Pb), titanium (Ti), and / or alloys thereof. Preferably, copper (Cu) may be included, but embodiments of this disclosure are not limited thereto. The plurality of first via layers 313 may include a plurality of connection vias penetrating at least a portion of the plurality of first insulating layers 311, thereby providing electrical connection paths in the plurality of first insulating layers 311, and the plurality of second via layers 323 may include a plurality of connection vias penetrating at least a portion of the plurality of second insulating layers 321, thereby providing electrical connection paths in the plurality of second insulating layers 321. Each of the plurality of connection vias may perform various functions according to design. For example, it may include signal connection vias, power connection vias, ground connection vias, etc. The plurality of connection vias may include filled vias (filled VIAs) with metal filling the via holes, and may also include conformal vias (conformal VIAs) with metal disposed along the wall surface of the via holes. Each of the plurality of connection vias may have a substantially tapered shape in a cross-section taken along its central axis. For example, the plurality of connection vias of the plurality of first via layers 313 may have a tapered shape in a cross-section taken along its central axis with an upper width greater than a lower width. Furthermore, the plurality of connection vias of the plurality of second via layers 323 may have a tapered shape in a cross-section taken along its central axis with a lower width greater than an upper width. Seed layers included in the plurality of first via layers 313 and the plurality of second via layers 323 may be integrated with seed layers included in the plurality of first wiring layers 312 and the plurality of second wiring layers 322, and plating included in the plurality of first via layers 313 and the plurality of second via layers 323 may be integrated with plating included in the plurality of first wiring layers 312 and the plurality of second wiring layers 322.

[0049] Both the first resist layer 331 and the second resist layer 332 may comprise a thermosetting resin (such as epoxy resin), a thermoplastic resin (such as polyimide), or a material comprising inorganic fillers and / or organic fillers, as well as thermosetting resins and / or thermoplastic resins. For example, the first resist layer 331 and the second resist layer 332 may be an Ajinomoto deposited film (ABF), solder resist (SR), etc., but the embodiments of this disclosure are not limited thereto. A plurality of first openings and a plurality of second openings may be formed in the first resist layer 331 and the second resist layer 332, respectively. In this case, the pad pattern of the uppermost first wiring layer 312 exposed through the plurality of first openings and the pad pattern of the lowermost second wiring layer 322 exposed through the plurality of second openings may be solder mask defined (SMD) shapes and / or non-solder mask defined (NSMD) shapes, but the embodiments of this disclosure are not limited thereto.

[0050] A plurality of first electrical connection metals 341 may be connected to a pad pattern exposed through a plurality of first openings on the uppermost first wiring layer 312, and a plurality of second electrical connection metals 342 may be connected to a pad pattern exposed through a plurality of second openings on the lowermost second wiring layer 322. The plurality of first electrical connection metals 341 and the plurality of second electrical connection metals 342 may be formed using a low-melting-point metal, such as solder (e.g., tin (Sn)-aluminum (Al)-copper (Cu)), but embodiments of this disclosure are not limited thereto, and the materials are not particularly limited thereto. Each of the plurality of first electrical connection metals 341 and the plurality of second electrical connection metals 342 may be a ball, a pin, etc. The plurality of first electrical connection metals 341 and the plurality of second electrical connection metals 342 may be formed as a plurality of layers or as a single integrated layer. When formed as a plurality of layers, copper pillars and solder may be included, and when formed as a single layer, tin-silver solder may be included, but embodiments of this disclosure are not limited thereto.

[0051] Multiple semiconductor chips can be mounted on a first resist layer 331 via multiple first electrical connection metals 341. The multiple semiconductor chips may include an integrated circuit (IC) die with hundreds to millions of components integrated into a single chip. The integrated circuit may be, for example, an application processor (AP) chip (such as a central processing unit (e.g., CPU), a graphics processing unit (e.g., GPU), a field-programmable gate array (FPGA), a digital signal processor, a cryptographic processor, a microprocessor, a microcontroller, etc.), a logic chip (such as an analog-to-digital converter, an application-specific integrated circuit (ASIC), etc.), etc., but embodiments of this disclosure are not limited thereto, and may be memory chips (such as volatile memory (e.g., DRAM), non-volatile memory (e.g., ROM or flash memory), high-bandwidth memory (HBM)) or other types of chips such as photonic integrated circuits (PIC).

[0052] Other content is substantially the same as that described regarding the printed circuit board 500A according to the above example and its manufacturing example.

[0053] Figure 5 This is a cross-sectional view showing another example of a printed circuit board according to an embodiment.

[0054] Unlike the printed circuit board 500A described in the example above, refer to Figure 5According to another example, the printed circuit board 500C may also include an electronic component 410 embedded in the glass layer 110. The electronic component 410 can be implemented as various types of active and / or passive components. Therefore, a variety of technologies required for next-generation semiconductors can be provided. The electronic component 410 may have a plurality of solder pads 412. The plurality of solder pads 412 may be connected to a plurality of metal patterns 126 respectively via a plurality of metal vias 135. The electronic component 410 may be directly embedded in the glass layer 110, but embodiments of the present disclosure are not limited thereto, and the electronic component 410 may be disposed in a cavity additionally formed in the glass layer 110. The plurality of metal vias 135 and the plurality of metal patterns 126 may be formed in the glass layer 110, but embodiments of the present disclosure are not limited thereto, and the plurality of metal vias 135 may additionally be formed in an insulating material filling the formed cavity. The number of electronic components 410 is not limited to any specific example, and a necessary number of electronic components 410 may be embedded in the glass layer 110.

[0055] The other content is essentially the same as that described regarding the manufacturing examples of printed circuit boards 500A and 500B, and printed circuit board 500A.

[0056] Figure 6 It is shown Figure 5 A cross-sectional view of a variant example of the printed circuit board shown.

[0057] Unlike the printed circuit board 500B described above according to the variant example, refer to Figure 6 According to a variant example, the printed circuit board 500D may also include an electronic component 410 embedded in the glass layer 110. The electronic component 410 may be connected to a first stacked structure 310 and / or a second stacked structure 320, depending on its embedding location. For example, the electronic component 410 may be electrically connected to at least a portion of a plurality of first via layers 313 and / or electrically connected to at least a portion of a plurality of second via layers 323 to at least a portion of a plurality of second wiring layers 322.

[0058] Other contents are substantially the same as those described in the manufacturing examples of printed circuit boards 500A, 500B, and 500C, as well as printed circuit board 500A.

[0059] Figure 7 This is a cross-sectional view showing another example of a printed circuit board according to an embodiment.

[0060] Unlike the printed circuit board 500A described in the example above, refer to Figure 7In a printed circuit board 500E according to another example, the interconnect unit 200' may not include multiple second pads. Furthermore, multiple third pads may not be provided on the lower surface of the glass layer 110. For example, multiple second pads and multiple third pads may not be provided. For example, a landless area of ​​the glass layer 110 providing electrical paths with micro-pitch and micro-size can be implemented, thereby providing electrical paths with micro-pitch and micro-size, thereby further improving signal characteristics and / or power characteristics.

[0061] Other descriptions are substantially the same as those described in the manufacturing examples of printed circuit boards 500A, 500B, 500C, and 500D, as well as printed circuit board 500A.

[0062] Figure 8 It is shown Figure 7 A cross-sectional view of a variant example of the printed circuit board shown.

[0063] Unlike the printed circuit board 500B described above according to the variant example, refer to Figure 8 In the printed circuit board 500F according to the variant example, the interconnect unit 200' may not include a plurality of second pads. Furthermore, a plurality of third pads may not be provided on the lower surface of the glass layer 110. For example, a plurality of second pads and a plurality of third pads may not be provided. Therefore, the lowermost first via layer 313 of the plurality of first via layers 313 may include a plurality of first connection vias that are directly connected to the upper side of the plurality of first through vias 231. Furthermore, the uppermost second via layer 323 of the plurality of second via layers 323 may include a plurality of second connection vias that are directly connected to the lower side of the plurality of second through vias 132. Each of the plurality of first connection vias may further penetrate the second passivation layer 213, so that the plurality of first connection vias may directly contact the plurality of first through vias 231 respectively.

[0064] Other contents are substantially the same as those described in the manufacturing examples of printed circuit boards 500A, 500B, 500C, 500D and 500E, as well as printed circuit board 500A.

[0065] According to the foregoing embodiments, a printed circuit board may be provided, which may have a relatively large body, can easily perform warp control, and can improve signal and / or power characteristics by improving signal and / or power paths.

[0066] Thickness, width, length, pitch, depth, etc., can be measured using a scanning electron microscope or optical microscope based on a polished or cut cross-section of a printed circuit board. The cross-section can be vertical or horizontal, and each value can be measured based on the desired cross-section. When the measured value of one of the thickness, width, length, pitch, depth, etc., is not constant, its value can be determined as the average of the values ​​measured at any five points. The upper and / or lower width of a via can be measured on a cross-section taken along the central axis in the thickness direction. The depth of a via can be the distance from the upper to the lower end of the via on a cross-section taken along the central axis in the thickness direction.

[0067] In this disclosure, the term "coverage" can include complete coverage and partial coverage, and may also include direct coverage and indirect coverage. Furthermore, the term "fill" can include complete filling and partial filling (e.g., the presence of some gaps or voids).

[0068] In this disclosure, "substantially" can be a concept that includes process errors, positional deviations, and measurement errors that occur during the manufacturing process. For example, the concept that line widths, distances, thicknesses, and heights are substantially the same can include cases where elements are numerically identical or have similar values. Furthermore, the concept of "substantially having a particular shape" can include cases where the element has exactly such a shape or cases where the element has approximately such a shape.

[0069] In this disclosure, "the same insulating material" can refer not only to insulating materials that are completely identical in material, but also to insulating materials of the same type. Therefore, the composition of the insulating materials can be substantially the same, but their specific composition ratios can be slightly different.

[0070] In this disclosure, "section" may refer to the cross-sectional shape when an object is cut vertically, or the cross-sectional shape when the object is viewed from a side view. Furthermore, "plane" may refer to the planar shape when an object is cut horizontally, or the planar shape when the object is viewed from a top or bottom view.

[0071] For ease of description, the term "lower" in the terms "lower side," "lower part," "lower surface," etc., may refer to the downward direction of the cross-section in the reference drawing; the term "upper" in the terms "upper side," "upper part," "upper surface," etc., may refer to the upward direction of the cross-section in the reference drawing; and the term "side" in the terms "side part," "side surface," etc., may refer to the lateral direction of the cross-section in the reference drawing, perpendicular to the upward and downward directions. However, for ease of description, the terms may be defined as above, and the scope of the claims is not particularly limited to the aforementioned terms.

[0072] In this disclosure, the term "connection" can refer not only to "direct connection" but also to "indirect connection" via adhesive layers or the like. Furthermore, the term "electrical connection" can include both cases where elements are "physically connected" and cases where elements are "not physically connected." Additionally, the terms "first," "second," etc., can be used to distinguish one element from other elements and do not limit the order and / or importance associated with the elements. In some cases, without departing from the scope of the claims, a first element may be referred to as a second element, and similarly, a second element may be referred to as a first element.

[0073] In this disclosure, the term "embodiment" may not refer to the same embodiment, but is provided to describe and emphasize the unique features of different embodiments. The possibility of combining features of the above-suggested embodiments with those of other embodiments is not excluded. For example, unless otherwise stated, even if a feature described in one embodiment is not described in other embodiments, such feature may be understood to be relevant to other embodiments.

[0074] Unless the singular form of an expression has a distinctly different meaning in the context, the singular form of an expression covers the plural form.

[0075] While embodiments have been shown and described above, it will be readily understood by those skilled in the art that modifications and variations may be made without departing from the scope of this disclosure as defined by the appended claims.

Claims

1. A printed circuit board comprising: a glass layer; a cavity through a portion of the glass layer from an upper surface of the glass layer; an interconnect unit including at least a portion disposed in the cavity and including a polymer layer and a plurality of first through-holes each through the polymer layer; and a plurality of second through-holes each through the glass layer from a lower surface of the glass layer to a bottom surface of the cavity, wherein the plurality of first through-holes are respectively connected to the plurality of second through-holes.

2. The printed circuit board of claim 1, wherein the interconnect unit is attached to the bottom surface of the cavity by an adhesive layer, and wherein the plurality of second through-holes are each further through the adhesive layer.

3. The printed circuit board of claim 2, wherein, each of the plurality of second through-holes has a tapered shape with a lower end width greater than an upper end width in a cross-section taken along a central axis thereof.

4. The printed circuit board of claim 1, wherein the interconnect unit further includes a plurality of first pads disposed on an underside of the polymer layer and respectively connected to an underside of the plurality of first through-holes, and wherein the plurality of second through-holes are respectively connected to the plurality of first through-holes by the plurality of first pads.

5. The printed circuit board of claim 4, wherein, the interconnect unit further includes a plurality of second pads disposed on an upper side of the polymer layer and respectively connected to an upper side of the plurality of first through-holes.

6. The printed circuit board of claim 4, further comprising: a plurality of third pads disposed on a lower surface of the glass layer and respectively connected to an underside of the plurality of second through-holes.

7. The printed circuit board of claim 4, further comprising: a plurality of third through-holes each through the glass layer between the upper surface and the lower surface of the glass layer in a region of the glass layer spaced apart from a region in which the cavity is disposed.

8. The printed circuit board of claim 7, wherein a minimum pitch between the plurality of first through-holes and a minimum pitch between the plurality of second through-holes are less than a minimum pitch between the plurality of third through-holes, and wherein a minimum diameter of each of the plurality of first through-holes and a minimum diameter of each of the plurality of second through-holes are less than a minimum diameter of each of the plurality of third through-holes.

9. The printed circuit board of claim 7, further comprising: a plurality of fourth pads disposed on an upper surface of the glass layer and respectively connected to an upper side of the plurality of third through-holes; and a plurality of fifth pads disposed on a lower surface of the glass layer and respectively connected to an underside of the plurality of third through-holes.

10. The printed circuit board of claim 1, further comprising: a first build-up structure disposed on the upper surface of the glass layer; and a second build-up structure disposed on the lower surface of the glass layer, The first accumulation structure includes a plurality of first insulating layers stacked on the upper surface of the glass layer, a plurality of first wiring layers respectively provided on and / or in the plurality of first insulating layers, and a plurality of first via layers respectively provided in the plurality of first insulating layers, The second accumulation structure includes a plurality of second insulating layers stacked on the lower surface of the glass layer, a plurality of second wiring layers respectively provided on and / or in the plurality of second insulating layers, and a plurality of second via layers respectively provided in the plurality of second insulating layers.

11. The printed circuit board of claim 10, wherein In the plurality of first via layers, a first via layer disposed at a lowermost side includes a plurality of first connection vias respectively directly connected to upper sides of the plurality of first through vias, In the plurality of second via layers, a second via layer disposed at an uppermost side includes a plurality of second connection vias respectively directly connected to lower sides of the plurality of second through vias, The interconnection unit further includes first and second passivation layers respectively disposed on lower and upper surfaces of the polymer layer, and The plurality of first connection vias respectively further penetrate the second passivation layer.

12. The printed circuit board of claim 10, further comprising: an electronic component embedded in the glass layer, The electronic component is electrically connected to at least a portion of the plurality of first wiring layers through at least a portion of the plurality of first via layers and / or electrically connected to at least a portion of the plurality of second wiring layers through at least a portion of the plurality of second via layers.

13. The printed circuit board of claim 1, wherein The cavities and the interconnection units are each provided as a plurality, and The plurality of interconnection units are respectively disposed in the plurality of cavities, or at least two of the plurality of interconnection units are disposed in one of the plurality of cavities.

14. A printed circuit board, comprising: a glass core having a blind cavity; an interconnection unit having at least a portion disposed in the blind cavity; a plurality of second through vias each penetrating a region of the glass core overlaid with the blind cavity when the glass core is viewed from above; a plurality of third through vias each penetrating a region of the glass core spaced apart from the blind cavity when the glass core is viewed from above; a first accumulation structure disposed at an upper side of the glass core and including a plurality of first wiring layers; and a second accumulation structure disposed at a lower side of the glass core and including a plurality of second wiring layers.

15. The printed circuit board of claim 14, a minimum pitch between the plurality of second through vias is smaller than a minimum pitch between the plurality of third through vias, and wherein, a minimum diameter of each of the plurality of second through vias is smaller than a minimum diameter of each of the plurality of third through vias.

16. The printed circuit board of claim 14, ​ wherein, The blind cavity penetrates a portion of the glass core from an upper surface toward a lower surface of the glass core, and wherein the first buildup structure covers at least a portion of the interconnect unit and fills at least a portion of a space of the blind cavity not occupied by the interconnect unit.

17. The printed circuit board of claim 14, wherein, the interconnect unit includes a plurality of first through-holes, wherein the plurality of first through-holes are respectively connected to the plurality of second through-holes, wherein at least a portion of the plurality of first wiring layers and at least a portion of the plurality of second wiring layers are electrically connected to each other through at least a portion of the plurality of first through-holes and at least a portion of the plurality of second through-holes.

18. A printed circuit board, comprising: a glass layer having a top surface and a bottom surface; a cavity penetrating only a portion of the glass layer from the top surface of the glass layer; an adhesive layer disposed on a bottom surface of the cavity; and a through-hole penetrating the glass layer from the bottom surface of the glass layer to the bottom surface of the cavity and extending into the cavity, and further penetrating the adhesive layer.

19. The printed circuit board of claim 18, further comprising an interconnect unit at least partially disposed inside the cavity and secured by the adhesive layer. the interconnect unit includes a polymer layer and a through-hole penetrating the polymer layer.

20. The printed circuit board of claim 19, wherein, a position of the through-hole within the cavity is aligned with a position of the through-hole such that the through-hole and the through-hole are connected to form an electrical path between a top surface of the interconnect unit and the bottom surface of the glass layer.

21. The printed circuit board of claim 20, wherein, 22. The printed circuit board of claim 18, further comprising a glass through-hole penetrating the glass layer between the top surface and the bottom surface of the glass layer, the glass through-hole disposed in a region of the glass layer spaced apart from the cavity. ​

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