Isolation device

Abstract

The invention discloses an isolation device. The isolation device comprises a circuit board; the annular magnetic core is completely embedded in the insulating medium; the first signal coil and the second signal coil are arranged around the annular magnetic core; the first signal coil comprises a first pattern part formed on the first conductive pattern layer, a second pattern part formed on the second conductive pattern layer and a first conductive via hole for connecting the first pattern part and the second pattern part; the second signal coil comprises a third pattern part formed on the first conductive pattern layer, a fourth pattern part formed on the second conductive pattern layer and a second conductive via hole for connecting the third pattern part and the fourth pattern part; the first pattern part and the third pattern part are located in different areas, and the second pattern part and the fourth pattern part are located in different areas; terminals of the first signal coil and the second signal coil are respectively led out from the corresponding pattern parts and are electrically connected to the bottom layer of the circuit board, and all space paths between the first signal coil and the second signal coil are separated by the insulating dielectric layer, so that complete isolation of an input side circuit and an output side circuit is realized.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of integrated circuits, and in particular to an isolation device. BACKGROUND

[0002] New energy vehicles and industrial data centers have an increasing demand for isolation packaging devices, and there are increasingly high requirements for the isolation ability and speed optimization of the isolation packaging devices. Power transistors need to use an isolator for driving, and the function of the isolator is to turn on and turn off the power device to reduce the loss. The existing isolation packaging devices mostly rely on photosensitive or capacitors to achieve isolation, and the photoelectric isolation sensitivity is not enough and the speed is low, and the capacitor isolation brings parasitic capacitance and is easy to break down.

[0003] At present, advanced signal isolation devices mostly use substrate integrated packaging technology, and the integrated circuit dies of the input side and the output side are integrated on a ceramic or organic substrate through wire bonding or flip-chip bonding, and are entirely covered in plastic packaging material. Such a structure has the advantages of small size, high integration, good thermal mechanical reliability, etc., and can be widely applied in the fields of industrial communication, power management, etc. However, due to factors such as substrate wiring density, chip edge electric field concentration, and plastic encapsulation internal micropores, the electrical isolation ability between the input and the output is usually only up to 2kV to 3kV of direct current. Although improvements are made by increasing isolation grooves or introducing high dielectric materials, it still faces great challenges to stably achieve an insulation level of 5kV or above of direct current, especially in high temperature and high humidity or high common mode transient interference environments, the isolation reliability significantly decreases. SUMMARY

[0004] The present application aims to at least solve one of the technical problems existing in the prior art. To this end, the present application proposes an isolation device, which realizes the complete isolation of the input side and the output side circuits in the physical space by constructing a full-embedded magnetic coupling structure inside a multi-layer circuit board, and can stably realize an isolation withstand voltage of 8kV of direct current.

[0005] According to an embodiment of the present application, an isolation device comprises: a circuit board, which is formed by alternately laminating a plurality of conductive pattern layers and a plurality of insulating medium layers, and at least comprises a first conductive pattern layer and a second conductive pattern layer, and a single layer or multiple layers of insulating medium are arranged between adjacent conductive pattern layers; a ring-shaped magnetic core, which is completely embedded in the single layer or multiple layers of insulating medium; a first signal coil and a second signal coil, which are both arranged around the center hole of the ring-shaped magnetic core and are not electrically connected to each other; the first signal coil comprises a first pattern part formed on the first conductive pattern layer, a second pattern part formed on the second conductive pattern layer, and a first conductive via hole connecting the first pattern part and the second pattern part; the second signal coil comprises a third pattern part formed on the first conductive pattern layer, a fourth pattern part formed on the second conductive pattern layer, and a second conductive via hole connecting the third pattern part and the fourth pattern part; wherein the first pattern part and the third pattern part are located in different regions of the first conductive pattern layer, and the second pattern part and the fourth pattern part are located in different regions of the second conductive pattern layer; the terminals of the first signal coil and the second signal coil are respectively led out from the corresponding pattern parts and electrically connected to the connection area of the bottom layer of the circuit board, and all the space paths between the first signal coil and the second signal coil are interrupted by the insulating medium layers to achieve electrical isolation.

[0006] Compared with the prior art isolating device adopting substrate integration and surface packaging process, the input side and the output side circuit are completely isolated in physical space by constructing the full-buried magnetic coupling structure inside the multilayer circuit board.

[0007] According to some embodiments of the present application, the first pattern part and the third pattern part both extend around the center hole of the ring-shaped magnetic core and are separated from each other in the circumferential direction in the plane of the first conductive pattern layer, and respectively occupy different sector regions of the outer periphery of the ring-shaped magnetic core; and the second pattern part and the fourth pattern part both extend around the center hole of the ring-shaped magnetic core and are separated from each other in the circumferential direction in the plane of the second conductive pattern layer, and respectively occupy different sector regions of the outer periphery of the ring-shaped magnetic core.

[0008] According to some embodiments of the present application, the connection region includes a first connection region and a second connection region isolated from each other, and the first connection region and the second connection region are respectively arranged on opposite sides of the circuit board bottom layer in the horizontal direction; the terminal of the first signal coil is electrically connected to at least one pad of the first connection region, and the terminal of the second signal coil is electrically connected to at least one pad of the second connection region; with the center of the annular magnetic core as a reference, the main winding of the first signal coil is located in the left side region of the annular magnetic core, and the first connection region is arranged on the left side of the circuit board bottom layer; the main winding of the second signal coil is located in the right side region of the annular magnetic core, and the second connection region is arranged on the right side of the circuit board bottom layer; wherein the first connection region and the second connection region each include a plurality of pads for respectively accessing input side signals and output side signals.

[0009] According to some embodiments of the present application, the connection region includes a first connection region and a second connection region isolated from each other, and the first connection region and the second connection region are respectively arranged on opposite sides of the circuit board bottom layer in the horizontal direction; the circuit board further includes a third conductive pattern layer located above the first conductive pattern layer and the second conductive pattern layer and isolated therefrom by the insulating medium layer; the third conductive pattern layer includes a fifth pattern part and a sixth pattern part isolated from each other; the first signal coil has a first end and a second end, the first end is electrically connected to a first pad of the first connection region, and the second end is electrically connected to a second pad of the first connection region; the fifth pattern part is simultaneously electrically connected to the first end and the first pad through a third conductive via and is simultaneously electrically connected to the second end and the second pad through a fourth conductive via; the second signal coil has a third end and a fourth end, the third end is electrically connected to a third pad of the second connection region, and the fourth end is electrically connected to a fourth pad of the second connection region; the sixth pattern part is simultaneously electrically connected to the third end and the third pad through a fifth conductive via and is simultaneously electrically connected to the fourth end and the fourth pad through a sixth conductive via.

[0010] According to some embodiments of the present application, further including an input side chip and an output side chip, the input side chip is electrically connected to the fifth pattern part for driving the first signal coil, and the output side chip is electrically connected to the sixth pattern part for receiving the output signal of the second signal coil; wherein a first dispensing layer is formed around the pins of the input side chip, and the first dispensing layer covers the pins of the input side chip and the adjacent fifth pattern part region; a second dispensing layer is formed around the pins of the output side chip, and the second dispensing layer covers the pins of the output side chip and the adjacent sixth pattern part region.

[0011] According to some embodiments of the present application, the plastic package is formed by an insulating plastic material, and completely covers the top layer of the circuit board to seal the exposed conductive structures of the input-side chip, the output-side chip, the fifth patterned portion and the sixth patterned portion of the top layer of the circuit board in the plastic package.

[0012] According to some embodiments of the present application, the connecting region includes a plurality of pads, at least some of which extend to the edge of the circuit board; a depth-controlled half-hole is provided on the pad extending to the edge of the circuit board, the depth-controlled half-hole is located at the region of the pad close to the edge of the circuit board and is exposed to the side edge of the circuit board; the depth of the depth-controlled half-hole is less than the total thickness of the circuit board, and the hole wall and the hole bottom of the depth-controlled half-hole are both metallized surfaces, so that the exposed side wall formed by the depth-controlled half-hole at the side edge of the circuit board is a continuous conductive surface.

[0013] According to some embodiments of the present application, a conductive via is further provided on the pad extending to the edge of the circuit board, the conductive via is located on the side of the depth-controlled half-hole facing the center of the circuit board and extends from the surface of the pad to the inside of the circuit board to electrically connect with the conductive structure of the inner layer; wherein the conductive via has a metallized hole wall and an insulating resin body filled therein, and the top of the conductive via is flush with the surface of the pad.

[0014] According to some embodiments of the present application, the depth-controlled half-hole does not have a metal cover at the outermost edge of the circuit board, and the metallized surfaces of the hole wall and the hole bottom of the depth-controlled half-hole terminate at the inner side of the outermost edge of the circuit board, exposing the insulating medium layer; the conductive part of the depth-controlled half-hole is separated from the outermost surface of the circuit board by the insulating medium layer, forming a non-conductive edge isolation region.

[0015] According to some embodiments of the present application, the circuit board is provided with a stepped profile adjacent to the side edge of the bottom layer, the stepped profile is composed of a vertical side wall surface and a horizontal bottom surface connected to the outer edge of the bottom; the depth-controlled half-hole penetrates the pad and extends to the vertical side wall surface, and does not extend to the horizontal bottom surface.

[0016] Additional aspects and advantages of the present application will be made apparent from the following description, which, taken in conjunction with the accompanying drawings, which are shown by way of illustration. BRIEF DESCRIPTION OF DRAWINGS

[0017] The above and / or additional aspects and advantages of the present application will become apparent and be readily understood from the following description, taken in conjunction with the accompanying drawings, in which: Figure 1 is a structural schematic diagram of the first perspective view of the isolation device according to an embodiment of the present application; Figure 2This is a schematic diagram of the isolation device from a second perspective according to an embodiment of the present invention; Figure 3 This is a schematic diagram of the internal structure of the isolation device without insulating medium according to an embodiment of the present invention. Figure 1 ; Figure 4 This is a schematic diagram of the internal structure of the isolation device without insulating medium according to an embodiment of the present invention. Figure 2 ; Figure 5 This is a schematic diagram of the internal structure of the isolation device without insulating medium according to an embodiment of the present invention. Figure 3 ; Figure 6 This is a frame diagram of the input and output circuits of the isolation device according to an embodiment of the present invention; Figure 7 This is a schematic diagram of the internal structure of an isolation device with an insulating medium according to an embodiment of the present invention. Figure 1 ; Figure 8 This is a schematic diagram of the internal structure of an isolation device with an insulating medium according to an embodiment of the present invention. Figure 2 ; Figure 9 This is a schematic diagram of the structure of the isolation device with a plastic encapsulation according to an embodiment of the present invention; Figure 10 This is a schematic diagram of the structure of the isolation device without a plastic encapsulation according to an embodiment of the present invention; Figure 11 This is a third-view structural schematic diagram of an isolation device according to an embodiment of the present invention; Figure 12 yes Figure 11 An enlarged schematic diagram of point A in the diagram.

[0018] Figure label: 1. Circuit board; 11. Insulating dielectric layer; 12. First conductive pattern layer; 13. Second conductive pattern layer; 14. Third conductive pattern layer; 15. Fifth pattern section; 16. Sixth pattern section; 17. Third conductive via; 18. Fourth conductive via; 19. Fifth conductive via; 20. Sixth conductive via; 2. Ring core; 3. First signal coil; 31. First pattern section; 32. Second pattern section; 33. First conductive via; 34. First end; 35. Second end; 4. Second signal coil; 41. Third pattern layer 42. Fourth graphic part; 43. Second conductive via; 44. Third end; 45. Fourth end; 5. First connection area; 51. First pad; 52. Second pad; 53. Controlled depth half-hole; 54. Conductive through-hole; 55. Edge isolation area; 56. Stepped profile; 5601. Vertical sidewall; 5602. Horizontal bottom surface; 6. Second connection area; 61. Third pad; 62. Fourth pad; 7. Input side chip; 71. First adhesive layer; 8. Output side chip; 9. Molded package; 10. Solder resist layer. Detailed Implementation

[0019] The embodiments of the present invention are described in detail below. The embodiments described with reference to the accompanying drawings are exemplary. The embodiments of the present invention are described in detail below.

[0020] The following is for reference. Figures 1-12 An isolation device according to an embodiment of the present invention is described. For example... Figures 1-6 As shown, this invention proposes a fully embedded magnetic isolation device structure based on a multilayer printed circuit board. The isolation device in this embodiment includes: a circuit board 1, a toroidal magnetic core 2, a first signal coil 3, and a second signal coil 4. The circuit board 1 is formed by alternating lamination of multiple conductive pattern layers and multiple insulating dielectric layers 11, with a single or multiple insulating dielectric layer between adjacent conductive pattern layers, including at least a first conductive pattern layer 12 and a second conductive pattern layer 13. The toroidal magnetic core 2 is completely embedded in the single or multiple insulating dielectric layer. The first signal coil 3 and the second signal coil 4 are both arranged around the central hole of the toroidal magnetic core 2 and are not electrically connected to each other.

[0021] Specifically, circuit board 1 is a double-layer circuit board, a triple-layer circuit board, or other multi-layer circuit board, formed by alternating stacking and thermoforming multiple conductive pattern layers and multiple insulating dielectric layers 11. Adjacent conductive pattern layers are electrically isolated from each other by one or more insulating dielectric layers 11. Circuit board 1 internally contains at least a first conductive pattern layer 12 and a second conductive pattern layer 13. The toroidal magnetic core 2 is entirely embedded within the insulating dielectric layer 11 inside circuit board 1, completely covered by the insulating dielectric material, and not exposed on the external surface of circuit board 1. The toroidal magnetic core 2 is a closed loop with a central hole, serving as the core component of the magnetic flux coupling path. A first signal coil 3 is wound around the central hole of the toroidal magnetic core 2, forming a multi-turn conductive coil structure, used to receive or transmit input-side signals. A second signal coil 4 is also arranged around the central hole of the toroidal magnetic core 2, its winding direction and position independent of the first signal coil 3. The two are spatially close to each other to achieve magnetic coupling, but are electrically completely isolated, with no direct or indirect conductive connection. The first signal coil 3 and the second signal coil 4 are led out to designated connection areas of the circuit board 1 through conductive vias or traces inside the circuit board 1, respectively, to establish electrical connections with external input and output circuits. The entire structure is integrally formed using a multilayer board lamination process. The toroidal magnetic core 2 is fixed in the insulating dielectric layer 11 during lamination to prevent displacement during subsequent reflow soldering or molding. Since the first signal coil 3 and the second signal coil 4 transmit signals only through magnetic field coupling, high electrical isolation between the input and output sides is achieved.

[0022] In a further embodiment of the present invention, the first signal coil 3 includes a first patterned portion 31 formed on the first conductive patterned layer 12, a second patterned portion 32 formed on the second conductive patterned layer 13, and a first conductive via 33 connecting the first patterned portion 31 and the second patterned portion 32. The second signal coil 4 includes a third patterned portion 41 formed on the first conductive patterned layer 12, a fourth patterned portion 42 formed on the second conductive patterned layer 13, and a second conductive via 43 connecting the third patterned portion 41 and the fourth patterned portion 42. The first patterned portion 31 and the third patterned portion 41 are located in mutually isolated regions of the first conductive patterned layer 12, and the second patterned portion 32 and the fourth patterned portion 42 are located in mutually isolated regions of the second conductive patterned layer 13.

[0023] It can be understood that the first signal coil 3 is composed of multiple conductive portions located on different conductive pattern layers, combined through a vertical interconnection structure. Specifically, the first signal coil 3 includes a first pattern portion 31 formed on the first conductive pattern layer 12, a second pattern portion 32 formed on the second conductive pattern layer 13, and a first conductive via 33 connecting the first pattern portion 31 and the second pattern portion 32. Both the first pattern portion 31 and the second pattern portion 32 are arc-shaped or spiral conductive traces extending around the central hole of the toroidal magnetic core 2. The first conductive via 33 penetrates the insulating dielectric layer 11 between them, electrically connecting the first pattern portion 31 and the second pattern portion 32, thereby forming part of a multi-turn winding.

[0024] The second signal coil 4 is also implemented using a cross-layer structure, including a third patterned portion 41 formed on the first conductive patterned layer 12, a fourth patterned portion 42 formed on the second conductive patterned layer 13, and a second conductive via 43 connecting the third patterned portion 41 and the fourth patterned portion 42. The third patterned portion 41 and the fourth patterned portion 42 are also arranged around the central hole of the annular magnetic core 2.

[0025] On the first conductive pattern layer 12, the first pattern section 31 and the third pattern section 41 are separated from each other, with sufficient insulation gap between them to ensure that there is no electrical connection between the input side and the output side on this layer. On the second conductive pattern layer 13, the second pattern section 32 and the fourth pattern section 42 are also arranged in different isolated areas, with no conductive bridging or shared copper foil between them. The two sets of coils are led out through their respective conductive paths, with no electrical connection between them. All pattern sections are integrally formed with the insulating dielectric layer 11 through the circuit board 1 lamination process, and conductive vias can achieve electrical connection through metallization of the via walls.

[0026] With the above layout, the first signal coil 3 forms the input side winding and the second signal coil 4 forms the output side winding. The two coils are physically coupled around the same toroidal magnetic core 2, but they are always electrically isolated in all conductive layers and via paths, thereby achieving a signal transmission function with high integration and high isolation strength within the circuit board 1.

[0027] Furthermore, the terminals of the first signal coil 3 and the second signal coil 4 are respectively led out from the corresponding graphic portion and electrically connected to the connection area on the bottom layer of the circuit board 1, and all spatial paths between the first signal coil 3 and the second signal coil 4 are isolated by the insulating dielectric layer 11 to achieve electrical isolation.

[0028] Specifically, the terminals of the first signal coil 3 are led out from their corresponding patterned portions and extended to the input-side connection area on the bottom layer of the circuit board 1 via conductive vias or traces. Similarly, the terminals of the second signal coil 4 are led out from their corresponding patterned portions and connected to the output-side connection area on the bottom layer of the circuit board 1 via conductive vias or traces. These input-side and output-side connection areas form electrically isolated external interfaces on the bottom layer of the circuit board 1 for connecting external circuits. On each conductive patterned layer, the input-side and output-side patterned portions are arranged in mutually isolated areas, filled with a dense insulating medium to ensure that the specified minimum creepage distance and clearance requirements are met. Therefore, throughout the entire signal transmission path, all conductive parts from the first signal coil 3 and its lead-out structure, and from the second signal coil 4 and its lead-out structure, remain electrically isolated in three-dimensional space. There are no shared conductive layers, vias, or pads between them, and they are completely separated by one or more insulating medium layers 11 at any cross-section or interlayer path. This three-dimensional isolation layout ensures that there are no direct or indirect conductive paths between the input and output sides, thereby achieving highly reliable electrical isolation in terms of physical structure.

[0029] In some embodiments, the entire magnetic coupling structure is completely embedded inside the multilayer circuit board 1. The toroidal magnetic core 2, the first signal coil 3, and the second signal coil 4 are all encased in an insulating medium and are not exposed on the outer surface of the circuit board 1. The insulating medium is an epoxy resin material with a dielectric strength greater than 45kV / mm. All conductive paths on the input and output sides, including coil patterns, conductive vias, and lead-out terminals, are completely filled and physically separated in three-dimensional space by the epoxy medium, eliminating weak points such as air gaps, solder joint interfaces, or delamination of the encapsulation. Thanks to the synergistic effect of the fully embedded magnetic core winding layout and the high dielectric strength epoxy medium, a highly reliable insulating barrier is formed between the input and output sides, significantly suppressing electric field concentration and partial discharge, giving the isolation device excellent overall electrical isolation performance.

[0030] Therefore, compared to existing isolation devices using substrate integration and surface-mount packaging processes, this invention achieves complete physical isolation between the input and output circuits by constructing a fully embedded magnetic coupling structure within the multilayer circuit board 1. Specifically, the toroidal magnetic core 2 is completely embedded in a high-dielectric-strength insulating dielectric layer 11. The first signal coil 3 and the second signal coil 4 are vertically interconnected through their respective independent first conductive vias 33 and 43, formed by patterned portions located on the first conductive patterned layer 12 and the second conductive patterned layer 13, respectively, creating a cross-layer distributed double-layer winding structure. This "double-layer pattern-vertical via interconnection" architecture not only ensures effective magnetic coupling of the signals, but more importantly, throughout the entire three-dimensional space, there are no shared conductive layers, shared vias, or adjacent traces between the input and output sides of any conductive path from the coil body and interlayer connections to the bottom connection area of ​​the circuit board. All potential electrical paths are completely isolated by one or more continuous and dense insulating dielectric layers 11, thus constructing a truly three-dimensional isolated path. Thanks to this physical-level complete isolation design, this invention fundamentally eliminates the risks of electric field concentration and partial discharge caused by exposed wire bonding areas, solder joints, or micro-gaps in the molding interface in traditional packaging. Actual measurements show that this isolation device can stably achieve an isolation withstand voltage of over 5kV DC, significantly better than the 2-3kV levels commonly achieved by existing technologies. While maintaining high integration and miniaturization, it meets the safety requirements of enhanced insulation, providing a high-performance and high-safety magnetic isolation solution for high-reliability applications such as new energy vehicles, medical equipment, and industrial control systems.

[0031] In some embodiments of the present invention, the first graphic portion 31 and the third graphic portion 41 both extend around the central hole of the annular magnetic core 2 and are circumferentially separated from each other in the plane of the first conductive graphic layer 12, respectively occupying different fan-shaped regions on the outer periphery of the annular magnetic core 2. Similarly, the second graphic portion 32 and the fourth graphic portion 42 both extend around the central hole of the annular magnetic core 2 and are circumferentially separated from each other in the plane of the second conductive graphic layer 13, respectively occupying different fan-shaped regions on the outer periphery of the annular magnetic core 2.

[0032] like Figure 3As shown, the first signal coil 3 and the second signal coil 4 are arranged in a circumferentially separated fan-shaped layout within the multilayer circuit board 1 to further improve the electrical isolation performance between the input and output sides. Specifically, on the first conductive pattern layer 12, the first pattern portion 31 constituting the first signal coil 3 and the third pattern portion 41 constituting the second signal coil 4 both extend around the central hole of the toroidal core 2, forming arc-shaped or spiral conductive traces. These two pattern portions are separated from each other along the circumference of the toroidal core 2 in the plane, without overlapping or being arranged adjacently, but rather occupying different fan-shaped areas on the outer periphery of the toroidal core 2. For example, the first pattern portion 31 can be arranged within a semicircular range of 0° to 160°, while the third pattern portion 41 is arranged within another semicircular range of 160° to 360°, with a sufficiently wide insulating gap between them to ensure that there are no close-range parallel segments on the conductive layer that could form capacitive coupling or leakage paths. Similarly, on the second conductive pattern layer 13, the second pattern portion 32 constituting the first signal coil 3 and the fourth pattern portion 42 constituting the second signal coil 4 also extend around the central hole of the toroidal core 2 and are circumferentially isolated from each other within the plane of this layer. The second pattern portion 32 and the fourth pattern portion 42 are respectively located in two non-overlapping fan-shaped regions on the outer periphery of the toroidal core 2, separated from each other by a complete insulating dielectric region, to avoid the formation of high electric field concentration areas during vertical projection or interlayer alignment.

[0033] Specifically, the projected areas of the first patterned portion 31 and the second patterned portion 32 in the vertical direction are approximately the same or completely overlap, meaning their coverage areas on different conductive layers are roughly consistent, ensuring a uniform magnetic field distribution in the vertical direction for the first signal coil 3. Similarly, the projected areas of the third patterned portion 41 and the fourth patterned portion 42 in the vertical direction are also approximately the same or completely overlap, resulting in a similarly uniform and efficient magnetic field distribution for the second signal coil 4. This design not only ensures the independence of the two sets of coils within their respective conductive layers but also maintains the consistency of the cross-layer windings, optimizing the overall magnetic coupling efficiency.

[0034] Therefore, by implementing this circumferentially separated fan-shaped layout in both the upper and lower conductive pattern layers, the input-side winding and the output-side winding achieve maximum physical separation throughout the three-dimensional space. This design not only significantly increases the shortest creepage distance and electrical clearance between the input and output, but also effectively reduces interlayer parasitic capacitance, thereby suppressing high-frequency common-mode noise coupling and improving common-mode transient immunity. Simultaneously, since both sets of coils still jointly encircle the same toroidal magnetic core 2, the magnetic flux path remains closed, and signals are efficiently coupled through the magnetic field, balancing isolation strength and transmission performance. This fan-shaped partitioning strategy, combined with the fully embedded structure inside the circuit board 1, ensures that the entire magnetic isolation unit is completely encased in a high-dielectric-strength insulating medium, further enhancing overall insulation reliability and providing a structural foundation for achieving high-voltage isolation above DC 5kV.

[0035] In some embodiments of the present invention, the connection area includes a first connection area 5 and a second connection area 6 isolated from each other, which are respectively disposed on opposite sides of the bottom layer of the circuit board 1 in the horizontal direction. The terminals of the first signal coil 3 are electrically connected to at least one pad in the first connection area 5, and the terminals of the second signal coil 4 are electrically connected to at least one pad in the second connection area 6. With the center of the toroidal core 2 as a reference, the main winding of the first signal coil 3 is located in the left region of the toroidal core 2, and the first connection area 5 is disposed on the left side of the bottom layer of the circuit board 1. The main winding of the second signal coil 4 is located in the right region of the toroidal core 2, and the second connection area 6 is disposed on the right side of the bottom layer of the circuit board 1. Each of the first connection area 5 and the second connection area 6 includes multiple pads, respectively used for receiving input-side signals and output-side signals.

[0036] like Figures 2-5 As shown, the bottom layer of circuit board 1 has a first connection area 5 and a second connection area 6 that are electrically isolated from each other. The two are arranged horizontally at opposite ends of the bottom layer of circuit board 1 to maximize the spacing between them. The directional descriptions such as "left side" and "right side" used here are only used to indicate the relative spatial distance between the two connection areas and are not a limitation on the actual installation direction or absolute coordinates of circuit board 1; any layout that separates the input side and output side connection structures on opposite edges of the bottom layer of circuit board 1 is an equivalent implementation of this solution.

[0037] The terminals of the first signal coil 3 are led out through internal conductive paths (such as conductive vias) and electrically connected to at least one pad in the first connection area 5; the terminals of the second signal coil 4 are led out through independent conductive paths (such as conductive vias) and electrically connected to at least one pad in the second connection area 6. With the center of the toroidal core 2 as a reference, the main winding of the first signal coil 3 is located in the left region of the toroidal core 2, and its lead-out traces naturally extend to the left region of the bottom layer of the circuit board 1; the main winding of the second signal coil 4 is located in the right region of the toroidal core 2, and its lead-out traces extend to the right region of the bottom layer. Since the two connection areas are located at opposite ends of the bottom layer of the circuit board 1, the shortest path along the surface between the input and output external electrical interfaces is significantly extended, i.e., the creepage distance is greatly increased. It can be understood that the longer the creepage distance, the lower the probability of leakage, electrochemical migration, or flashover breakdown along the surface of the insulating material. Especially under harsh operating conditions such as high temperature and humidity or the presence of ionic contaminants, the longer creepage path can effectively block the formation of surface conductive channels, thereby significantly improving the long-term reliability and withstand voltage of the isolation barrier. Combined with the epoxy dielectric (dielectric strength > 45kV / mm), fully embedded magnetic core structure, and three-dimensional spatial isolation of multi-layer conductive patterns used inside circuit board 1, the above layout further strengthens the overall insulation system. Actual measurements show that this structure can stably withstand isolation voltages above 5kV DC, far superior to conventional 2kV-3kV solutions, truly achieving a balance between high integration and high isolation reliability.

[0038] In some embodiments of the present invention, the connection region includes a first connection region 5 and a second connection region 6 isolated from each other, the first connection region 5 and the second connection region 6 being respectively disposed on opposite sides of the bottom layer of the circuit board 1 along the horizontal direction. The circuit board 1 also includes a third conductive pattern layer 14, which is located above the first conductive pattern layer 12 and the second conductive pattern layer 13 and is isolated from them by an insulating dielectric layer 11. The third conductive pattern layer 14 includes a fifth pattern portion 15 and a sixth pattern portion 16 isolated from each other. The first signal coil 3 has a first end 34 and a second end 35, the first end 34 being electrically connected to a first pad 51 of the first connection region 5, and the second end 35 being electrically connected to a second pad 52 of the first connection region 5. The fifth pattern portion 15 is electrically connected to both the first end 34 and the first pad 51 through a third conductive via 17, and is electrically connected to both the second end 35 and the second pad 52 through a fourth conductive via 18. The second signal coil 4 has a third end 44 and a fourth end 45, the third end 44 being electrically connected to the third pad 61 of the second connection region 6, and the fourth end 45 being electrically connected to the fourth pad 62 of the second connection region 6. The sixth graphic section 16 is electrically connected to the third terminal 44 and the third pad 61 simultaneously through the fifth conductive via 19, and is electrically connected to the fourth terminal 45 and the fourth pad 62 simultaneously through the sixth conductive via 20.

[0039] like Figure 4, Figure 5 , Figure 7 and Figure 8 As shown, the third conductive pattern layer 14 is located above the first conductive pattern layer 12 and the second conductive pattern layer 13, and is electrically isolated from the underlying conductive pattern layer by one or more insulating dielectric layers 11. The third conductive pattern layer 14 has a fifth pattern portion 15 and a sixth pattern portion 16 isolated from each other, which serve as mounting areas for the input-side chip 7 and the output-side chip 8, respectively. The input-side chip 7 is fixed to the fifth pattern portion 15 by flip-chip bonding or wire bonding, and its signal port is electrically connected to the fifth pattern portion 15; the output-side chip 8 is similarly mounted on the sixth pattern portion 16 and electrically connected to it.

[0040] The first signal coil 3 has a two-terminal structure, without a center tap or other intermediate leads, and only has a first end 34 and a second end 35. The first end 34, the first pad 51 in the first connection area 5 of the bottom layer of the circuit board 1, and a portion of the fifth pattern section 15 are electrically connected to the same input signal node, and are vertically interconnected through at least one through-the-three-layer conductive via. The second end 35, the second pad 52 in the first connection area 5 of the bottom layer, and another portion of the fifth pattern section 15 constitute another input signal node, also connected through three layers via an independent conductive via. Thus, the input-side chip 7 can interact with the two terminals of the first signal coil 3 via the fifth pattern section 15, and the signal can be led out to the outside of the device via the bottom pad.

[0041] Correspondingly, the second signal coil 4 also has a two-terminal structure, without any center tap, and only has a third terminal 44 and a fourth terminal 45. The third terminal 44, the third pad 61 in the bottom second connection area 6, and a part of the sixth pattern section 16 constitute the same output signal node, which is vertically interconnected through a shared conductive via; the fourth terminal 45, the fourth pad 62, and another part of the sixth pattern section 16 constitute another output signal node, which is connected in three layers through another set of conductive vias. The output-side chip 8 thus establishes a complete path with the second signal coil 4 and the external interface.

[0042] The adoption of a two-terminal coil structure is a key design feature for improving the reliability of high-voltage isolation. Omitting the center tap avoids introducing additional conductive nodes and interlayer vias in the middle of the coil, thereby reducing areas of concentrated electric field and potential leakage paths in the insulating medium. Since each coil group requires only two external connection points, the first connection area 5 and the second connection area 6 on the bottom layer of the circuit board 1 can be arranged at opposite ends, significantly increasing the creepage distance along the surface and the electrical clearance in the air. In high-temperature, high-humidity, or polluted environments, the longer creepage path effectively suppresses the risk of surface leakage and flashover. Simultaneously, the two-terminal structure ensures that there is only a single magnetic coupling path between the input and output sides, with no branch conductors crossing the isolation barrier, better meeting the safety requirements of reinforced insulation for continuous, uninterrupted insulation systems.

[0043] Because the fifth pattern section 15 and the sixth pattern section 16 are isolated from each other on the top layer, and all conductive paths—including the coil body, chip mounting area, vertical interconnect vias, and bottom pads—are completely covered by a high-dielectric-strength epoxy dielectric (dielectric strength greater than 45kV / mm), the entire signal transmission link achieves complete physical isolation in three-dimensional space. Therefore, this structure can stably withstand isolation voltages above 5kV DC, far superior to conventional 2kV-3kV solutions, truly achieving high reliability and high voltage withstand magnetic isolation performance while supporting highly integrated chip mounting. Furthermore, by printing a solder resist layer 10 (such as ink), the top layer of the circuit board has a protective function, exposing the third conductive pattern layer 14.

[0044] In some embodiments of the present invention, the isolation device further includes an input-side chip 7 and an output-side chip 8. The input-side chip 7 is electrically connected to the fifth patterned section 15 for driving the first signal coil 3, and the output-side chip 8 is electrically connected to the sixth patterned section 16 for receiving the output signal of the second signal coil 4. A first adhesive layer 71 is formed around the pins of the input-side chip 7, covering the pins of the input-side chip 7 and the adjacent area of ​​the fifth patterned section 15. A second adhesive layer is formed around the pins of the output-side chip 8, covering the pins of the output-side chip 8 and the adjacent area of ​​the sixth patterned section 16.

[0045] like Figures 7-10 As shown, the input-side chip 7 is electrically connected to the fifth patterned portion 15 via flip-chip bonding bumps or wire bonding, with multiple pins distributed around the chip's periphery. A first adhesive layer 71 is formed around the pins of the input-side chip 7, covering the pins of the input-side chip 7 and the adjacent surface area of ​​the fifth patterned portion 15, forming a continuous encapsulation structure. Similarly, the output-side chip 8 is connected to the sixth patterned portion 16 via flip-chip bonding or wire bonding, with a second adhesive layer formed around its pins, covering the pins of the output-side chip 8 and the adjacent area of ​​the sixth patterned portion 16.

[0046] The first and second dispensing layers 71 and 72 are composed of low-stress, high-insulation adhesive materials, such as modified epoxy resin or silicone colloids, possessing good dielectric properties, resistance to damp heat, and adhesive strength. The functions of the dispensing layers include: fixing chip pins or bonding wires to prevent connection failures caused by thermal cycling or mechanical vibration; filling the micro-gaps between pins and patterned areas to eliminate air gaps and prevent partial discharge; covering exposed copper surfaces and solder joints to block the path of moisture and contaminants intruding along the surface, significantly improving local creepage distance; and smoothing geometric abrupt changes at the pin roots to reduce the electric field concentration factor and suppress corona or flashover under high voltage. Thus, since the dispensing layers only cover localized areas around their respective chips, and the fifth and sixth patterned areas 15 and 16 are already sufficiently electrically isolated at the top layer, the first and second dispensing layers are independent of each other and will not form conductive or ion channels across the isolation barrier. This local dispensing design further enhances the insulation reliability from chip pins to external interfaces, providing further assurance for stably achieving isolation withstand voltages above 5kV DC.

[0047] In some embodiments of the present invention, the isolation device further includes a molding compound 9, which is formed of an insulating molding compound and completely covers the top layer of the circuit board 1 to seal all the exposed conductive structures of the input-side chip 7, the output-side chip 8, the fifth graphic portion 15, and the sixth graphic portion 16 of the top layer of the circuit board 1 within the molding compound 9.

[0048] Specifically, the molding compound 9 covers the top surface of the circuit board 1, embedding all exposed conductive structures of the input-side chip 7, output-side chip 8, fifth graphic portion 15, and sixth graphic portion 16 located on the top layer. After curing, the molding compound 9 forms a dense, non-porous protective layer, effectively isolating external moisture, dust, and contaminants from erosion of the chip pins, bonding wires, and graphic portion surfaces. Simultaneously, since the conductive structures on the input and output sides are separated by the spatial isolation of the fifth graphic portion 15 and the sixth graphic portion 16 on the top layer, the molding compound 9 forms a continuous, highly insulating fill between them, further extending the creepage path along the top surface and eliminating the risk of partial discharge that may be caused by air gaps. This molding compound 9 strengthens the integrity of the overall isolation barrier at the packaging level, providing further assurance for achieving high withstand voltage isolation of over 5kV DC.

[0049] Furthermore, among the existing packaged devices based on circuit board 1, the following types mainly exist: The first type is a PCB with no metal sidewalls. In this type, the PCB sidewalls lack metallization, and the solder paste is only connected through bottom pads. At high temperatures, the pads are prone to detachment, resulting in poor soldering reliability and overall low reliability. The second type is a PCB with metal sidewalls and surface-mount devices (surface-mount without plastic encapsulation). In this type, because the sidewall metal is formed through vias, effective plastic encapsulation is impossible, significantly reducing the overall isolation capability of the device. The third type is a PCB with metal sidewalls and surface-mount devices (surface-mount with plastic encapsulation). Although the surface of this type can be plastic encapsulated, the sidewall metal needs to be cut later to form the plastic encapsulation. During the cutting process, metal residue and bare metal on the cut surface are prone to oxidation, affecting the solder paste application and posing reliability issues.

[0050] To overcome the shortcomings of the prior art, the present invention further proposes a packaging structure. Specifically, the connection area includes multiple pads, at least a portion of which extend to the edge of the circuit board 1. A depth-controlled semi-via 53 is provided on the pads extending to the edge of the circuit board 1. The depth-controlled semi-via 53 is located in the area of ​​the pads near the edge of the circuit board 1 and is exposed on the side of the circuit board 1. The depth of the depth-controlled semi-via 53 is less than the total thickness of the circuit board 1. The walls and bottom of the depth-controlled semi-via 53 are metallized surfaces, making the exposed sidewall formed by the depth-controlled semi-via 53 on the side of the circuit board 1 a continuous conductive surface.

[0051] like Figures 11-12 As shown, the controlled-depth half-hole 53 is located in the area near the edge of the circuit board 1, forming an opening on the side of the circuit board 1, thus exposing the hole wall structure of the controlled-depth half-hole 53 to the outer surface of the circuit board 1. The depth of the controlled-depth half-hole 53 is much less than the total thickness of the circuit board 1, and its hole wall and bottom are metallized to form a continuous conductive surface. Since the controlled-depth half-hole 53 does not penetrate the entire circuit board 1, its bottom terminates in an internal insulating layer, thus not forming an electrical connection with other conductive layer structures. At the same time, the exposed sidewall formed by the controlled-depth half-hole 53 on the side of the circuit board 1 is a complete and continuous metal surface, which can serve as a reliable external electrical contact interface, suitable for direct access of test probes, connector inserts, or solder pins.

[0052] Compared with existing technologies, the present invention, by setting the controlled-depth half-hole 53, has the following significant advantages: First, the sidewall metallization provides a soldering contact surface, enhancing soldering strength and reliability, and avoiding the high-temperature detachment problem when relying solely on the bottom pad. Second, the design of the controlled-depth half-hole 53 allows surface molding compound to cover the top layer and sidewalls without worrying about interference from the sidewall metallization, thereby improving the overall device isolation performance. Third, after the hole walls and bottom of the controlled-depth half-hole 53 are metallized, oxidation of the sidewall metal can be effectively prevented, improving the solder paste application effect and ensuring long-term electrical connection reliability. Fourth, by setting the controlled-depth half-hole 53 on the bottom pad of the circuit board 1, the function of the bottom pad for conventional surface mounting is retained, while additional lateral electrical access paths are provided. Furthermore, the metallized sidewalls form an efficient heat conduction channel, rapidly transferring the heat generated by the input-side chip 7 or the output-side chip 8 during operation from inside the circuit board 1 through the copper wall of the controlled-depth semi-via 53 to the device's side surface. The heat is then further dissipated through contact with the system PCB or heat dissipation structure, significantly reducing the chip junction temperature and improving the long-term reliability of the device under high load or high temperature environments. Additionally, since the controlled-depth semi-via 53 is only exposed in a localized area on the side of the circuit board 1, and its depth is controlled and does not penetrate the isolation barrier, the main isolation path between the input and output sides remains intact, significantly improving the device's testability and system integration flexibility.

[0053] It is worth noting that the controlled-depth half-hole 53 in this solution not only metallizes its hole walls but also fully metallizes its bottom surface. This design differs from existing technologies that only metallize the half-hole walls. Specifically, in traditional half-hole structures, if the bottom is not metallized, a blind cavity composed of insulating medium will be formed inside the circuit board 1. When the device is fully encapsulated, the high-temperature fluid dynamic encapsulation material can easily seep into the bottom of the blind hole along the gaps in the hole walls under pressure, forming closed bubbles, microcracks, or interface delamination after curing. These defects not only weaken the mechanical strength of the package but may also become the starting point for partial discharge under high-voltage operating conditions, reducing isolation reliability. In this solution, by simultaneously metallizing the bottom of the controlled-depth half-hole 53, a continuous and dense conductive surface is formed throughout the entire half-hole cavity, including the sidewalls and bottom, thereby completely eliminating the internal blind hole cavity. When the encapsulation material comes into contact with this fully metallized surface, it is effectively blocked due to the lack of penetration channels, ensuring a complete and defect-free interface between the encapsulation body 9 and the pad area. This not only improves the sealing performance but also avoids thermal stress concentration and electric field distortion caused by internal voids. Furthermore, bottom metallization further enhances the thermal and electrical conductivity of the depth-controlled half-hole 53, enabling it to more efficiently conduct chip heat through the metal cavity to the sidewalls and then dissipate it to the external environment while serving as a side-welding pin. Combined with the side wetting surface formed by the metallized hole walls, this fully metallized half-hole structure outperforms solutions with only hole wall metallization in terms of electrical connectivity, thermal management, and package reliability.

[0054] In some embodiments of the present invention, conductive vias 54 are also provided on the pads extending to the edge of the circuit board 1. The conductive vias 54 are located on the side of the controlled depth half-hole 53 facing the center of the circuit board 1, and extend from the surface of the pad into the interior of the circuit board 1, and are electrically connected to the conductive structure of the inner layer. The conductive vias 54 have metallized holes and insulating resin filling them, and their tops are flush with the surface of the pads.

[0055] It is understood that conductive vias 54 and depth-controlled half-vias 53 are simultaneously provided on the pads extending to the edge of circuit board 1. The conductive via 54 is located on the side of the depth-controlled half-via 53 facing the center of circuit board 1, extending from the surface of the pad into the interior of circuit board 1, establishing an electrical connection with the conductive structure of the inner layer, and used to introduce or lead external signals to the multilayer wiring network. The conductive via 54 has metallized hole walls to ensure good conductivity and thermal conductivity; simultaneously, an insulating resin is filled inside the metallized hole wall, completely filling the cavity, and after curing, it is coplanarized with the surface of the pad, making the top of the conductive via 54 flush with the surface of the pad. This structure retains the vertical interconnection function of vias while eliminating the depressions or protrusions formed on the surface by traditional vias, providing a flat substrate for subsequent molding processes.

[0056] This structure achieves electrical interconnection between the pad pins and internal / external networks through two independent connection paths: conductive vias 54 and controlled-depth half-vias 53 with metallized sidewalls. On one hand, conductive vias 54 provide a reliable vertical interconnect channel, ensuring signal integrity; on the other hand, the metallized surface formed on the sidewall of the controlled-depth half-via 53 provides an additional wetting interface for the solder. This dual-connection mechanism significantly improves the connection reliability and mechanical strength of the device pin pads, making them less prone to pull-out or pad detachment under high-temperature reflow soldering or thermal cycling stress. Simultaneously, the metallized sidewalls and the copper structure of the conductive vias 54 together form an efficient heat conduction path, rapidly dissipating the heat generated during chip operation and enhancing the device's heat dissipation capabilities. Furthermore, the conductive via 54, with its inward-shifted layout and electroplated filling design, offers several advantages: First, the conductive via 54 does not penetrate the circuit board 1 and is located away from the side openings, effectively preventing the formation of a through channel between the surface and bottom layers due to the via connection. Second, during subsequent molding, the smooth surface filled with insulating resin prevents molding compound from flowing into or overflowing from the via, ensuring uniform molding material thickness and no air gaps, thus guaranteeing the overall manufacturability and sealing reliability of the surface molding. Third, during the final soldering of the device to the system PCB, the filled via structure prevents solder from seeping into the interior along the via walls, avoiding solder siphoning that could lead to poor solder joints, voids, or internal contamination, thereby improving soldering yield and long-term reliability. Additionally, the metallized design of the pad sidewalls allows the solder to climb upwards along the sidewalls during soldering, forming solder joints that wrap around the sides of the pads. This side wetting effect not only makes the weld stronger, but also exposes the solder joint in the side view, making it easier to directly inspect the weld quality through optical or X-ray methods, and promptly detect defects such as cold solder joints, insufficient solder, or cracks, significantly reducing welding risks and improving the controllability of the production process and product consistency.

[0057] In summary, this composite pin structure achieves high-reliability electrical connection, efficient heat dissipation, molding process compatibility, and testability simultaneously without compromising the high isolation barrier between the input and output sides, providing key packaging support for the high-density integration and high-reliability application of high-voltage isolation devices above DC 5kV.

[0058] In some embodiments of the present invention, the controlled-depth semi-via 53 does not have a metal cover at the outermost edge of the circuit board 1, and the metallized surfaces of its hole walls and bottom terminate at the inner side of the outermost edge of the circuit board 1, exposing the insulating dielectric layer 11. The conductive portion of the controlled-depth semi-via 53 is separated from the outermost surface of the circuit board 1 by the insulating dielectric layer 11, forming a non-conductive edge isolation region 55.

[0059] Specifically, during the manufacturing process, by etching the copper of the exposed control-depth semi-hole 53 on the sidewall of the circuit board 1 inward, the sidewall metal can be moved inward, thereby exposing the insulating medium and forming a non-conductive edge isolation area 55. This edge isolation area 55 effectively avoids metallization along the entire sidewall direction, thus preventing the molding material from flowing into the device or overflowing along the board edge through the through-channel formed by the sidewall metallization during subsequent top-layer overall molding. This not only ensures the sealing integrity of the molding body 9, but also ensures the machinability and consistency of the surface molding process, avoiding voids, delamination, or contamination caused by molding material leakage. Secondly, compared with the traditional process that requires sidewall metallization of the entire thickness of the circuit board 1 (such as full-depth milling + deep hole electroplating), the control-depth semi-hole 53 used in this solution has a shallower processing depth, usually only penetrating one or two layers before terminating in the internal insulating medium. This shallow depth structure significantly reduces the difficulty of controlling the mechanical stress of drilling or milling and the flow resistance of electroplating solution, greatly improving the processing yield and reducing manufacturing costs. Therefore, the design of the controlled-depth semi-hole 53 combined with the edge insulation isolation area not only meets the requirements of high-reliability electrical connection and lateral heat dissipation, but also takes into account high voltage isolation, molding process compatibility and manufacturability.

[0060] In some embodiments of the present invention, the circuit board 1 has a stepped profile 56 on its side adjacent to its bottom layer. The stepped profile 56 is formed by a vertical sidewall 5601 and a horizontal bottom surface 5602 connecting its bottom outer edge. A depth-controlled half-hole 53 penetrates the pad and extends to the vertical sidewall 5601, but does not extend to the horizontal bottom surface 5602.

[0061] Specifically, circuit board 1 has a stepped profile 56 on its side adjacent to its bottom layer. This stepped profile 56 is formed by a vertical sidewall 5601 and a horizontal bottom surface 5602 connected to its outer bottom edge, creating an inwardly recessed stepped structure. A controlled-depth semi-via 53 penetrates the pad and extends to the vertical sidewall 5601, but its depth and position are precisely controlled so that it does not extend to the horizontal bottom surface 5602. It can be understood that the stepped profile 56 is located in the non-metallic coverage area of ​​the device edge, while the metallized portion of the sidewall on the pad (i.e., the metallized surface of the controlled-depth semi-via 53) is offset inwards from the device, so that the metallized area is not on the same plane as the outermost physical edge of circuit board 1. After the entire board is manufactured, individual isolation devices are separated from the motherboard by mechanical cutting or laser division along the horizontal bottom surface 5602. Because the cutting path is located in the metal-free horizontal bottom surface 5602 region, the cutting process does not touch any conductive structures, thus completely avoiding metal residue, burrs, or exposed fresh metal surfaces caused by traditional all-metal sidewall cutting. This design effectively solves a key pain point in the prior art: in conventional sidewall metallized devices, cutting exposes the active metal surface, which oxidizes rapidly in air, forming a high-resistance oxide layer, severely affecting the wettability and creepage ability of the solder during subsequent reflow soldering, resulting in cold solder joints, insufficient solder, or insufficient solder joint strength. In this solution, only the horizontal bottom surface 5602 composed of insulating medium is exposed on the side of the device after cutting, while all metallized structures remain on the inner side of the vertical sidewall 5601, away from the cutting surface. Therefore, the sidewall metal remains intact and undamaged, ensuring that the solder can effectively wet the metallized sidewall of the controlled-depth half-hole 53 during soldering, forming a strong and reliable solder joint.

[0062] Furthermore, due to the physical misalignment between the metallized area and the outermost edge of the device, even in high-humidity or polluted environments, external contaminants are unlikely to directly contact the conductive surface, further enhancing the electrical stability during long-term use. Combined with the fully metallized walls and bottom of the controlled-depth semi-via 53, the non-conductive edge isolation area 55, and the overall encapsulation of the top molding compound 9, this stepped profile 56 design ensures a balance between device cutability, soldering reliability, and high-voltage isolation performance from the manufacturing stage, providing crucial process support for the large-scale production of high-density, high-reliability magnetically isolated devices.

[0063] Therefore, this invention provides a miniaturized magnetically isolated packaged device with high isolation, high reliability, and manufacturability. This device is based on a multilayer printed circuit board integrated construction, in which the toroidal magnetic core 2 is completely embedded in a high dielectric strength epoxy medium, and an internal magnetic coupling structure is formed by two layers of patterned parts and vias. At the same time, the circuit board 1 is filled with an insulating medium to achieve complete physical isolation. The input-side chip 7 and the output-side chip 8 are respectively mounted on the top layer of patterned areas that are isolated from each other, and magnetically isolated signal transmission is achieved through a dual-terminal tapless signal coil. The entire top layer structure is completely covered by an insulating plastic encapsulation 9, and the bottom layer has input / output connection areas with two separate ends to ensure that the input and output circuits are physically completely isolated in three-dimensional space. The device lead pads are connected to the inner layer network through inwardly moved conductive vias 54. After metallization, the vias are filled with insulating resin and ground flat to be flush with the pad surface, ensuring the reliability of vertical interconnects and preventing molding compound seepage or solder siphoning. Simultaneously, the pads extend to the board edge and integrate depth-controlled half-holes 53. The walls and bottom of these half-holes are metallized, and their conductive portion terminates on the inner side of the outermost edge of the circuit board 1, forming a non-conductive edge isolation area 55. The metallized sidewall area and the cut surface are staggered by a pre-designed stepped structure, ensuring that no metal is exposed on the sidewalls and there is no risk of oxidation after a single device is cut. During soldering, solder can wet and climb along the metallized sidewalls, forming strong, visible solder joints, significantly improving connection strength and process reliability. Thanks to the synergistic effect of the fully embedded magnetic core and the internal conductive distribution of the circuit board 1, the epoxy dielectric, the end-to-end pad layout, the fully metallized deep half-hole 53, and the edge insulation design, this device achieves an ultra-high isolation withstand voltage of 8kV DC, which is far higher than the industry's conventional 2kV–3kV level. At the same time, the overall size is small, providing a magnetic isolation solution with high performance, high integration, and mass production feasibility for high-safety applications such as new energy vehicles, industrial control, and medical electronics.

[0064] In the description of this invention, it should be understood that the terms "center," "longitudinal," "lateral," "length," "width," "thickness," "upper," "lower," "front," "rear," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," "outer," "clockwise," "counterclockwise," "axial," "radial," and "circumferential" indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are used only for the convenience of describing this invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this invention.

[0065] In the description of this specification, references to terms such as "one embodiment," "some embodiments," "illustrative embodiment," "example," "specific example," or "some examples," etc., refer to specific features, structures, materials, or characteristics described in connection with that embodiment or example, which are included in at least one embodiment or example of the present invention. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example.

[0066] Although embodiments of the invention have been shown and described, those skilled in the art will understand that various changes, modifications, substitutions and alterations can be made to these embodiments without departing from the principles and spirit of the invention, the scope of which is defined by the claims and their equivalents.

Claims

1. An isolation device, characterized by, The application relates to a circuit board (1) comprising: a plurality of conductive pattern layers and a plurality of insulating medium layers (11) are alternately laminated, at least comprising a first conductive pattern layer (12) and a second conductive pattern layer (13) between adjacent conductive pattern layers, and a single layer or multiple layers of insulating medium are arranged therebetween; a ring-shaped magnetic core (2) is completely embedded in the single layer or multiple layers of insulating medium; a first signal coil (3) and a second signal coil (4) are arranged around the center hole of the ring-shaped magnetic core (2) and are not electrically connected to each other; the first signal coil (3) comprises a first pattern part (31) formed on the first conductive pattern layer (12), a second pattern part (32) formed on the second conductive pattern layer (13), and a first conductive via (33) connecting the first pattern part (31) and the second pattern part (32); the second signal coil (4) comprises a third pattern part (41) formed on the first conductive pattern layer (12), a fourth pattern part (42) formed on the second conductive pattern layer (13), and a second conductive via (43) connecting the third pattern part (41) and the fourth pattern part (42); wherein the first pattern part (31) and the third pattern part (41) are located in different regions of the first conductive pattern layer (12) and are isolated from each other, the second pattern part (32) and the fourth pattern part (42) are located in different regions of the second conductive pattern layer (13) and are isolated from each other; the terminals of the first signal coil (3) and the terminals of the second signal coil (4) are respectively led out from the corresponding pattern parts and electrically connected to the connection areas on the bottom layer of the circuit board (1), and all the space paths between the first signal coil (3) and the second signal coil (4) are separated by the insulating medium layers (11) to realize electrical isolation.

2. The isolation device of claim 1, wherein, the first pattern part (31) and the third pattern part (41) extend around the center hole of the ring-shaped magnetic core (2) and are separated from each other in the circumferential direction in the plane of the first conductive pattern layer (12) and respectively occupy different sector regions of the outer periphery of the ring-shaped magnetic core (2); and the second pattern part (32) and the fourth pattern part (42) extend around the center hole of the ring-shaped magnetic core (2) and are separated from each other in the circumferential direction in the plane of the second conductive pattern layer (13) and respectively occupy different sector regions of the outer periphery of the ring-shaped magnetic core (2).

3. The isolation device of claim 1, wherein, the connection areas comprise a first connection area (5) and a second connection area (6) which are isolated from each other, and the first connection area (5) and the second connection area (6) are respectively arranged on the opposite sides of the bottom layer of the circuit board (1) in the horizontal direction; the terminals of the first signal coil (3) are electrically connected to at least one pad of the first connection area (5), and the terminals of the second signal coil (4) are electrically connected to at least one pad of the second connection area (6). The main winding of the first signal coil (3) is located at the left side region of the ring-shaped magnetic core (2) with the center of the ring-shaped magnetic core (2) as a reference, and the first connecting region (5) is arranged at the left side of the bottom layer of the circuit board (1); the main winding of the second signal coil (4) is located at the right side region of the ring-shaped magnetic core (2), and the second connecting region (6) is arranged at the right side of the bottom layer of the circuit board (1); The first connecting region (5) and the second connecting region (6) each include a plurality of pads for respectively connecting input side signals and output side signals.

4. The isolation device of claim 1, wherein, The connecting region includes the first connecting region (5) and the second connecting region (6) which are isolated from each other and are arranged at opposite sides in the horizontal direction of the bottom layer of the circuit board (1); The circuit board (1) further includes a third conductive pattern layer (14) which is located above the first conductive pattern layer (12) and the second conductive pattern layer (13) and is isolated therefrom by the insulating medium layer (11); the third conductive pattern layer (14) includes a fifth pattern portion (15) and a sixth pattern portion (16) which are isolated from each other; The first signal coil (3) has a first end (34) and a second end (35), the first end (34) is electrically connected to a first pad (51) of the first connecting region (5), and the second end (35) is electrically connected to a second pad (52) of the first connecting region (5); the fifth pattern portion (15) is electrically connected to the first end (34) and the first pad (51) through a third conductive via (17) and is electrically connected to the second end (35) and the second pad (52) through a fourth conductive via (18); The second signal coil (4) has a third end (44) and a fourth end (45), the third end (44) is electrically connected to a third pad (61) of the second connecting region (6), and the fourth end (45) is electrically connected to a fourth pad (62) of the second connecting region (6); the sixth pattern portion (16) is electrically connected to the third end (44) and the third pad (61) through a fifth conductive via (19) and is electrically connected to the fourth end (45) and the fourth pad (62) through a sixth conductive via (20).

5. The isolation device of claim 4, wherein, The input side chip (7) is electrically connected to the fifth pattern portion (15) for driving the first signal coil (3), and the output side chip (8) is electrically connected to the sixth pattern portion (16) for receiving the output signal of the second signal coil (4). The first dispensing layer (71) is formed around the pins of the input-side chip (7) and covers the pins of the input-side chip (7) and the region of the adjacent fifth pattern part (15); the second dispensing layer is formed around the pins of the output-side chip (8) and covers the pins of the output-side chip (8) and the region of the adjacent sixth pattern part (16).

6. The isolation device of claim 5, wherein, Further comprising: The plastic package (9) is formed by an insulating plastic package material and completely covers the top layer of the circuit board (1) to seal the exposed conductive structures of the input-side chip (7), the output-side chip (8), the fifth pattern part (15) and the sixth pattern part (16) of the top layer of the circuit board (1) in the plastic package (9).

7. The isolation device of claim 1, wherein The connecting region comprises a plurality of pads, at least some of which extend to the edge of the circuit board (1); The pad extending to the edge of the circuit board (1) is provided with a depth control half-hole (53) located in the region close to the edge of the circuit board (1) and exposed to the side edge of the circuit board (1); the depth of the depth control half-hole (53) is less than the total thickness of the circuit board (1), the hole wall and the hole bottom of the depth control half-hole (53) are both metallized surfaces, and the exposed side wall formed on the side edge of the circuit board (1) is a continuous conductive surface.

8. The isolation device of claim 7, wherein, The pad extending to the edge of the circuit board (1) is also provided with a conductive via (54) located on the side of the depth control half-hole (53) facing the center of the circuit board (1) and extending from the surface of the pad to the inside of the circuit board (1) to electrically connect with the conductive structure of the inner layer; The conductive via (54) has a metallized hole wall and an insulating resin body filled therein, and the top thereof is flush with the surface of the pad.

9. The isolation device of claim 7, wherein, The depth control half-hole (53) does not have metal coverage at the outermost edge of the circuit board (1), and the metallized surfaces of the hole wall and the hole bottom terminate on the inner side of the outermost edge of the circuit board (1), exposing the insulating medium layer (11); The conductive part of the depth control half-hole (53) is separated from the outermost surface of the circuit board (1) by the insulating medium layer (11) to form a non-conductive edge isolation region (55).

10. The isolation device according to claim 7 or 9, characterized in that The circuit board (1) is provided with a stepped profile (56) adjacent to the side edge of the bottom layer, which is composed of a vertical side wall surface (5601) and a horizontal bottom surface (5602) connected to the outer edge of the bottom; the depth control half-hole (53) penetrates the pad and extends to the vertical side wall surface (5601) and does not extend to the horizontal bottom surface (5602).

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