Storage array and preparation method thereof, memory and electronic equipment

Abstract

The embodiment of the invention provides a storage array and a preparation method thereof, a memory and electronic equipment, relates to the field of electronics, and is used for improving the electrical performance of the storage array. Transistors in the storage array are double-gate transistors, a first word line (a first gate) is arranged on the outer side of a channel structure, a second word line (a second gate) is arranged on the inner side of the channel structure, and therefore the channel structure is controlled by the first word line and the second word line jointly. The first word line can control the part, corresponding to the first word line, of the channel structure, the second word line can control the whole channel structure, and for the channel structure, a non-grid-control channel region without grid control does not exist any more, so that parasitic resistance and contact resistance of the transistor are reduced. Namely, the parasitic resistance and the contact resistance of the transistor in the memory array are reduced by changing grid control, the driving current of the transistor is increased, and the electrical performance of the memory array is improved.

Description

Technical Field

[0001] This application relates to the field of electronics, and more particularly to a storage array and its fabrication method, a memory, and an electronic device. Background Technology

[0002] With the continuous evolution of integrated circuit technology, the number of transistors per unit area on chips in electronic devices such as computers and mobile phones is constantly increasing, thereby continuously optimizing the performance of electronic devices. For example, dynamic random access memory (DRAM), as a memory structure, can be used to temporarily store data processed by the central processing unit (CPU). To adapt to the processing speed of the processor, the read and write speed of memory is constantly being improved, and the storage density of memory is also constantly increasing to meet people's data processing needs in the information age.

[0003] As memory technology advances towards higher densities and greater bandwidth, various memory cell structures have emerged. Furthermore, by transforming single-layer memory cells into multi-layer stacked structures, the bottleneck of horizontal miniaturization limited by photolithography size has been overcome. However, with increasing memory density, ensuring the electrical performance of the memory remains a key research focus for those skilled in the art. Summary of the Invention

[0004] This application provides a memory array, a method for fabricating the memory array, a memory containing the memory array, and an electronic device containing the memory, for improving the electrical performance of the memory array.

[0005] A first aspect of this application provides a storage array, which can be used, for example, in dynamic random access memory (DRAM).

[0006] The memory array includes multiple memory layers, a first word line (or first gate line), a first gate dielectric layer, a second word line, and a second gate dielectric layer. The multiple memory layers are spaced apart along a first direction. Each memory layer includes a channel structure, a bit line, and a capacitor; the channel structure encloses a channel via, and the bit line and capacitor are distributed outside the channel structure; the bit line extends along a second direction, intersecting the first direction. The first word line extends along the first direction and is located outside the multiple channel structures stacked along the first direction in the multiple memory layers. The first gate dielectric layer is disposed between the first word line and the channel structure. The second word line extends along the first direction and passes through the channel vias of the multiple channel structures stacked along the first direction in the multiple memory layers. The second gate dielectric layer is disposed between the second word line and the channel structure.

[0007] The memory array provided in this application provides a first word line (i.e., the first gate of the transistor) on the outside of the channel structure and a second word line (i.e., the second gate of the transistor) on the inside of the channel structure, so that the channel structure is jointly controlled by the first word line and the second word line. Although the first word line can only control the portion of the channel structure corresponding to the first word line, the regions of the channel structure that do not correspond to the first word line and do not contact the bit lines and capacitors (extension regions) are not controlled by the first word line, resulting in a large parasitic resistance in the extension regions of the transistors. Simultaneously, the regions of the channel structure that contact the bit lines and capacitors (contact regions) are also not controlled by the first word line, and the contacts formed between undoped and ungate-controlled channel materials and electrodes typically have high contact resistance. However, the second word line passes through the channel via and is located inside the channel structure, allowing the second word line to control the entire channel structure. For the channel structure, the ungate-controlled extension region and the ungate-controlled contact region corresponding to the first word line WL1 can be controlled by the second word line, thereby reducing the parasitic resistance and contact resistance of the transistors. That is, by changing the gate control, the parasitic resistance and contact resistance of the transistors in the memory array are reduced, thereby increasing the transistor drive current. Furthermore, the first and second word lines overlap, and this region is jointly controlled by the inner and outer word lines, which can further increase the transistor drive current. Moreover, at the overlap of the first and second word lines, the electric fields applied from the outside and inside of the channel structure cancel each other out within the channel structure, reducing the electrical degradation caused by the electric fields and improving the reliability of the transistors. This achieves the goal of improving the electrical performance and reliability of the memory array.

[0008] In one possible implementation, the sheet resistance (or sheet resistance) of the first word line is less than that of the second word line. Sheet resistance refers to the resistance between edges of a square thin-film conductive material.

[0009] The sheet resistance of the first word line is less than that of the second word line, meaning the signal conduction capability of the first word line is stronger than that of the second word line. During the driving of the channel structure, the first word line acts as the main driving gate, and the second word line acts as the auxiliary driving gate. The thickness and material of the gate dielectric layer (here, the first gate dielectric layer) of the main driving gate determine the core performance of the transistor. Therefore, it is not necessary to pursue a thinner or higher dielectric constant second gate dielectric layer to consider the driving capability of the second word line. The physical thickness of the second gate dielectric layer can be increased, or a second gate dielectric layer material with a lower dielectric constant can be used to reduce the damage to the channel structure during the fabrication of the second word line, improving the electrical performance and reliability of the transistor, and further enhancing the electrical performance and reliability of the memory array.

[0010] In one possible implementation, the physical thickness of the first gate dielectric layer is less than the physical thickness of the second gate dielectric layer. Since a thinner gate dielectric layer provides better gate control, a thinner first gate dielectric layer results in stronger gate control of the channel structure by the first word line than by the second word line. Thus, the first word line acts as the main driving gate, and the second word line acts as the auxiliary driving gate. This eliminates the need for a thinner second gate dielectric layer to compensate for the driving capability of the second word line. Increasing the physical thickness of the second gate dielectric layer enhances channel protection, reducing damage to the channel structure during the fabrication of the second word line electrodes, improving the electrical performance and reliability of the transistor, and further enhancing the electrical performance and reliability of the memory array.

[0011] In one possible implementation, the dielectric constant of the first gate dielectric layer is greater than that of the second gate dielectric layer. Since a higher dielectric constant results in better gate control, the higher dielectric constant of the first gate dielectric layer makes the gate control of the channel structure by the first word line stronger than that by the second word line. Thus, the first word line acts as the main driving gate, and the second word line acts as the auxiliary driving gate. This eliminates the need to use a second gate dielectric layer with a higher dielectric constant to compensate for the driving capability of the second word line. Materials with lower dielectric constants but less impact on the channel during fabrication can be used as the second gate dielectric to reduce damage to the channel structure during the fabrication of the second word line, improving the electrical performance and reliability of the transistor, and further enhancing the electrical performance and reliability of the memory array. For the same thickness, materials with lower dielectric constants have a larger equivalent thickness.

[0012] In one possible implementation, the physical thickness of the portion of the second gate dielectric layer that contacts the channel structure is greater than or equal to the physical thickness of the portion of the second gate dielectric layer that does not contact the channel structure. This can improve the protective effect of the second gate dielectric layer on the channel structure and reduce damage to the channel structure.

[0013] In one possible implementation, the first word line has a recess on the side facing the channel structure, with a portion of the channel structure extending into the recess. This allows the first word line to overlap with all three surfaces of the channel structure, resulting in a large controllable area and good gate control performance.

[0014] In one possible implementation, the first word line and the second word line are insulated from each other. This allows the first and second word lines to receive different control signals; for example, a read / write control signal can be applied to the first word line, while a separate signal can be applied to the second word line to regulate the transistor's threshold voltage, thereby further optimizing the transistor's electrical performance.

[0015] In one possible implementation, the first word line and the second word line can also be interconnected. For example, the first word line and the second word line receive the same control signals (e.g., read / write control signals) to simplify the architecture of the memory array.

[0016] In one possible implementation, the memory array includes multiple first word lines, which are spaced apart on the outer side of the channel structure. By correspondingly setting multiple first word lines on the outer side of each channel structure, the gate width of the first word lines is increased, further increasing the drive current of the transistors and improving the read / write speed of the transistors.

[0017] In one possible implementation, the first direction is perpendicular to the substrate, the second direction is parallel to the substrate, and the third direction is parallel to the substrate and orthogonal to the second direction. The memory array of this application can be applied to vertical word line (VWL) memory arrays.

[0018] In one possible implementation, the channel structure is made of metal-oxide-semiconductor (MOS) materials. MOS materials have low leakage current characteristics; by using MOS materials to fabricate the channel structure, leakage current can be significantly reduced, thereby increasing the retention time and reducing the refresh rate and power consumption.

[0019] A second aspect of the embodiments of this application provides a memory, the memory comprising: a memory array as described in any of the first aspects and a controller, the controller being electrically connected to the memory array and used to control the reading and writing of the memory array.

[0020] A third aspect of the embodiments of this application provides an electronic device, the electronic device comprising: a circuit board; a memory as described in the second aspect, wherein a processor is electrically connected to the circuit board.

[0021] A fourth aspect of this application provides a method for fabricating a memory array. The method includes: forming a plurality of memory layers, a first gate dielectric layer, and a first word line; the plurality of memory layers are spaced apart along a first direction, each memory layer including a channel structure, a bit line, and a capacitor; the channel structure surrounds a channel aperture, and the bit line and capacitor are distributed outside the channel structure; the bit line extends along a second direction, intersecting the first direction; the first word line extends along the first direction and is located outside the plurality of channel structures stacked along the first direction in the plurality of memory layers; the first gate dielectric layer is disposed between the first word line and the channel structure; a second gate dielectric layer and a second word line are formed; the second word line extends along the first direction and passes through the channel aperture of the plurality of channel structures stacked along the first direction in the plurality of memory layers, and the second gate dielectric layer is disposed between the second word line and the channel structure. The beneficial effects of the method for fabricating a memory array provided in the fourth aspect are the same as those of a memory array, and will not be repeated here.

[0022] In one possible implementation, forming multiple memory layers, a first gate dielectric layer, and a first word line includes: forming multiple intermediate layers including a sacrificial layer, a bit line, and a capacitor; the bit line and capacitor are located on the side of the sacrificial layer; forming a first gate dielectric layer and a first word line, the first word line being located outside the multiple sacrificial layers stacked along a first direction among the multiple intermediate layers; the first gate dielectric layer being located between the first word line and the sacrificial layer; and patterning the sacrificial layer to form a channel structure to form the memory layer. The first word line is formed before the channel structure; therefore, the formation of the first word line does not damage the channel structure, and a first gate dielectric layer and first word line with good gate control effect can be formed to ensure transistor performance.

[0023] In one possible implementation, the sheet resistance of the first word line is less than that of the second word line; and / or, the dielectric constant of the first gate dielectric layer is greater than that of the second gate dielectric layer; and / or, the physical thickness of the first gate dielectric layer is less than that of the second gate dielectric layer. Attached Figure Description

[0024] Figure 1 An architectural diagram of an electronic device provided in an embodiment of this application;

[0025] Figure 2 A schematic diagram of the structure of a memory provided in an embodiment of this application;

[0026] Figures 3A-3C A schematic diagram illustrating a packaging method for a storage array and a controller provided in an embodiment of this application;

[0027] Figure 4 An architecture diagram of a memory provided for an embodiment of this application;

[0028] Figure 5 A circuit diagram of a storage cell provided in an embodiment of this application;

[0029] Figure 6 An embodiment provided in this application Figure 5 The circuit diagram shown depicts the memory cells arranged in an array.

[0030] Figure 7 A schematic diagram of the equivalent structure of a storage array provided in an embodiment of this application;

[0031] Figure 8A This is a schematic diagram of the structure of a storage array provided in an embodiment of this application;

[0032] Figure 8B This is a top view schematic diagram of a storage array provided in an embodiment of this application;

[0033] Figure 9This is a schematic diagram of the structure of a storage array provided in an embodiment of this application;

[0034] Figure 10 This is a schematic diagram of the fabrication process of a storage array provided in an embodiment of this application;

[0035] Figures 11A-11O This is a schematic diagram illustrating the fabrication process of a storage array, as provided in an embodiment of this application.

[0036] Figure 12 An embodiment provided in this application Figure 11O Figure (a) is a sectional view along the C-C' direction;

[0037] Figures 13A-13C A top view of a storage unit provided in an embodiment of this application;

[0038] Figures 14A-14G for Figure 13A A cross-sectional view along the A-A' direction. Detailed Implementation

[0039] The technical solutions of the embodiments of this application will be described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments.

[0040] This application provides an electronic device, which may include consumer electronics, home electronics, automotive electronics, financial electronics, servers, workstations, etc. Consumer electronics include mobile phones, tablets, laptops, e-readers, personal computers (PCs), personal digital assistants (PDAs), desktop monitors, smart wearables (e.g., smartwatches, smart bracelets), virtual reality (VR) electronic devices, augmented reality (AR) electronic devices, drones, etc. Home electronics include smart door locks, televisions, refrigerators, and small rechargeable household appliances (e.g., soymilk makers, robot vacuum cleaners), etc. Automotive electronics include car navigation systems, car DVDs, etc. Financial electronics include ATMs and self-service electronic devices, etc.

[0041] Figure 1 This is an architectural diagram of an electronic device provided in an embodiment of this application.

[0042] like Figure 1As shown, the electronic device 100 may include a bus 203 and a system-on-chip (SOC) connected to the bus 203. The SOC can be used to process data, such as processing application data, processing image data, and caching temporary data.

[0043] In some embodiments, the SOC may include an application processor (AP) 211 for processing applications, a graphics processing unit (GPU) 212 for processing image data, and random access memory (RAM) 213 for caching high-speed data. The RAM 213 may be static random access memory (SRAM) or embedded flash (eflash), etc. The AP 211, GPU 212, and RAM 213 may be integrated into a single die or disposed in multiple dies.

[0044] For example Figure 1 As shown, the electronic device 100 may also include a memory 300 connected to the SOC via a bus 203. This memory 300 may be dynamic random access memory (DRAM). The memory 300 can be used to store volatile data, such as temporary data generated by the SOC. The storage capacity of the memory 300 is typically larger than that of RAM 213, but its read speed is typically slower.

[0045] In addition, the electronic device 100 may also include a communication chip 201 and a power management chip 202 connected to the SOC via a bus 203. The communication chip 201 may be used for protocol stack processing, or for amplifying, filtering, or performing other processing on analog radio frequency signals, or simultaneously performing the above functions. The power management chip 202 may be used to supply power to other chips. In some embodiments, the SOC and the memory 300 may be packaged in a single package structure, such as using a 2.5-dimensional (D) or three-dimensional (3D) package, to achieve faster inter-chip data transfer rates and reduce chip footprint.

[0046] The electronic device 100 may also include a circuit board, and the aforementioned memory 300, SOC, communication chip 201 and power management chip 202 and other structures can all be electrically connected to the circuit board.

[0047] Figure 2This is a schematic diagram of the structure of a memory provided in an embodiment of this application.

[0048] like Figure 2 As shown, the memory 300 includes a memory array 31 and a controller 32 for accessing the memory array 31. The controller 32 is used to control the read and write operations of the memory array 31.

[0049] Figure 2 The storage array 31 and controller 32 shown have a variety of implementable packaging structures, for example, several implementable packaging structures are given below.

[0050] Figures 3A-3C This is a schematic diagram illustrating a packaging method for a storage array and a controller provided in an embodiment of this application.

[0051] In some embodiments, such as Figure 3A As shown, the memory array 31 and the controller 32 are two independent chips, which are integrated on the substrate 33. For example, the memory array 31 and the controller 32 can be electrically connected through metal traces laid on the substrate 33. In this structure, since the memory array 31 and the controller 32 are two independent chips, the memory array 31 can be referred to as a stand-alone memory.

[0052] In other embodiments, such as Figure 3B As shown, the storage array 31 and the controller 32 are two independent chips, as described above. Figure 3A The difference is that, in Figure 3B In this configuration, the memory array 31 and the controller 32 are stacked. For example, the memory array 31 and the controller 32 can be connected via through-silicon vias (TSVs) or redistribution layers (RDLs). In this structure, the memory array 31 can also be referred to as an independent memory.

[0053] In some other embodiments, such as Figure 3C As shown, the memory array 31 and the controller 32 are integrated into the same chip 3, which is integrated onto a substrate 33. Therefore, this memory array 31 can be referred to as an embedded memory. Figure 3CIn the structure shown, the controller 32 can be integrated on the substrate via a front-end-of-line (FEOL) process, while the interconnects and memory array are integrated on the controller 32 via a back-end-of-line (BEOL) process. The controller 32 can generate control signals, which can be read / write control signals used to control read / write operations on data in the memory array 31. Alternatively, the controller 32 may also include analog circuitry, such as a sensitive amplifier.

[0054] The aforementioned memory array 31 can be a single memory layer or multiple memory layers stacked in a direction perpendicular to the substrate. When it contains two or more memory layers, such a memory 300 can be referred to as a three-dimensional integrated memory structure to increase storage capacity.

[0055] Figure 4 This is an architecture diagram of a memory provided in an embodiment of this application.

[0056] In some embodiments, such as Figure 4 As shown, the storage array 31 may include multiple arrayed storage cells 400, each of which can store 1 bit or more bits of data. The storage array 31 may also include word lines (WL) and bit lines (BL). Each storage cell 400 is electrically connected to a corresponding word line (WL) and bit line (BL). Different storage cells 400 can be electrically connected via word lines (WL) and bit lines (BL). One or more of the aforementioned word lines (WL) and bit lines (BL) are used to select the storage cell 400 in the storage array 31 that is waiting to be read or written, by receiving a control level output from the control circuit, thereby realizing data read and write operations.

[0057] The controller 32 in the memory 300 may include Figure 4 The circuit structure shown includes one or more of the following: decoder 321, driver 322, timing controller 323, buffer 324, or input / output driver 325.

[0058] exist Figure 4In the memory 300 structure shown, decoder 321 decodes the received address to determine the memory cell 400 to be accessed. Driver 322 controls the level of signal lines based on the decoding result generated by decoder 321, thereby enabling access to the specified memory cell 400. Buffer 324 buffers read data, for example, using a first-in-first-out (FIFO) buffering method. Timing controller 323 controls the timing of buffer 324 and controls driver 322 to drive the signal lines in memory array 31. Input / output driver 325 drives transmission signals, such as driven received data signals and driven data signals to be sent, enabling long-distance transmission of data signals.

[0059] The aforementioned memory array 31, decoder 321, driver 322, timing controller 323, buffer 324, and input / output driver 325 can be integrated into one chip or into multiple chips respectively.

[0060] In some examples, memory 300 may be electrically connected to a processor (e.g., a system-on-a-chip) in electronic device 100, and memory 300 is used to store data generated by the processor.

[0061] The memory 300 involved in this application embodiment can be dynamic random access memory (DRAM). For example, it can be a DRAM including 1T1C memory cells. T represents a transistor, and C represents a capacitor.

[0062] Figure 5 This is a circuit diagram of a storage unit provided in an embodiment of this application.

[0063] like Figure 5 As shown, in some embodiments, the memory cell 400 belongs to a 1T1C memory cell structure, that is, a memory cell 400 includes a transistor Tr and a capacitor C.

[0064] The first electrode of transistor Tr is electrically connected to the bit line (BL), the second electrode of transistor Tr is electrically connected to the first capacitor electrode of capacitor C, and the gate of transistor Tr is electrically connected to the word line (WL). The second capacitor electrode of capacitor C is electrically connected to the plate line (PL).

[0065] In the embodiments involved in this application, such as those described above. Figure 5The transistor Tr shown can be an NMOS (N-channel metal oxide semiconductor) transistor.

[0066] Furthermore, in the embodiments involved in this application, one of the drain or source terminals of the transistor Tr is called the first terminal, and the corresponding other terminal is called the second terminal. The control terminal of the transistor is the gate. The drain and source terminals of the transistor can be determined according to the direction of current flow.

[0067] Figure 6 An embodiment provided in this application Figure 5 The circuit diagram shown depicts memory cells arranged in an array.

[0068] like Figure 6 As shown, the gates of transistors Tr in a plurality of memory cells 400 arranged in the same direction can be electrically connected to the same word line WL, the first electrodes of transistors Tr in a plurality of memory cells 400 arranged in the same direction can be electrically connected to the same bit line BL, and the second capacitor electrodes of these plurality of capacitors C can be electrically connected to the same plate line PL. The plate line PL can, for example, be electrically connected to a reference ground voltage terminal.

[0069] DRAM is widely used in the memory of electronic devices. With the development of chip technology, DRAM, like processors, is constantly being miniaturized to improve density and storage performance. 3D DRAM is an important direction for the future evolution of DRAM in the industry. By changing the 1T1C memory cell 400 of DRAM from a single layer to a multi-layer stacked structure, it breaks through the bottleneck of horizontal miniaturization limited by photolithography size.

[0070] Figure 7 This is a schematic diagram of the equivalent structure of a storage array provided in an embodiment of this application.

[0071] In some embodiments, such as Figure 7 As shown in the embodiment of this application, the storage array 31 includes multiple storage layers, and these multiple storage layers are spaced apart along a first direction. For example, an electrically isolated dielectric layer is provided between adjacent storage layers to electrically isolate the adjacent storage layers.

[0072] The first direction can be parallel to the substrate or perpendicular to it. This embodiment illustrates the case where the first direction is perpendicular to the substrate (direction Z). The second direction Y and the third direction X are both parallel to the substrate. The first direction Z, the second direction Y, and the third direction X intersect each other (e.g., perpendicularly).

[0073] The memory cells 400 in the memory array 31 are arranged in a three-dimensional array, for example. Each memory layer may include multiple memory cells 400 arranged in an array, with the memory cells 400 in different memory layers overlapping in the first direction Z. The memory array 31 can be integrated onto the substrate 100 through a back-end process. This improves memory density and performance. The memory array 31 provided in this embodiment may or may not include a substrate. This embodiment only illustrates a memory array 31 including a substrate and does not constitute a limitation on the embodiments of this application.

[0074] Traditional silicon (Si)-based DRAM memory cells 400 experience increasing power consumption with increasing density. By using oxide semiconductors to fabricate the transistors Tr in the 1T1C memory cell 400, leakage current can be significantly reduced, thereby increasing the retention time, which in turn reduces refresh frequency and power consumption. Therefore, 3D DRAM based on oxide semiconductor channel materials is an important technology for future DRAM architectures.

[0075] Figure 8A This is a schematic diagram of a storage array provided in an embodiment of this application. Figure 8B This is a top view schematic diagram of a storage array provided in an embodiment of this application.

[0076] This application provides a memory array 31 based on a metal-oxide-semiconductor transistor Tr, such as... Figure 8A As shown, the memory array 31 is a device structure with a mirrored dual-gate configuration. The two mirrored gate electrodes are electrically interconnected and can be equivalent to a single-gate device. The two ends of the channel structure CH along the second direction Y are the first source / drain electrodes and the second source / drain electrodes of a transistor, respectively. The first source / drain electrode of the transistor is electrically connected to the bit line BL, and the second source / drain electrode of the transistor is electrically connected to the capacitor C. Two first word lines WL1 are mirrored on the outer side of the channel structure CH, and these two first word lines WL1 serve as the gate structure of the memory cell. Figure 8B As shown, based on Figure 8A The structure shown will have non-gate-controlled channel (extension) regions. Figure 8B (The area marked by the dashed ellipse in the middle). Because the two first word lines WL1 and the bit line BL, and the two first word lines WL1 and the capacitor C need to be insulated from each other and cannot have large parasitic capacitances, the length of the extension area cannot be arbitrarily reduced.

[0077] Semiconductor materials typically have high resistivity without gate control. Since the extension region is ungate-controlled, it introduces additional parasitic resistance when the device is on, thus limiting the on-state current of the memory cell. In planar memory arrays, the resistivity of the extension region can be altered by doping to reduce parasitic resistance. However, in three-dimensional memory arrays, the extension region is incompatible with doping processes, meaning that doping methods cannot reduce the parasitic resistance of the extension region in a three-dimensional memory array. This, in turn, leads to a decrease in the on-state current of the memory cell, affecting the performance of the memory array 31.

[0078] like Figure 8B As shown, based on Figure 8A In the structure shown, the bit line BL contacts the channel structure CH, and the capacitor C contacts the channel structure CH, forming two contact regions respectively. Figure 8B (The area within the dashed rectangle).

[0079] The contact resistance between semiconductor materials and metal electrodes is typically high. In planar memory arrays, the contact resistance can be reduced by doping or by applying gate control. However, in three-dimensional memory arrays, the contact area is incompatible with doping processes, making it impossible to reduce the contact resistance of the contact area using doping methods. Furthermore, since the contact area is not gate-controlled, the contact resistance is higher, limiting the on-state current of the memory cells and consequently reducing it, thus affecting the performance of the memory array 31.

[0080] Figure 9 This is a schematic diagram of a storage array provided in an embodiment of this application. Figure 10 This is a schematic diagram illustrating the fabrication process of a storage array provided in an embodiment of this application. Figures 11A-11O This is a schematic diagram illustrating the fabrication process of a storage array according to an embodiment of this application. Figure 11A For example, Figure 11A Figure (a) is a top view. Figure 11A Figure (b) is a cross-sectional view along the A-A' direction in Figure (a). Figure 11A Figure (c) is a cross-sectional view along the B-B' direction in Figure (a). Figures 11B-11O The same applies to (a), (b), and (c) in the example.

[0081] This application also provides a storage array and a method for its fabrication, such as... Figure 9 As shown, the memory array includes multiple memory layers, bit lines BL, and a first word line WL1.

[0082] Multiple memory layers are spaced apart along a first direction Z. Each memory layer includes a channel structure CH, a bit line BL, and a capacitor C. The channel structure CH has a channel aperture c. The bit line BL and the capacitor C are distributed outside the channel structure CH. The extension direction of the bit line BL intersects the first direction Z.

[0083] The side of the channel structure CH that encloses the channel hole c can be understood as the inner side of the channel structure CH, and the inner contour of the channel structure CH is the contour of the channel hole c. The outer side of the channel structure CH is opposite to the inner side of the channel structure CH, and the side of the channel structure CH that is away from the channel hole c is the outer side of the channel structure CH.

[0084] The first word line WL1 extends along the first direction Z and is located outside the multiple channel structures CH stacked along the first direction Z in the multiple memory layers. The second word line WL2 extends along the first direction Z and passes through the channel holes c enclosing the multiple channel structures CH stacked along the first direction Z in the multiple memory layers.

[0085] The memory array 31 includes multiple memory cells 400. Each memory cell 400 includes a channel structure CH, a bit line BL on the outside of the channel structure CH, a first word line WL1, a capacitor C, and a second word line WL2 on the inside of the channel structure CH. The multiple memory cells 400 can be arranged in a three-dimensional array.

[0086] like Figure 10 As shown, the method for fabricating a storage array includes:

[0087] S10 forms bit line BL, capacitor C, first gate dielectric layer 313, first word line WL1 and channel structure CH.

[0088] For example, step S10 includes:

[0089] S11, forming multiple intermediate layers including a sacrificial layer, bit line BL, and capacitor C.

[0090] For example, step S11 includes:

[0091] S111, such as Figure 11A As shown, a multilayer electrically isolated dielectric layer 311 and a multilayer sacrificial layer 312 are formed on one side of the substrate.

[0092] For example, an electrically insulating dielectric layer 311 and a sacrificial layer 312 can be formed on one side of the substrate using a deposition process, with multiple layers of electrically insulating dielectric layer 311 and multiple layers of sacrificial layer 312 arranged alternately. For instance, the multiple layers of electrically insulating dielectric layer 311 and multiple layers of sacrificial layer 312 are arranged alternately along a first direction Z perpendicular to the substrate. Figure 11A The example shown is a three-layer sacrificial layer 312 and a four-layer electrically isolated dielectric layer 311 formed on a substrate.

[0093] The substrate can be formed of or comprise semiconductor materials. For example, the substrate can be a single-crystal silicon wafer or a silicon-on-insulator (SOI) wafer. It is understood that other film layers (such as etch stop layers) may also be included between the substrate and the electrically isolating dielectric layer 311, but this application embodiment does not limit this. During the fabrication of the memory array, film layers can be added or removed based on the film layer structure illustrated in the application embodiment; this application embodiment does not constitute a limitation on the implementation of this application.

[0094] The material of the electrical isolation dielectric layer 311 includes various insulating materials, such as oxides, nitrides, and carbon oxides, like silicon oxide (SiO2). x ), silicon nitride (Si x N y ), silicon dioxide (Si) x O y C z ), Hafnium oxide (HfO) x ), Hafnium silicon oxide (Hf) x Si y O z ), aluminum oxide (Al) x O y One or more of gallium oxide (GaO), etc.

[0095] The material of the sacrificial layer 312 may include an insulating material different from that of the electrically insulating dielectric layer 311, for example, including oxides, nitrides, carbon oxides, such as SiO2. x Si x N y Si x O y C z HfO x ), Hf x Si y O z Al x O y One or more of GaO, etc. The material of the sacrificial layer 312 may also include semiconductor materials such as polysilicon (poly-Si).

[0096] S112, such as Figure 11B As shown, the multilayer electrical isolation dielectric layer 311 and the multilayer sacrificial layer 312 are patterned to form the region where the bit line is to be formed.

[0097] For example, the area of ​​bit line BL is defined by photolithography, a deep hole / deep trench is formed by etching process, a portion of sacrificial layer 312 is laterally etched by selective etching method, and finally, in the area where bit line is to be formed, sacrificial layer 312 is recessed relative to electrical isolation dielectric layer 311.

[0098] S113, such as Figure 11C As shown, bit line BL is formed in the region where bit lines are to be formed.

[0099] For example, a deposition process can be used to form conductive portions in the area where bit lines are to be formed. Subsequently, photolithography and etching methods can be used to retain the portions of the conductive portions located between adjacent electrically insulating dielectric layers 311 as bit lines BL. The bit lines BL in each layer are separated, and filling portions are formed to fill the gaps. The material of the filling portion can be any insulating material, and the material of the filling portion can be the same as or different from the material of the electrically insulating dielectric layer 311.

[0100] Bit line BL is located on the side of sacrificial layer 312, and bit line BL may contact the side of sacrificial layer 312, for example. The extension direction of bit line BL may be parallel to the substrate, for example, bit line BL may extend along a third direction X. Bit line BL may be a single-layer structure or a multilayer structure.

[0101] The material of the bit line BL is a conductive material, such as a metal, oxide, or nitride. In alternative embodiments, the material of the bit line BL can be nickel-platinum alloy (NiPt), titanium nitride (TiN), tantalum nitride (TaN), titanium (Ti), gold (Au), tungsten (W), molybdenum (Mo), aluminum (Al), copper (Cu), ruthenium (Ru), silver (Ag), nickel (Ni), tungsten silicide (WSi2), or cobalt silicide (CoSi). x ), titanium silicide (Ti x Si y One or more of conductive materials such as indium tin oxide (ITO).

[0102] S114, such as Figure 11D As shown, the multilayer electrical isolation dielectric layer 311 and the multilayer sacrificial layer 312 are patterned to form the region of the capacitor to be formed.

[0103] For example, the region of capacitor C is defined by photolithography, a deep hole / deep trench is formed by etching process, and then a portion of the sacrificial layer 312 is etched laterally by selective etching method, with the sacrificial layer 312 being recessed relative to the electrically isolating dielectric layer 311.

[0104] S115, such as Figure 11E As shown, capacitor C is formed in the region where the capacitor is to be formed.

[0105] For example, a deposition process can be used to form a conductive portion in the area where a capacitor is to be formed. Then, the portion of the conductive portion located between adjacent electrically insulating dielectric layers 311 can be retained by photolithography and etching to serve as the first capacitor electrode SN of the capacitor C. The first capacitor electrodes SN in each layer are separated.

[0106] Next, a dielectric portion is formed in the area where the capacitor is to be formed. Then, the portion of the dielectric portion located between adjacent electrically isolated dielectric layers 311 is retained by photolithography and etching to serve as the capacitor dielectric layer DL of the capacitor C. The capacitor dielectric layers DL in each layer are separated.

[0107] Next, a conductive portion is formed in the area where the capacitor is to be formed, and the conductive portion serves as the second capacitor electrode PL of each layer of capacitor C. Then, the capacitors C in adjacent layers are coupled to each other.

[0108] In capacitor C, both the first capacitor electrode SN and the second capacitor electrode PL are made of conductive materials. The selection of materials for the first capacitor electrode SN and the second capacitor electrode PL can refer to the selection of materials for the bit line BL described above. The material for the capacitor dielectric layer DL can, for example, include materials with high density and high dielectric constant (K) values. The material for the capacitor dielectric layer DL can include SiO₂. x Si x N y Al x O y Hafnium oxide (HfO) x Zirconium oxide (ZrO) x Titanium oxide (TiO) x ), Yttrium oxide (Y) x O y ), Hafnium aluminum oxide (HfAlO) x Insulating materials such as Hf can also be used for the capacitor dielectric layer DL. x Al y O z Hafnium silicon oxide (Hf) x Si y O z ), Hafnium Zirconium Oxide (Hf x Zr y O z ), Hafnium Lanthanum Oxide (Hf x La y O z ), Hafnium Yttrium Oxygen (Hf x Y y O z Ferroelectric materials such as ferroelectric materials.

[0109] Capacitor C is located on the side of sacrificial layer 312; for example, bit line BL and capacitor C are located on opposite sides of sacrificial layer 312. The structure of capacitor C in this application embodiment is not limited; the structures of capacitor C in related technologies are applicable to the embodiments of this application. Figure 11E This is just an illustration.

[0110] By performing the above steps S111-S115, multiple intermediate layers including a sacrificial layer 312, a bit line L, and a capacitor C can be formed.

[0111] S12, forming the first gate dielectric layer 313 and the first word line WL1.

[0112] S121, such as Figure 11F As shown, the multilayer electrical isolation dielectric layer 311 and the multilayer sacrificial layer 312 are patterned to form the area where the first word line is to be formed.

[0113] For example, the region of the first word line WL1 is defined by photolithography, a deep hole / deep trench is formed by etching process, a portion of the sacrificial layer 312 is laterally etched by selective etching method, and finally, in the region where the first word line is to be formed, the sacrificial layer 312 is recessed relative to the electrically isolated dielectric layer 311.

[0114] S122, such as Figure 11G As shown, a first gate dielectric layer 313 is formed.

[0115] The first gate dielectric layer 313 may only cover the side surface of the sacrificial layer 312, or it may cover the side surface of both the sacrificial layer 312 and the electrically isolated dielectric layer 311, as long as the first gate dielectric layer 313 is present between the subsequently formed first word line WL1 and the sacrificial layer 312 (the subsequently formed channel structure CH). Figure 11G This is for illustrative purposes only.

[0116] S123, such as Figure 11H As shown, the first character line WL1 is formed.

[0117] For example, a conductive portion is formed in the area where the first word line is to be formed, and the conductive portion serves as the first word line WL1 of each layer. Then, the first word lines WL1 in adjacent layers are coupled to each other.

[0118] For example, the first word line WL1 extends along a first direction Z perpendicular to the substrate (through the multilayer electrically insulating dielectric layer 311 and the multilayer sacrificial layer 312). The first word line WL1 is located outside of a plurality of sacrificial layers 312 located in the same row (e.g., a vertical column) along the first direction Z in a plurality of intermediate layers.

[0119] The first word line WL1 can be a single-layer structure or a multi-layer structure, as long as the first word line WL1 is a conductive structure.

[0120] In some embodiments, the storage array 31 may include only one first word line WL1. This reduces the footprint of a single storage cell and increases storage density.

[0121] The storage array may also include multiple first word lines (WL1), with the multiple first word lines (WL1) spaced apart. For example... Figure 11H As shown, the storage array includes two first word lines WL1, which are arranged opposite to each other.

[0122] The first word line WL1 is equivalent to the first gate of transistor Tr. By setting multiple first word lines WL1 in the memory array 31, the equivalent width of the first word line WL1 is increased, which is equivalent to increasing the width of the equivalent first gate of transistor Tr, thereby increasing the drive current of transistor Tr and improving the read and write speed of memory array 31.

[0123] S124. The outer gate dielectric and metal of the area on the surface where the first word line is to be formed are removed by photolithography-etching or chemical mechanical polishing (CMP) to expose the electrical isolation dielectric layer 311 on the surface.

[0124] S13. Patterned sacrificial layer to form a channel structure to form a storage layer.

[0125] For example, step S13 includes:

[0126] S131, such as Figure 11I As shown, the multilayer electrical isolation dielectric layer 311 and the multilayer sacrificial layer 312 are patterned to form a first deep hole.

[0127] For example, the region of the first deep hole is defined by photolithography, and the first deep hole is formed by etching. This application does not limit the shape of the first deep hole; any closed pattern is acceptable.

[0128] S132, such as Figure 11J As shown, the sacrificial layer 312 is selectively etched to form a horizontal trench.

[0129] The horizontal trench exposes the bit line BL, the first capacitor electrode SN, and the first gate dielectric layer 313, and the horizontal trench is connected to the first deep hole.

[0130] For example, by selective etching, the sacrificial layer 312 is etched laterally to expose the exposure bit line BL, the first capacitor electrode SN, and the first gate dielectric layer 313.

[0131] S133, such as Figure 11K As shown, trench material is filled into the horizontal excavation trench.

[0132] For example, a deposition process can be used to fill the transverse trench with channel material. The channel material fills the transverse trench and extends into the first deep hole; this embodiment is merely illustrative. The outer side of the channel material contacts the bit line BL, the first capacitor electrode SN, and the first gate dielectric layer 313, respectively.

[0133] Channel materials include, for example, oxide semiconductor materials. These materials can contain elements such as In, Ga, Zn, Sn, W, Mg, Al, and Si. Examples of such channel materials include indium gallium zinc oxide (InGaZnO, IGZO), indium tin oxide (InSnO), indium gallium oxide (InGaO), and indium magnesium oxide (InMgO). Oxide semiconductor materials have low leakage current characteristics; using these channel materials can reduce the leakage current of the memory array, thereby reducing power consumption and optimizing performance.

[0134] Channel materials can also include amorphous structures. Channel materials can also include partially crystalline structures, such as polycrystalline IGZO (poly-IGZO) and IGZO with novel crystal structures (CAAC-IGZO). Channel materials can also include monocrystalline silicon, polycrystalline silicon (poly-Si, p-Si), and amorphous silicon (amorphous-Si, a-Si).

[0135] S134, such as Figure 11L As shown, the channel material is partitioned to form the channel structure CH.

[0136] After performing step S134, the memory layer in the memory array can be obtained. The memory layer includes a channel structure CH, a bit line BL, and a capacitor C. The channel structure CH surrounds a channel hole c, and the bit line BL and the capacitor C are distributed on the outside of the channel structure CH.

[0137] The memory array includes multiple memory layers spaced apart along a first direction Z. For example, an electrically insulating dielectric layer 311 is disposed between adjacent memory layers. The extension direction of the bit line BL intersects the first direction Z, which can be perpendicular to or parallel to the substrate. Figure 11L This is just one example.

[0138] The bit line BL, capacitor C, and first word line WL1 are all disposed outside the channel structure CH. This application does not limit the outline shape of the channel structure CH, nor does it limit the distribution of the bit line BL, capacitor C, and first word line WL1 outside the channel. Figure 11L This is just one example.

[0139] S20, forming the second gate dielectric layer 314 and the second word line WL2.

[0140] For example, step S20 includes:

[0141] S21, such as Figure 11M As shown, a second gate dielectric layer 314 is formed.

[0142] For example, a deposition process can be used to form the second gate dielectric layer 314, and the material selection for the second gate dielectric layer 314 can refer to the material selection for the first gate dielectric layer 313 described above.

[0143] In some embodiments, the dielectric constant K of the first gate dielectric layer 313 is greater than the dielectric constant K of the second gate dielectric layer 314. Since the deposition process of materials with a smaller dielectric constant K causes less damage to the channel structure CH than materials with a higher dielectric constant K, reducing the dielectric constant K of the second gate dielectric layer 314 can reduce the damage to the channel during the subsequent formation of the second word line WL2, thereby improving the electrical performance and reliability of the memory array 41. With the same physical thickness, materials with a smaller dielectric constant K have a higher equivalent thickness. That is, in some embodiments, the equivalent thickness of the second gate dielectric layer 314 is greater than the equivalent thickness of the first gate dielectric layer 313.

[0144] In some embodiments, the physical thickness of the second gate dielectric layer 314 is greater than the physical thickness of the first gate dielectric layer 313. By increasing the physical thickness of the second gate dielectric layer 314, the channel structure CH can be protected, reducing the damage to the channel caused by the deposition process during the subsequent formation of the second word line WL2, and improving the electrical performance and reliability of the memory array 41.

[0145] S22, such as Figure 11N As shown, the second character line WL2 is formed.

[0146] For example, a deposition process can be used to form the second character line WL2. The material of the second character line WL2 can be a different conductive material than the first character line WL1. The material type of the second character line WL2 can be referred to the description of the material type of the first character line WL1 above.

[0147] A second word line WL2 is formed within the channel via c of the channel structure CH. The second word line WL2 extends along the first direction Z and passes through the channel via c of the multiple channel structures CH stacked along the first direction Z in the multiple memory layers. The second word line WL2 can be equivalent to the second gate of the transistor Tr. In the memory array 31, the transistor Tr is a dual-gate controlled transistor.

[0148] The second letter WL2 can be a columnar structure or a U-shaped structure. Figure 11N This is for illustrative purposes only.

[0149] S23. The gate dielectric and metal on the surface are removed by photolithography-etching or CMP to expose the surface electrical isolation dielectric layer 311.

[0150] In some embodiments, the preparation method further includes:

[0151] S30, such as Figure 11O As shown, a filling layer 315 is formed in the channel hole c of the channel structure CH.

[0152] For example, a filling layer 315 is formed using a deposition process, and the material selection for the filling layer 315 can refer to the material selection for the electrically insulating dielectric layer 311 described above. The filling layer 315 is disposed on the surface of the second word line WL2, and for example, it can fill the channel holes c of the channel structure CH.

[0153] In the memory array 31, the two sides of the channel structure CH are in contact with the bit line BL and the memory device C, respectively, forming the source and drain of the transistor Tr. The first word line WL1 is located outside the channel structure CH, serving as the first control gate of the transistor Tr. The second word line WL2 is located inside the channel structure CH, serving as the second control gate of the transistor Tr. The first and second control gates can be electrically interconnected or independent. The memory array 31 includes a dual-gate transistor structure, where the transistor Tr is connected to the first capacitor electrode SN of the capacitor C, forming a 1T1C memory cell 400. Figure 11O As shown, in each layer, there is an in-situ sacrificial layer for insulation between the bit line BL and the first word line WL1, and between the first word line WL1 and the capacitor C. In adjacent layers, there is also an electrically insulating dielectric layer 311 for insulation between the bit lines BL of each layer.

[0154] Figure 12 An embodiment provided in this application Figure 11O Figure (a) is a cross-sectional view along the C-C' direction.

[0155] Combination Figure 11O and Figure 12 As shown, in the storage array 31, a portion of the outer region of the channel structure CH corresponds to the first word line WL1, but the inner side of the channel structure CH is surrounded by a second word line WL2. For the channel structure CH, the extension region corresponding to the first word line WL1 is controlled by the second word line WL2.

[0156] The memory array 31 provided in this application embodiment provides a first word line WL1 (first gate) on the outside of the channel structure CH and a second word line WL2 (second gate) on the inside of the channel structure CH, so that the channel structure CH is jointly controlled by the first word line WL1 and the second word line WL2. Although the first word line WL1 can only control the portion of the channel structure CH corresponding to the first word line WL1, the region of the channel structure CH that does not correspond to the first word line WL1 and does not contact the bit line BL and capacitor C (extension region) is not controlled by the first word line WL1, resulting in a large parasitic resistance in the transistor Tr in the extension region. Simultaneously, the region of the channel structure CH that contacts the bit line BL and capacitor C (contact region) is also not controlled by the first word line WL1, and the contact between the undoped and ungate-controlled channel material and the electrode typically has a high contact resistance. However, the second word line WL2 passes through the channel hole c and is located inside the channel structure CH, allowing the second word line WL2 to control the entire channel structure CH. For the channel structure CH, the gateless extension region and gateless contact region corresponding to the first word line WL1 can be controlled by the second word line WL2, thereby reducing the parasitic resistance and contact resistance of the transistor Tr. That is, by changing the gate control, the parasitic resistance and contact resistance of the transistor Tr are reduced, increasing the drive current of the transistor Tr. In addition, there is an overlapping region between the first word line WL1 and the second word line WL2. This region is jointly controlled by the inner and outer word lines, which can further increase the drive current of the transistor Tr. Furthermore, at the overlapping position of the first word line WL1 and the second word line WL2, the electric field applied from the outside of the channel structure CH and the electric field applied from the inside of the channel structure CH will cancel each other out in the channel structure CH, which can reduce the electrical degradation caused by the electric field on the channel structure CH and improve the reliability of the transistor Tr. Thus, the goal of improving the electrical performance and reliability of the memory array 31 is achieved.

[0157] In some embodiments, the first word line WL1 and the second word line WL2 are insulated from each other.

[0158] In this way, the first word line WL1 and the second word line WL2 can receive the same control signal (e.g., read / write control signal), or the first word line WL1 and the second word line WL2 can receive different control signals (e.g., apply a separate signal to the second word line WL2 to regulate the threshold voltage of transistor Tr), further optimizing the performance of transistor Tr.

[0159] In other embodiments, the first word line WL1 and the second word line WL2 are interconnected. For example, the first word line WL1 and the second word line WL2 can be interconnected through a subsequent process.

[0160] This simplifies the signal routing of the storage array 31.

[0161] In some embodiments, the sheet resistance of the first word line WL1 is less than the sheet resistance of the second word line WL2. Sheet resistance refers to the resistance between edges of a square thin-film conductive material.

[0162] The sheet resistance of the first word line WL1 is less than that of the second word line WL2, therefore the signal conduction capability of the first word line WL1 is stronger than that of the second word line WL2. During the driving of the channel structure CH, the first word line WL1 serves as the main driving gate, and the second word line WL2 serves as the auxiliary driving gate. The thickness and material of the gate dielectric layer (here, the first gate dielectric layer 313) of the main driving gate determine the core performance of the transistor Tr. In this way, it is not necessary to pursue a thinner or higher dielectric constant second gate dielectric layer 314 to consider the driving capability of the second word line WL2. The physical thickness of the second gate dielectric layer 314 can be increased, or a material with a lower dielectric constant K can be used for the second gate dielectric layer 314 to reduce damage to the channel structure CH during the fabrication of the second word line WL2, thereby improving the electrical performance and reliability of the transistor Tr, and further enhancing the electrical performance and reliability of the memory array 31.

[0163] In some embodiments, the physical thickness of the first gate dielectric layer 313 is less than the physical thickness of the second gate dielectric layer 314.

[0164] Since a thinner gate dielectric layer results in better gate control, the physical thickness of the first gate dielectric layer 313 is less than that of the second gate dielectric layer 314. This makes the gate control of the channel structure CH by the first word line WL1 stronger than that by the second word line WL2. Therefore, the first word line WL1 acts as the main driving gate, and the second word line WL2 acts as the auxiliary driving gate. This eliminates the need for a thinner second gate dielectric layer 314 due to concerns about the driving capability of the second word line WL2. Increasing the physical thickness of the second gate dielectric layer 314 enhances channel protection, reducing damage to the channel structure CH during the fabrication of the second word line WL2 electrodes, improving the electrical performance and reliability of the transistor Tr, and further enhancing the electrical performance and reliability of the memory array 31.

[0165] In some embodiments, the dielectric constant K of the first gate dielectric layer 313 is greater than the dielectric constant K of the second gate dielectric layer 314.

[0166] Since a higher dielectric constant K results in better gate control, the dielectric constant K of the first gate dielectric layer 313 is greater than that of the second gate dielectric layer 314. This makes the gate control of the channel structure CH by the first word line WL1 stronger than that by the second word line WL2. Therefore, the first word line WL1 acts as the main driving gate, and the second word line WL2 acts as the auxiliary driving gate. This eliminates the need to use a second gate dielectric layer 314 with a higher dielectric constant K to compensate for the driving capability of the second word line WL2. Materials with lower dielectric constant K but less impact on the channel structure CH during fabrication can be used as the second gate dielectric to reduce damage to the channel structure CH during the fabrication of the second word line WL2, improving the electrical performance and reliability of the transistor Tr, and further enhancing the electrical performance and reliability of the memory array 31. Furthermore, with the same physical thickness, a smaller dielectric constant K results in a larger equivalent thickness. Equivalent thickness can be understood as equivalent oxide thickness (EOT), which is related to the dielectric constant and physical thickness of the dielectric material.

[0167] The memory array 41 provided in this application embodiment can be protected within the scope of this application embodiment if it satisfies one or more of the following three conditions, and is not limited to only one or all of them. The aforementioned three conditions include: the sheet resistance of the first word line WL1 is less than the sheet resistance of the second word line WL2; the physical thickness of the first gate dielectric layer 313 is less than the physical thickness of the second gate dielectric layer 314; and the dielectric constant K of the first gate dielectric layer 313 is greater than the dielectric constant K of the second gate dielectric layer 314.

[0168] Figures 13A-13C This is a top view of a storage unit provided in an embodiment of this application.

[0169] In some embodiments, such as Figure 13A As shown, each memory cell 400 in the memory array includes multiple first word lines WL1, which are spaced apart on the outside of the channel structure CH. Figure 13A The following is an illustration of a memory array where each memory cell 400 includes two first word lines WL1, with the two first word lines WL1 positioned on opposite sides of the channel structure CH.

[0170] By setting multiple first word lines WL1 on the outside of each channel structure CH, the gate width of the first word lines WL1 is increased, which further increases the drive current of transistor Tr and improves the read and write speed of transistor Tr.

[0171] In other embodiments, such as Figure 13B and Figure 13CAs shown, each storage cell 400 in the storage array includes a first word line WL1. This reduces the area occupied by the first word line WL1, which helps to increase the storage density of the storage array 41.

[0172] Regarding the channel structure CH, from the top view:

[0173] In some embodiments, such as Figure 13A As shown, the channel structure CH is a ring structure. For example, the channel structure CH can be a closed ring structure such as a circular ring, rectangular ring, triangular ring, or pentagonal ring. The inner ring of the channel structure CH forms a closed channel hole c.

[0174] In other embodiments, such as Figure 13B As shown, the channel structure CH is a non-ring structure.

[0175] For example, the channel structure CH is a U-shaped structure, and the U-shaped area enclosed by the channel structure CH is the aforementioned channel hole c. The bit line BL, the first word line WL1, and the capacitor C are respectively arranged on three sides of the channel structure CH.

[0176] In some embodiments, such as Figure 13B As shown, the channel structure CH is a non-circular structure, while the second word line WL2 is still a circular structure.

[0177] In other embodiments, such as Figure 13C As shown, the channel structure CH is a non-circular structure, and the second word line WL2 is also a non-circular structure.

[0178] In this embodiment, the shape of the channel structure CH and the second word line WL2 can be various. These are just some examples and not exhaustive.

[0179] Figures 14A-14G for Figure 13A A cross-sectional view along the A-A' direction.

[0180] Regarding the channel structure CH, from the cross-sectional view:

[0181] In some embodiments, such as Figure 14A and Figure 14B As shown, the first character line WL1 is planar on the side facing the channel structure CH.

[0182] In other embodiments, such as Figures 14C-14G As shown, the first character line WL1 has a recess on the side facing the channel structure CH, and part of the channel structure CH extends into the recess.

[0183] In this way, the first word line WL1 can overlap with all three surfaces of the channel structure CH, resulting in a large controllable area and good gate control effect.

[0184] In some embodiments, such as Figures 14A-14D As shown, the cross-section of the channel structure CH is a block structure.

[0185] For example, such as Figure 14A , Figure 14C , Figure 14D As shown, the second word line WL2 only overlaps with the outer surface of the channel structure CH.

[0186] Or, for example, Figure 14B As shown, the second word line WL2 overlaps with all three surfaces of the channel structure CH, resulting in a large controllable area and good gate control effect.

[0187] In other embodiments, such as Figures 14E-14G As shown, the cross-section of the channel structure CH is a groove-shaped structure.

[0188] For example, such as Figure 14E As shown, the second gate dielectric layer 314 is also a groove structure, and the second word line WL2 is formed in the groove. The second word line WL2 can overlap with the three surfaces of the channel structure CH. The controllable area of ​​the second word line WL2 is large and the gate control effect is good.

[0189] Or, for example, Figure 14F and Figure 14G As shown, the second gate dielectric layer 314 fills the groove of the channel structure CH, and the physical thickness of the portion of the second gate dielectric layer 314 in contact with the channel structure CH is greater than the physical thickness of the portion of the second gate dielectric layer 314 not in contact with the channel structure CH. This can improve the protective effect of the second gate dielectric layer 314 on the channel structure CH and reduce damage to the channel structure CH.

[0190] The second gate dielectric layer 314 can be a single-layer structure or a multi-layer structure. If the second gate dielectric layer 314 is a multi-layer structure, the materials used in the multi-layer structures can be different, for example.

[0191] Of course, such as Figures 14A-14E As shown, the physical thickness of the portion of the second gate dielectric layer 314 that contacts the channel structure CH can also be equal to the physical thickness of the other portions of the second gate dielectric layer 314 that do not contact the channel structure CH.

[0192] In some embodiments, such as Figures 14A-14C , Figure 14E , Figure 14F As shown, the second character line WL2 is a hollow columnar structure, and the filling layer 315 fills the hollow area of ​​the second character line WL2.

[0193] In other embodiments, such as Figure 14D As shown, the second character line WL2 is a solid columnar structure.

[0194] The above are merely specific embodiments of this application, but the scope of protection of this application is not limited thereto. Any changes or substitutions within the technical scope disclosed in this application should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

Claims

1. A memory array comprising: The memory array comprises: a plurality of memory layers, the plurality of memory layers being spaced apart along a first direction; the memory layer comprising a channel structure, a bit line and a capacitor; the channel structure enclosing a channel hole, the bit line and the capacitor being distributed outside the channel structure; the bit line extending along a second direction, the second direction intersecting the first direction; a first word line extending along the first direction and located outside a plurality of the channel structures stacked along the first direction in the plurality of memory layers; a first gate dielectric layer disposed between the first word line and the channel structure; a second word line extending along the first direction and penetrating the channel hole of a plurality of the channel structures stacked along the first direction in the plurality of memory layers; a second gate dielectric layer disposed between the second word line and the channel structure.

2. The storage array of claim 1, wherein, The sheet resistance of the first word line is less than the sheet resistance of the second word line.

3. The storage array of claim 1 or 2, wherein, The physical thickness of the first gate dielectric layer is less than the physical thickness of the second gate dielectric layer.

4. The storage array of any of claims 1-3, wherein, The dielectric constant of the first gate dielectric layer is greater than the dielectric constant of the second gate dielectric layer.

5. The storage array of any of claims 1-4, wherein, The physical thickness of the portion of the second gate dielectric layer in contact with the channel structure is greater than or equal to the physical thickness of other portions.

6. The storage array of any of claims 1-5, wherein, The first word line has a recess toward one side of the channel structure, and part of the channel structure extends into the recess.

7. The storage array of any of claims 1-6, wherein, The first word line and the second word line are insulated from each other.

8. The storage array of any of claims 1-7, wherein, The memory array comprises a plurality of the first word lines, the plurality of the first word lines being spaced apart outside the channel structure.

9. The storage array of any of claims 1-8, wherein, The first direction is perpendicular to the substrate.

10. The storage array of any of claims 1-9, wherein, The material of the channel structure comprises metal oxide semiconductor.

11. A memory, comprising: The memory array comprises: The memory array of any one of claims 1-10; a controller electrically connected to the memory array, the controller being configured to control reading and writing of the memory array.

12. An electronic device, comprising: The memory array comprises: a circuit board; The memory of claim 11, the circuit board being electrically connected to the memory.

13. A method of fabricating a memory array, comprising: The method for manufacturing comprises: forming a plurality of memory layers, a first gate dielectric layer and a first word line; the plurality of memory layers being spaced apart along a first direction; the memory layer comprising a channel structure, a bit line and a capacitor; the channel structure enclosing a channel hole, the bit line and the capacitor being distributed outside the channel structure; the bit line extending along a second direction, the second direction intersecting the first direction; the first word line extending along the first direction and located outside a plurality of the channel structures stacked along the first direction in the plurality of memory layers; the first gate dielectric layer being disposed between the first word line and the channel structure; forming a second gate dielectric layer and a second word line; the second word line extending along the first direction and penetrating the channel hole of a plurality of the channel structures stacked along the first direction in the plurality of memory layers, the second gate dielectric layer being disposed between the second word line and the channel structure.

14. The method of claim 13, wherein, forming a plurality of memory layers, a first gate dielectric layer and a first word line comprises: forming a plurality of intermediate layers comprising a sacrificial layer, the bit line and the capacitor; the bit line and the capacitor being located on the side of the sacrificial layer; forming the first gate dielectric layer and the first word line, the first word line is located outside of a plurality of the sacrificial layers stacked along the first direction in the plurality of intermediate layers; the first gate dielectric layer is located between the first word line and the sacrificial layer; patterning the sacrificial layer to form the channel structure to form the storage layer.

15. The manufacturing method of claim 13 or 14, wherein, a sheet resistance of the first word line is less than a sheet resistance of the second word line; and / or, a dielectric constant of the first gate dielectric layer is greater than a dielectric constant of the second gate dielectric layer; and / or, a physical thickness of the first gate dielectric layer is less than a physical thickness of the second gate dielectric layer.

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