Memory device and manufacturing method thereof
By forming isolation structures and word line trenches in DRAM memory cells and employing wet and dry etching processes, the problem of uneven landing area size between transistors and capacitors was solved, thereby achieving improved electrical connection stability and performance of the memory device.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-12-11
- Publication Date
- 2026-03-10
AI Technical Summary
In the prior art, the non-uniformity of the landing area size between the transistor and the capacitor in the DRAM memory cell is difficult to control, which affects the overlap and uniformity of the landing area and leads to a decrease in memory performance.
By forming isolation structures and character line trenches on the substrate, wet and dry etching processes are used to form protrusions extending from the substrate, and character line trenches are etched in different directions to ensure that the landing area between the active area and the capacitor is large enough. A double-layer isolation structure is used to enhance dimensional uniformity.
This improves the uniformity of the landing area size between transistors and capacitors, ensuring the stability of electrical connections and performance enhancement of memory devices.
Smart Images
Figure CN121645864A_ABST
Abstract
Description
Technical Field
[0001] This invention relates to a memory device and a method for manufacturing the same. Background Technology
[0002] A typical DRAM (Dynamic Random Access Memory) cell incorporates capacitors and transistors, where capacitors temporarily store data based on their state of charge. Transistors may contain active regions located in the substrate, and word lines are embedded in the substrate to control the transistors. Typically, active regions are formed by creating a hard mask with multiple stripes over the substrate, cutting the stripes into islands, and then etching the substrate through the island-shaped hard mask. During the cutting of the stripes into islands, the uniformity of island size is difficult to control. The loading effect of etching the substrate can also lead to different dimensions at the ends of the active regions. The factors mentioned above can affect the uniformity of the landing area size between the transistor and the capacitor, and the overlap between the word lines and the active region may also need to be considered. Therefore, a method is needed to enhance the uniformity of the landing area size between the transistor and the capacitor. Summary of the Invention
[0003] Some embodiments of the present invention provide a method for forming a memory device, comprising: etching a substrate to form a protrusion extending from the substrate; forming a first isolation structure above the substrate and on opposite sides of the protrusion; forming first, second, and third character line trenches that cut through the protrusion and the first isolation structure; forming sacrificial layers correspondingly in the first, second, and third character line trenches; removing a first portion of the sacrificial layer to expose the first and third character line trenches; etching the protrusion through the first and third character line trenches; removing a second portion of the sacrificial layer to expose a second character line trench; and forming first, second, and third character line structures correspondingly in the first, second, and third character line trenches.
[0004] In some embodiments, forming the first isolation structure includes forming a dielectric layer over a substrate and forming a second masking layer over the dielectric layer, wherein the second masking layer includes stripes extending longitudinally along a first direction; patterning the dielectric layer through the second masking layer; forming an isolation trench in the substrate by etching through the dielectric layer; and forming the first isolation structure in the isolation trench.
[0005] In some embodiments, the protruding portions are etched through the first and third character line trenches using a wet etching process.
[0006] In some embodiments, during the etching of the protrusions through the first and third character line trenches, the sidewalls of the first and third character line trenches are offset inward from the sidewalls of the dielectric layer.
[0007] In some embodiments, the method further includes forming a second isolation structure in the first and third character line trenches respectively before forming the first, second and third character line structures in the first, second and third character line trenches.
[0008] In some embodiments, forming a second isolation structure in the first and third character line trenches includes: forming a dielectric filling layer that overfills the first and third character line trenches; and forming the second isolation structure by etching the dielectric filling layer through the dielectric layer.
[0009] In some embodiments, the second isolation structure overlaps with the intersection portions of the first and third character line trenches and the protruding portions of the substrate.
[0010] In some embodiments, the second isolation structure divides the protruding portion of the substrate into active regions, and in a top view, each of the active regions intersects with the second character line structure.
[0011] In some embodiments, in a top view, the active region has two opposing sides, and the two opposing sides curve inward.
[0012] In some embodiments, before removing the first portion of the sacrificial layer to expose the first and third character line grooves, a second masking layer is formed having an opening that overlaps with the first portion of the sacrificial layer, and the diameter of one of the openings is 110% to 130% of the width of the top of one of the sacrificial layers.
[0013] Some embodiments of the present invention provide a memory device comprising a substrate, an isolation structure, and a word line structure. The isolation structure is embedded in the substrate, wherein the isolation structure defines an active region in the substrate. In a top view, the active region has a first sidewall and a second sidewall opposite to the first sidewall, and the first and second sidewalls are curved inward. The word line structure is embedded in the substrate.
[0014] In some embodiments, in a top view, the active region further has a third sidewall and a fourth sidewall opposite to the third sidewall, the third sidewall connecting the first sidewall and the second sidewall, the fourth sidewall connecting the first sidewall and the second sidewall, and the third sidewall and the fourth sidewall being substantially straight.
[0015] In some embodiments, the isolation structure includes a first isolation structure located on the opposite side of the active region in a first direction, and a second isolation structure correspondingly contacting the first sidewall and the second sidewall of the active region.
[0016] In some embodiments, the depth of the first isolation structure is different from the depth of the second isolation structure.
[0017] In some embodiments, the memory device further includes another character line structure embedded in the substrate and interfacing with one of the second isolation structures.
[0018] In some embodiments, another character line structure contacts one of the first isolation structures.
[0019] In some embodiments, the interface between another character line and one of the second isolation structures is adjacent to the interface between another character line structure and one of the first isolation structures.
[0020] In some embodiments, the character line structure includes a first conductive layer embedded in the active region and a gate dielectric layer located between the active region and the first conductive layer.
[0021] In some embodiments, the character line structure further includes a second conductive layer located above the first conductive layer, wherein the gate dielectric layer is located between the active region and the second conductive layer.
[0022] In some embodiments, the character line structure further includes a top cap layer located above the second conductive layer.
[0023] It should be understood that both the above-described invention and the following embodiments are illustrative examples and are intended to provide further explanation of the invention as claimed. Attached Figure Description
[0024] The invention can be more fully understood by reading the following detailed description of the embodiments and referring to the accompanying drawings: Figure 1 The circuit diagram of the memory device is shown.
[0025] Figure 2A A top view illustrating a method of manufacturing a memory device according to some embodiments of the present invention is shown.
[0026] Figure 2B It is drawn along Figure 2A A cross-sectional view taken along line A-A'.
[0027] Figure 2C It is drawn along Figure 2A A cross-sectional view taken along line B-B'.
[0028] Figure 3A A top view illustrating a method of manufacturing a memory device according to some embodiments of the present invention is shown.
[0029] Figure 3B It is drawn along Figure 3A A cross-sectional view taken along line A-A'.
[0030] Figure 3C It is drawn along Figure 3AA cross-sectional view taken along line B-B'.
[0031] Figure 4A A top view illustrating a method of manufacturing a memory device according to some embodiments of the present invention is shown.
[0032] Figure 4B It is drawn along Figure 4A A cross-sectional view taken along line A-A'.
[0033] Figure 4C It is drawn along Figure 4A A cross-sectional view taken along line B-B'.
[0034] Figure 5 It is illustrated Figures 4A to 4C A top view of the manufacturing method of the memory device after the process.
[0035] Figures 6 to 8 It is drawn along Figure 5 A cross-sectional view taken along line A-A'.
[0036] Figure 9 It is illustrated Figure 8 A top view of the manufacturing method of the memory device after the process.
[0037] Figures 10 to 13 It is drawn along Figure 9 A cross-sectional view taken along line A-A'.
[0038] Figure 14 It is illustrated Figure 13 A top view of the manufacturing method of the memory device after the process.
[0039] Figures 15 to 18 It is drawn along Figure 14 A cross-sectional view taken along line A-A'.
[0040] Figure 19 It is illustrated Figure 18 A top view of the manufacturing method of the memory device after the process.
[0041] Figures 20 to 22 It is drawn along Figure 19 A cross-sectional view taken along line A-A'. Detailed Implementation
[0042] Figure 1 A circuit diagram of the memory device is shown. (Refer to...) Figure 1Memory devices (e.g., dynamic random access memory, DRAM) can contain multiple memory cells MC. A typical DRAM memory cell includes a capacitor CA and a transistor TR, wherein the capacitor CA temporarily stores data based on its charging state. The capacitor CA is electrically connected to the source / drain region of the transistor TR, the bit line BL is electrically connected to another source / drain region of the transistor TR, and the word line WL is electrically connected to the gate region of the transistor TR. In this invention, we will focus on the manufacturing process of the word line and the transistor. The manufacturing process of the bit line and the capacitor will not be mentioned again in this invention.
[0043] Figure 2A , Figure 3A and Figure 4A A top view illustrating a method of manufacturing a memory device according to some embodiments of the present invention is shown. Figure 2B , Figure 3B and Figure 4B Correspondingly, the path along... Figure 2A , Figure 3A and Figure 4A A cross-sectional view taken along line A-A'. Figure 2C , Figure 3C and Figure 4C Correspondingly, the path along... Figure 2A , Figure 3A , Figure 4A A cross-sectional view taken along line B-B'. (Refer to...) Figure 2A , Figure 2B and Figure 2C A substrate 100 is provided. The substrate 100 may be a semiconductor substrate, such as a silicon substrate. The substrate 100 includes a semiconductor layer 102 and a semiconductor layer 104 located above the semiconductor layer 102. The semiconductor layer 102 and the semiconductor layer 104 may have different conductivity types. In some embodiments, if the semiconductor layer 102 is an n-type region, then the semiconductor layer 104 may be a p-type region. If the semiconductor layer 102 is a p-type region, then the semiconductor layer 104 is an n-type region.
[0044] Reference Figure 3A , Figure 3B and Figure 3C A dielectric layer 110 is formed over a substrate 100, and a masking layer HM1 is formed over the dielectric layer 110. The masking layer HM1 is patterned using, for example, a photolithography process, and then the dielectric layer 110 is patterned over the masking layer HM1. After the masking layer HM1 and the dielectric layer 110 are patterned, both the masking layer HM1 and the dielectric layer 110 contain stripes extending longitudinally along direction D1. In some embodiments, the dielectric layer 110 may be made of silicon nitride. In some embodiments, the masking layer HM1 is made of a material different from that of the dielectric layer 110. For example, the masking layer HM1 may be made of silicon oxide, carbon, SiON, or a combination thereof.
[0045] Subsequently, the substrate 100 is etched through the mask layer HM1 to form a protrusion PR extending from the substrate 100. An isolation trench TI is formed between the protrusions PR of the substrate 100. The protrusions PR of the substrate 100 and the isolation trench TI extend longitudinally along direction D1. The depth of the isolation trench TI is greater than the thickness of the semiconductor layer 104. That is, the isolation trench TI exposes the semiconductor layer 102.
[0046] Reference Figure 4A , Figure 4B and Figure 4C An isolation structure 106 is formed above the substrate 100 and within the isolation trench TI, and thus on the opposite side of the protrusion PR. Specifically, a dielectric material layer that overfills the isolation trench TI can be formed, and then a planarization process can be performed to remove excess portions of the dielectric material layer to form the isolation structure 106 within the isolation trench TI. The planarization process is performed until the top surface of the dielectric layer 110 is exposed. That is, the masking layer HM1 is removed during the planarization process. The isolation structures 106 are formed to be embedded in the substrate 100, and each of the isolation structures 106 is sandwiched by the protrusion PR of the substrate 100. Since the isolation trench TI extends longitudinally along direction D1, the isolation structures 106 also extend longitudinally along direction D1. The isolation structure 106 can be made of silicon oxide. In some embodiments, an annealing process can be performed before the planarization process to densify the isolation structure 106.
[0047] Figure 5 It is illustrated Figures 4A to 4C A top view of the manufacturing method of the memory device after the process. Figures 6 to 8 It is along Figure 5 The cross-sectional view taken along line A-A'. It is worth noting that... Figure 5 Only the isolation structure 106, the protruding part PR, and the character line groove TW are shown; other components are omitted for simplicity. (See reference...) Figure 5 and Figure 6A mask layer HM2 is formed above the dielectric layer 110. The mask layer HM2 is patterned using, for example, a photolithography process. After patterning, the mask layer HM2 includes stripes extending longitudinally along direction D3. The dielectric layer 110 is patterned through the mask layer HM2, and character line trenches TW that cut protrusions PR and isolation structures 106 are formed in the substrate 100 by etching through the dielectric layer 110. The character line trenches TW may include character line trenches TW1, TW2, and TW3. The character line trenches TW intersect with the protrusions PR of the substrate 100 and extend longitudinally along direction D3. The depth of the character line trenches TW is greater than the thickness of the semiconductor layer 104. That is, the character line trenches TW expose the semiconductor layer 102. In some embodiments, the mask layer HM2 is made of a material different from that of the dielectric layer 110. For example, the masking layer HM2 can be made of silicon oxide, carbon, SiON, or a combination thereof.
[0048] Reference Figure 5 and Figure 7 Remove the hard mask layer HM2 and expose the top surface of the dielectric layer 110. The hard mask layer HM2 can be removed by an etching process.
[0049] Reference Figure 5 and Figure 8 A sacrificial layer 120 is formed in the character line trench TW. Specifically, a sacrificial material layer that overfills the character line trench TW can be formed, followed by a planarization process to remove excess portions of the sacrificial material layer until the top surface of the dielectric layer 110 is exposed. Thus, a sacrificial layer 120 is formed in the character line trench TW. The sacrificial layer 120 is made of a material different from that of the substrate 100 and the dielectric layer 110. In some embodiments, the sacrificial layer 120 can be made of an organic material, such as polyimide, or an inorganic layer.
[0050] Figure 9 It is illustrated Figure 8 A top view of the manufacturing method of the memory device after the process. Figures 10 to 13 It is drawn along Figure 9 The cross-sectional view taken along line A-A'. It is worth noting that... Figure 9 Only the isolation structure 106, the protruding part PR, the character line groove TW, and the opening OP are shown; other components are omitted for simplicity. (See reference...) Figure 9 and Figure 10A mask layer HM3 is formed above the substrate 100, and a photoresist layer PL is formed above the mask layer HM3. The photoresist layer PL has an opening OP that overlaps with a first portion of the sacrificial layer 120, and the photoresist layer PL covers a second portion of the sacrificial layer 120. The first portion of the sacrificial layer 120 is located in a first portion of the character line trench TW, and the second portion of the sacrificial layer 120 is located in a second portion of the character line trench TW. In some embodiments, the opening OP may include opening OP1 and opening OP2, and opening OP1 and opening OP2 are formed in the photoresist layer PL during different processes. For example, opening OP1 is formed before opening OP2 is formed. Along the longitudinal direction (i.e., direction D1) of the protrusion PR of the substrate 100, two second portions (such as character line trench TW2) of the character line trench TW are located between two first portions (e.g., character line trenches TW1 and TW3) of the character line trench TW. The width of the opening OP is greater than the width of the top of the sacrificial layer 120 in the character line trench TW. In some embodiments, the diameter of the opening OP in the photoresist layer PL is the character line trench TW (such as, e.g., Figure 10 The top 110% to 130% of the sacrificial layer 120 in the character line trenches TW1 and TW3 shown. The opening OP partially overlaps with the intersection of the character line trench TW and the protrusion PR of the substrate 100, and the remaining intersection of the character line trench TW and the protrusion PR of the substrate 100 is covered by the photoresist layer PL. In some embodiments, the masking layer HM1 is made of a material different from that of the dielectric layer 110. For example, the masking layer HM3 may be made of silicon oxide, carbon, SiON, or a combination thereof.
[0051] Reference Figure 9 and Figure 11 The mask layer HM3 is patterned using a photoresist layer PL, thus transferring the opening OP of the photoresist layer PL onto the mask layer HM3. The outline of the opening OP in the mask layer HM3 inherits the outline of the opening OP of the photoresist layer PL, and therefore the mask layer HM3 also covers the second portion of the sacrificial layer 120, and the opening OP overlaps with the first portion of the sacrificial layer 120. The width of the opening OP in the hard mask layer HM3 is greater than the width of the top of the sacrificial layer 120 in the character line trench TW. In some embodiments, the diameter of the opening OP in the mask layer HM3 is 110% to 130% of the top of the sacrificial layer 120 in the character line trench TW.
[0052] Reference Figure 9 and Figure 12 The first portion of the sacrificial layer 120 in the character line trench TW is removed using, for example, a dry etching process to expose the first portion of the character line trench TW. The second portion of the sacrificial layer 120 is covered by a masking layer HM3 and is not removed during the etching process. For example, along... Figure 12In the longitudinal direction (i.e., direction D1) of the protruding portion PR of the substrate 100 shown, the sacrificial layer 120 in the character line trenches TW1 and TW3 is removed to expose the character line trenches TW1 and TW3, while the sacrificial layer 120 in the character line trench TW2 remains in place.
[0053] Subsequently, the mask layer HM3 is removed, exposing the second portion of the sacrificial layer 120. The hard mask layer HM3 can be removed using an etching process.
[0054] Reference Figure 13 The first portion of the character line trench TW is enlarged by performing a wet etching process on the substrate 100. An etchant for the wet etching process is selected to etch the substrate 100 while the dielectric layer 110 remains substantially intact. Therefore, after performing the wet etching process, the width and depth of the first portion of the character line trench TW increase. The sidewalls of the first portion of the character line trench TW are offset inward from the sidewalls of the dielectric layer 110. The second portion of the character line trench TW is covered by the sacrificial layer 120, so after performing the wet etching process, the width and depth of the second portion of the character line trench TW remain unchanged. That is, the width of the first portion of the character line trench TW is greater than the width of the second portion of the character line trench TW, and the depth of the first portion of the character line trench TW is greater than the depth of the second portion of the character line trench TW. For example, along as... Figure 13 In the longitudinal direction (i.e., direction D1) of the protruding portion PR of the substrate 100 shown, the widths of character line trenches TW1 and TW3 are greater than the width of character line trench TW2, and the depths of character line trenches TW1 and TW3 are greater than the depth of character line trench TW2. The sidewalls of character line trenches TW1 and TW3 are offset inward from the sidewalls of the dielectric layer 110.
[0055] Figure 14 It is illustrated Figure 13 A top view of the manufacturing method of the memory device after the process. Figures 15 to 18 It is along Figure 14 A cross-sectional view taken along line A-A'. Figure 14 The isolation structure 130 in is Figures 15 to 18 It was formed during the process. It is worth noting that... Figure 13 Only the isolation structures 106 and 130, the protruding portion PR, and the character line groove TW are shown; other components are omitted for simplicity. (See reference...) Figure 15A dielectric filling layer 132 is formed, which constitutes a first portion of the overfilled word line trench TW and extends to the top surface of the dielectric layer 110. The dielectric filling layer 132 also covers a second portion of the sacrificial layer 120 in the second portion of the word line trench TW, and is not formed in the second portion of the word line trench TW due to the presence of the sacrificial layer 120. The dielectric filling layer 132 is made of a material different from that of the dielectric layer 110. For example, the dielectric filling layer 132 may be made of silicon oxide. In some embodiments, an annealing process may be performed to densify the dielectric filling layer 132. Figure 15 The dielectric filling layer 132 in is used for in Figure 14 And the isolation structure 130 is formed in subsequent processes.
[0056] Reference Figure 16 A planarization process is performed to remove excess portions of the dielectric fill layer 132 until the top surface of the dielectric layer 110 is exposed.
[0057] Reference Figure 14 and Figure 17 An isolation structure 130 is formed in the first portion of the character line trench TW by etching the dielectric fill layer 132 through the dielectric layer 110, and is thus formed to be embedded in the substrate 100. For example, along such Figure 17 Along the length direction (i.e., direction D1) of the protruding portion PR of the substrate 100 shown, isolation structures 130 are formed in character line trenches TW1 and TW3, but not in character line trench TW2. Isolation structure 130 overlaps with the intersection of the character line trenches TW and the protruding portion PR of the substrate 100. Isolation structure 130 divides the protruding portion PR of the substrate 100 into active regions 108 and electrically isolates adjacent active regions 108. That is, isolation structures 130 and 106 define active regions 108. Each of the active regions 108 intersects with two character line trenches TW and is divided into three regions R1, R2, and R3 by the two character line trenches TW. For example, along as shown... Figure 17 Along the length direction (i.e., direction D1) of the protruding portion PR of the substrate 100 shown, the isolation structure 130 in the word line trenches TW1 and TW3 defines the active region 108, and the two word line trenches TW2 divide the active region 108 into regions R1, R2, and R3. Region R2 is located at the center of the active region 108, and regions R1 and R3 are located at both ends of the active region 108. Region R2 electrically connects to bit lines, such as... Figure 1 The bit lines mentioned above, and regions R1 and R3 will be electrically connected to the capacitor, such as Figure 1The capacitor CA mentioned in the invention. In this invention, since the active regions 108 are isolated by an isolation structure 130 having a circular shape, each of the active regions 108 has two opposing sides, and the two opposing sides are curved inward. Specifically, in the top view, each of the active regions has a sidewall S1 and a sidewall S2 opposite to the sidewall S1, and the sidewalls S1 and S2 are curved inward (i.e., recessed). In the top view, each of the active regions 108 further has a sidewall S3 and a sidewall S4 opposite to the sidewall S3. Sidewall S3 connects sidewalls S1 and S2, sidewall S4 connects sidewalls S1 and S2, and sidewalls S3 and S4 are substantially straight. Therefore, in the top view, the active regions 108 extend longitudinally along direction D1, and the width of each of the active regions 108 in direction D1 gradually decreases and then increases along direction D2 perpendicular to direction D1.
[0058] In this invention, the memory device includes an isolation structure 130 and an isolation structure 106 formed in different steps. The isolation structure 106 is located on opposite sides of the active regions 108 in direction D2. The isolation structure 130 is located between adjacent active regions 108 in a direction D1 perpendicular to direction D2, and correspondingly contacts the sidewalls S1 and S2 of the active regions 108. The isolation structures 130 and 106 between the active regions 108 are formed in different steps. The formation of the isolation structure 130 in this invention ensures that the landing area (i.e., regions R1 and R3) between the active regions 108 and the capacitor is sufficiently large to electrically connect the active regions 108 and the capacitor. Specifically, this is achieved by enlarging the first portion of the word line trench TW (see...). Figure 13 Then, a dielectric filler layer is filled in the first enlarged portion of the character line trench TW (see...). Figures 15 to 17 An isolation structure 130 is formed. That is, the isolation structure 130, which divides the protruding portion PR of the substrate 100 into an active region 108, is self-aligned with the character line trench TW. Therefore, the landing area (i.e., regions R1 and R3) between the active region 108 and the capacitor is large enough to ensure electrical connection between the active region 108 and the capacitor. Since the isolation structure 130 and the isolation structure 106 are formed in different steps, the depth d1 of the isolation structure 130 can be different from the depth d2 of the isolation structure 106.
[0059] Reference Figure 14 and Figure 18 The second portion of the sacrificial layer 120 is removed, for example, by a dry etching process, to expose the second portion of the character line trench TW. The second portion of the character line trench TW is not covered by the isolation structure 130, while the first portion of the character line trench TW is covered by the isolation structure 130. For example, along as... Figure 18In the longitudinal direction (i.e., direction D1) of the protruding portion PR of the substrate 100 shown, the sacrificial layer 120 in the character line trench TW2 is removed to expose the character line trench TW2.
[0060] Figure 19 It is illustrated Figure 18 A top view of the manufacturing method of the memory device after the process. Figures 20 to 22 It is drawn along Figure 19 A cross-sectional view taken along line A-A'. Figure 19 The character line structure 140 in the middle is Figures 20 to 22 It was formed during the process. It is worth noting that... Figure 19 Only isolation structures 106 and 130, the protruding portion PR, and the character line structure 140 are shown; other components are omitted for simplicity. (See reference...) Figure 20 The dielectric layer 110 is removed, and then a gate dielectric layer 142 with an inner word line trench TW is formed. In some embodiments, the gate dielectric layer 142 is made of silicon oxide.
[0061] Reference Figure 21 A conductive layer 144 is formed by overfilling the character line trench (TW), and then the conductive layer 144 is etched back to lower the top surface of the conductive layer 144 to form a conductive layer 144 embedded in the substrate 100. A gate dielectric layer 142 is formed between the active region 108 and the corresponding conductive layer 144. In some embodiments, the conductive layer 144 is made of a metal nitride, such as titanium nitride (TiN).
[0062] Subsequently, a conductive layer 146 is formed over a filler trench (TW) and located above the conductive layer 144. Then, the conductive layer 146 is etched back to reduce its top surface area. A gate dielectric layer 142 is formed between the active region 108 and the corresponding conductive layer 146. The conductive layers 146 and 144 are made of different materials. In some embodiments, the work function value of the conductive layer 146 is lower than that of the conductive layer 144. In some embodiments, the conductive layer 146 is made of polysilicon.
[0063] Reference Figure 19 and Figure 22A top cap layer 148 is formed over a word line trench TW and located above the conductive layer 146, and then a planarization process is performed on the top cap layer 148. In some embodiments, the top cap layer 148 is made of silicon nitride. The gate dielectric layer 142, conductive layer 144, conductive layer 146, and top cap layer 148 located within the same word line trench TW are referred to as word line structures 140. The memory device of the present invention includes a plurality of word line structures 140, such as word line structure 140A formed in word line trench TW1, word line structure 140B formed in word line trench TW2, and word line structure 140C formed in word line trench TW3. The word line structures 140 are embedded in the substrate 100 and intersect with the active region 108. The character line structure 140 in the second portion of the character line trench TW contacts the substrate 100, and the character line structure 140 in the first portion of the character line trench TW is separated from the active region 108 of the substrate 100 by the isolation structure 130. For example, along such Figure 22 In the longitudinal direction (i.e., direction D1) of the protruding portion PR of the substrate 100 shown, the character line structure 140B is embedded in and contacts the substrate 100. Character line structures 140A and 140C are separated from the active region 108 of the substrate 100 by an isolation structure 130, and the character line structures 140A and 140C are in contact with the isolation structure 130. Character line structures 140A and 140C are also in contact with the isolation structure 106. In some embodiments, such as Figure 19 As shown, the interface between character line structure 140A and isolation structure 130 is interconnected with the interface between character line structure 140A and isolation structure 130. The interface between character line structure 140C and isolation structure 130 is interconnected with the interface between character line structure 140C and isolation structure 130.
[0064] As mentioned above, the isolation structure for the electrically isolated active region is formed in two steps. The isolation structure is self-aligned with the word line trench. Therefore, the landing area between the active region and the capacitor is large enough to ensure that the active region is electrically connected to the capacitor. The performance of the memory device can be enhanced.
[0065] While the invention has been described in considerable detail with reference to certain embodiments thereof, other embodiments are also possible. Therefore, the spirit and scope of the appended claims should not be limited to the embodiments described herein.
[0066] Those skilled in the art will understand that various modifications and variations can be made to this invention without departing from its scope or spirit. In view of the foregoing, this invention is intended to cover any modifications and variations that fall within the scope of the appended claims.
[0067] [Symbol Explanation] 100: Substrate 102: Semiconductor layer 104: Semiconductor layer 106: Isolation Structure 108: Active Area 110: Dielectric layer 120: Sacrifice Layer 130: Isolation Structure 132: Dielectric filling layer 140: Character Line Structure 140A: Character Line Structure 140B: Character Line Structure 140C: Character Line Structure 142: Gate dielectric layer 144: Conductive layer 146: Conductive layer 148: Top Cover Layer A-A': line B-B': Line BL: Bitline CA: Capacitor d1: Depth d2: Depth D1: Direction D2: Direction D3: Direction HM1: Masking layer HM2: Masking layer HM3: Masking layer MC: Memory Unit OP: Opening OP1: Opening OP2: Opening PL: Photoresist layer PR: Highlighting the key points R1: Region R2: Region R3: Region S1: Sidewall S2: Sidewall S3: Sidewall S4: Sidewall TI: Isolation Trench TR: Transistor TW: Character line groove TW1: Character line groove TW2: Character line groove TW3: Character line groove WL: Character line.
Claims
1. A method of fabricating a memory device, characterized by, comprising the steps of: etching a substrate to form a protruding portion extending from the substrate; forming a plurality of first isolation structures over the substrate and on opposite sides of the protruding portion; forming first, second, and third wordline trenches that cut through the protruding portion and the plurality of first isolation structures; forming a plurality of sacrificial layers in the first, second, and third wordline trenches, respectively; removing a first portion of the plurality of sacrificial layers to reveal the first and third wordline trenches; etching the protruding portion through the first and third wordline trenches; removing a second portion of the plurality of sacrificial layers to reveal the second wordline trench; and forming first, second, and third wordline structures in the first, second, and third wordline trenches, respectively. wherein forming the plurality of first isolation structures comprises the steps of:
2. The method of claim 1, wherein, forming a dielectric layer over the substrate and a first mask layer over the dielectric layer, wherein the first mask layer comprises stripes extending longitudinally along a first direction; patterning the dielectric layer through the first mask layer; forming a plurality of isolation trenches in the substrate by etching the substrate through the dielectric layer; and forming the plurality of first isolation structures in the plurality of isolation trenches. wherein etching the protruding portion through the first and third wordline trenches is performed by a wet etching process.
3. The method of claim 2, wherein, wherein during etching the protruding portion through the first and third wordline trenches, a plurality of sidewalls of the first and third wordline trenches are inwardly offset from a plurality of sidewalls of the dielectric layer.
4. The method of claim 2, wherein, further comprising the steps of:
5. The method of claim 2, wherein, forming a plurality of second isolation structures in the first and third wordline trenches, respectively, prior to forming the first, second, and third wordline structures in the first, second, and third wordline trenches, respectively. wherein forming the plurality of second isolation structures in the first and third wordline trenches comprises the steps of:
6. The method of claim 5, wherein, forming a dielectric fill layer that overfills the first and third wordline trenches; and etching the dielectric fill layer through the dielectric layer to form the plurality of second isolation structures. wherein the plurality of second isolation structures overlap with intersection portions of the first and third wordline trenches and the protruding portion of the substrate.
7. The method of claim 5, wherein, wherein the plurality of second isolation structures divide the protruding portion of the substrate into a plurality of active regions, and in a top-down view, each of the plurality of active regions intersects the second wordline structure.
8. The method of claim 5, wherein, wherein in the top-down view, each of the plurality of active regions has two opposite sides, and the two opposite sides are inwardly curved.
9. The method of claim 8, wherein, 10. The method of claim 1, wherein, Wherein before removing the first portions of the plurality of sacrificial layers to reveal the first wordline trench and the third wordline trench, a second mask layer is formed, the second mask layer has a plurality of openings overlapping the first portions of the plurality of sacrificial layers, and a diameter of one of the plurality of openings is 110% to 130% of a width of a top of one of the plurality of sacrificial layers.
11. A memory device, comprising: Comprising: a substrate; a plurality of isolation structures embedded in the substrate, wherein the plurality of isolation structures defines an active region in the substrate, wherein in a top-down view, the active region has a first sidewall and a second sidewall opposite to the first sidewall, and the first sidewall and the second sidewall are inwardly curved; and a wordline structure embedded in the substrate.
12. The memory device of claim 11, wherein, Wherein in the top-down view, the active region further has a third sidewall and a fourth sidewall opposite to the third sidewall, the third sidewall connects the first sidewall and the second sidewall, the fourth sidewall connects the first sidewall and the second sidewall, and the third sidewall and the fourth sidewall are substantially straight.
13. The memory device of claim 11, wherein, Wherein the plurality of isolation structures comprises: a plurality of first isolation structures on a plurality of opposite sides of the active region in a first direction; and a plurality of second isolation structures in contact with the first sidewall of the active region and the second sidewall of the active region, respectively.
14. The memory device of claim 13, wherein, Wherein depths of the plurality of first isolation structures are different from depths of the plurality of second isolation structures.
15. The memory device of claim 13, wherein, Further comprising another wordline structure embedded in the substrate and in contact with one of the plurality of second isolation structures.
16. The memory device of claim 15, wherein, Wherein the another wordline structure is in contact with one of the plurality of first isolation structures.
17. The memory device of claim 15, wherein, Wherein an interface between the another wordline structure and the one of the plurality of first isolation structures is connected to an interface between the another wordline structure and the one of the plurality of second isolation structures.
18. The memory device of claim 11, wherein, Wherein the wordline structure comprises: a first conductive layer embedded in the active region; and a gate dielectric layer between the active region and the first conductive layer.
19. The memory device of claim 18, wherein, Wherein the wordline structure further comprises: a second conductive layer above the first conductive layer, wherein the gate dielectric layer is between the active region and the second conductive layer.
20. The memory device of claim 19, wherein, Wherein the wordline structure further comprises: a cap layer above the second conductive layer.