Memory structure and forming method thereof

Abstract

The invention discloses a memory structure and a forming method thereof. The memory structure comprises a substrate; the isolation layers and the word line grid layers are located on the substrate, the isolation layers and the word line grid layers are sequentially and alternately stacked, and the word line grid layers are located between the adjacent isolation layers; the charge trapping layer is positioned on the side walls of the isolation layer and the word line gate layer; the channel layer is located on the side wall of the charge trapping layer, and the channel layer located on the side wall of the isolation layer comprises a metal compound layer. The channel layer located on the side wall of the isolation layer comprises a metal compound layer, the resistance can be effectively reduced, the channel layer with the metal silicide layer has larger advantages on nodes where the number of layers of a higher memory structure is stacked, and the performance of a device is improved more obviously.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of semiconductor manufacturing, and in particular to a memory structure and a forming method thereof. BACKGROUND

[0002] In recent years, the development of flash memory is particularly rapid, and the main feature of flash memory is that it can keep the stored information for a long time without power supply.

[0003] NAND flash memory is a better storage solution than hard disk drive, and since NAND flash memory reads and writes data in units of pages, it is suitable for storing continuous data such as pictures, audio or other file data; at the same time, it is widely used in the storage field of mobile communication devices and portable multimedia devices due to its low cost, large capacity, fast writing speed and short erasing time.

[0004] However, the performance of the NAND memory structure formed in the prior art still needs to be improved. SUMMARY

[0005] The technical problem solved by the present application is to provide a memory structure and a forming method thereof to improve the electrical performance of the device structure.

[0006] To solve the above problems, the present application provides a memory structure, comprising: a substrate; a plurality of isolation layers and a plurality of word line grid layers located on the substrate, the isolation layers and the word line grid layers are alternately stacked in sequence, and the word line grid layers are located between adjacent isolation layers; a charge trapping layer located on the side wall of the isolation layer and the word line grid layer; a channel layer located on the side wall of the charge trapping layer, wherein the channel layer located on the side wall of the isolation layer comprises a metal compound layer.

[0007] Optionally, the projection area of the word line grid layer towards the substrate is located within the projection area of the isolation layer towards the substrate, and the adjacent isolation layers have grooves therebetween.

[0008] Optionally, the projection area of the isolation layer towards the substrate is located within the projection area of the word line grid layer towards the substrate, and the adjacent word line grid layers have grooves therebetween.

[0009] Optionally, the projection area of the word line grid layer towards the substrate coincides with the projection area of the isolation layer towards the substrate.

[0010] Optionally, the channel layer located on the side wall of the isolation layer is the metal compound layer.

[0011] Optionally, the channel layer located at the sidewall of the isolation layer comprises: a semiconductor layer, and the metal compound layer located at the sidewall of the semiconductor layer.

[0012] Optionally, the charge trapping layer comprises: a barrier layer located at the sidewall of the isolation layer and the word line grid layer, a storage layer located at the sidewall of the barrier layer, and a tunneling layer located at the sidewall of the storage layer.

[0013] Optionally, the memory structure further comprises: a conductive layer, which is electrically connected with the channel layer; and a bit line layer, which is electrically connected with the conductive layer.

[0014] Correspondingly, the present application also provides a forming method of the memory structure, comprising: providing a substrate; forming a plurality of isolation layers and a plurality of word line grid layers on the substrate, the isolation layers and the word line grid layers are alternately stacked in sequence, and the word line grid layers are located between adjacent isolation layers; forming a charge trapping layer at the sidewall of the isolation layer and the word line grid layer; and forming a channel layer at the sidewall of the charge trapping layer, wherein the channel layer located at the sidewall of the isolation layer comprises a metal compound layer.

[0015] Optionally, the forming method of the word line grid layer comprises: forming a plurality of isolation layers and a plurality of first sacrificial layers on the substrate, the isolation layers and the first sacrificial layers are alternately stacked in sequence, and the first sacrificial layers are located between adjacent isolation layers; removing the first sacrificial layers to form word line grooves between adjacent isolation layers; and forming the word line grid layer in the word line grooves.

[0016] Optionally, the projection area of the word line grid layer towards the substrate is located within the projection area of the isolation layer towards the substrate, and a groove is formed between adjacent isolation layers.

[0017] Optionally, the forming method of the channel layer comprises: etching part of the first sacrificial layers to form the groove between adjacent isolation layers; forming an initial channel layer at the sidewall of the isolation layer and in the groove; forming a second sacrificial layer in the groove, the second sacrificial layer covers the initial channel layer located in the groove; and performing a metalization treatment on the exposed initial channel layer to form the channel layer.

[0018] Optionally, the projection area of the isolation layer towards the substrate is located within the projection area of the word line grid layer towards the substrate, and a groove is formed between adjacent word line grid layers.

[0019] Optionally, the method for forming the channel layer includes: etching a portion of the isolation layer to form the groove between adjacent first sacrificial layers; forming a first sub-channel layer in the groove; metallizing the first sub-channel layer to form the metal compound layer; and after forming the metal compound layer, forming a second sub-channel layer on the sidewall of the first sacrificial layer and the sidewall of the metal compound layer, thereby forming the channel layer by the metal compound layer and the second sub-channel layer.

[0020] Optionally, the projection area of ​​the word line gate layer toward the substrate coincides with the projection area of ​​the isolation layer toward the substrate.

[0021] Optionally, the channel layers located on the sidewalls of the isolation layer are all the metal compound layers.

[0022] Optionally, the channel layer located on the sidewall of the isolation layer includes: a semiconductor layer and a metal compound layer located on the sidewall of the semiconductor layer.

[0023] Optionally, after forming the channel layer, the method further includes: forming a conductive layer electrically connected to the channel layer; and forming a bit line layer electrically connected to the conductive layer.

[0024] Compared with the prior art, the technical solution of the present invention has the following advantages:

[0025] In the memory structure of the present invention, the channel layer located on the sidewall of the isolation layer includes a metal compound layer, which can effectively reduce resistance. Moreover, at nodes with a higher number of memory structure layers, the channel layer with the metal silicide layer has a greater advantage, resulting in a more significant improvement in device performance.

[0026] In the method for forming the memory structure of the present invention, the channel layer located on the sidewall of the isolation layer includes a metal compound layer, which can effectively reduce resistance. Moreover, at nodes with a higher number of memory structure layers, the channel layer with the metal silicide layer has a greater advantage, resulting in a more significant improvement in device performance. Attached Figure Description

[0027] Figures 1 to 10 This is a schematic diagram of the structure of each step in the method for forming the memory structure in an embodiment of the present invention;

[0028] Figures 11 to 19 This is a schematic diagram of the steps in the method for forming a memory structure in another embodiment of the present invention. Detailed Implementation

[0029] As described in the background section, the performance of existing NAND memory structures still needs improvement. This will be explained in detail below.

[0030] As 3D NAND technology advances, the number of layers increases, meaning more and more memory transistors are connected in a single series. This leads to a problem: the length of the series-connected channels becomes longer. Since the channel material is polysilicon, which has inherently high resistance, excessive channel resistance in higher-layer 3D NAND can potentially slow down read speeds and impair the ability to distinguish between 1 and 0 signals. Therefore, at higher technology nodes, the need to reduce channel resistance becomes increasingly important.

[0031] Currently, the main methods to reduce resistance are to heavily dop the channel to form larger grains within it; or to add an annealing process in a hydrogen environment at the end of the process to reduce dangling bonds and unsaturated bonds in the channel, thereby reducing potential levels and improving conductivity.

[0032] However, existing technologies can only improve the conductivity of polysilicon to a certain extent. For the current need for higher layer counts, where layer height or channel length may reach tens of micrometers, the above methods cannot effectively solve the problem of excessive channel resistance.

[0033] Based on this, the present invention provides a memory structure and a method for forming the same. The channel layer located on the sidewall of the isolation layer includes a metal compound layer, which can effectively reduce resistance. Moreover, at nodes with a higher number of memory structure layers, the channel layer with the metal silicide layer has a greater advantage, resulting in a more significant improvement in device performance.

[0034] To make the above-mentioned objects, features and advantages of the present invention more apparent and understandable, specific embodiments of the present invention will be described in detail below with reference to the accompanying drawings.

[0035] Figures 1 to 10 This is a schematic diagram of the structure of each step in the method for forming the memory structure in an embodiment of the present invention.

[0036] Please refer to Figure 1 Substrate 100 is provided.

[0037] In this embodiment, the substrate 100 is made of silicon.

[0038] In other embodiments, the substrate material may also be germanium, silicon germanide, silicon carbide, gallium arsenide, or indium galliumide.

[0039] Please continue to refer to this. Figure 1 After providing the substrate 100, the substrate 100 is subjected to source / drain ion doping treatment to form a source layer 101 in the substrate 100.

[0040] In this embodiment, since the formed memory structure consists of several transistors connected in series and stacked sequentially, and all transistors share the same source layer 101, only one source layer 101 needs to be formed in the substrate 100.

[0041] After providing the substrate 100, the method further includes: forming a plurality of isolation layers and a plurality of word line gate layers on the substrate 100, wherein the isolation layers and the word line gate layers are stacked alternately in sequence, and the word line gate layers are located between adjacent isolation layers; forming charge trapping layers on the sidewalls of the isolation layers and the word line gate layers; and forming channel layers on the sidewalls of the charge trapping layers, wherein the channel layers located on the sidewalls of the isolation layers include metal compound layers. For details of the formation process, please refer to [reference needed]. Figures 2 to 9 .

[0042] Please refer to Figure 2 A plurality of isolation material layers 102 and a plurality of first sacrificial material layers 103 are formed on the substrate 100. The isolation material layers 102 and the first sacrificial material layers 103 are stacked alternately in sequence, and the first sacrificial material layers 103 are located between adjacent isolation material layers 102.

[0043] It should be noted that, in this embodiment, the isolation material layer 102 is used to form the isolation layer after subsequent patterning process, and its function is to isolate adjacent transistors. The first sacrificial material layer 103 is used to form the first sacrificial layer (i.e., pseudo gate layer) after subsequent patterning process. The first sacrificial layer is used to occupy the formation position of the word line gate layer in advance, and it needs to be removed later to replace the word line gate layer.

[0044] In order to reduce etch damage to the isolation layer during the subsequent removal of the first sacrificial layer, the first sacrificial layer and the isolation layer need to have a certain etch selectivity ratio, that is, the materials of the first sacrificial material layer 103 and the isolation material layer 102 need to be different.

[0045] In this embodiment, the material of the isolation material layer 102 is silicon oxide, and the material of the first sacrificial material layer 103 is silicon nitride.

[0046] Please refer to Figure 3 The isolation material layer 102 and the first sacrificial material layer 103 are patterned and etched to form a plurality of isolation layers 104 and a plurality of first sacrificial layers 105. The isolation layers 104 and the first sacrificial layers 105 are stacked alternately in sequence, and the first sacrificial layers 105 are located between adjacent isolation layers 104.

[0047] In this embodiment, since the isolation layer 104 is formed by patterning and etching the isolation material layer 102, the material of the isolation layer 104 is also silicon oxide; the first sacrificial layer 105 is formed by patterning and etching the first sacrificial material layer 103, so the material of the first sacrificial layer 105 is also silicon nitride.

[0048] Please refer to Figure 4 The first sacrificial layer 105 is etched to form a groove 114 between adjacent isolation layers 104.

[0049] In this embodiment, the etching process for the first sacrificial layer 105 is a wet etching process.

[0050] In other embodiments, the first sacrificial layer may not be etched, i.e., the groove may not be formed.

[0051] Please refer to Figure 5 After the groove 114 is formed, a charge trapping layer 106 is formed on the sidewalls of the isolation layer 104 and the first sacrificial layer 105.

[0052] In this embodiment, the charge trapping layer 106 formed on the sidewall of the first sacrificial layer 105 is located within the groove 114.

[0053] In this embodiment, the charge trapping layer 106 is a composite layer, that is, the charge trapping layer 106 includes: a barrier layer located on the sidewall of the isolation layer 104 and the first sacrificial layer 105, a storage layer located on the sidewall of the barrier layer, and a tunneling layer (not shown) located on the sidewall of the storage layer.

[0054] The barrier layer and the tunneling layer are both made of silicon oxide, while the storage layer is made of silicon nitride, meaning the charge trapping layer 106 has an ONO structure (Oxide-Nitride-Oxide). The charge trapping layer 106 stores charge, and its charge storage mechanism is as follows: charge is stored through the silicon nitride storage layer. When electrons are injected into the silicon nitride, these electrons are captured by the trap centers, thus achieving data storage. This storage method is non-volatile, meaning that the stored data remains unchanged even without power.

[0055] Please refer to Figure 6 After the charge trapping layer 106 is formed, an initial channel layer 107 is formed in the sidewall of the isolation layer 104 and in the groove 114.

[0056] In this embodiment, the initial channel layer 107 is also located on the sidewall of the charge trapping layer 106.

[0057] In this embodiment, the initial channel layer 107 is made of silicon.

[0058] In other embodiments, the material of the initial channel layer may also be germanium or silicon-germanium.

[0059] Please refer to Figure 7 A second sacrificial layer 108 is formed in the groove 114, and the second sacrificial layer 108 covers the initial channel layer 107 located in the groove 114.

[0060] In this embodiment, the method of forming the second sacrificial layer 108 in the groove 114 includes: forming a second sacrificial material layer (not shown) in the groove 114 and the sidewall of the initial channel layer 107; etching back the second sacrificial material layer to remove the second sacrificial material layer located on the sidewall of the initial channel layer 107, thereby forming the second sacrificial layer 108.

[0061] In this embodiment, the second sacrificial layer 108 is used to cover the initial channel layer 107 located on the sidewall of the first sacrificial layer 105 to prevent it from being metallized during subsequent metallization processes, and the second sacrificial layer 108 itself cannot be metallized. Therefore, the material of the second sacrificial layer 108 can be an insulating material, a carbon layer, or some other metal materials that are not easily reactive with semiconductor materials.

[0062] Please refer to Figure 8 The exposed initial channel layer 107 is metallized to form the channel layer 109.

[0063] In this embodiment, the method of metallizing the exposed initial channel layer 107 to form the channel layer 109 includes: forming a metal layer (not shown) on the exposed sidewall of the initial channel layer 107 and the sidewall of the second sacrificial layer 108; performing an annealing process to react the exposed initial channel layer 107 with the metal layer to form the metal compound layer 1091, and the second sacrificial layer 108 covering the initial channel layer 107 and the metal compound layer 1091 to form the channel layer 109.

[0064] In this embodiment, the material of the metal layer can be nickel, titanium or cobalt, and the corresponding material of the metal compound layer 1091 is nickel silicide, titanium silicide or cobalt silicide.

[0065] In this embodiment, the metal layer consumes all of the exposed initial channel layer 107, so that the channel layers 109 located on the sidewall of the isolation layer 104 are all the metal compound layer 1091.

[0066] In other embodiments, the metal layer may not completely consume the exposed initial channel layer, such that the channel layer located on the sidewall of the isolation layer includes: a semiconductor layer and the metal compound layer located on the sidewall of the semiconductor layer, wherein the semiconductor layer is the initial channel layer.

[0067] The channel layer 109 located on the sidewall of the isolation layer 104 includes a metal compound layer 1091, which can effectively reduce resistance. At nodes with a higher number of memory structure layers, the channel layer 109 with the metal silicide layer has a greater advantage and a more significant improvement in device performance.

[0068] Please refer to Figure 9 After forming the channel layer 109, a dielectric layer 110 is formed on the substrate 100, the dielectric layer 110 covering the isolation layer 104 and the first sacrificial layer 105; the first sacrificial layer 105 is removed, and word line slots (not shown) are formed between adjacent isolation layers 104; the word line gate layer 111 is formed in the word line slots.

[0069] In this embodiment, the word line gate layer 111 is a metal gate used to control the opening and closing of the channel layer 109.

[0070] In this embodiment, the projection area of ​​the word line gate layer 111 toward the substrate 100 is located within the projection area of ​​the isolation layer 104 toward the substrate 100, and the groove 114 is provided between adjacent isolation layers 104.

[0071] In other embodiments, when the groove is not formed, the projection area of ​​the word line gate layer toward the substrate coincides with the projection area of ​​the isolation layer toward the substrate.

[0072] Please refer to Figure 10 After forming the word line gate layer 111, a conductive layer 112 is formed, which is electrically connected to the channel layer 109; a bit line layer 113 is formed, which is electrically connected to the conductive layer 112.

[0073] In this embodiment, the method for forming the conductive layer 112 includes: etching back the dielectric layer 110 to form a groove 114, the groove 114 exposing a portion of the channel layer 109; and forming the conductive layer 112 within the groove 114.

[0074] In this embodiment, the conductive layer 112 is made of silicon.

[0075] In this embodiment, the bit line layer 113 is used to connect the drain layer (not shown) formed in the subsequent process. Since the formed memory structure is a number of transistors connected in series and stacked in sequence, all transistors share the same drain layer, so only one drain layer needs to be formed.

[0076] Accordingly, this invention also provides a memory structure, please refer to the following: Figure 10 The system includes: a substrate 100; a plurality of isolation layers 104 and a plurality of word line gate layers 111 located on the substrate 100, wherein the isolation layers 104 and the word line gate layers 111 are stacked alternately in sequence, and the word line gate layers 111 are located between adjacent isolation layers 104; a charge trapping layer 106 located on the sidewalls of the isolation layers 104 and the word line gate layers 111; and a channel layer 109 located on the sidewalls of the charge trapping layer 106, wherein the channel layer 109 located on the sidewalls of the isolation layers 104 includes a metal compound layer 1091.

[0077] The channel layer 109 located on the sidewall of the isolation layer 104 includes a metal compound layer 1091, which can effectively reduce resistance. At nodes with a higher number of memory structure layers, the channel layer 109 with the metal silicide layer has a greater advantage and a more significant improvement in device performance.

[0078] In this embodiment, the projection area of ​​the word line gate layer 111 toward the substrate 100 is located within the projection area of ​​the isolation layer 104 toward the substrate 100, and there is a groove 114 between adjacent isolation layers 104.

[0079] In other embodiments, the projection area of ​​the word line gate layer toward the substrate may also overlap with the projection area of ​​the isolation layer toward the substrate.

[0080] In this embodiment, the channel layers 109 located on the sidewall of the isolation layer 104 are all the metal compound layers 1091.

[0081] In other embodiments, the channel layer located on the sidewall of the isolation layer may further include: a semiconductor layer and the metal compound layer located on the sidewall of the semiconductor layer.

[0082] In this embodiment, the charge trapping layer 106 includes: a blocking layer located on the sidewalls of the isolation layer 104 and the word line gate layer 111, a storage layer located on the sidewalls of the blocking layer, and a tunneling layer located on the sidewalls of the storage layer.

[0083] In this embodiment, it further includes: a conductive layer 112, which is electrically connected to the channel layer 109; and a bit line layer 113, which is electrically connected to the conductive layer 112.

[0084] In this embodiment, the material of the metal compound layer 1091 can be nickel silicide, titanium silicide, or cobalt silicide.

[0085] Figures 11 to 19 This is a schematic diagram of the steps in the method for forming a memory structure in another embodiment of the present invention.

[0086] Please refer to Figure 11 Substrate 200 is provided.

[0087] In this embodiment, the substrate 200 is made of silicon.

[0088] In other embodiments, the substrate material may also be germanium, silicon germanide, silicon carbide, gallium arsenide, or indium galliumide.

[0089] Please continue to refer to this. Figure 11 After providing the substrate 200, the substrate 200 is subjected to source / drain ion doping treatment to form a source layer 201 in the substrate 200.

[0090] In this embodiment, since the formed memory structure consists of several transistors connected in series and stacked sequentially, and all transistors share the same source layer 201, only one source layer 201 needs to be formed in the substrate 200.

[0091] After providing the substrate 200, the method further includes: forming a plurality of isolation layers and a plurality of word line gate layers on the substrate 200, wherein the isolation layers and the word line gate layers are stacked alternately in sequence, and the word line gate layers are located between adjacent isolation layers; forming charge trapping layers on the sidewalls of the isolation layers and the word line gate layers; and forming channel layers on the sidewalls of the charge trapping layers, wherein the channel layers located on the sidewalls of the isolation layers include metal compound layers. For details of the formation process, please refer to [reference needed]. Figures 12 to 18 .

[0092] Please refer to Figure 12 A plurality of isolation material layers 202 and a plurality of first sacrificial material layers 203 are formed on the substrate 200. The isolation material layers 202 and the first sacrificial material layers 203 are stacked alternately in sequence, and the first sacrificial material layers 203 are located between adjacent isolation material layers 202.

[0093] It should be noted that, in this embodiment, the isolation material layer 202 is used to form the isolation layer after subsequent patterning process, and its function is to isolate adjacent transistors. The first sacrificial material layer 203 is used to form the first sacrificial layer (i.e., pseudo gate layer) after subsequent patterning process. The first sacrificial layer is used to occupy the formation position of the word line gate layer in advance, and it needs to be removed later to replace the word line gate layer.

[0094] In order to reduce etch damage to the isolation layer during the subsequent removal of the first sacrificial layer, the first sacrificial layer and the isolation layer need to have a certain etch selectivity ratio, that is, the materials of the first sacrificial material layer 203 and the isolation material layer 202 need to be different.

[0095] In this embodiment, the insulating material layer 202 is made of silicon oxide, and the first sacrificial material layer 203 is made of silicon nitride.

[0096] Please refer to Figure 13 The isolation material layer 202 and the first sacrificial material layer 203 are patterned and etched to form a plurality of isolation layers 204 and a plurality of first sacrificial layers 205. The isolation layers 204 and the first sacrificial layers 205 are stacked alternately in sequence, and the first sacrificial layers 205 are located between adjacent isolation layers 204.

[0097] In this embodiment, since the isolation layer 204 is formed by patterning and etching the isolation material layer 202, the material of the isolation layer 204 is also silicon oxide; the first sacrificial layer 205 is formed by patterning and etching the first sacrificial material layer 203, so the material of the first sacrificial layer 205 is also silicon nitride.

[0098] Please refer to Figure 14 The isolation layer 204 is etched to form a groove 206 between adjacent first sacrificial layers 205.

[0099] In this embodiment, the etching process for the isolation layer 204 is a wet etching process.

[0100] Please refer to Figure 15 After the groove 206 is formed, a charge trapping layer 207 is formed on the sidewalls of the isolation layer 204 and the first sacrificial layer 205.

[0101] In this embodiment, the charge trapping layer 207 formed on the sidewall of the isolation layer 204 is located within the groove 206.

[0102] In this embodiment, the charge trapping layer 207 is a composite layer, that is, the charge trapping layer 207 includes: a barrier layer located on the sidewall of the isolation layer 204 and the first sacrificial layer, a storage layer located on the sidewall of the barrier layer, and a tunneling layer (not shown) located on the sidewall of the storage layer.

[0103] In this design, both the barrier layer and the tunneling layer are made of silicon oxide, while the storage layer is made of silicon nitride, meaning the charge trapping layer 207 has an ONO structure (Oxide-Nitride-Oxide). The charge trapping layer 207 stores charge, and its charge storage mechanism is as follows: charge is stored through the silicon nitride storage layer. When electrons are injected into the silicon nitride, these electrons are captured by the trap centers, thus achieving data storage. This storage method is non-volatile, meaning that the stored data remains unchanged even without a power source.

[0104] Please refer to Figure 16 A first sub-channel layer (not shown) is formed in the groove 206; the first sub-channel layer is metallized to form the metal compound layer 208.

[0105] In this embodiment, the method of forming the first sub-channel layer in the groove 206 includes: forming a channel material layer (not shown) on the sidewall of the first sacrificial layer 205 and in the groove 206; etching back the channel material layer to remove the channel material layer located on the sidewall of the first sacrificial layer 205, thereby forming the first sub-channel layer in the groove 206.

[0106] In this embodiment, the channel material layer is made of silicon.

[0107] In other embodiments, the channel material layer may also be made of germanium or silicon-germanium.

[0108] In this embodiment, the method of metallizing the first sub-channel layer to form the metal compound layer 208 includes: forming a metal layer (not shown) on the sidewall of the first sub-channel layer and the sidewall of the charge trapping layer 207; and performing an annealing process to react the metal layer with the first sub-channel layer to generate the metal compound layer 208.

[0109] In this embodiment, the material of the metal layer can be nickel, titanium or cobalt, and the corresponding material of the metal compound layer 208 is nickel silicide, titanium silicide or cobalt silicide.

[0110] In this embodiment, the metal layer consumes all of the exposed first sub-channel layer.

[0111] In other embodiments, the metal layer may not completely consume the exposed first sub-channel layer.

[0112] Please refer to Figure 17 After the metal compound layer 208 is formed, a second sub-channel layer 209 is formed on the sidewall of the first sacrificial layer 205 and the sidewall of the metal compound layer 208, and the channel layer is formed by the metal compound layer 208 and the second sub-channel layer 209.

[0113] The channel layer located on the sidewall of the isolation layer 204 includes a metal compound layer 208, which can effectively reduce resistance. Moreover, at nodes with a higher number of memory structure layers, the channel layer with the metal silicide layer has a greater advantage and a more significant improvement in device performance.

[0114] Please refer to Figure 18 After forming the channel layer, a dielectric layer 210 is formed on the substrate 200, the dielectric layer 210 covering the isolation layer 204 and the first sacrificial layer 205; the first sacrificial layer 205 is removed, and word line slots are formed between adjacent isolation layers 204; the word line gate layer 211 is formed in the word line slots.

[0115] In this embodiment, the word line gate layer 211 is a metal gate used to control the opening and closing of the channel layer.

[0116] In this embodiment, the projection area of ​​the isolation layer 204 toward the substrate 200 is located within the projection area of ​​the word line gate layer 211 toward the substrate 200, and the groove 206 is provided between adjacent word line gate layers 211.

[0117] Please refer to Figure 19 After forming the word line gate layer 211, a conductive layer 212 is formed, which is electrically connected to the channel layer; a bit line layer 213 is formed, which is electrically connected to the conductive layer 212.

[0118] In this embodiment, the method for forming the conductive layer 212 includes: etching back the dielectric layer 210 to form a groove 206, the groove 206 exposing a portion of the channel layer; and forming the conductive layer 212 within the groove 206.

[0119] In this embodiment, the conductive layer 212 is made of silicon.

[0120] In this embodiment, the bit line layer 213 is used to connect to the drain layer (not shown) formed in subsequent processes. Since the formed memory structure consists of several transistors connected in series and stacked sequentially, and all transistors share the same drain layer, only one drain layer needs to be formed.

[0121] Accordingly, this invention also provides a memory structure, please refer to the following: Figure 19 The system includes: a substrate 200; a plurality of isolation layers 204 and a plurality of word line gate layers 211 located on the substrate 200, wherein the isolation layers 204 and the word line gate layers 211 are stacked alternately in sequence, and the word line gate layers 211 are located between adjacent isolation layers 204; a charge trapping layer 207 located on the sidewalls of the isolation layers 204 and the word line gate layers 211; and a channel layer located on the sidewalls of the charge trapping layer 207, wherein the channel layer located on the sidewalls of the isolation layers 204 includes a metal compound layer 208.

[0122] The channel layer located on the sidewall of the isolation layer 204 includes a metal compound layer 208, which can effectively reduce resistance. Moreover, at nodes with a higher number of memory structure layers, the channel layer with the metal silicide layer has a greater advantage and a more significant improvement in device performance.

[0123] In this embodiment, the projection area of ​​the isolation layer 204 toward the substrate 200 is located within the projection area of ​​the word line gate layer 211 toward the substrate 200, and the groove 206 is provided between adjacent word line gate layers 211.

[0124] In this embodiment, the charge trapping layer 207 includes: a blocking layer located on the sidewalls of the isolation layer 204 and the word line gate layer 211, a storage layer located on the sidewalls of the blocking layer, and a tunneling layer located on the sidewalls of the storage layer.

[0125] In this embodiment, it further includes: a conductive layer 212, which is electrically connected to the channel layer; and a bit line layer 213, which is electrically connected to the conductive layer 212.

[0126] In this embodiment, the material of the metal compound layer 208 can be nickel silicide, titanium silicide, or cobalt silicide.

[0127] While the present invention has been disclosed above, it is not limited thereto. Any person skilled in the art can make various modifications and alterations without departing from the spirit and scope of the invention; therefore, the scope of protection of the present invention should be determined by the scope defined in the claims.

Claims

1. A memory structure, comprising: Comprise: a substrate; a plurality of isolation layers and a plurality of word line grid layers on the substrate, the isolation layers and the word line grid layers are alternately stacked in sequence, the word line grid layers are located between adjacent isolation layers; a charge trapping layer on the side wall of the isolation layer and the word line grid layer; a channel layer on the side wall of the charge trapping layer, wherein the channel layer on the side wall of the isolation layer comprises a metal compound layer.

2. The memory structure of claim 1, wherein, The projection area of the word line grid layer towards the substrate is within the projection area of the isolation layer towards the substrate, and there is a groove between adjacent isolation layers.

3. The memory structure of claim 1, wherein, The projection area of the isolation layer towards the substrate is within the projection area of the word line grid layer towards the substrate, and there is a groove between adjacent word line grid layers.

4. The memory structure of claim 1, wherein, The projection area of the word line grid layer towards the substrate coincides with the projection area of the isolation layer towards the substrate.

5. The memory structure of claim 1, wherein, The channel layer on the side wall of the isolation layer is the metal compound layer.

6. The memory structure of claim 1, wherein, The channel layer on the side wall of the isolation layer comprises a semiconductor layer and a metal compound layer on the side wall of the semiconductor layer.

7. The memory structure of claim 1, wherein, The charge trapping layer comprises a barrier layer on the side wall of the isolation layer and the word line grid layer, a storage layer on the side wall of the barrier layer, and a tunneling layer on the side wall of the storage layer.

8. The memory structure of claim 1, wherein, Further comprise: a conductive layer, the conductive layer is electrically connected with the channel layer; a bit line layer, the bit line layer is electrically connected with the conductive layer.

9. A method of forming a memory structure, comprising: Comprise: providing a substrate; forming a plurality of isolation layers and a plurality of word line grid layers on the substrate, the isolation layers and the word line grid layers are alternately stacked in sequence, the word line grid layers are located between adjacent isolation layers; forming a charge trapping layer on the side wall of the isolation layer and the word line grid layer; forming a channel layer on the side wall of the charge trapping layer, wherein the channel layer on the side wall of the isolation layer comprises a metal compound layer.

10. The method of claim 9, wherein the memory structure is formed by a process selected from the group consisting of: The forming method of the word line grid layer comprises: forming a plurality of isolation layers and a plurality of first sacrificial layers on the substrate, the isolation layers and the first sacrificial layers are alternately stacked in sequence, the first sacrificial layers are located between adjacent isolation layers; removing the first sacrificial layers to form word line grooves between adjacent isolation layers; forming the word line grid layers in the word line grooves. ​ 11. The method for forming the memory structure as described in claim 10, characterized in that, The projection area of the word line grid layer towards the substrate is within the projection area of the isolation layer towards the substrate, and there is a groove between adjacent isolation layers.

12. The method of claim 11, wherein the memory structure is formed by a process selected from the group consisting of: The forming method of the channel layer comprises: etching part of the first sacrificial layer to form the groove between adjacent isolation layers; forming an initial channel layer in the side wall of the isolation layer and the groove; forming a second sacrificial layer in the groove, the second sacrificial layer covers the initial channel layer located in the groove; and performing a metallization treatment on the exposed initial channel layer to form the channel layer. ​ 13. The method for forming the memory structure as described in claim 10, characterized in that, The projection area of the isolation layer towards the substrate is within the projection area of the word line grid layer towards the substrate, and there is a groove between adjacent word line grid layers.

14. The method of claim 13, wherein The method for forming the channel layer comprises: etching part of the isolation layer to form the groove between the adjacent first sacrificial layers; forming a first sub-channel layer in the groove; performing a metallization process on the first sub-channel layer to form the metal compound layer; after forming the metal compound layer, forming a second sub-channel layer on the side wall of the first sacrificial layer and the side wall of the metal compound layer, and forming the channel layer by the metal compound layer and the second sub-channel layer.

15. The method for forming the memory structure as described in claim 9, characterized in that, The projection area of the word line grid layer on the substrate is in the same range as the projection area of the isolation layer on the substrate.

16. The method of claim 9, wherein The channel layer on the side wall of the isolation layer is the metal compound layer.

17. The method for forming the memory structure as described in claim 9, characterized in that, The channel layer on the side wall of the isolation layer comprises a semiconductor layer and the metal compound layer on the side wall of the semiconductor layer.

18. The method of forming a memory structure of claim 9, wherein, After forming the channel layer, the method further comprises: forming a conductive layer electrically connected to the channel layer; and forming a bit line layer electrically connected to the conductive layer.

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