Memory device

Abstract

The present disclosure provides a memory device with improved reliability. According to one embodiment, a memory device includes a memory cell array. Comprising a first local wiring extending in a first direction, a second local wiring extending in a second direction intersecting with the first direction, a third local wiring extending in the second direction, a first memory cell arranged between the first local wiring and the second local wiring, and a second memory cell arranged between the first local wiring and the third local wiring; a first switching circuit connected to the first local wiring and provided on one end side of the memory cell array in the first direction; a second switching circuit connected to the second local wiring and the third local wiring and provided on one end side of the memory cell array in the second direction; a first circuit that performs a write operation or a read operation of the memory cell array; and a first global wiring and a second global wiring connected between the second switching circuit and the first circuit, the second local wiring is disposed between the first switching circuit and the third local wiring in the first direction, the second local wiring is connected to the first global wiring via the second switching circuit, and the third local wiring is connected to the second global wiring via the second switching circuit. The length of the second global wiring is shorter than the length of the first global wiring.

Description

Technical Field

[0001] Embodiments of the present invention relate to memory devices. Background Technology

[0002] Memory devices that use variable resistance elements (e.g., magnetoresistive effect elements) as storage elements are known. Various technologies related to memory devices have been researched and developed to improve their characteristics. Summary of the Invention

[0003] The storage device implemented in this way improves the reliability of the storage device.

[0004] The storage device according to the embodiment includes: a storage cell array, including a first partial wiring extending along a first direction, a second partial wiring extending along a second direction intersecting the first direction, a third partial wiring extending along the second direction, a first storage cell disposed between the first partial wiring and the second partial wiring, and a second storage cell disposed between the first partial wiring and the third partial wiring; a first switching circuit connected to the first partial wiring and disposed at one end of the storage cell array in the first direction; and a second switching circuit connected to the second partial wiring and the third partial wiring. A first circuit is disposed at one end of the storage cell array in the second direction; a second circuit performs a write operation or a read operation of the storage cell array; and a first global wiring and a second global wiring are connected between the second switching circuit and the first circuit. The second local wiring is disposed between the first switching circuit and the third local wiring in the first direction. The second local wiring is connected to the first global wiring via the second switching circuit, and the third local wiring is connected to the second global wiring via the second switching circuit. The length of the second global wiring is shorter than the length of the first global wiring. Attached Figure Description

[0005] Figure 1 This is a block diagram illustrating a configuration example of the storage device according to the first embodiment.

[0006] Figure 2 This is a circuit diagram illustrating a configuration example of the memory cell array of the memory device according to the first embodiment.

[0007] Figure 3 This is a bird's-eye view showing an example of the configuration of the memory cell array of the memory device according to the first embodiment.

[0008] Figure 4 This is a cross-sectional view showing an example of the configuration of the memory cell array of the memory device according to the first embodiment.

[0009] Figure 5 This is a cross-sectional view showing an example of the configuration of the memory cell array of the memory device according to the first embodiment.

[0010] Figure 6 This is a schematic diagram showing an example of the configuration of the storage cell of the storage device according to the first embodiment.

[0011] Figure 7 This is a plan view showing an example of the configuration of the storage device according to the first embodiment.

[0012] Figure 8 This is a cross-sectional view showing an example of the configuration of the storage device according to the first embodiment.

[0013] Figure 9 This is a cross-sectional view showing an example of the configuration of the storage device according to the first embodiment.

[0014] Figure 10 This is a plan view showing an example of the configuration of the storage device according to the first embodiment.

[0015] Figure 11 This is a cross-sectional view showing an example of the configuration of the storage device according to the first embodiment.

[0016] Figure 12 This is a cross-sectional view showing an example of the configuration of the storage device according to the first embodiment.

[0017] Figure 13 This is a plan view showing an example of the configuration of the storage device according to the second embodiment.

[0018] Figure 14 This is a plan view showing an example of the configuration of the storage device according to the second embodiment.

[0019] Figure 15 This is a plan view showing an example of the configuration of the storage device according to the third embodiment.

[0020] Figure 16 This is a plan view showing an example of the configuration of the storage device according to the third embodiment.

[0021] Figure 17 This is a diagram illustrating a modified example of the storage device according to the embodiment.

[0022] Figure 18 This is a diagram illustrating a modified example of the storage device according to the embodiment.

[0023] Explanation of reference numerals in the attached figures

[0024] 100: Storage device; 110: Storage cell array; 120: Column control circuit; 121-1, 121-2: Column switching circuit; 130: Row control circuit; 131-1, 131-2: Row switching circuit; MC, MCa: Storage cell; 1: Storage element; 2: Switching element. Detailed Implementation

[0025] Hereinafter, this embodiment will be described in detail with reference to the accompanying drawings. In the following description, elements having the same function and structure are labeled with the same reference numerals.

[0026] In the following embodiments, for the same multiple components (e.g., circuits, wiring, various voltages, and signals, etc.), sometimes a number / letter is marked at the end of the reference numeral for distinction. Components marked with reference numerals at the end for distinction may use a description (reference numeral) with the numerals / letters at the end omitted when they can be used without distinguishing them from each other.

[0027] (Implementation Method)

[0028] (1) First Embodiment

[0029] Reference Figures 1 to 12 The storage device 100 of the first embodiment will be described.

[0030] (a) Example of composition

[0031] Reference Figures 1 to 12 Here, an example of the configuration of the storage device in this embodiment will be described.

[0032] (a-1) Overall Composition

[0033] Figure 1 This is a diagram showing an example of the configuration of the storage device 100 according to this embodiment.

[0034] like Figure 1 As shown, the storage device 100 of this embodiment is connected to a device (hereinafter referred to as an external device) 900 outside the storage device 100.

[0035] External device 900 sends instructions CMD, address ADR, and control signals CNT to storage device 100. Data DT is transferred between storage device 100 and external device 900. During a write operation, external device 900 sends the data to be written to storage device 100 (hereinafter referred to as write data) to storage device 100. During a read operation, external device 900 receives data read from storage device 100 (hereinafter referred to as read data).

[0036] The storage device 100 in this embodiment includes a storage cell array 110, a column control circuit 120, a row control circuit 130, a write circuit 140, a read circuit 150, a voltage generation circuit 160, an input / output circuit 170, and a control circuit 180.

[0037] The memory cell array 110 includes multiple memory cells MC, multiple word lines WL, and multiple bit lines BL.

[0038] Multiple memory cells (MCs) are associated with multiple rows and columns within the memory cell array 110. Each memory cell (MC) is connected to a corresponding word line (WL) among multiple word lines (WL). Each memory cell (MC) is connected to a corresponding bit line (BL) among multiple bit lines (BL).

[0039] Column control circuit 120 controls the columns of memory cell array 110. Column control circuit 120 is connected to memory cell array 110 via bit lines (local wiring) BL. Column control circuit 120 receives the column address (or the decoded result of the column address) of memory cell array 110 from address ADR. Column control circuit 120 controls multiple bit lines BL based on the decoded result of the column address. Thus, column control circuit 120 sets each of the multiple bit lines BL (multiple columns) to a selected state or a non-selected state. Hereinafter, the bit line BL set to the selected state is referred to as the selected bit line BL, and the bit lines BL other than the selected bit line BL are referred to as the non-selected bit line BL. Column control circuit 120 includes one or more column switch circuits 121. Each column switch circuit 121 controls the connection between the selected bit line BL and the global wiring described later.

[0040] Row control circuit 130 controls the rows of memory cell array 110. Row control circuit 130 is connected to memory cell array 110 via word lines (local wiring) WL. Row control circuit 130 receives the row address (or the decoded result of the row address) of memory cell array 110 from address ADR. Row control circuit 130 controls multiple word lines WL based on the decoded result of the row address. Thus, row control circuit 130 sets each of the multiple word lines WL (multiple rows) to a selected state or a non-selected state. Hereinafter, the word line WL set to the selected state is called the selected word line WL, and the word lines WL other than the selected word line WL are called the non-selected word lines WL. Row control circuit 130 includes one or more row switch circuits 131. Each row switch circuit 131 controls the connection between the selected word line WL and the global wiring described later.

[0041] The write circuit 140 writes data to the memory cell MC. The write circuit 140 is connected to the column control circuit 120 and the row control circuit 130 via global routing (GBL, GWL). The write circuit 140 supplies voltage (or current) for writing data to the select word line WL and the select bit line BL via the global routing (GBL, GWL), respectively. Thus, a certain write voltage (or write current) is supplied to the selected memory cell MC. The write circuit 140 can supply any of a plurality of write voltages corresponding to the write data to the selected memory cell MC. For example, each of the plurality of write voltages has a polarity (bias direction) corresponding to the write data. For example, the write circuit 140 includes a write driver (not shown) and a write synchronizer (not shown), etc.

[0042] The readout circuit 150 reads data from the memory cell MC. The readout circuit 150 is connected to the column control circuit 120 and the row control circuit 130 via global routing (GBL) and GWL. The readout circuit 150 amplifies the signal output from the selected memory cell MC to the select bit line BL. The readout circuit 150 determines the data within the memory cell MC based on the amplified signal. For example, the readout circuit 150 includes a preamplifier (not shown), a sense amplifier (not shown), a readout driver (not shown), and a readout synchronizer (not shown).

[0043] The voltage generation circuit 160 uses the power supply voltage provided from the external device 900 to generate voltages for various operations of the memory cell array 110. For example, the voltage generation circuit 160 generates various voltages for write operations. The voltage generation circuit 160 outputs the generated voltages to the write circuit 140. For example, the voltage generation circuit 160 generates various voltages for read operations. The voltage generation circuit 160 outputs the generated voltages to the read circuit 150.

[0044] Input / output circuit 170 functions as an interface circuit for various signals (ADR, CMD, CNT, DT) between storage device 100 and external device 900. Input / output circuit 170 transmits address (ADR) from external device 900 to control circuit 180. Input / output circuit 170 transmits instruction (CMD) from external device 900 to control circuit 180. Input / output circuit 170 transmits various control signals (CNT) between external device 900 and control circuit 180. Input / output circuit 170 transmits write data (DT) from external device 900 to write circuit 140. Input / output circuit 170 transmits data (DT) from read circuit 150 as read data to external device 900.

[0045] The control circuit (also referred to as a sequencer, state machine, or internal controller) 180 decodes the instruction CMD. Based on the decoding result of the instruction CMD and the control signal CNT, the control circuit 180 controls the operation of the column control circuit 120, row control circuit 130, write circuit 140, read circuit 150, voltage generation circuit 160, and input / output circuit 170 within the storage device 100. The control circuit 180 decodes the address ADR. The control circuit 180 sends the decoding result of the address ADR to the column control circuit 120 and row control circuit 130, etc. For example, the control circuit 180 includes a register circuit (not shown) that temporarily stores the instruction CMD and the address ADR. Furthermore, the register circuit, the circuit for decoding the instruction CMD (instruction decoder), and the circuit for decoding the address ADR (address decoder) may also be external to the control circuit 180 but located within the storage device 100.

[0046] (a-2) Storage cell array

[0047] Reference Figures 2 to 5 An example of the configuration of the storage cell array 110 in the storage device 100 of this embodiment will be described.

[0048] Figure 2 This is an equivalent circuit diagram showing an example of the configuration of the memory cell array 110 of the memory device 100 in this embodiment.

[0049] like Figure 2 As shown, multiple memory cells (MCs) are arranged in a matrix within the memory cell array 110. Each memory cell (MC) is connected to multiple bit lines (BLs). <1> BL <2> BL <n>The corresponding bit line BL and multiple word lines WL (WL) in the text. <1> WL <2> ... WL <m>The corresponding word line WL in ) . M and N are integers greater than or equal to 1.

[0050] Each storage unit MC includes a storage element 1 and a switching element 2.

[0051] Storage element 1 is, for example, a variable resistance element. The resistance state of storage element 1 changes to any one of a plurality of resistance states (e.g., a low resistance state and a high resistance state) depending on the supplied voltage (or current). Storage element 1 can store data by associating the resistance state of element 1 with data (e.g., "0" data and "1" data).

[0052] The switching element (or selector element, or simply selector) 2 functions as the selection element for the storage cell MC. The switching element 2 controls the voltage (or current) supply to the storage cell 1 when writing data to and reading data from the corresponding storage cell 1.

[0053] For example, when a voltage applied to a memory cell MC is lower than the threshold voltage of switching element 2 within that memory cell MC, switching element 2 is set to an OFF state (high resistance state, non-conducting state). In this case, switching element 2 cuts off the voltage (or current) to memory element 1. When a voltage applied to a memory cell MC is higher than the threshold voltage of switching element 2 within that memory cell MC, switching element 2 is set to an ON state (low resistance state, conducting state). In this case, switching element 2 supplies voltage (or current) to memory element 1.

[0054] Regardless of the direction of current flow within the storage cell MC, the switching element 2 can switch between having current flowing or not flowing within the storage cell MC based on the magnitude of the voltage applied to the storage cell MC.

[0055] For example, switch element 2 is a two-terminal type element. In Figure 2 In this example, one end of switching element 2 is connected to word line WL. The other end of switching element 2 is connected to one end of storage element 1. The other end of storage element 1 is connected to bit line BL.

[0056] Figures 3 to 5 This is a diagram illustrating an example of the configuration of the memory cell array 110 of the memory device 100 in this embodiment. Figure 3 This is a bird's-eye view illustrating an example of the configuration of the storage cell array 110. Figure 4 This is a schematic cross-sectional view showing the cross-sectional structure of the memory cell array 110 along the first direction (axis). Figure 5 This is a schematic cross-sectional view showing the cross-sectional configuration of the memory cell array 110 along the second direction (axis). Figures 3 to 5 In the example, the first direction corresponds to the X direction, and the second direction corresponds to the Y direction.

[0057] like Figures 3 to 5 As shown, the memory cell array 110 is disposed above the upper surface of the substrate 90. The X direction is a direction parallel to the upper surface of the substrate 90. The Y direction is a direction parallel to the upper surface of the substrate 90 and intersecting the X direction. Hereinafter, the surface parallel to the upper surface of the substrate 90 is called the XY plane. The direction (axis) perpendicular to the XY plane is designated as the Z direction (Z-axis). The surface parallel to the surface encompassing both the X and Z directions is called the XZ plane. The surface parallel to the surface encompassing both the Y and Z directions is called the YZ plane.

[0058] Multiple wirings (conductive layers) 50 are disposed above the upper surface of the substrate 90 in the Z direction, separated by an insulating layer 80. The multiple wirings 50 are arranged along the X direction. Each wiring 50 extends along the Y direction. The multiple wirings 50 function, for example, as word lines (WL).

[0059] Multiple wirings (conductive layers) 51 are disposed above multiple wirings 50 in the Z direction. The multiple wirings 51 are arranged along the Y direction. Each wiring 51 extends along the X direction. The multiple wirings 51 function, for example, as bit lines BL.

[0060] Multiple memory cells MC are disposed between multiple wirings 50 and multiple wirings 51. The multiple memory cells MC are arranged in a matrix in the XY plane.

[0061] Multiple memory cells MC arranged in the Y direction are positioned above a wiring 50. Two memory cells MC arranged in the Y direction are adjacent to each other with a predetermined interval. The multiple memory cells MC arranged in the Y direction are each connected to a common wiring 50 (word line WL) via a corresponding contact 52. Multiple contacts 52 are disposed on a wiring 50.

[0062] Multiple memory cells MC arranged in the X direction are disposed below a wiring 51. Two memory cells MC arranged in the X direction are adjacent to each other with a predetermined interval. The multiple memory cells MC arranged in the X direction are each connected to a common wiring 51 (bit line BL) via a corresponding contact 53. Multiple contacts 53 are disposed below a wiring 51.

[0063] For example, in the storage cell array 110 having Figure 2 In the circuit configuration, the switching element 2 is positioned below the storage element 1 in the Z direction. The switching element 2 is positioned between the storage element 1 and the wiring 50 (word line WL). The storage element 1 is positioned between the wiring 51 (bit line BL) and the switching element 2.

[0064] Thus, each memory cell MC is a stack of memory element 1 and switching element 2. Through these memory cells MC, the memory cell array 110 has a stacked configuration.

[0065] The memory cell MC sometimes has a tapered cross-sectional shape depending on the process (e.g., etching method) used in the formation of the memory cell array 110.

[0066] An insulating layer 60 is disposed above the substrate 90. The insulating layer 60 covers the memory cell MC, wiring 50, 51, and contacts 52, 53. An insulating layer 62 is disposed on the insulating layer 60 and the wiring 51.

[0067] exist Figure 4 as well as Figure 5 The diagram illustrates an example where an insulating layer 80 is disposed between multiple wirings 50 and a substrate 90. When the substrate 90 is a semiconductor substrate, one or more field-effect transistors (FETs) TR can also be disposed on a semiconductor region on the upper surface of the substrate 90. The FETs TR are covered by the insulating layer 80. The FETs TR are disposed on a semiconductor region surrounded by a component separation insulating layer 99. The FETs TR include a gate electrode 91, a gate insulating film 92, and source / drain layers 93a and 93b. The source / drain layers (diffusion layers) 93a and 93b are disposed within the semiconductor region. The gate electrode 91 is disposed on the semiconductor region between the source / drain layers 93a and 93b, separated by the gate insulating film 92. A contact plug CP is disposed on the gate electrode 91 and the source / drain layers 93a and 93b.

[0068] Within the insulating layer 80, multiple conductive layers M0, M1, M2, M3 with a multilayer wiring structure, contact plugs CP, and via plugs VP (VP0, VP1, VP2, VP3) are provided. The field-effect transistor TR on the substrate 90 is a component of circuits such as the column control circuit 120 and the row control circuit 130. The field-effect transistor TR is connected to the memory cell array 110 via the conductive layers M0, M1, M2, M3 within the insulating layer 80, and the contact plugs CP and via plugs VP0, VP1, VP2, VP3. Thus, circuitry for controlling the operation of the memory cell array 110 can be provided below the memory cell array 110 in the Z direction.

[0069] The circuit configuration and structure of the stacked memory cell array 110 are not limited to Figures 2 to 5 The example shown illustrates this. Based on the connection relationships of storage element 1 and switching element 2 relative to bit line BL and word line WL, the circuit configuration and structure of the memory cell array 110 can be appropriately modified. For example, it may have... Figure 2 The construction of the memory cell array 110 composed of circuits is not limited to Figures 3 to 5 For example, the switching element 2 can also be positioned above the storage element 1 in the Z direction. In this case, wiring 50 is used as the bit line BL, and wiring 51 is used as the word line WL.

[0070] (a-3) Storage unit

[0071] Figure 6 This is a cross-sectional view showing an example of the configuration of the storage cell MC in the storage device 100 of this embodiment.

[0072] like Figure 6 As shown, in the storage cell MC of the stack, storage element 1 and switching element 2 are arranged in the Z direction. In this example, storage element 1 is disposed on switching element 2 in the Z direction.

[0073] For example, the variable resistance element as storage element 1 is a magnetoresistive element. In this case, the storage device 100 of this embodiment is a magnetic memory such as MRAM (Magnetoresistive Random Access Memory).

[0074] <Example of a magnetoresistive element>

[0075] For example, the magnetoresistive element 1 includes at least two magnetic layers 11 and 13 and a non-magnetic layer 12. The non-magnetic layer 12 is disposed between the two magnetic layers 11 and 13 in the Z direction. Figure 6 In the example, from the word line WL (wiring 50) side toward the bit line BL (wiring 51) side, multiple layers 11, 12, and 13 are arranged sequentially in the Z direction in the order of magnetic layer 11, non-magnetic layer 12, and magnetic layer 13.

[0076] Two magnetic layers 11 and 13 and a non-magnetic layer 12 form a magnetic tunnel junction. Hereinafter, the magnetoresistive effect element 1 including the magnetic tunnel junction is referred to as MTJ (Magnetic Tunnel Junction) element 1. The non-magnetic layer 12 in MTJ element 1 is referred to as the tunnel barrier layer.

[0077] Magnetic layers 11 and 13 are, for example, ferromagnetic layers containing cobalt (Co), iron (Fe), and / or boron (B). Magnetic layers 11 and 13 can be monolayer films (e.g., alloy films) or multilayer films (e.g., artificial lattice films). Tunnel barrier layer 12 is, for example, an insulating layer containing magnesium oxide. Tunnel barrier layer 12 can be a monolayer film or a multilayer film.

[0078] When MTJ element 1 is a perpendicularly magnetized magnetoresistive element, each magnetic layer 11 and 13 exhibits perpendicular magnetic anisotropy. The easy magnetization axis of each magnetic layer 11 and 13 is perpendicular to the surface (film) of the magnetic layers 11 and 13. Each magnetic layer 11 and 13 has magnetization perpendicular to its surface. The direction of magnetization of each magnetic layer 11 and 13 is parallel to the alignment direction (Z direction) of the magnetic layers 11 and 13.

[0079] In the two magnetic layers 11 and 13, the orientation of magnetization of one magnetic layer is variable, while the orientation of magnetization of the other magnetic layer remains constant. The MTJ element 1 can have multiple resistance states (resistance values) based on the relative relationship (magnetization arrangement) between the orientations of magnetization of one magnetic layer and the other magnetic layer.

[0080] For example, the magnetization orientation of magnetic layer 13 is variable. The magnetization orientation of magnetic layer 11 is constant (fixed state). Hereinafter, magnetic layer 13 with variable magnetization orientation is referred to as a storage layer. Hereinafter, magnetic layer 11 with constant magnetization orientation (fixed state) is referred to as a reference layer. Furthermore, storage layer 13 is sometimes referred to as a free layer, a magnetized free layer, or a magnetized variable layer. Reference layer 11 is sometimes referred to as a pinned layer, a pinned layer, a magnetized constant layer, or a magnetized fixed layer.

[0081] In this embodiment, "the orientation of the magnetization of the reference layer (magnetic layer) remains unchanged" or "the orientation of the magnetization of the reference layer (magnetic layer) is fixed" means that when a current or voltage for changing the orientation of the magnetization of the storage layer 13 is supplied to the MTJ element 1, the orientation of the magnetization of the reference layer 11 will not change before or after the supply of the current / voltage due to the supplied current or voltage.

[0082] When the magnetization orientation of storage layer 13 is the same as that of reference layer 11 (when the magnetization arrangement of MTJ elements 1 is parallel), the resistance state of MTJ elements 1 is the first resistance state. When the magnetization orientation of storage layer 13 is different from that of reference layer 11 (when the magnetization arrangement of MTJ elements 1 is antiparallel), the resistance state of MTJ elements 1 is the second resistance state, which is different from the first resistance state. The resistance value of MTJ elements 1 in the second resistance state (antiparallel arrangement) is higher than the resistance value of MTJ elements 1 in the first resistance state (parallel arrangement).

[0083] The following refers to the magnetization arrangement state of MTJ element 1. The parallel arrangement state is also referred to as the P state, and the anti-parallel arrangement state is also referred to as the AP state.

[0084] For example, MTJ element 1 is connected to two electrodes 31 and 32. Magnetic layers 11 and 13 and tunnel barrier layer 12 are disposed between the two electrodes 31 and 32 in the Z direction. Reference layer 11 is disposed between electrode (referred to as intermediate electrode) 31 and tunnel barrier layer 12. Storage layer 13 is disposed between electrode (referred to as upper electrode) 32 and tunnel barrier layer 12.

[0085] For example, a displacement elimination layer 14 can be disposed within the MTJ element 1. In this case, the displacement elimination layer 14 is disposed between the reference layer 11 and the intermediate electrode 31. The displacement elimination layer 14 is a magnetic layer used to mitigate the influence of the leakage magnetic field of the reference layer 11. When the MTJ element 1 includes the displacement elimination layer 14, a non-magnetic layer 15 is disposed between the displacement elimination layer 14 and the reference layer 11. The non-magnetic layer 15 is, for example, a metal layer such as a ruthenium (Ru) layer. The displacement elimination layer 14 is antiferromagnetically coupled to the reference layer 11 via the non-magnetic layer 15. Thus, the stack including the reference layer 11 and the displacement elimination layer 14 forms a SAF (Synthetic antiferromagnetic) structure. In the SAF structure, the magnetization orientation of the displacement elimination layer 14 is opposite to the magnetization orientation of the reference layer 11. Through the SAF structure, the magnetization orientation of the reference layer 11 can be more stably fixed. In addition, the combination of the two magnetic layers 11 and 14 and the non-magnetic layer 15 that form the SAF structure is sometimes referred to as the reference layer.

[0086] For example, the MTJ element 1 may include at least one of a base layer (not shown) and a capping layer (not shown). The base layer is disposed between the magnetic layer (here, a shift-eliminating layer) 14 and the intermediate electrode 31. The base layer is a non-magnetic layer (e.g., a conductive layer). The base layer is a layer used to improve the properties (e.g., crystallinity and / or magnetic properties) of the magnetic layer 14 in contact with the base layer. The capping layer is disposed between the magnetic layer (here, a storage layer) 13 and the upper electrode 32. The capping layer is a non-magnetic layer (e.g., a conductive layer). The capping layer is a layer used to improve the properties (e.g., crystallinity and / or magnetic properties) of the magnetic layer 13 in contact with the capping layer. Furthermore, the base layer and the capping layer may each be considered as constituent elements of the electrodes 31 and 32.

[0087] <Example of a switching element>

[0088] like Figure 6 As shown, when the switching element 2 is a two-terminal type element, the switching element 2 includes at least one variable resistor layer (also referred to as a switch layer or selector layer) 20. The variable resistor layer 20 is disposed between the two electrodes 30 and 31 in the Z direction. The variable resistor layer 20 can take multiple resistance states.

[0089] An electrode (referred to as the lower electrode) 30 is disposed below the variable resistor layer 20 in the Z direction, and an intermediate electrode 31 is disposed above the variable resistor layer 20 in the Z direction. For example, the lower electrode 30 is disposed between the wiring 50 and the variable resistor layer 20. The electrode 31 is disposed between the variable resistor layer 20 and the MTJ element 1.

[0090] The variable resistance layer 20 is connected to the wiring 50 via the lower electrode 30 and the contact 52. The variable resistance layer 20 is connected to the MTJ element 1 via the middle electrode 31.

[0091] Depending on the voltage applied to the switching element 2 (memory cell MC), the resistance state of the variable resistor layer 20 becomes either a high resistance state (non-conducting state) or a low resistance state (conducting state). When the resistance state of the variable resistor layer 20 is high, the switching element 2 is off. When the resistance state of the variable resistor layer 20 is low, the switching element 2 is on.

[0092] When the memory cell MC is set to the selected state, the switching element 2 is turned on, therefore, the resistance state of the variable resistor layer 20 becomes a low resistance state. When the memory cell MC is set to the non-selected state, the switching element 2 is turned off, therefore, the resistance state of the variable resistor layer 20 becomes a high resistance state.

[0093] Furthermore, depending on the material of the variable resistance layer 20, the change in the resistance state of the variable resistance layer 20 may also depend on the current flowing in the switching element 2 (memory cell MC) (e.g., the magnitude of the current).

[0094] For example, the lower electrode 30 and the upper electrode 32 are conductive layers made of titanium (Ti), tungsten (W), titanium nitride (TiN), or tungsten nitride (WN). The intermediate electrode 31 is a conductive layer made of carbon (C) or carbon nitride (CN).

[0095] have Figures 3 to 6 The constructed storage cell array 110 can be formed using well-known techniques.

[0096] (a-4) Composition of global word lines and global bit lines

[0097] Figures 7 to 12 This is a diagram illustrating the configuration of the global wiring within the memory cell array 110 of the MRAM 100 in this embodiment.

[0098] Figure 7 This is a plan view showing an example of the configuration of global word lines in the MRAM100 of this embodiment.

[0099] like Figure 7 As shown, the storage cell array 110 has a quadrilateral layout when viewed from the Z direction.

[0100] M bar line WL <1> WL <2> ... WL <x>……、WL <m-1>、WL <m>The memory cell array 110 is arranged in the X direction at predetermined intervals. N bit lines BL <1> BL <2> BL <y>……、BL <n-1>、BL <n>The memory cell array 110 is arranged at predetermined intervals in the Y direction. Bit lines BL are positioned above word lines WL in the Z direction. Multiple word lines WL have the same length. Multiple bit lines BL have the same length.

[0101] For example, a memory cell MC is configured at coordinates (x, y) within the memory cell array 110. The memory cell MC is located at word line WL. <x>With bit line BL <y>The position of the intersection. x is an integer greater than or equal to 1 and less than M. y is an integer greater than or equal to 1 and less than N.

[0102] For example, the value of "M" is equal to the value of "N". The spacing between memory cells MC in the X direction is equal to the spacing between memory cells MC in the Y direction. The memory cell array 110 has a square layout (planar structure) when viewed from the Z direction.

[0103] When multiple memory cells MC are arranged at predetermined intervals in the X direction, the wiring resistance between two adjacent memory cells MC in the X direction has a resistance value of "Rs_x". When the address of word line WL changes by 1, the wiring resistance applied to the memory cell MC changes by the amount corresponding to "Rs_x". When multiple memory cells MC are arranged at predetermined intervals in the Y direction, the wiring resistance between two adjacent memory cells MC in the Y direction has a resistance value of "Rs_y". When the address of bit line BL changes by 1, the wiring resistance applied to the memory cell MC changes by the amount corresponding to "Rs_y".

[0104] For example, in this embodiment, the value of "Rs_x" is equal to the value of "Rs_y". Hereinafter, the resistance between memory cells MC is also denoted as "Rs".

[0105] like Figure 7 As shown, in the MRAM of this embodiment, the row control circuit 130 includes a row switch circuit 131-1. The row switch circuit 131-1 is disposed at one end of the memory cell array 110 in the Y direction. Hereinafter, within the memory cell array 110, the region on the side closer to the row switch circuit 131-1 is referred to as the near region (near side), and the region on the side farther from the row switch circuit 131-1 is referred to as the far region (far side).

[0106] The horizontal switching circuit 131-1 is connected to multiple word lines WL. The horizontal switching circuit 131-1 is connected to multiple global word lines GWL (GWL... <1> ,GWL <xx>、 SEE Each global word line (GWL) is connected to the write circuit 140 and the read circuit 150.

[0107] The row switching circuit 131-1 includes multiple row switches SWR. The row switches SWR are, for example, field-effect transistors TR. One end of each row switch SWR is electrically connected to a corresponding word line WL among multiple word lines WL. The other end of each row switch SWR is electrically connected to a corresponding global word line GWL among multiple global word lines GWL.

[0108] In the row switch circuit 131-1, each row switch SWR is set to an on or off state according to the supplied address ADR. Depending on the on / off state of the multiple row switches SWR in the row switch circuit 131-1, a word line WL is electrically connected to the global word line GWL via a row switch SWR in the on state.

[0109] The distance between the storage cell MC and the column switch SWC changes according to the X-direction (row) coordinate of the storage cell MC within the storage cell array 110.

[0110] As a result, when the MRAM100 is in operation, the wiring resistance of the bit line BL applied to the memory cell MC within the memory cell array 110 varies according to the X-direction (row) coordinate of the memory cell MC.

[0111] In this embodiment, multiple global word lines GWL have different lengths. Therefore, the MRAM 100 of this embodiment can mitigate the effects caused by differences in the wiring resistance of the bit lines BL corresponding to the coordinates of the memory cells MC.

[0112] In a certain line of BL <y>It is connected to multiple storage units MCa, MCb, and MCc.

[0113] The memory cell MCa is connected to the word line WL <1> The memory cell MCb is connected to the word line WL. <x>The memory cell MCC is connected to the word line WL. <m>.

[0114] The Y-axis (column) coordinates of memory cells MCa, MCb, and MCc are the same. The distances between memory cells MCa, MCb, and MCc and their corresponding row switches SWR are also the same. Therefore, the wiring resistance (hereinafter referred to as word line resistance) applied to the word line WL of each memory cell MCa, MCb, and MCc is the same (y×Rs_y).

[0115] The X-direction (row) coordinates of memory cells MCa, MCb, and MCc are different. Therefore, the distances between memory cells MCa, MCb, and MCc and the column switch circuit 121 (column switch SWC) are different. As a result, the wiring resistance (hereinafter referred to as bit line resistance) applied to the bit line BL of each memory cell MCa, MCb, and MCc is different. The bit line resistance between the nearby memory cell MCa and the column switch SWC is "1×Rs_x". The bit line resistance between memory cell MCb and the column switch SWC is "x×Rs_x". The bit line resistance between the distant memory cell MCc and the column switch SWC is "M×Rs_x". The bit line resistance (1×Rs_x) between memory cell MCa and the column switch SWC is lower than the bit line resistance x×Rs_x and the bit line resistance M×Rs_x. The bit line resistance x×Rs_x between memory cell MCb and column switch SWC is higher than the bit line resistance 1×Rs_x but lower than the bit line resistance M×Rs_x. The bit line resistance M×Rs_x between memory cell MCc and column switch SWC is higher than both the bit line resistance 1×Rs_x and the bit line resistance x×Rs_x.

[0116] Thus, for multiple memory cells MC connected to a common bit line BL, the magnitude of the bit line resistance applied to the selected memory cell MC varies according to the X coordinate of the memory cell MC.

[0117] Each global word line (GWL) is associated with a set of multiple word lines (hereinafter referred to as word line groups) WG1, WGxx, and WGi. Each word line group WG1, WGxx, and WGi includes a predetermined number of word lines (WL).

[0118] Global Word Line (GWL) <1> The word line WL is located in the region of the memory cell array 110 in the X direction, which includes the side with the column switch circuit 121-1 configured (one end of the memory cell array 110 in the X direction). <1> The word line group WG1 is associated with it. Global word line GWL <1> Multiple word lines WL are connected to word line group WG1 via multiple row switches SWR.

[0119] Global Word Line (GWL) Word lines in the region opposite to the side of the memory cell array 110 in the X direction where the column switch circuit 121-1 is configured (the other end of the memory cell array 110 in the X direction). <m>The word line group WGi is associated with it. Global word line GWL Multiple word lines WL are connected to the word line group WGi via multiple row switches SWR.

[0120] Global Word Line (GWL) <xx>The word line WL within the region (central region) between one end and the other end of the memory cell array 110 in the X direction. <x>The word line group WGxx is associated with it. Global word line GWL <xx>Multiple word lines WL within the word line group WGxx are connected via multiple row switches SWR.

[0121] As described above, global word lines (GWL) and global bit lines (GBL) are disposed in the Z direction between the substrate 90 and the memory cell array 110. Multiple global word lines (GWL) are disposed within a multilayer wiring structure on the substrate 90.

[0122] Figure 8 as well as Figure 9 This is a cross-sectional view schematically showing a construction example of multiple global word lines (GWLs) in the MRAM100 of this embodiment.

[0123] Figure 8 Showing the Global Word Lines (GWLs) among multiple Global Word Lines (GWLs) <1> The structure of. Figure 9 Showing the Global Word Lines (GWLs) among multiple Global Word Lines (GWLs) The structure of.

[0124] like Figure 8 as well as Figure 9 As shown, a horizontal switch SWR (field-effect transistor TR) is disposed on a semiconductor substrate 90. One end of the horizontal switch SWR is connected to the word line WL via multiple conductive layers M0, M1, M2, M3, contact plugs CP, and via plugs VP0, VP1, VP2, VP3. The other end of the horizontal switch SWR is connected to one end of the global word line GWL via multiple conductive layers M0, M1, contact plugs CP, and via plugs VP0, VP1.

[0125] The field-effect transistor TR of the global switch GXSW is disposed on the semiconductor substrate 90. One end of the global switch GXSW is connected to the other end of the global word line GWL. The other end of the global switch GXSW is connected to the wiring DX via multiple conductive layers M0, 71, contact plugs CP, and via plugs VP0. The wiring DX is connected to the write circuit 140 or the read circuit 150.

[0126] Multiple global word lines (GWLs) are positioned below the memory cell array 110 in the Z direction. The GWLs connect between the transistor TR of the row switch SWR and the transistor TR of the global switch GXSW. For example, the GWLs are positioned within the layer (wiring level) of conductive layer M2. Figure 8 As shown, the global word line GWL <1> Includes a 70N conductive layer. For example... Figure 9 As shown, the global word line GWL Includes conductive layer 70F.

[0127] For example, the cross-sectional area SGWL of the global word line GWL is larger than the cross-sectional area SWL of the word line WL and the cross-sectional area SBL of the bit line BL. Therefore, the resistivity of the material used for the global word line GWL is preferably higher than that of the material used for the bit line BL. The materials of the conductive layers 70N and 70F of the global word line GWL are different from the materials of the conductive layers M0, M1, M2, and M3. The materials of the conductive layers 70N and 70F are preferably materials with relatively high resistivity. For example, the materials of the conductive layers 70N and 70F are selected from any one of tantalum (Ta), titanium (Ti), tungsten (W) oxides, tungsten nitrides, silicon (Si) oxides, and silicon nitrides. The materials of the conductive layers M0, M1, M2, and M3 are, for example, copper (Cu).

[0128] In order to adjust the length of the global word line GWL, the positions of the row switch SWR and the global switch GXSW on the semiconductor substrate 90 can be changed appropriately.

[0129] The width (dimension in the X direction) of the global word line GWL is greater than the width (dimension in the X direction) of the word line WL.

[0130] like Figures 7 to 9 As shown, the Global Word Line (GWL) mainly extends along the Y direction.

[0131] Global Word Line (GWL) <1> It has a length (wiring length) LY1. Global word line GWL <xx>It has a length of LYxx. Global word line GWL It has a length LYi. Length LY1 is longer than lengths LYxx and LYi. Length LYxx is shorter than length LY1 but longer than length LYi. Length LYi is shorter than lengths LY1 and LYxx. For example, length LY1 is equal to the dimension of the memory cell array 110 in the Y direction (the length of the set of memory cells arranged in the Y direction).

[0132] Thus, the memory cell MCa, which is shorter in distance than the column switch circuit 121-1, is connected to the global word line GWL, which has a longer wiring length. <1> The memory cell MCC, which is longer than the column switch circuit 121-1, is connected to the global word line GWL, which has a shorter wiring length. .

[0133] The resistance of a wiring is proportional to its length. Therefore, the Global Word Line (GWL) <1> The wiring resistance is higher than that of the global word line (GWL). <xx>Wiring resistors and global word lines (GWL) The wiring resistance is high. Global word line (GWL) <xx>The wiring resistance is higher than that of the global word line (GWL). <1> The wiring resistance is low and higher than that of the Global Word Line (GWL). The wiring resistance is high. Global word line (GWL) The wiring resistance is higher than that of the global word line (GWL). <1> Wiring resistors and global word lines (GWL) <xx>The wiring resistance is low.

[0134] When the resistance per unit length of the global word line GWL is represented by "RGWL", the global word line GWL <1> The wiring resistor is "LY1×RGWL", and the global word line is GWL. <xx>The wiring resistor is "LYxx×RGWL", and the global word line is GWL. The wiring resistance is "LYi×RGWL".

[0135] For example, the difference between the bit line resistance of memory cell MCa and the bit line resistance of memory cell MCc is "(M-1)×Rs_x". Additionally, the global word line GWL... <1> The resistance value and the global word line GGL The difference in resistance values ​​is "(LY1-LYi)×RGWL".

[0136] When the difference in bit line resistance is offset, the size of (LY1-LYi)×RGWL is preferably close to the size of (M-1)×Rs_x. When the size of (LY1-LYi)×RGWL is equal to the size of (M-1)×Rs_x, the effect of the difference in bit line resistance becomes practically zero.

[0137] When the unit length Ly of the global word line GWL is represented as the same as the pitch between memory cells MC, "N×RGWL×Ly" is preferably equal to "M×Rs_x". When N and M are equal, the resistivity per unit length of the global word line GWL can be equal to the resistivity per unit length of the bit line.

[0138] As described above, the difference in bit line resistance corresponding to the X-axis coordinate of the memory cell MC is reduced by the difference in wiring resistance of the global word line GWL.

[0139] Figure 10 This is a plan view showing an example of the configuration of the Global Bit Line (GBL) in the MRAM 100 of this embodiment.

[0140] In MRAM 100, column control circuit 120 includes column switch circuit 121-1. Column switch circuit 121-1 is disposed at one end of memory cell array 110 in the X direction. Hereinafter, within memory cell array 110, the region on the side closer to column switch circuit 121-1 is referred to as the near region (near side), and the region on the side farther from column switch circuit 121-1 is referred to as the far region (far side).

[0141] Column switch circuit 121-1 is connected to multiple bit lines BL. Column switch circuit 121-1 is connected to multiple global bit lines GBL (GBL). <1> GBL <yy>、GBL <j>Each global bit line (GBL) is connected to the write circuit 140 and the read circuit 150.

[0142] The column switch circuit 121-1 includes multiple column switches SWC. The column switches SWC are, for example, field-effect transistors (TR). One end of each column switch SWC is electrically connected to a corresponding bit line BL among multiple bit lines BL. The other end of each column switch SWC is electrically connected to a corresponding global bit line GBL among multiple global bit lines GBL.

[0143] In column switch circuit 121-1, each column switch SWC is set to an on or off state according to the supplied address ADR. Based on the on / off state of the multiple column switches SWCs in column switch circuit 121-1, a bit line BL is electrically connected to the corresponding global bit line GBL via the on-state column switch SWC.

[0144] The distance between the storage cell MC and the row switch SWR varies according to the Y-direction (column) coordinate of the storage cell MC within the storage cell array 110.

[0145] As a result, when the MRAM100 is operating, the wiring resistance of the word line WL applied to the memory cell MC within the memory cell array 110 varies depending on the Y-axis coordinate of the memory cell MC.

[0146] In this embodiment, multiple global bit lines (GBLs) have different lengths. Therefore, the MRAM 100 of this embodiment can mitigate the effects of differences in the wiring resistance of word lines (WLs) caused by the coordinates of the memory cells (MCs).

[0147] like Figure 10 As shown, in a certain word line WL <x>It is connected to multiple storage units MCd, MCe, and MCf.

[0148] The memory cell MCd is connected to the bit line BL. <1> The memory cell MCe is connected to the bit line BL. <y>The memory cell MCf is connected to the bit line BL. <n>.

[0149] The X-axis (row) coordinates of memory cells MCd, MCe, and MCf are the same. Therefore, the bit line resistance applied to each memory cell MCd, MCe, and MCf is the same (x×Rs_x).

[0150] The Y-coordinates of memory cells MCd, MCE, and MCf are different. Therefore, the distances between each memory cell MCd, MCE, and MCf and the row switch circuit 131 (row switch SWR) are different. As a result, the word line resistance applied to each memory cell MCd, MCE, and MCf is different. The word line resistance between the nearby memory cell MCd and the row switch SWR is "1×Rs_y". The word line resistance between the memory cell MCE and the row switch SWR is "y×Rs_y". The word line resistance between the distant memory cell MCf and the row switch SWR is "N×Rs_y". The word line resistance 1×Rs_y between memory cell MCd and the row switch SWR is lower than the word line resistances y×Rs_y and N×Rs_y. The word line resistance y×Rs_y between memory cell MCE and the row switch SWR is higher than the word line resistance 1×Rs_y but lower than the word line resistance N×Rs_y. The word line resistance N×Rs_y between the memory cell MCf and the row switch SWR is higher than the word line resistance 1×Rs_y and the word line resistance N×Rs_y.

[0151] Thus, for multiple memory cells MC connected to a common word line WL, the magnitude of the word line resistance applied to the selected memory cell MC varies according to the Y coordinate of the memory cell MC.

[0152] Furthermore, the resistivity per unit length (Ω / nm) of the global word line GWL is preferably the same as that of the bit line BL.

[0153] like Figure 10 As shown, each global bit line (GBL) is associated with a set of multiple bit lines (hereinafter referred to as bit line groups) BG1, BGyy, and BGj. Each bit line group BG1, BGyy, and BGj includes a predetermined number of bit lines (BL).

[0154] Global Bitline (GBL) <1> Bit line group BG1 is associated with bit line BL1 in the region comprising the side of the memory cell array 110 in the Y direction where the row switching circuit 131-1 is configured (one end of the memory cell array 110 in the Y direction). Global bit line GBL <1> Multiple bit lines BL within bit line group BG1 are connected via multiple column switches SWC.

[0155] Global Bitline (GBL) <j>Bit line BL in the region opposite to the side of the memory cell array 110 in the Y direction where the row switching circuit 131-1 is configured (the other end of the memory cell array 110 in the Y direction). <n>The bit line group BGj is associated with it. Global bit line GBL <j>Multiple bit lines BL within bit line group BGj are connected via multiple column switches SWC.

[0156] Global Bitline (GBL) <yy>Bit lines BL within the region (central region) between one end and the other end of the memory cell array 110 in the Y direction <y>The bit line group BGyy is associated with it. Global bit line GBL <yy>Multiple bit lines BL within bit line group BGyy are connected via multiple column switches SWC.

[0157] As described above, the Global Bit Line (GBL) is disposed in the Z direction between the substrate 90 and the memory cell array 110. Multiple Global Bit Lines (GBLs) are disposed within the multilayer wiring structure on the substrate 90.

[0158] Figure 11 as well as Figure 12 This is a cross-sectional view schematically showing a construction example of multiple global bit lines (GBLs) in the MRAM100 of this embodiment.

[0159] Figure 11 Showing the Global Bit Line (GBL) among multiple Global Bit Lines (GBLs) <1> The structure of. Figure 12 Showing the Global Bit Line (GBL) among multiple Global Bit Lines (GBLs) <j>The structure of.

[0160] like Figure 11 as well as Figure 12 As shown, a column switch SWC (field-effect transistor TR) is disposed on a semiconductor substrate 90. One end of the column switch SWC is connected to the bit line BL via multiple conductive layers M0, M1, M2, M3, contact plugs CP, and via plugs VP0, VP1, VP2, VP3, and VPA. The other end of the column switch SWC is connected to one end of the global bit line GBL via multiple conductive layers M0, M1, M2, contact plugs CP, and via plugs VP0, VP1, and VP2.

[0161] The field-effect transistor TR of the global switch GYSW is disposed on the semiconductor substrate 90. One end of the global switch GYSW is connected to the other end of the global bit line GBL. The other end of the global switch GYSW is connected to the wiring DY via multiple conductive layers M0, 73, contact plug CP, and via plug VP0. The wiring DY is connected to the write circuit 140 or the read circuit 150.

[0162] Multiple global bit lines (GBLs) are positioned below the memory cell array 110 in the Z direction. The GBLs connect between the transistor TR of the column switch SWC and the transistor TR of the global switch GYSW. In a multi-layer wiring configuration, the layer in which the global bit lines (GBLs) are positioned differs from the layer in which the global word lines (GWLs) are positioned. For example, the GBLs may be positioned within the layer of conductive layer M3. Furthermore, the layer in which the GBLs are positioned can be a lower layer than the layer in which the global word lines (GWLs) are positioned (e.g., the layer in conductive layer M0, or the layer in conductive layer M1). Alternatively, the layer in which the GBLs are positioned may be the same as the layer in which the global word lines (GWLs) are positioned.

[0163] like Figure 11 As shown, the global bit line GBL <1> Includes a 72N conductive layer. For example... Figure 12 As shown, the global bit line GBL <j>Includes conductive layer 72F.

[0164] For example, the cross-sectional area SGBL of the global bit line GBL is larger than the cross-sectional area SWL of the word line WL and the cross-sectional area SBL of the bit line BL. Therefore, the resistivity of the material used for the global bit line GBL is preferably higher than that of the material used for the bit line BL. The materials of the conductive layers 72N and 72F are preferably materials with relatively high resistivity. For example, the materials of the conductive layers 72N and 72F are selected from any one of tantalum (Ta), titanium (Ti), tungsten (W) oxides, tungsten nitrides, silicon (Si) oxides, and silicon nitrides.

[0165] In order to adjust the length of the global bit line GBL, the positions of the column switch SWC and the global switch GYSW on the semiconductor substrate 90 can be changed appropriately.

[0166] The width (size in the Y direction) of the global bit line GBL is larger than the width (size in the Y direction) of the bit line BL.

[0167] like Figures 10 to 12 As shown, the global bit line (GBL) mainly extends along the X direction.

[0168] Global Bitline (GBL) <1> It has a length (wiring length) of L x 1. Global Bit Line (GBL) <yy>It has a length of LXyy. Global bit line GBL <j>It has a length LYj. Length LX1 is longer than lengths LXyy and LXj. Length LXyy is shorter than length LX1 but longer than length LXj. Length LXj is shorter than lengths LX1 and LXyy.

[0169] Thus, the memory cell MCd, which is shorter in distance than the row switching circuit 131-1, is connected to the global bit line GBL, which has a longer wiring length. <1> The memory cell MCf, which is longer than the row switch circuit 131-1, is connected to the global bit line GBL, which has a shorter wiring length. <j>.

[0170] Global Bitline (GBL) <1> The wiring resistance is higher than that of the global bit line GBL. <yy>Wiring resistance and global bit line GBL <j>The wiring resistance is high. Global Bit Line (GBL) <yy>The wiring resistance is higher than that of the global bit line GBL. <1> The wiring resistance is low and compared to the global bit line GBL. <j>The wiring resistance is high. Global Bit Line (GBL) <j>The wiring resistance is higher than that of the global bit line GBL. <1> Wiring resistance and global bit line GBL <yy>The wiring resistance is low.

[0171] When the resistance value per unit length of the global bit line GBL is represented by "RGBL", the global bit line GBL... <1> The wiring resistor is "LX1×RGBL", and the global bit line is GBL. <yy>The wiring resistance is "LXyy×RGBL", and the global bit line is GBL. The wiring resistance is "LXj×RGBL".

[0172] For example, the difference between the word line resistance of memory cell MCd and the word line resistance of memory cell MCf is "(N-1)×Rs_y". Additionally, the global bit line GBL... <1> The resistance value and the global bit line GBL <j>The difference in resistance values ​​is "(LX1-LXj)×RGBL".

[0173] When the difference in word line resistance is offset, the size of (LX1-LXj)×RGBL is preferably close to the size of (N-1)×Rs_y. When the size of (LX1-LXj)×RGBL is equal to the size of (N-1)×Rs_y, the effect of the difference in bit line resistance becomes practically zero.

[0174] When the unit length Lx of the global bit line GBL is expressed as the same as the spacing between memory cells MC, "M×RGBL×Lx" is preferably equal to "N×Rs_y". When N and M are equal, the resistivity per unit length of the global bit line GBL can be equal to the resistivity per unit length of the word line WL.

[0175] As described above, the difference in word line resistance corresponding to the Y-axis coordinate of the memory cell MC is reduced by the difference in wiring resistance of the global bit line GBL.

[0176] (b) Example of an action

[0177] An example of the operation of the MRAM100 in this embodiment will be described.

[0178] In this embodiment, the MRAM 100 receives instructions CMD, address ADR, and various control signals CNT from the external device 900. When the instruction CMD to be executed is a write operation, the MRAM 100 also receives write data DT from the external device 900.

[0179] The MRAM100 initiates the commanded action (write or read action) based on the instruction CMD, address ADR, and various control signals CNT.

[0180] The control circuit 180 performs various controls corresponding to the actions to be executed based on the instruction CMD and various control signals CNT. The control circuit 180 decodes the address ADR.

[0181] The column control circuit 120 and the row control circuit 130 activate the column switch circuit 121-1 and the row switch circuit 131-1 based on the decoding result of the address ADR.

[0182] The memory cell (selection cell) MC indicated by address ADR is accessed via the activated column switch circuit 121-1 and the activated row switch circuit 131-1. The voltage and current required to perform the operation are supplied to the selection cell MC via the global bit line GBL, bit line BL, global word line GWL, and word line WL.

[0183] The row switch SWR connected to the selected word line WL and the column switch SWC connected to the selected bit line BL are turned on.

[0184] Like connecting to the word line WL <1> and bitline BL <1> Like the memory cell MC, when the memory cell MC is operated in the vicinity of the row switch circuit 131-1 and the column switch circuit 121-1, the word line resistance and the bit line resistance applied to the memory cell MC are relatively small.

[0185] In this embodiment, such as Figure 7 as well as Figure 10 As shown, the global word line GWL has a long wiring length LY1. <1> Connected to the select word line WL via the line switch SWR (e.g., word line WL) <1> Global bit line GBL with a long wiring length of LX1 <1> Connected to the select bit line BL via column switch SWC (e.g., bit line BL) <1> ).

[0186] Like connecting to the word line WL <m>and bitline BL <n>As with the memory cell MC, when operating the memory cell MC which is separate from the row switch circuit 131-1 and the column switch circuit 121-1, the word line resistance and the bit line resistance applied to the memory cell MC are relatively large.

[0187] In this embodiment, such as Figure 7 as well as Figure 10 As shown, the global word line GWL has a short routing length LYi. Connected to the select word line WL via the line switch SWR (e.g., word line WL) <m>Global bit line GBL with short routing length LYj <j>Connected to the select bit line BL via column switch SWC (e.g., bit line BL) <n>).

[0188] Thus, in this embodiment, the MRAM 100 connects one global word line GWL with different wiring lengths LY and one global bit line GBL with different wiring lengths LX to the memory cell of the target, according to the magnitude of the word line resistance and bit line resistance applied to the memory cell in the memory cell array 110.

[0189] Therefore, in the MRAM100 of this embodiment, the difference in wiring resistance corresponding to the coordinates of the memory cell MC is reduced.

[0190] (c) Summary

[0191] In a memory cell array constructed at intersections, the wiring resistance applied to the memory cells varies depending on the cell's coordinates. This difference in wiring resistance can potentially degrade the read margin across multiple cells in the array.

[0192] The MRAM100 in this embodiment includes multiple global word lines GWL with different routing lengths LY and multiple global bit lines GBL with different routing lengths LX.

[0193] The global word line GWL and the global bit line GBL connected to the memory cell MC are different depending on the coordinates of the memory cell MC.

[0194] When a memory cell MC is selected that is close to the coordinates of the row switch circuit 131-1, the selected memory cell MC is connected to the global bit line GBL with a long wiring length of LX1 via the bit line BL. <1> When a memory cell MC is selected at a coordinate far from the row switch circuit 131-1, the selected memory cell MC is connected to the global bit line GBL with a short wiring length LXj via bit line BL. <j>.

[0195] When a memory cell MC is selected that is close to the coordinates of the column switch circuit 121-1, the selected memory cell MC is connected to the global word line GWL with a long wiring length LY1 via word line WL. <1> When a memory cell MC is selected at a coordinate farthest from the column switch circuit 121-1, the selected memory cell MC is connected to the global word line WL of short wiring length LYi via word line WL. .

[0196] Therefore, the MRAM100 of this embodiment can reduce the difference in wiring resistance applied to the memory cell MC caused by the coordinates of the memory cell MC.

[0197] As a result, the MRAM100 of this embodiment is able to suppress the degradation of read margin.

[0198] As described above, the storage device 100 of this embodiment can improve the reliability of the operation of the storage cell MC.

[0199] (2) Second implementation method

[0200] Reference Figure 13 as well as Figure 14 The storage device of the second embodiment will be described.

[0201] Figure 13 as well as Figure 14 This is a plan view showing a construction example of the global routing GWL and GBL in the memory device (MRAM) 100 of this embodiment.

[0202] like Figure 13 as well as Figure 14 As shown, in addition to the wiring lengths LY and LX, multiple global cablings GWL and GBL can also have different widths WX (WX1, WXxx, WXi) and WY (WY1, WYyy, WYj).

[0203] like Figure 13 As shown, the global word line GWL <1> It has a width (wiring width) WX1 in the X direction. Global word line GWL <xx>It has a wiring width WXxx in the X direction. Global word line GWL The wiring width is WXi in the X direction. The wiring widths WX1, WXxx, and WXi are all different.

[0204] The wiring width WX1 is smaller than both wiring widths WXxx and WXj. The wiring width WXxx is smaller than WXj but larger than WX1. The wiring width WXj is larger than both WX1 and WXxx.

[0205] The routing resistance of the Global Word Line (GWL) varies depending on the routing width WX. With the routing thickness and length remaining constant, the routing resistance of the GWL decreases as the routing width WX increases.

[0206] Therefore, the global word line GWL Wiring resistance and global word line (GWL) <1> The wiring resistance is further reduced compared to the previous method.

[0207] like Figure 14 As shown, the global bit line GBL <1> It has a wiring width WY1 in the Y direction. Global bit line GBL <yy>It has a wiring width WYyy in the Y direction. Global Bit Line (GBL) <j>The wiring has a width WYj in the Y direction. The wiring widths WY1, WYyy, and WYj are all different.

[0208] The wiring width WY1 is smaller than the wiring widths WYyy and WYj. The wiring width WYyy is smaller than the wiring width WYj but larger than the wiring width WY1. The wiring width WYj is larger than the wiring widths WY1 and WYyy.

[0209] The routing resistance of the Global Bit Line (GBL) varies depending on the routing width (WY). With the routing thickness and length remaining constant, the resistance of the GBL decreases as the routing width (WY) increases.

[0210] Therefore, the global bit line GBL <j>The wiring resistance is further reduced compared to the wiring resistance of the global bit line (GBL).

[0211] Here, the resistivity of the global word line GWL is represented by "ρGWL", and the resistivity of the bit line BL is represented by "ρBL". Additionally, the global word line GWL... <1> The cross-sectional area is represented by "SGWL1", and the global word line GWL The cross-sectional area is represented by "SGWLi". The unit length of the bit line BL is represented by "Lb".

[0212] Connected to bit line BL <y>and word line WL <1> The bit line resistance of the memory cell MCa is connected to the bit line BL. <y>and word line WL <m>The difference in bit line resistance of the memory cell MCc is expressed by the following formula (f1).

[0213] (M-1)×ρBL×Lb / SBL…(f1)

[0214] Global Word Line (GWL) <1> Wiring resistance and global word line (GWL) The difference in wiring resistance is expressed by the following formula (f2).

[0215] ρGWL×LY1 / SGWL1-ρGWL×LYi / SGWLi…(f2)

[0216] As described above, by making the value of equation (f2) approximately the same as the value of equation (f1), the difference between the bit line resistance of memory cell MCa and the bit line resistance of memory cell MCc is reduced.

[0217] To minimize the impact of the difference in bit line resistance within the memory cell array 110, it is preferable to satisfy the following equation (f3).

[0218] ρGWL×LY1 / SGWL1-ρGWL×LYi / SGWLi

[0219] = (M-1)×ρBL×Lb / SBL…(f3)

[0220] Additionally, the resistivity of the global bit line GBL is represented by "ρGBL", and the resistivity of the word line WL is represented by "ρWL". Furthermore, the global bit line GBL... <1> The cross-sectional area is represented by SGBL1, and the global bit line is GBL. <j>The cross-sectional area is represented by SGBLj. The unit length of the character line WL is represented by "Lw".

[0221] Connected to word line WL <x>and bitline BL <1> The word line resistor of the memory cell MCd is connected to the word line WL <x>and bitline BL <n>The difference in word line resistance of the memory cell MCf is expressed by the following equation (f4).

[0222] (N-1)×ρWL×Lw / SWL…(f4)

[0223] Global Bitline (GBL) <1> Wiring resistance and global bit line GBL <j>The difference in wiring resistance is expressed by the following formula (f5).

[0224] ρGBL×LX1 / SGBL1-ρGBL×LXj / SGBLj…(f5)

[0225] As described above, by making the value of equation (f5) approximately the same as that of equation (f4), the difference between the word line resistance of memory cell MCd and the word line resistance of memory cell MCf is reduced.

[0226] To minimize the impact of word line resistance differences within the memory cell array 110, it is preferable to satisfy the following equation (f6).

[0227] ρGBL×LX1 / SGBL1-ρGBL×LXj / SGBLj

[0228] = (N-1)×ρWL×Lw / SWL…(f6)

[0229] Generally, in semiconductor manufacturing processes, it is difficult to change the film thickness of conductive layers (wiring) within the same layer for each conductive layer. Therefore, as in this embodiment, it is effective to change the resistance values ​​of global wiring GWL and GBL by controlling the wiring width. However, the film thickness of global word line GWL can be changed for each global word line GWL. Similarly, the film thickness of global bit line GBL can be changed for each global bit line GBL.

[0230] As described above, in this embodiment, the routing resistance of the global routing is controlled not only by the routing length but also by the routing width. For example, the length of the global routing GWL and GBL may be limited based on the chip layout and the size of the memory cell array.

[0231] Therefore, the MRAM100 of this embodiment can flexibly cope with the constraints of the layout within the chip.

[0232] As described above, the storage device 100 of this embodiment can achieve the same effects as the embodiments described above.

[0233] (3) Third implementation

[0234] Reference Figure 15 as well as Figure 16 The storage device of the third embodiment will be described.

[0235] Figure 15 as well as Figure 16 This is a plan view showing a construction example of the global routing GWL and GBL in the memory device (MRAM) 100 of this embodiment.

[0236] like Figure 15 as well as Figure 16 As shown, the MRAM100 sometimes includes two column switch circuits 121-1 and 121-2 and two row switch circuits 131-1 and 131-2.

[0237] One column switch circuit 121-1 is disposed at one end of the memory cell array 110 in the X direction. The other column switch circuit 121-2 is disposed at the other end of the memory cell array 110 in the X direction.

[0238] When the memory cell array 110 is configured between two column switch circuits 121-1 and 121-2, the regions of one end and the other end of the memory cell array 110 in the X direction become the near region relative to the column switch circuit 121, and the central region of the memory cell array 110 becomes the far region relative to the column switch circuit 121.

[0239] For example, when an action is taken on a memory cell MC, the column switch circuit 121 of the two column switch circuits 121-1 and 121-2 that is closer to the selected memory cell MC is activated.

[0240] In this case, such as Figure 15 As shown, the global word line GWL corresponds to the central word line group WGxx in the X direction of the memory cell array 110. <xx>The wiring length LYxx is proportional to the global word line GWL corresponding to the word line group WG1 at one end of the X direction of the memory cell array 110. <1> The wiring length LY1, and the global word line GWL corresponding to the word line group WBi on the other side of the X direction of the memory cell array 110. The wiring length LY1 is short. For example, the global word line GWL The wiring length LY1 and the global word line GWL <1> The wiring length LY1 is equal.

[0241] In addition, the global word line GWL <xx>The wiring width can also be compared with the global word line (GWL). <1> ,GWL The wiring widths differ. For example, the Global Word Line (GWL) <xx>The wiring width is greater than the global word line (GWL). <1> ,GWL The wiring width is wide.

[0242] One row switch circuit 131-1 is configured at one end of the memory cell array 110 in the Y direction. The other row switch circuit 131-2 is configured at the other end of the memory cell array 110 in the Y direction.

[0243] For example, when an action is taken on a memory cell MC, the column switch circuit 121 of the two column switch circuits 121-1 and 121-2 that is closer to the selected memory cell MC is activated.

[0244] When the memory cell array 110 is configured between two row switch circuits 131-1 and 131-2, the regions on one end and the other end of the memory cell array 110 in the Y direction become the near region relative to the row switch circuit 131, and the central region of the memory cell array 110 becomes the far region relative to the row switch circuit 131.

[0245] In this case, such as Figure 16 As shown, the global bit line GBL corresponds to the central bit line group BGyy in the Y direction of the memory cell array 110. <yy>The length ratio of the wiring length LXyy to the global bit line GBL corresponding to the bit line group BG1 at one end of the X direction of the memory cell array 110 is... <1> The wiring length LX1, and the global bit line GBL corresponding to the bit line group BGj on the other side of the X direction of the memory cell array 110. <j>The wiring length LX1 is short. For example, the global bit line GBL <j>The wiring length LY1 and the global bit line GBL <1> The wiring length LY1 is equal.

[0246] In addition, the global bit line GBL <yy>The wiring width can also be compared with the global bit line (GBL). <1> GBL <j>The wiring widths of the global bit lines GBL <yy>wiring width than the global bit lines GBL<1>, GBL <j>The wiring width is wide.

[0247] Even if the MRAM 100 has the configuration in which the switching circuits 121, 131 are provided at both ends of the memory cell array 110 as in this embodiment, the selected memory cell MC can be connected to a corresponding one of the global word lines GWL of different wiring lengths LY and a corresponding one of the global bit lines GBL of different wiring lengths LX according to the coordinates of the memory cell MC.

[0248] Therefore, the memory device 100 of this embodiment can achieve substantially the same effects as the memory device of the above-described embodiment.

[0249] (4) Modification

[0250] Reference Figure 17 and Figure 18 A modification of the memory device of the embodiment will be described.

[0251] Figure 17 and Figure 18 is a plan view showing a planar shape of a global wiring (global bit line or global word line) GL in the modification of the memory device of the embodiment.

[0252] As shown in Figure 17 , regarding the global bit line GBL or the global word line GWL, the global wiring GL having a high wiring resistance (long wiring length) can have a meandering planar shape when viewed from a direction (Z direction) perpendicular to the semiconductor substrate 90.

[0253] The global wiring GL includes a plurality of portions 74 extending in an A direction (X direction or Y direction) and a plurality of portions 75 extending in a B direction (Y direction or X direction) intersecting the A direction. The portions 74 and the portions 75 are alternately arranged in the A direction.

[0254] Thus, the effective length of the global wiring GL is increased.

[0255] As shown in Figure 18 , the global wiring GL having a high resistance value can have a folded-back shape when viewed from the Z direction.

[0256] The global wiring GL includes two portions 76 extending in the A direction and a portion 77 extending in the B direction.

[0257] The portion 77 connects one of the portions 76 to the other portion 76 at one end of the two portions 76 in the A direction.

[0258] Thus, the effective length of the global wiring GL is increased.

[0259] As a result Figure 17 and Figure 18 As a result, the resistance value of the global wiring GL increases.

[0260] In this way, the resistance values of the plurality of global wirings GL can be adjusted by controlling the planar shape of the global wiring GL.

[0261] The memory device 100 of the present modified example can obtain substantially the same effects as those of the above-described embodiment.

[0262] (5) Others

[0263] In the above-described embodiment, the MRAM is exemplified as the memory device 100 of the present embodiment. However, the memory device 100 of the present embodiment can also be a memory device other than the MRAM.

[0264] For example, the memory device 100 of the present embodiment can also be a memory device in which a transition metal oxide element having a variable resistance characteristic is used as a storage element (a resistive random access memory such as ReRAM (Resistive Random Access Memory), a phase change memory in which a phase change element is used as a storage element (a phase change random access memory such as PCRAM (Phase Change Random Access Memory)), or a ferroelectric memory in which a ferroelectric element is used as a storage element (a ferroelectric random access memory such as FeRAM (Ferroelectric Random Access Memory)).

[0265] The memory device 100 of the present embodiment can obtain the effects described in the above-described embodiment even if it is a memory device other than the MRAM.

[0266] Several embodiments of the present application have been described, but these embodiments are presented as examples, and are not intended to limit the scope of the application. These new embodiments can be implemented in various other ways, and various omissions, substitutions, and changes can be made without departing from the scope of the application. These embodiments and / or modifications are included in the scope, gist, and the range of the application, and are included in the range of the application and equivalents thereof recited in the claims.< / j> < / yy> < / j> < / yy> < / j> < / j> < / yy> < / xx> < / xx> < / xx> < / j> < / n> < / x> < / x> < / j> < / m> < / y> < / y> < / j> < / j> < / yy> < / xx> < / j> < / n> < / j> < / m> < / n> < / m> < / j> < / yy> < / yy> < / j> < / j> < / yy> < / j> < / yy> < / j> < / j> < / yy> < / j> < / j> < / yy> < / y> < / yy> < / j> < / n> < / j> < / n> < / y> < / x> < / j> < / yy> < / xx> < / xx> < / xx> < / xx> < / xx> < / xx> < / x> < / xx> < / m> < / m> < / x> < / y> < / xx> < / y> < / x> < / n> < / y> < / m> < / x> < / m> < / n>

Claims

1. A memory device comprising: an array of memory cells including a first local wiring extending in a first direction, a second local wiring extending in a second direction intersecting the first direction, a third local wiring extending in the second direction, a first memory cell provided between the first local wiring and the second local wiring, and a second memory cell provided between the first local wiring and the third local wiring; a first switching circuit connected to the first local wiring and provided on one end side in the first direction of the array of memory cells; a second switching circuit connected to the second local wiring and the third local wiring and provided on one end side in the second direction of the array of memory cells; a first circuit performing a write operation or a read operation of the array of memory cells; and a first global wiring and a second global wiring connected between the second switching circuit and the first circuit, the second local wiring being disposed between the first switching circuit and the third local wiring in the first direction, the second local wiring being connected to the first global wiring via the second switching circuit, the third local wiring being connected to the second global wiring via the second switching circuit, and the second global wiring being shorter in length than the first global wiring.

2. The memory device according to claim 1, wherein a length of the first local wiring between the second memory cell and the first switching circuit is longer than a length of the first local wiring between the first memory cell and the first switching circuit.

3. The memory device according to claim 1, further comprising a third global wiring connected between the second switching circuit and the first circuit, the array of memory cells including: a fourth local wiring extending in the second direction and provided between the second local wiring and the third local wiring in the first direction; and a third memory cell provided between the first local wiring and the fourth local wiring, the fourth local wiring being connected to the third global wiring via the second switching circuit, the third global wiring being shorter in length than the first global wiring and longer in length than the second global wiring.

4. The memory device according to claim 1, wherein a width of the second global wiring is larger than a width of the first global wiring.

5. The memory device according to claim 1, further comprising a fourth global wiring and a fifth global wiring connected between the first switching circuit and the first circuit, the array of memory cells further including: a fifth local wiring extending in the first direction and disposed between the first local wiring and the second switching circuit in the second direction; and a fourth memory cell provided between the second local wiring and the fifth local wiring, the first local wiring being connected to the fourth global wiring via the first switching circuit, the fifth local wiring being connected to the fifth global wiring via the first switching circuit, and the fourth global wiring being shorter in length than the fifth global wiring. ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ ​ 6. The storage device according to claim 1, the storage cell array is provided above a substrate, the first and second global wirings are provided between the storage cell array and the substrate in a third direction perpendicular to a surface of the substrate.

7. The storage device according to claim 1, the first local wiring is a first bit line, the second local wiring is a first word line, the third local wiring is a second word line, the first switch circuit is a row switch circuit, the first global wiring is a first global word line, the second global wiring is a second global word line.

8. The storage device according to claim 1, the first local wiring is a first word line, the second local wiring is a first bit line, the third local wiring is a second bit line, the first switch circuit is a column switch circuit, the first global wiring is a first global bit line, the second global wiring is a second global bit line.

9. The storage device according to claim 1, resistivities of the first and second global wirings are higher than resistivities of the first to third local wirings.

10. The storage device according to claim 1, the first and second global wirings have a relationship of the following formula (f0) with respect to the first local wiring, ρGWLxLY1 / SGWL1-ρGWLxLYi / SGWLi = (M-1) x ρBLxLb / SBL... (f0) wherein, the ρGWL corresponds to a resistivity of the first and second global wirings, the LY1 corresponds to a wiring length of the first global wiring, the LYi corresponds to a wiring length of the second global wiring, the SGWL1 corresponds to a cross-sectional area of the first global wiring, the SGWLi corresponds to a cross-sectional area of the second global wiring, the M corresponds to a number of pitches in the first direction within the storage cell array, the ρBL corresponds to a resistivity of the first local wiring, the Lb corresponds to a unit length of the first local wiring, and the SBL corresponds to a cross-sectional area of the first local wiring.

11. A storage device comprising: a storage cell array including a first local wiring extending in a first direction, a second local wiring extending in a second direction intersecting the first direction, a third local wiring extending in the second direction, a fourth local wiring extending in the second direction, a first storage cell provided between the first and second local wirings, a second storage cell provided between the first and third local wirings, and a third storage cell provided between the first and fourth local wirings; a first switch circuit connected to the first local wiring and provided on one end side in the first direction of the storage cell array; a second switch circuit connected to the first local wiring and provided on the other end side in the first direction of the storage cell array. a third switch circuit connected to the second local wiring, the third local wiring, and the fourth local wiring, and provided on one end side in the second direction of the memory cell array; a fourth switch circuit connected to the second local wiring, the third local wiring, and the fourth local wiring, and provided on the other end side in the second direction of the memory cell array; a first circuit that performs a write operation or a read operation of the memory cell array; and a first global wiring, a second global wiring, and a third global wiring connected between the third switch circuit and the first circuit, the fourth local wiring is disposed between the second local wiring and the third local wiring in the first direction, the first global wiring is connected to the second local wiring via at least one of the third switch circuit and the fourth switch circuit, the second global wiring is connected to the third local wiring via at least one of the third switch circuit and the fourth switch circuit, the third global wiring is connected to the fourth local wiring via at least one of the third switch circuit and the fourth switch circuit, the length of the third global wiring is shorter than the length of the first global wiring and the length of the second global wiring.

12. The memory device according to claim 11, the length of the first global wiring is equal to the length of the second global wiring.

13. The memory device according to claim 11, the length of the first local wiring between the second memory cell and the first switch circuit is longer than the length of the first local wiring between the first memory cell and the first switch circuit.

14. The memory device according to claim 11, the width of the third global wiring is larger than the width of the first global wiring.

15. The memory device according to claim 11, further comprising a fourth global wiring and a fifth global wiring connected between the first switch circuit and the first circuit, the memory cell array further includes: a fifth local wiring extending in the first direction and disposed between the first local wiring and the third switch circuit in the second direction; and a fourth memory cell disposed between the second local wiring and the fifth local wiring, the first local wiring is connected to the fourth global wiring via the first switch circuit, the fifth local wiring is connected to the fifth global wiring via the first switch circuit, the length of the fourth global wiring is shorter than the length of the fifth global wiring.

16. The memory device according to claim 11, the memory cell array is disposed above a substrate, the first global wiring to the third global wiring are disposed between the memory cell array and the substrate in a third direction perpendicular to a surface of the substrate.

17. The memory device according to claim 11, the first local wiring is a first bit line, the second local wiring is a first word line, the third local wiring is a second word line, the fourth local wiring is a third word line, the first switch circuit is a first row switch circuit, The second switch circuit is a second row switch circuit, The third switch circuit is a first column switch circuit, The fourth switch circuit is a second column switch circuit, The first global wiring is a first global word line, The second global wiring is a second global word line, The third global wiring is a third global word line.

18. The memory device of claim 11, The first local wiring is a first word line, The second local wiring is a first bit line, The third local wiring is a second bit line, The fourth local wiring is a third bit line, The first switch circuit is a first column switch circuit, The second switch circuit is a second column switch circuit, The third switch circuit is a first row switch circuit, The fourth switch circuit is a second row switch circuit, The first global wiring is a first global bit line, The second global wiring is a second global bit line, The third global wiring is a third global bit line.

19. The memory device of claim 11, The first global wiring to the third global wiring has a higher resistivity than the first local wiring to the third local wiring.

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