Method for manufacturing silicon carbide power electronics with improved input capacitance definition for silicon carbide power electronics

Abstract

The invention relates to a method for manufacturing a silicon carbide power electronic device with improved input capacitance definition of the silicon carbide power electronic device. A method of manufacturing a vertical conductive power device is provided. An example includes forming a body region of a second conductivity opposite to a first conductivity in a body including a semiconductor material and of the first conductivity; forming a source region of a first conductivity in the respective body region; forming gate structures, each including an insulated gate region, a conductive gate region on the insulated gate region, and a passivated gate region on the conductive gate region, where the conductive gate region partially overlaps the source region of a corresponding adjacent body region; and forming source metallization regions on the body and the gate structures including contact portions between adjacent gate structures with respective source regions. Forming the contact portion includes: forming a spacer dielectric layer on the gate structure and the body; and anisotropically etching the spacer dielectric layer up to the source region.

Description

[0001] Cross-references to (one or more) related applications

[0002] This application claims priority to Italian patent application No. 102024000020143, filed on September 10, 2024, entitled “PROCESSO DI FABBRICAZIONE PERDISPOSITIVI ELETTRONICIDIPOTENZA IN CARBURO DI SILICIO AVENTE UNA MIGLIORATADEFINIZIONE DELLA CAPACITA'DI INGRESSO DEGLI STESSI”, which is incorporated herein by reference to the fullest extent permitted by law. Technical Field

[0003] This disclosure relates to a method for manufacturing a silicon carbide power electronic device having an improved input capacitance definition. Background Technology

[0004] As is known, semiconductor materials with wide bandgap (e.g., greater than 1.1 eV), low on-resistance, high thermal conductivity, high operating frequency, and high charge carrier saturation velocity allow for electronic devices, such as diodes and transistors, to have better performance than silicon electronic devices, especially for power applications (i.e., for operating voltages, for example, between 600 V and 1300 V, or under specific operating conditions such as high temperatures).

[0005] In detail, it is known that such electronic devices are obtained from wafers of silicon carbide (SiC), such as 3C-SiC, 4H-SiC, and 6H-SiC, which are distinguished by the characteristics listed above. Power electronic devices that can be obtained using SiC-type semiconductors can be, for example, vertically conducting MOSFETs or JFET transistors.

[0006] In MOSFET devices, the input capacitance is primarily defined by the sum of the capacitance between the gate and source terminals (also known as "gate-source capacitance") and the capacitance between the gate and drain terminals (also known as "gate-drain capacitance"). The input capacitance defines the dynamic behavior of the device and affects its efficiency in a specific application. The value of the input capacitance available for a given device is mainly defined by the structure of the device's basic unit and the on-board configuration.

[0007] MOSFET devices used in high-power applications, especially SiC technology power devices such as power inverters, consist of multiple basic units that are typically assembled in parallel to reduce the on-resistance of each inverter stage. This configuration can cause ringing effects in the gate-source and drain-source waveforms during the switching phase of the device (especially at power-up), primarily due to gate-source coupling.

[0008] To prevent oscillations in parallel configurations of MOSFET devices, a series of capacitors can be inserted in parallel with the device's gate-source and / or gate-drain capacitances to increase its input capacitance (e.g., one or more discrete capacitors mounted on an application-specific electronic board). However, introducing such discrete capacitors can introduce several disadvantages, such as higher manufacturing costs, efficiency losses, and greater complexity in managing the drive circuitry. Summary of the Invention

[0009] Therefore, the purpose of this disclosure is to overcome or at least partially mitigate the disadvantages and limitations of the prior art.

[0010] According to this disclosure, a method for manufacturing a silicon carbide power electronic device is provided.

[0011] In one example embodiment, a method for manufacturing a vertically conducting power device includes: forming a body region having a second conductivity opposite to the first conductivity in a body comprising a semiconductor material and having a first conductivity; forming a source region having the first conductivity in a respective body region; forming a gate structure, each gate structure including an insulating gate region on the body, a conductive gate region on the insulating gate region, and a passivated gate region on the conductive gate region, the conductive gate regions partially overlapping source regions of respective adjacent body regions; forming source metallization regions on the body and the gate structures, the source metallization regions including contact portions between adjacent gate structures and corresponding source regions; wherein forming the contact portions includes: forming spacer dielectric layers on the gate structures and the body in a conformal manner; and anisotropically etching the spacer dielectric layers down to the source regions.

[0012] In various embodiments, etching the spacer dielectric layer includes performing unmasked etching.

[0013] In various embodiments, the passivated gate region of each gate structure is formed by a first dielectric selected from oxides, oxynitrides, or a combination of oxides or nitrides and oxynitrides.

[0014] In various embodiments, the spacer dielectric layer is formed of a second dielectric selected from oxides, oxynitrides, or a combination of oxides or nitrides and oxynitrides.

[0015] In various embodiments, the spacer dielectric layer has a minimum thickness of 0.2 μm and laterally covers the gate structure.

[0016] In various embodiments, forming a gate structure includes forming a gate conductive layer and patterning the gate conductive layer such that each resulting conductive gate region overlaps on a corresponding source region in a corresponding overlapping region along a first direction, and the conductive gate regions of adjacent gate structures are separated by a distance along a second direction perpendicular to the first direction, the ratio of this distance to the pitch of the power device being a value between 0.4 and 0.9.

[0017] In various embodiments, the etched spacer dielectric layer includes defining a pair of spacer portions on the side of each gate structure.

[0018] In various embodiments, a pair of spacers partially seal the conductive gate region of each gate structure.

[0019] In various embodiments, the source region includes a corresponding body contact region, wherein each body contact region extends into the corresponding body region.

[0020] In various embodiments, the body includes a substrate and an epitaxial layer, the body region and the source region are formed in the epitaxial layer, and the semiconductor material comprises silicon carbide.

[0021] In various embodiments, the substrate has a main back side, and the method further includes forming a drain metallization region on the back side.

[0022] In one example embodiment, the vertically conducting power device includes: a body comprising a semiconductor material and having a first conductivity; a body region extending into the body and having a second conductivity opposite to the first conductivity; a source region extending into a corresponding body region and having a first conductivity; gate structures, each gate structure including an insulating gate region on the body, a conductive gate region on the insulating gate region, and a passivated gate region on the conductive gate region, the conductive gate regions partially overlapping source regions of corresponding adjacent body regions along a first direction; source metallization regions on the body and on the gate structures, the source metallization regions including contact portions with corresponding source regions between adjacent gate structures; and wherein each gate structure laterally includes a plurality of spacer portions that contact the body and define corresponding contact portions.

[0023] In various embodiments, each conductive gate region overlaps on a corresponding source region in a corresponding overlapping region along a first direction, and the conductive gate regions of adjacent gate structures are separated by a distance along a second direction perpendicular to the first direction, the ratio of this distance to the pitch of the power device being a value between 0.4 and 0.9.

[0024] In various embodiments, the vertically conducting power device further includes: a source terminal electrically connected to a source metallization region; and a gate terminal electrically connected to each conductive gate region of the gate structure, the power device having a capacitance between the gate terminal and the source terminal depending on the ratio between the distance and the pitch of the power device.

[0025] In various embodiments, the semiconductor material comprises silicon carbide. Attached Figure Description

[0026] To better understand this disclosure, preferred embodiments are provided with reference to the accompanying drawings by way of non-limiting example only, in which:

[0027] Figure 1 A cross-section through a power device according to an embodiment of the present disclosure is schematically shown;

[0028] Figures 2A-2E The illustration schematically shows the sequential manufacturing steps of a manufacturing method according to an embodiment of the present disclosure. Figure 1 The cross-section of the power device; and

[0029] Figure 3 Is with Figures 2A-2E A simplified flowchart related to the method. Detailed Implementation

[0030] The following description refers to the arrangement shown in the accompanying drawings; therefore, expressions such as “above,” “below,” “upper,” “lower,” “top,” “bottom,” “right,” and “left” are related to the drawings and should not be interpreted in a restrictive manner.

[0031] A power device manufactured according to embodiments of the present disclosure is illustrated in a portion thereof. Figure 1 In the figure, it is indicated by the number 1. Power device 1 is, for example, a MOSFET—specifically a power MOSFET, and more specifically a vertically conducting MOSFET made using silicon carbide (SiC) technology—and is housed in a die not shown in the figure. Therefore, in the following text, power device 1 is also referred to as "MOSFET," interchangeably without any loss of generality.

[0032] Figure 1 MOSFET 1 is shown in its cross section in a coordinate system with orthogonal axes X, Y, Z.

[0033] MOSFET 1 comprises multiple basic units—only one of which is shown in the figure—these basic units are equal to each other and arranged in the same die to share the drain terminal D, the gate terminal G, and the source terminal S; that is, the basic units are electrically connected in parallel with each other.

[0034] MOSFET 1 is formed in a body 2 of semiconductor material. Body 2 is defined at the top by a front side 2a and at the bottom by a back side 2b, with the front and back sides facing opposite directions along the Z-axis. Body 2 may include a substrate or a substrate having one or more epitaxial layers grown thereon, and is silicon carbide, in one of its polytypes, such as the 4H-SiC polytype. In one embodiment, in particular, body 2 includes a substrate 21 defined at the bottom by the back side 2b and an epitaxial layer 22 extending on the substrate 21 and defined at the top by the front side 2a.

[0035] Drift area 3, multiple main areas 5 ( Figure 1 Two are shown in the image) and multiple source regions 7 ( Figure 1 Two (shown in the diagram) are formed in the epitaxial layer 22. The semiconductor material body 2, i.e., substrate 21, drift region 3, and source region 7, have a first conductivity, such as N-type. The body region 5 has a second conductivity, which is P-type, opposite to the first conductivity. Each body region 5 has, for example, a 1.10 17 atoms / cm 3 With 1.10 20 atoms / cm 3 The doping levels are between; each source region 7 has, for example, a doping level of 1.10. 18 atoms / cm 3 With 1.10 20 atoms / cm 3 The doping levels between them.

[0036] The main body regions 5 extend from the front side 2a into the main body 2 and are separated from each other along the X-axis by the surface portions 31 of the drift regions 3. Each source region 7 extends from the front side 2a into the main body 2 and is embedded in the corresponding main body region 5. Each basic unit of the MOSFET 1 includes at least one main body contact region 51, which has a second conductivity and extends from the front side 2a through the corresponding source region 7 to one of the main body regions 5. A channel region 52 is defined in the main body region 5 between the corresponding source region 7 and the surface portion 31 of the drift region 3.

[0037] The main body region 5, the source region 7, and the main body contact region 51 also extend along the Y-axis and have, for example, a strip or a ring shape in the top view (not shown here).

[0038] In the epitaxial layer 22 of MOSFET 1, during use, i.e., when the voltage (V) between the gate terminal G and the source terminal S... GS () greater than the threshold voltage (V) of the basic unit TH When the current flows between the source terminal S and the drain terminal D, it passes through each channel region 52 and the drift region 3. In fact, the drift region 3 forms a drift layer of charge carriers during use.

[0039] The MOSFET 1 also includes a plurality of gate structures 4 disposed above the front side 2a of the body 2. Each gate structure 4 includes: an insulating gate region 41 (e.g., silicon oxide) in contact with the front side 2a of the body 2; a conductive gate region 42 (e.g., polysilicon) directly overlapping the insulating gate region 41; and a passivated gate region 43 (e.g., oxide) covering the conductive gate region 42 and sealing the conductive gate region 42 together with the insulating gate region 41. The conductive gate regions 42 of the gate structures 4 are electrically connected in parallel in a manner not shown herein to form the gate terminal G of the MOSFET 1. In particular, in one embodiment, for each gate structure 4, the width (along the X-axis) of the conductive gate region 42—hereinafter referred to as the gate strip width L—is substantially consistent with the width (along the X-axis) of the insulating gate region 41.

[0040] The conductive gate region 42 of each gate structure 4 extends between the source regions 7 of a pair of adjacent body regions 5. Specifically, the conductive gate region 42 partially overlaps the source regions 7 of the two adjacent body regions 5 and extends over the channel region 52 included between the source regions 7 and the surface portion 31 of the drift region 3. For more details, refer to... Figure 1 The single basic unit shown, the conductive gate region 42, projected below and onto the corresponding source region 7 (along the Z-axis), defines a corresponding overlapping region 71 with a dimension along the X-axis, referred to below as the overlap width s. The gate strip width L is greater than the overlap width s. Furthermore, as a first approximation, the gate strip width L is equal to the sum of the following: twice the overlap width s, twice the width of the corresponding channel region 52, and the width of the surface portion 31 of the drift region 3.

[0041] MOSFET 1 also includes a source metallization region 6, such as a metal material and / or metal silicide, which forms the source terminal S of MOSFET 1 and extends on the front side 2a of the body 2 in direct electrical contact with the source region 7 and the body contact region 51. In fact, the body contact region 51 is used to bias the body region 5 at the potential of the source terminal S.

[0042] In MOSFET 1, adjacent gate structures 4 are separated by corresponding contact portions 61 of source metallization regions 6. More specifically, each contact portion 61 of the source metallization region 6 is inserted in contact between the passivated gate regions 43 of two adjacent gate structures 4. Furthermore, the contact portion 61 forms electrical contact with the corresponding source region 7 and the body contact region 51. Hereinafter, the width of each contact portion 61 along the X-axis at the interface with the corresponding source region 7 is referred to as the contact width C, and is intended to be measured near the front surface 2a of the body 2 between the corresponding passivated gate regions 43 of the two adjacent gate structures 4.

[0043] As expected, the passivated gate region 43 of each gate structure 4 is on top and laterally covers the corresponding conductive gate region 42. More specifically, the passivated gate region 43 includes a spacer portion 44 that extends on the sides of the corresponding insulating gate region 41 and conductive gate region 42 and defines a corresponding contact portion 61 in the X-axis direction. In other words, the spacer portion 44 is arranged on the opposite side (along the X-axis) of the conductive gate region 42 of the gate structure 4. As explained below, the spacer portion 44 may be made of a different material than the corresponding passivated gate region 43 (e.g., different types of oxides). The width of each spacer portion 44 along the X-axis is hereinafter referred to as the spacer width t and is intended to be measured close to the front surface 2a of the body 2.

[0044] Therefore, in MOSFET 1, the conductive gate regions 42 belonging to adjacent gate structures 4 are separated by a gate strip distance T, which is equal to the sum of the following: the spacer width t (referring to the spacer portion 44 of the gate structure 4), the contact width C of the inserted contact portion 61, and the spacer width t (referring to the spacer portion 44 of the other gate structure 4). More specifically, the sum of the gate strip width L and the gate strip distance T defines the pitch PT of MOSFET 1, which is greater than 4 μm in the present device. The pitch PT indicates the size of the basic cell of MOSFET 1 (along the X-axis).

[0045] The MOSFET 1 finally includes a drain metallization region 8 of conductive material (e.g., metal or silicide) that extends on the back side 2b of the body 2 (in the opposite direction to the source metallization region 6), is in direct electrical contact with the substrate 21, and forms the drain terminal D of the MOSFET 1.

[0046] The capacitance between the gate terminal G and the source terminal S of MOSFET 1 (also known as the "gate-source capacitance", C) GSThe overlap width s is determined by the overlap region 71 between the conductive gate region 42 and the corresponding source region 7. More specifically, the overlap width s is selected according to design preferences to define the input capacitance (C) of MOSFET 1 in an accurate and flexible manner relative to the desired target parameters and / or the desired application. IN In MOSFET 1, the gate-source capacitance C GS The value increases with the increase of the overlap width s. The capacitance between the gate terminal G and the drain terminal D (also known as the "gate-drain capacitance") is alternatively independent of the overlap width s. Furthermore, the overlap width s is chosen without modifying the pitch PT of MOSFET 1, and more specifically, as explained below, and for a given width of the source region 7 (along the X-axis), the contact width C of the contact portion 61 of the source metallization region 6 is not modified. In MOSFET 1, reliable control of the device's dynamic behavior can be achieved through the accurate definition of the input capacitance, preventing unwanted phenomena such as oscillations during switching phases.

[0047] In practice, in order to change the overlap width s relative to conventional devices without modifying the pitch PT of MOSFET 1 and the contact width C of the contact portion 61 of the source metallization region 6, this disclosure allows for changing the gate strip distance T between conductive gate regions 42 belonging to adjacent gate structures 4 according to design preferences. More specifically, in order to increase the gate-source capacitance C GS Given the pitch PT of MOSFET 1, the gate strip width L of the conductive gate region 42 can be increased, thereby increasing the overlap width s. As a result, in MOSFET 1, the overlap width s is changed by inversely altering the spacer width t of the spacer portion 44 of the corresponding passivated gate region 43; therefore, when the overlap width s is maximized, the spacer width t is correspondingly minimized, having the same contact width C of the contact portion 61.

[0048] More specifically, the gate-source capacitance C of MOSFET 1 GS And finally, the input capacitor C IN This is related to the difference between the pitch PT and the gate strip distance T between the conductive gate regions 42 belonging to adjacent gate structures 4. If the gate strip distance T approaches zero in the limiting case, the input capacitance C is obtained. IN Maximum limit value C IN T By selecting the corresponding value of the overlap width s of the overlap region 71, the effective minimum value C can be determined. IN MIN With the effective maximum value C IN MAX Select the input capacitor C between IN .

[0049] Correspondingly, the input capacitance C of MOSFET1 is obtained as a function of the ratio between the gate strip distance T and the pitch PT of MOSFET1. IN The value of this ratio is between 0.4 and 0.9 for MOSFET 1. Specifically, C... IN MIN and C IN MAX The value is given by the following formula:

[0050] C IN MIN =40%·C IN T And C IN MAX =90%·C IN T .

[0051] The applicant has verified that, for MOSFET 1, an input capacitance C that is 20% larger than that of a MOSFET with the same contact width C as the contact portion 61 of the source metallization region 6 can be obtained. IN The effective maximum value.

[0052] You can refer to the following: Figures 2A-2E And for illustrative reference Figure 3 The flowchart describes the manufacturing method to obtain Figure 1 MOSFET 1.

[0053] Figure 2A A cross-section of a silicon carbide (e.g., 4H-SiC polytype) wafer 100 is shown, exhibiting a first conductivity (N-type). The wafer 100 is defined at the top by a front side 2a and at the bottom by a back side 2b, and initially includes a substrate 21 on which an epitaxial layer 22 is formed by epitaxial growth (first step S1), having a thickness, for example, between 1 μm and 100 μm along the Z-axis.

[0054] Using a specific mask (not shown) on the front side 2a, a body region 5, a body contact region 51, and a source region 7 are formed in the epitaxial layer 22 of the wafer 100 (second step S2). Each body region 5 extends from the front side 2a with a depth, for example, equal to 1 μm, and has a width (along the X-axis), for example, equal to 3 μm. Each source region 7 extends from the front side 2a within the corresponding body region 5 with a depth, for example, equal to 0.4 μm, and a width (along the X-axis), for example, equal to 2.4 μm; the width of the source region 7 is set, for example, according to design preferences and the power performance of the MOSFET 1. Each body contact region 51 extends from the front side 2a within the corresponding body region 5 with a depth, for example, equal to 0.4 μm, greater than or equal to the depth of the source region 7, and a width (along the X-axis), for example, equal to 1 μm. The N+ type source region 7 has a doping level that is generally higher than that of the wafer 100. The P+ type body contact region 51 has a doping level that is generally higher than that of the body region 5.

[0055] Therefore, the basic unit of MOSFET 1 is completed ( Figures 2A-2E (One is shown in the diagram). The drift region 3 is thus defined in a portion of the epitaxial layer 22 that is not occupied by the main body region 5. Finally, the entire main body 2 of the MOSFET 1 is also completed.

[0056] Subsequently, Figure 2B A gate insulating layer 141 (e.g., silicon oxide), a gate conductive layer 142 (e.g., polysilicon), and a gate passivation layer (or "intermediate dielectric layer") 143 are sequentially formed on the body 2 (third step S3). Specifically, the gate insulating layer 141 is formed on the front side 2a of the body 2, for example, through an oxidation process of the body 2; the gate conductive layer 142 is formed on the gate insulating layer 141, for example, by deposition or epitaxial reaction growth from a seed layer (not shown); and the gate passivation layer 143 is formed on the gate conductive layer 142, for example, by deposition. The gate passivation layer 143 is formed of an intermediate dielectric, such as an oxide, an oxynitride, or a combination of an oxide or nitride and an oxynitride.

[0057] Subsequently, as Figure 2C As shown, the gate insulating layer 141, gate conductive layer 142, and gate passivation layer 143 are patterned by etching at a location corresponding to the source region 7 using a mask (not shown) to form a first opening 140 and a corresponding intermediate gate structure 145 (fourth step S4). Specifically, the first opening 140 (along the Z-axis) extends to the front surface 2a of the body 2 and at least partially exposes the source region 7 and the body contact region 51. Furthermore, the first opening 140 has an extension along the X-axis corresponding to the gate strip distance T, which, as expected, is relative to the gate-source capacitance C of the MOSFET 1. GSThe design parameters are defined. Therefore, the resulting intermediate gate structure 145 has a dimension along the X-axis corresponding to the final gate strip width L of the conductive gate region 42 of the MOSFET 1.

[0058] refer to Figure 2D Then, spacer dielectric layers 144 are formed conformally on the body 2 and the intermediate gate structure 145, for example by deposition (fifth step S5). Specifically, the spacer dielectric layer 144 has a thickness substantially corresponding to the spacer width t, and covers the remaining portion of the gate passivation layer 143, the front side 2a of the body 2 exposed in the first opening 140, and laterally covers the sides of the intermediate gate structure 145. This seals the gate conductive layer 142 of each preliminary gate structure 145. The spacer dielectric layer 144 can be formed of a dielectric that is different from the dielectric of the gate passivation layer 143, but still compatible with it in terms of adhesion; for example, the spacer dielectric layer 144 is formed of oxide, or of oxynitride, or of a combination of oxide or nitride and oxynitride. Furthermore, the spacer width t can have a minimum value, for example, equal to 0.2 μm.

[0059] Subsequently, reference Figure 2E Vertical etching of the spacer dielectric layer 144 is performed, for example, timed and / or selective etching. Vertical etching is, for example, anisotropic etching performed without mask assistance (“blanket etching”), for example, in a CF4 environment. This etching completely removes the portion of the spacer dielectric layer 144 parallel to the front surface 2a of the body 2, forming the second opening 150 (sixth step S6). The portion of the spacer dielectric layer 144 covering the side of the intermediate gate structure 145 remains substantially unchanged and forms the corresponding spacer portion 44. More specifically, the second opening 150 (along the Z-axis) extends to the front surface 2a of the body 2 and at least partially exposes the source region 7 and the body contact region 51. Furthermore, the dimension of the second opening 150 along the X-axis defines the previously described contact width C and is determined according to design preferences by the dimension of the first opening 140 along the X-axis and by the thickness of the spacer dielectric layer 144.

[0060] Finally (seventh step S7), a source metallization layer is formed, for example by deposition, which completely fills the second opening 150 and forms the source metallization region 6 of the MOSFET 1, especially the contact portion 61. A drain metallization region 8 is also formed on the back side 2b of the body 2, ultimately obtaining... Figure 1 MOSFET 1.

[0061] Therefore, compared to photolithography processes performed using dedicated masks, the manufacturing method of this disclosure allows for greater freedom in varying the gate strip distance T between conductive gate regions 42 belonging to two adjacent gate structures 4 for a given contact width C of the contact portion 61 of the source metallization region 6. Specifically, for a given contact width C, the spacer dielectric layer 144 allows for minimizing the spacer width t, and thus also minimizing the gate strip distance T. Therefore, with the same pitch PT, the gate strip width L of the conductive gate region 42 is larger, and consequently the overlap width s and input capacitance C of the MOSFET 1 are also larger. IN This is also increased. More generally, the spacer width t of the spacer portion 44 can be selected based on the desired overlap width s of the overlap region 71 between the conductive gate region 42 and the corresponding source region 7. Furthermore, the manufacturing method of this disclosure allows for avoiding the use of a mask to pattern the contact portion 61 of the source metallization region 6, thereby giving the MOSFET 1 greater overall reliability.

[0062] Finally, it is clear that modifications and changes may be made to the description and illustrations herein without departing from the scope of this disclosure as defined in the appended claims.

[0063] For example, in the source region of a MOSFET, there may be no bulk contact region.

[0064] The spacer portion of the gate structure may have a profile with the sides arranged facing the source metallization region, the contact portion being inclined relative to the front of the body, i.e. having a different inclination from the vertical direction shown.

[0065] In one embodiment of the manufacturing method (not shown), the first opening is formed... Figure 2C The etching stops on the gate insulating layer, thus forming the second opening ( Figure 2E The spacer portion of the gate structure subsequently obtained includes a front portion near the body formed of the same material as the gate insulating layer. In other words, in such an embodiment, the insulated gate region of the gate structure extends along the X-axis with a length equal to the sum of the gate strip width L and twice the spacer width t.

[0066] In an alternative embodiment having the same advantages as previously described, the MOSFET further includes: a deep body region disposed below and in contact with the corresponding body region previously described; a first current spreading layer (CSL) region disposed below and in contact with the corresponding deep body region; and a second current spreading layer region disposed in the drift region between two adjacent body regions and extending at least from the front side of the body to the first current spreading layer region.

[0067] More generally, the MOSFETs of this disclosure may include body regions and source regions that differ from those described and shown in terms of shape and dopant distribution. For example, some body regions may include portions having a dopant concentration higher than the average dopant concentration of the body region.

Claims

1. A method for manufacturing a vertical conduction power device, comprising: - forming body regions in a body, the body comprising a semiconductor material and having a first conductivity, the body regions having a second conductivity opposite to the first conductivity; - forming source regions in respective body regions, the source regions having the first conductivity; - forming gate structures, each gate structure comprising an insulating gate region on the body, a conductive gate region on the insulating gate region, and a passivation gate region on the conductive gate region, the conductive gate region partially overlapping a source region of a respective adjacent body region; - forming source metallization regions on the body and on the gate structures, the source metallization regions comprising contact portions to respective source regions between adjacent gate structures; wherein forming the contact portions comprises: - forming a spacer dielectric layer on the gate structures and on the body in a conformal manner; and - anisotropically etching the spacer dielectric layer down to the source regions.

2. The method for manufacturing a vertical conducting power device according to claim 1, wherein, Etching the spacer dielectric layer comprises performing a maskless etching.

3. The method for manufacturing a vertical conducting power device according to claim 1, wherein, The passivation gate region of each gate structure is formed of a first dielectric selected from: an oxide, an oxynitride, or a combination of an oxide or a nitride with an oxynitride.

4. The method for manufacturing a vertical conducting power device according to claim 1, wherein, The spacer dielectric layer is formed of a second dielectric selected from: an oxide, an oxynitride, or a combination of an oxide or a nitride with an oxynitride.

5. The method for manufacturing a vertical conducting power device according to claim 1, wherein, The spacer dielectric layer has a minimum thickness equal to 0.2 pm and laterally covers the gate structures.

6. The method for manufacturing a vertical conducting power device of claim 1, wherein, Forming the gate structures comprises forming a gate conductive layer and patterning the gate conductive layer so that each resulting conductive gate region overlaps a respective source region in a respective overlapping region along a first direction, and wherein, along a second direction perpendicular to the first direction, the conductive gate regions of adjacent gate structures are separated by a distance having a ratio with a pitch of the power device taking a value between 0.4 and 0.

9.

7. The method for manufacturing a vertical conducting power device according to claim 1, wherein, Etching the spacer dielectric layer comprises defining a pair of spacer portions at a side of each gate structure.

8. The method for manufacturing a vertical conducting power device according to claim 1, wherein, The pair of spacer portions seals the conductive gate region of each gate structure.

9. The method for manufacturing a vertical conducting power device according to claim 1, wherein, The source regions comprise respective body contact regions, wherein each body contact region extends up to a respective body region.

10. The method for manufacturing a vertical conducting power device of claim 1, wherein, The body comprises a substrate and an epitaxial layer, the body regions and the source regions being formed in the epitaxial layer, and wherein the semiconductor material comprises silicon carbide.

11. The method for manufacturing a vertical conducting power device according to claim 1, wherein, The substrate has a back face of the body, the method further comprising forming a drain metallization region on the back face.

12. A vertical conduction power device, comprising: - a body comprising a semiconductor material and having a first conductivity; - one or more body regions extending into the body and having a second conductivity opposite to the first conductivity; - one or more source regions extending into respective body regions and having the first conductivity; - one or more gate structures, each gate structure comprising an insulating gate region on the body, a conductive gate region on the insulating gate region, and a passivation gate region on the conductive gate region, the conductive gate region partially overlapping along a first direction over a source region of a respective adjacent body region; - a source metallization region on the body and on the gate structures, the source metallization region comprising a contact portion to the respective source region between adjacent gate structures; and wherein each gate structure laterally comprises a plurality of spacer portions in contact with the body and delimiting the respective contact portion.

13. The vertical conducting power device of claim 12, wherein, Each conductive gate region overlaps along the first direction over the respective source region in a respective overlap region, and wherein along a second direction perpendicular to the first direction, the conductive gate regions of adjacent gate structures are separated by a distance, the ratio between the distance and the pitch of the power device taking a value comprised between 0.4 and 0.

9.

14. The vertical conducted power device of claim 13, comprising: a source terminal electrically connected to the source metallization region; and a gate terminal electrically connected to each conductive gate region of the gate structures, the power device having a capacitance between the gate terminal and the source terminal depending on the ratio between the distance and the pitch of the power device.

15. The vertical conducted power device of claim 12, wherein, The semiconductor material comprises silicon carbide.

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